A logic standardization processing method of a distributed power distribution terminal

Abstract

The application provides a logic standardization processing method of a distributed power distribution terminal, and belongs to the technical field of information processing, and comprises the following steps: obtaining original logic configuration of core functions of the power distribution terminal; performing syntax normalization conversion on a private logic expression, extracting a self-defined operator, a composite variable and an operation relationship, and mapping the conversion result and the extraction result to a preset standardized logic meta-phrase set to generate a standardized logic topology expression describing a connection relationship of logic units, wherein the standardized logic meta-phrase set corresponds to the core functions; performing lexical and syntax analysis on the standardized logic topology expression, extracting non-divisible logic atomic units, and matching a physical quantity mapping relationship of a hardware interface and a communication interface of the corresponding power distribution terminal; and based on logic interaction rules among multiple power distribution terminals and in combination with the physical quantity mapping relationship, a logic execution dependency graph is constructed to realize collaborative work of the distributed power distribution terminal. Cross-terminal logic standardization is realized, and processing efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of information processing technology, and in particular to a logic standardization processing method for distributed power distribution terminals. Background Technology

[0002] With the large-scale integration of renewable energy sources (such as distributed photovoltaic and wind power) and electric vehicles, the power distribution network is transforming from a traditional unidirectional power supply mode to a complex system with multi-source collaboration. Distribution terminals, as edge devices of the smart grid, undertake core functions such as data acquisition, control execution, and fault handling. However, distribution terminals from different manufacturers typically use proprietary logic expressions, hardware interface definitions, and communication protocols, resulting in poor interoperability and difficulty in achieving efficient collaborative control. For example, a feeder terminal unit (FTU) from one manufacturer may use a custom logic expression to describe a fault isolation strategy, while a station terminal unit (DTU) from another manufacturer uses different variable naming rules and operators, making it impossible to directly reuse or interact with the logic configurations of cross-vendor devices, thus reducing work efficiency.

[0003] Therefore, this invention proposes a logic standardization processing method for distributed power distribution terminals. Summary of the Invention

[0004] This invention provides a logic standardization processing method for distributed power distribution terminals to solve the aforementioned technical problems.

[0005] This invention proposes a logic standardization processing method for distributed power distribution terminals, comprising:

[0006] Step 1: Obtain the original logical configuration of the core functions of the power distribution terminal, wherein the original logical configuration includes private logical expressions, hardware interface definitions and communication interface definitions;

[0007] Step 2: Perform syntax normalization transformation on the private logic expression. At the same time, extract custom operators, compound variables and operation relationships, and map the transformation results and extraction results to a preset standardized logic meta-expression set to generate a standardized logic topology expression describing the connection relationship of logic units. The standardized logic meta-expression set corresponds to the core function.

[0008] Step 3: Perform lexical and syntactic analysis on the standardized logical topology expression, extract indivisible logical atomic units, and match the physical quantity mapping relationship of the corresponding power distribution terminal's hardware interface and communication interface.

[0009] Step 4: Based on the logical interaction rules between multiple power distribution terminals and combined with the physical quantity mapping relationship, construct a logical execution dependency graph to realize the collaborative work of distributed power distribution terminals.

[0010] Preferably, step 2 includes:

[0011] Based on the lexical analyzer, the private logic is recursively traversed and parsed to identify and mark custom operators, compound variables and operation relationships, and generate a syntax feature vector containing operator type, variable dimension and operation level.

[0012] Based on the ontology library of the power system domain, the functional intent of the private logic is semantically annotated, and the semantic annotation results are mapped into standardized semantic vectors. Cosine similarity matching is performed with the preset functional tag libraries of protection, control and metering to preliminarily locate the meta-language category to which the private logic belongs.

[0013] The scope, data type, and value constraints of composite variables are recorded in real time, and a hierarchical symbol table is constructed. The scope includes global domain, local domain, and cross-terminal shared domain. The hierarchical symbol table includes terminal level, logical unit level, and meta-language instance level. The numerical values ​​of composite variables are uniformly mapped based on the range normalization algorithm.

[0014] The grammatical feature vector, the meta-language category to which the private logic belongs, and the hierarchical symbol table are mapped to a preset standardized set of logic meta-languages.

[0015] Preferably, step 2 further includes:

[0016] Based on the temporal dependencies of logical operations in the operational relations, temporal keywords are extracted and labeled to construct temporal dependency chains;

[0017] Based on the arbitration mechanism formed by the aforementioned temporal dependency chain, the many-to-one or one-to-many mapping conflict from private logic to the standardized logic metaphrase set is eliminated, and a standardized logical topology expression describing the connection relationship of logical units is generated. Each metaphrase contains a functional template, interface specification, and hardware adaptation matrix.

[0018] Preferably, step 3 includes:

[0019] An extended context-free grammar is used to define nesting rules for standardized logical topology, and a recursive descent parser is used to generate a syntax tree with position tags and mark the operation priority.

[0020] The functional intent of the topological nodes of the syntax tree is identified by semantic role labeling, and a functional dependency graph is constructed by combining the operation priority.

[0021] The physical constraints, timing constraints, and operational constraints of the input and output of the standardized logical topology are extracted, and a constraint satisfaction problem model is formed by combining the functional dependency graph. The variables of the constraint satisfaction problem model are logical nodes, and the constraints are parameter boundaries and functional dependencies.

[0022] Based on the functional integrity of all logic under each basic function in the functional dependency graph and the constraint closure of the problem model to form a closed set, the syntax tree is backtracked to extract indivisible logical atomic units.

[0023] The logical atom unit is subjected to security and activity verification. Once the verification is successful, a unique hash identifier for the logical atom unit is generated and attached to the logical atom unit.

[0024] If the verification fails, an exception flag is generated and attached to the logical atom unit.

[0025] Preferably, step 3 further includes:

[0026] Extract the static and dynamic attributes of the sampling channels and control loops that match the hardware interface in the power distribution terminal to construct the hardware resource ontology;

[0027] Analyze the protocol frame structure and communication parameters related to the communication interface in the power distribution terminal, and generate a protocol state machine;

[0028] Based on the hardware resource ontology and protocol state machine, the physical quantity mapping relationship of the logical atomic unit is matched.

[0029] Preferably, before constructing the hardware resource ontology, the following steps are included:

[0030] Input a standard signal to the hardware circuit that matches the hardware resource body, and collect the raw value output by the hardware circuit. At the same time, send a standard command to the control loop and record the actual action time of the control loop.

[0031] The original values ​​are compared and analyzed with the standard values, and the least squares method is used for fitting to obtain the first calibration curve of the standard values;

[0032] Meanwhile, the actual action time is compared and analyzed with the upper and lower limit trigger times, and least squares fitting is used to obtain a double calibration curve of the set trigger time.

[0033] The trigger time for the upper and lower limits is adjusted based on the first calibration curve and the dual calibration curve;

[0034]

[0035] in, This is the first calibration curve; a k b k represents the slope and intercept of the first calibration curve; X represents the standard signal.

[0036] Using the intermediate threshold Rmid as the boundary, fit the upper boundary curve R fac,low and lower boundary curve Rfac,high :

[0037] R fac,low =b low,m R ref +c low,m ;

[0038] R fac,high =b high,m R ref +c lhigh,m ;

[0039] Among them, b low,m c low,m b represents the fitted slope and intercept of the fitted upper boundary curve; high,m c lhigh,m R represents the fitted slope and intercept of the fitted lower boundary curve; ref This represents the theoretical time for a standard trigger instruction; R fac This refers to the actual operating time of the control loop;

[0040] Construct the objective optimization function J to optimize the upper and lower limit trigger times of the control loop:

[0041] J = 0.6|R fac -R ref |+0.3|ΔV th +0.1N a ;

[0042] R low,min ≤R low +ΔR low ≤R low,max ,R high,min ≤R high +ΔR high ≤R high,max ;

[0043] Among them, R low,min R low,max R high,min R high,max Two time safety boundaries based on the lower trigger time and two time safety boundaries based on the upper trigger time; ΔV th The threshold change is N. a Adjust the number of times to trigger the time; R low R high These are the original lower limit trigger time and the original upper limit trigger time, respectively; ΔR low ΔR high For the lower boundary trigger time adjustment amount and the upper boundary trigger time adjustment amount;

[0044] Based on the first calibration curve, the original value Yk is converted into a standardized physical quantity. Where ∝T is the temperature compensation term;

[0045] Update trigger threshold

[0046] Where f is the threshold-time mapping function;

[0047] Based on standardized physical quantities and updated trigger thresholds, the physical quantities in the hardware resource body are updated.

[0048] Preferably, step 4 includes:

[0049] Collect the physical state, logical attributes, and environmental information of the power distribution terminal to construct a 12-dimensional state vector;

[0050] The change fields of the 12-dimensional state vector are identified using a hash difference algorithm;

[0051] Based on the logical interaction rules, a change vector for each changed field is constructed, and the set of abnormal attributes of the change vector is obtained.

[0052] Determine the coverage probability of each physical quantity in the physical quantity mapping relationship to each abnormal attribute in the abnormal attribute set, and construct a logical execution dependency graph;

[0053] The execution dependency graph is used to control the collaborative operation of distributed power distribution terminals.

[0054] Preferably, a logical execution dependency graph is constructed, including:

[0055] For each anomalous attribute in the set of anomalous attributes, perform temporal and spatial feature extraction to obtain a combined feature vector;

[0056] Extract the range, accuracy, and hardware channel of physical quantities to construct static feature vectors. At the same time, collect ambient temperature, load rate, and electromagnetic interference in real time to generate dynamic feature vectors.

[0057] Historical correlation data between physical quantities and abnormal attributes are mined, and strong correlation rules are extracted using association rule mining to generate historical correlation feature vectors.

[0058] Based on a multi-layer perception mechanism, static feature vectors, dynamic feature vectors, and historical correlation feature vectors are integrated to output a 32-dimensional influence factor vector F.

[0059] Based on the current physical quantity Ft and the anomaly feature At of the combined anomaly vector, the coverage probability is inferred;

[0060] A logical execution dependency graph is constructed based on the coverage probability and the strength of logical dependencies between logical atomic units.

[0061] Compared with the prior art, the beneficial effects of this application are as follows:

[0062] By employing a full-process approach—from private logic standardization and transformation to precise extraction of atomic units, dynamic mapping of physical quantities, and construction of a distributed collaborative dependency graph—the problem of heterogeneous logic among distribution terminals from multiple vendors is solved. This achieves cross-terminal logic standardization, improves processing efficiency, and enhances the precision of logic execution through constraint verification of logical atomic units and dynamic mapping of physical quantities. The distributed collaborative dependency graph ensures the temporal consistency of actions across multiple terminals, significantly improving the operational reliability and control efficiency of the distribution network.

[0063] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description and the accompanying drawings.

[0064] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0065] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0066] Figure 1 This is a flowchart of a logic standardization processing method for a distributed power distribution terminal according to an embodiment of the present invention;

[0067] Figure 2 This is a logic execution dependency graph in an embodiment of the present invention. Detailed Implementation

[0068] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0069] This invention proposes a logic standardization processing method for distributed power distribution terminals, such as... Figure 1 As shown, it includes:

[0070] Step 1: Obtain the original logical configuration of the core functions of the power distribution terminal, wherein the original logical configuration includes private logical expressions, hardware interface definitions, and communication interface definitions; Step 2: Perform syntax normalization on the private logical expressions, and simultaneously extract custom operators, composite variables, and operational relationships. Map the transformation results and extraction results to a preset standardized logical meta-expression set to generate a standardized logical topology expression describing the connection relationship of logical units, wherein the standardized logical meta-expression set corresponds to the core functions; Step 3: Perform lexical and syntactic analysis on the standardized logical topology expression, extract indivisible logical atomic units, and match the physical quantity mapping relationship of the corresponding hardware interface and communication interface of the power distribution terminal; Step 4: Based on the logical interaction rules between multiple power distribution terminals and combined with the physical quantity mapping relationship, construct a logical execution dependency graph to realize the collaborative work of distributed power distribution terminals.

[0071] In this embodiment, the core functions refer to the basic functions of the distribution terminal in controlling the operation of the distribution network, including three categories: protection (fault detection and isolation), control (switch opening and closing, load regulation), and metering (electrical quantity acquisition and calculation). For example, overcurrent protection (triggers tripping when the line current exceeds a threshold), automatic transfer switch control (automatically switches to backup power when the main power supply fails), and harmonic metering (collects the harmonic content of voltage / current). The original logic configuration is a configuration file or code provided by the terminal manufacturer that describes the logic for implementing the core functions. It contains proprietary syntax rules and interface definitions. For example, a manufacturer's overcurrent protection configuration file (XML format) contains a logical description of outputting a trip command when the A-phase current is >1.2 times the rated current and lasts for 50ms. Specifically, the configuration file is read through the terminal debugging interface (such as RS485, Ethernet) or the offline configuration package provided by the manufacturer is parsed.

[0072] In this embodiment, the private logical expression is a combination of symbols that the manufacturer defines to describe logical operations. It includes custom operators and variable naming rules. For example, the manufacturer uses Feeder_Prot(Ia,1.2Ie,50ms) to indicate that feeder protection is triggered when Ia>1.2Ie for 50ms. Here, Feeder_Prot is a custom operator, and "Ia" and "Ie" are private variables. Specifically, the expression structure is parsed using a lexical analysis tool (such as ANTLR) to extract operators and variables.

[0073] In this embodiment, the hardware interface definition describes the parameters connecting the terminal to external hardware (such as current transformers and relays), including the attributes of the sampling channel and control loop. For example, the sampling channel definition is Channel_0: A-phase current, range 0-63kA, accuracy 0.1%; the control loop definition is Relay_1: tripping circuit, trigger voltage 12V, action time 20-50ms. Specifically, it involves reading the terminal hardware register (e.g., reading the channel configuration via Modbus) or parsing the hardware manual provided by the manufacturer.

[0074] In this embodiment, the communication interface definition describes the protocol parameters for communication between the terminal and external systems (such as the master station and other terminals), including frame structure, baud rate, and data format. For example, the communication interface definition protocol of a certain terminal is Modbus-RTU, baud rate 9600, slave address 1, and the data frame contains current value (2 bytes) and status bit (1 byte). Specifically, the communication packets are captured by a protocol analysis tool (such as Wireshark), and the frame structure and parameters are reverse-analyzed.

[0075] In this embodiment, syntax normalization transformation unifies the syntax rules of private logical expressions to a preset standard (such as operator and variable formats), eliminating vendor differences. For example, the vendor's Feeder_Prot(Ia,1.2Ie,50ms) is converted to the standard format OVER_CURRENT(Ia,1.2,Ie,50ms), and OVER_CURRENT is used to uniformly represent overcurrent protection. Specifically, based on a preset syntax rule library (such as defining > to uniformly represent exceeding), the private symbols are replaced by a lexical analyzer.

[0076] Standardized logic meta-expressions are pre-defined sets of basic logic units that uniformly describe core functions. They are categorized by protection, control, and metering. For example, protection meta-expressions include `OVER_CURRENT(I,Set,Delay)` (overcurrent protection, input current I, threshold set, delay delay); and control meta-expressions include `SWITCH_CONTROL(ID,Cmd)` (switch control, input switch ID, command Cmd). Specifically, they define the input / output interfaces and operation rules of meta-expressions based on power industry standards (such as IEC 61850), forming an extensible meta-expression library. Standardized logic topology expressions are expressions that describe the connection relationships between logic units (meta-expression instances) in a unified format, including input / output associations between units. For example, an XML-formatted topology expression describes the connection of "current sampling unit → overcurrent protection meta-expression → trip control meta-expression," indicating that "the input of the overcurrent protection meta-expression is the current sampling value, and the output triggers trip control." Specifically, based on meta-expression interface specifications, unit connections are defined using a topology description language (such as extended XML) to ensure cross-terminal parsing.

[0077] In this embodiment, lexical and syntax analysis parses standardized logical topological expressions, identifies variables, operators, and grammatical structures, and verifies whether they conform to preset rules. For example, lexical analysis identifies symbols such as "OVER_CURRENT", "I", and "Set" in the topological expression; syntax analysis verifies whether "OVER_CURRENT(I,Set,Delay)" conforms to the syntax rule of "matrix(parameter1,parameter2,parameter3)". Specifically, a recursive descent parser is used to generate a syntax tree and mark the location of syntax errors (such as "missing parameters" or "mismatched parentheses").

[0078] In this embodiment, the logic atom unit is the smallest indivisible and fully functional logic unit, which includes three parts: input, operation, and output. It satisfies functional self-consistency (independently implements a certain basic function). For example, the current sampling → threshold comparison unit (input current value, calculate whether it exceeds the threshold, output comparison result). If any link is missing, the current over-limit judgment function cannot be completed. Specifically, based on the functional dependency graph (such as overcurrent protection depending on current sampling and threshold comparison), the smallest fully functional unit is extracted by backtracking search, and its input and output constraints (such as current threshold ≤ sampling range) are verified.

[0079] The physical quantity mapping relationship is the correspondence between the abstract parameters of a logical atomic unit (such as the current value) and the actual physical quantities of the terminal hardware / communication interface (such as the AD conversion value of the sampling channel). For example, the current value I of the logical atomic unit is mapped to the AD sampling value of the hardware channel Channel_0 (AD value = I × 1000, where 1000 is the conversion coefficient); the trip instruction is mapped to the 3rd-4th byte of the communication protocol frame, which indicates a trip when it is 0x0001. Specifically, a physical quantity mapping table is constructed to record the correspondence between logical parameters and hardware interfaces (such as the range and conversion coefficient of the logical current I corresponding to Channel_0), and hardware errors (such as sampling deviations caused by temperature) are corrected through calibration curves.

[0080] In this embodiment, the logical interaction rule is a constraint rule for the collaborative execution of logical units among multiple terminals. It includes data interaction format, timing requirements and access control. For example, after terminal A triggers overcurrent protection, it needs to send a fault signal to the adjacent terminal B. Terminal B needs to return confirmation within 5ms. Otherwise, terminal A will be forced to trip. Specifically, the rule is defined based on industry standards (such as DL / T1400), and the interaction process (request → response → execution) is described by a state machine.

[0081] In this embodiment, the logic execution dependency graph is a model that uses a directed graph to represent the dependency relationship between logical atomic units. Nodes are atomic units, and edges represent the input-output relationship between units (such as the overcurrent protection unit depending on the output of the current sampling unit). For example, in the directed graph, the current sampling unit points to the overcurrent protection unit (indicating that the overcurrent protection depends on the current sampling result), and the edge is marked with a delay ≤10ms (the sampling result must be transmitted to the protection unit within 10ms). Specifically, based on the logical interaction rules and the mapping relationship of physical quantities, a dependency graph is constructed using graph theory algorithms (such as topological sorting) to ensure no circular dependencies (avoiding logical deadlock).

[0082] Distributed collaborative work involves multiple terminals executing logical units synchronously based on a logical execution dependency graph to achieve global goals of the distribution network (such as rapid fault isolation and load balancing). For example, when a line fault occurs, terminal A triggers the collaboration of terminals B and C through the dependency graph: terminal A trips, terminal B disconnects the upstream switch, and terminal C activates the backup power supply. The time difference between the actions of the three is ≤5ms, achieving fault isolation and load transfer. Specifically, time synchronization (such as IEEE1588) ensures that the terminal clocks are consistent, topology sorting based on the dependency graph controls the execution order, and distributed locks are used to solve resource contention (such as avoiding multiple terminals from controlling the same switch at the same time).

[0083] The beneficial effects of the above technical solution are as follows: through the whole process of private logic standardization conversion → precise extraction of atomic units → dynamic mapping of physical quantities → construction of distributed collaborative dependency graph, the problem of logic heterogeneity of multi-vendor power distribution terminals is solved, cross-terminal logic standardization is achieved, processing efficiency is improved, and the constraint verification of logic atomic units and dynamic mapping of physical quantities improve the accuracy of logic execution. The distributed collaborative dependency graph ensures the timing consistency of actions of multiple terminals, which significantly improves the operational reliability and control efficiency of the power distribution network.

[0084] This invention proposes a logic standardization processing method for distributed power distribution terminals, step 2 of which includes:

[0085] The private logic is recursively parsed using a lexical analyzer to identify and label custom operators, composite variables, and operational relationships, generating a syntactic feature vector containing operator type, variable dimension, and operational level. Based on a power system domain ontology library, the functional intent of the private logic is semantically annotated, and the annotated results are mapped to standardized semantic vectors. These vectors are then matched with pre-defined functional tag libraries for protection, control, and metering using cosine similarity to initially determine the metaphrase category to which the private logic belongs. The scope, data type, and value constraints of composite variables are recorded in real time, constructing a hierarchical symbol table. The scope includes global, local, and cross-terminal shared domains. The hierarchical symbol table includes terminal-level, logic unit-level, and metaphrase instance-level elements, and the numerical values ​​of composite variables are uniformly mapped using a range normalization algorithm. Finally, the syntactic feature vectors, the metaphrase category to which the private logic belongs, and the hierarchical symbol table are mapped to a pre-defined standardized logic metaphrase set.

[0086] A lexical analyzer is a tool that parses text according to preset grammar rules to identify syntactic units (such as operators and variables) in a string. For example, using the ANTLR tool to build a dedicated lexical analyzer for power distribution logic, a grammar rule file (such as a .g4 file) is configured to define operators as starting with a letter and variables as containing numbers and underscores. Proprietary logic is logic description (such as protection criteria and control strategies) written by a manufacturer for a specific terminal and not following general standards. For example, a manufacturer might use LineProt(Ia,Ib,50ms) to describe triggering line protection when the currents of phases A and B simultaneously exceed their limits and persist for 50ms.

[0087] Recursive traversal parsing is a depth-first parsing method that processes nested structures (such as operations within multiple layers of parentheses) through recursive calls. For example, when parsing (Ia>1.2Ie)&(Ib>1.2Ie)|(Ic>1.2Ie), the inner parentheses' Ia>1.2Ie are parsed recursively first, and then the outer "AND" and "OR" operations are processed. Specifically, the child nodes are recursively traversed to identify the nesting level (such as AND operations nested within OR operations).

[0088] Custom operators are symbols or strings (non-general operators) defined by the manufacturer to represent specific logical functions. For example, in DelayTrig(OverCurrent,100ms), DelayTrig means delayed triggering and OverCurrent means overcurrent condition. They are marked as [CUSTOM_OP:DelayTrig] in the Token stream and associated with the function description (such as "delay trigger operator, parameter 1 is the trigger condition, parameter 2 is the delay value").

[0089] Composite variables: Variables composed of basic variables, units, or terminal identifiers (including additional attributes). For example, in Uab_Threshold@T2, Uab_Threshold is the basic variable (AB phase voltage threshold), and @T2 represents the exclusive variable of terminal T2. The marking method is to record the variable composition (basic variable + additional attributes), such as [VAR:Uab_Threshold,ATTR:Terminal=T2].

[0090] Operational relationships are the combinational logic of variables and operators (such as comparison, logical operations, and timing relationships). For example, Ia>1.2Ie→Trip means that if the current exceeds the limit, a trip will be triggered (> is a comparison relationship, → is a causal relationship); TrigAfter(OverVolt,200ms) means that after an overvoltage, a 200ms delay is required to trigger the trip (timing relationship).

[0091] The syntax feature vector is a multi-dimensional vector quantized from the parsing result, used for subsequent normalization mapping. For example, for DelayTrig (Ia>1.2Ie, 50ms), the vector [operator type = delay trigger (1), variable dimension = current (2), operation level = 2 (nesting 1 level)] is generated (the numbers are preset codes). The generation method is to assign codes to the operator type (protection / control / metering), variable dimension (current / voltage / time), and operation level (0 to 5 levels of nesting), and fill the vector according to the parsing result.

[0092] The power system ontology is a structured knowledge base that defines the core concepts of the power system (such as overcurrent protection and automatic transfer switch) and the relationships between concepts (such as overcurrent protection belonging to the protection category). For example, in the ontology, overcurrent protection is defined as a protection function that triggers tripping or alarm when the line current exceeds the rated value. The associated attributes are input = current value and output = tripping command. Specifically, the ontology is constructed using the OWL language, and the protection category includes sub-concepts such as overcurrent protection and overvoltage protection.

[0093] In this embodiment, the functional intent is the core function that the private logic wants to achieve (such as detecting overcurrent and tripping, measuring three-phase active power). For example, the functional intent of LineProt(Ia,Ib,50ms) is three-phase current over-limit protection.

[0094] Semantic annotation adds concept tags from the domain ontology to private logic, clarifying its functional affiliation. For example, the tag LineProt(Ia,Ib,50ms) is labeled as protection class → overcurrent protection → three-phase coordinated protection. Specifically, the ontology concept is automatically associated through keyword matching (such as Prot matching protection) and rule reasoning (such as containing current parameters + delay → protection class).

[0095] Standardized semantic vectors are numerical vectors converted from semantic annotation results to quantify concept similarity. For example, the overcurrent protection vector is [1,0,0,0.8,0.2] (the first 3 bits represent the protection / control / metering classification, and the last 2 bits represent the weights of overcurrent and delay features). The generation method is based on the concept hierarchy of the ontology library and uses the Word2Vec algorithm to map the labels into vectors (dimension = 50 to ensure that vectors of the same type of concept are closer).

[0096] The label library consists of three categories: protection, control, and metering. These are preset label sets categorized by core functions, with each category containing subcategories. Protection category: [overcurrent protection, overvoltage protection, differential protection, ...]; Control category: [automatic transfer switch, load transfer, voltage regulation, ...]; Metering category: [active power metering, harmonic analysis, load statistics, ...].

[0097] Cosine similarity is used to measure the similarity between semantic vectors and tag library vectors (the closer the value is to 1, the higher the similarity). For example, the cosine value of LineProt's semantic vector and the overcurrent protection tag vector is 0.92, and the cosine value of the backup self-submission is 0.31. Therefore, it is determined to be a protection class. Specifically, the cosine value of the vector to be matched and all vectors in the tag library is calculated, and the tag corresponding to the maximum value is taken as the meta-language category (threshold ≥ 0.7, if it is lower than the threshold, manual confirmation is triggered).

[0098] Metaphrase categories are functional classifications within the standardized logical metaphrase set (corresponding to protection / control / measurement). Each category contains multiple basic metaphrases. For example, protection metaphrase categories include OVER_CURRENT(I,Set,Delay) and OVER_VOLTAGE(U,Set,Delay).

[0099] In this embodiment, the scope is the effective range of a composite variable, determining which logical units can access the variable. Global scope: variables visible to all terminals (e.g., system rated voltage Ue); Local scope: variables visible only to a specific logical unit (e.g., temporary threshold TempSet within an overcurrent protection unit); Cross-terminal shared scope: variables used collaboratively by multiple terminals (e.g., load threshold LoadMax shared by terminals T1 and T2). Recording method: The scope attribute of the variable is marked in the symbol table (e.g., [VAR:LoadMax,SCOPE:Shared(T1,T2)]).

[0100] Data type: The numeric type of the composite variable (such as integer, floating-point, Boolean), used to constrain the legality of operations. For example, Ia is a floating-point type (unit: A), TripCmd is a Boolean type (0 = open, 1 = closed), and Delay is an integer type (unit: ms). Value constraints are the allowed value range of the variable (such as range, upper and lower limits of threshold), to prevent logical operation errors. For example, the value constraint of Ia is [0, 63000] (unit: A, corresponding to a 0-63kA range); the constraint of Delay is [10, 500] (unit: ms, to avoid excessively short or long delays).

[0101] The hierarchical symbol table is a table that records variable information in a three-level structure of terminal, logical unit, and meta-language instance, supporting fast query and conflict detection.

[0102] Terminal level: Records global domain and cross-terminal shared variables (such as Ue = 10kV for terminal T1).

[0103] Logical unit level: Record local domain variables (such as TempSet = 1.2Ie for overcurrent protection unit).

[0104] Metaphrase instance level: Records internal variables of the metaphrase (such as I = Ia of the OVER_CURRENT metaphrase).

[0105] Specifically, a hash table is used for storage, with the key being the variable name and scope, and the value being attributes such as data type and value constraints, supporting conflict detection (such as duplicate variable names within the same scope).

[0106] Range normalization is an algorithm that converts variable values ​​from different manufacturers into a unified range, eliminating hardware differences. For example, manufacturer A's current variable Ia_A has a range of 0-50kA, while manufacturer B's Ia_B has a range of 0-63kA. After normalization, both are mapped to per-unit values ​​of 0-1 (e.g., Ia_A = 25kA → 0.5, Ia_B = 31.5kA → 0.5). Specifically, a linear transformation formula is used: y = (x - x_min) / (x_max - x_min), where x is the original value, x_min / x_max is the manufacturer's range, and y is the normalized value (retaining 6 decimal places).

[0107] The mapping method involves matching syntactic feature vectors (such as the operator = delayed triggering), metaword categories (such as protection classes), hierarchical symbol tables (such as the range of variable I) with metawords in the metaword set to generate standardized logical expressions (such as mapping Feeder_Prot(Ia,1.2Ie,50ms) to OVER_CURRENT(Ia,1.2*Ue,50)).

[0108] The beneficial effects of the above technical solution are: by extracting grammatical features through lexical analysis, locating functional categories through semantic annotation, and managing variables through hierarchical symbol tables, the system can ultimately achieve a precise mapping of private logic to standardized meta-languages, effectively improving the accuracy of standardized mapping.

[0109] This invention proposes a logic standardization processing method for distributed power distribution terminals, step 2 of which further includes:

[0110] Based on the temporal dependencies of logical operations in the operational relationship, temporal keywords are extracted and labeled to construct a temporal dependency chain. Based on the arbitration mechanism formed by the temporal dependency chain, the many-to-one or one-to-many mapping conflict from private logic to the standardized logical metaphrase set is eliminated, and a standardized logical topology expression describing the connection relationship of logical units is generated. Each metaphrase contains a functional template, interface specification, and hardware adaptation matrix.

[0111] In this embodiment, the logical operations in the operation relationship describe the rules of logical combination or timing relationship between variables (such as executing condition B after condition A is met, or triggering an action when both A and B are met simultaneously). For example, after overcurrent determination, tripping is executed after a 50ms delay (timing relationship); protection is triggered when both phase A and phase B are overcurrent (logical AND relationship). The timing dependency relationship is the implicit time sequence constraint in the logical operation (such as sampling first, then operation, and then output). For example, the order of current sampling completion → overcurrent determination → delay timing → tripping command. If sampling is not completed, overcurrent determination cannot be performed.

[0112] Temporal keywords are specific symbols or words that mark temporal dependencies (such as keywords indicating sequence, interval, or synchronization). For example, AFTE in AFTER(OverCurrent,50ms) means after; SYNC in SYNC(SampleA,SampleB) means synchronous execution; and DELAY in DELAY(Trig,100ms) means delay. The extraction method is to scan the operation relationship by a lexical analyzer, match it with a preset temporal keyword library (including AFTER, BEFORE, SYNC, DELAY, etc.), mark the position and associate it with time parameters (such as 50ms).

[0113] A timing dependency chain is a chain structure (including time constraints) formed by linking timing keywords to describe the execution order of logic. For example, for sampling → overcurrent determination → delay → tripping, the dependency chain is constructed as: SampleA → [AFTER, 0ms] → OverCurrentCheck → [DELAY, 50ms] → TripCmd, where "→ [keyword, time parameter] →" represents the dependency relationship. Specifically, it is a node dependency relationship based on the syntax tree, with directed edges connecting logical units. The edge attributes are timing keywords and time parameters, forming a chain structure (ensuring no circular dependencies).

[0114] The arbitration mechanism based on the temporal dependency chain resolves conflicts in the mapping from private logic to standardized metaphrases (such as multiple private logics corresponding to the same metaphrase, or one private logic corresponding to a metaphrase). For example, if the private logic "DelayTrig(OverCurrent,50ms)" matches both the standardized metaphrases "OVER_CURRENT_DELAY" and "TRIP_DELAY", the arbitration mechanism determines that its core temporal sequence is "overcurrent delay trip" through the temporal dependency chain "OverCurrent→Delay→Trip", and preferentially maps it to "OVER_CURRENT_DELAY" (a temporal sequence that better fits overcurrent protection). Specifically, it constructs an arbitration rule base containing rules such as "temporal matching priority" (keyword overlap ≥ 80%), "time parameter compatibility" (private delay of 50ms is within the metaphrase's allowed range of 10-100ms), and "functional relevance" (similarity between metaphrase function and private logic intent ≥ 90%), and the rule engine automatically determines the optimal mapping.

[0115] Many-to-one or one-to-many mapping conflicts are phenomena where the mapping relationship between private logic and the standardized metaphrase set is not unique. A many-to-one conflict occurs when multiple private logics (such as OverCurrentDelay from vendor A and FeederProtDelay from vendor B) correspond to the same standardized metaphrase OVER_CURRENT_DELAY. A one-to-many conflict occurs when a private logic (such as TrigAfterAnyFault) can match multiple metaphrs such as OVER_CURRENT_DELAY and OVER_VOLTAGE_DELAY.

[0116] Standardized logical topology expressions are expressions that describe the connection relationships between logical units (matrix instances) in a unified format, including the temporal dependencies and data interactions between units.

[0117] The content expresses that the output of the current sampling unit is used as the input of the overcurrent delay judgment unit. After the overcurrent judgment is completed, the trip command is triggered directly. There is no additional delay in the timing. The function template is a process template (including input processing, operation rules, and output conditions) built into the standardized meta-language and describes the core functional logic. For example, the function template of the meta-language OVER_CURRENT_DELAY is: Input current value I → compare with threshold Set → if I≥Set, start the delay timer → output the action signal after the timer reaches Delay.

[0118] Interface specifications standardize the input / output data format, parameter types, and constraints of meta-pronouns (ensuring interoperability between meta-pronouns). For example, the input interface specifications for OVER_CURRENT_DELAY are: current value I (floating-point, unit A, range 0-63kA), threshold Set (floating-point, unit A), and delay Delay (integer, unit ms, range 10-500ms); the output interface specifications are: action signal (Boolean, 0 = no action, 1 = action).

[0119] The hardware adaptation matrix is ​​a table describing the compatibility relationship between standardized meta-languages ​​and terminal hardware (such as sampling channels and control loops) (including hardware parameter constraints). For example, the adaptation matrix for OVER_CURRENT_DELAY requires that the sampling channel supports a range of 0-63kA (accuracy ≥ 0.2%) and the control loop response time ≤ 10ms to ensure that the meta-languages ​​can be effectively executed on the hardware.

[0120] The beneficial effects of the above technical solution are: by extracting timing keywords to construct dependency chains and combining them with arbitration mechanisms to accurately resolve mapping conflicts, the resulting standardized logical topology expression achieves timing alignment, functional matching, and hardware compatibility between private logic and standardized meta-languages, laying a foundation for timing consistency and interface unification for subsequent extraction of logical atomic units and distributed collaboration.

[0121] This invention proposes a logic standardization processing method for distributed power distribution terminals, step 3 of which includes:

[0122] An extended context-free grammar is used to define nested rules for standardized logical topologies. A recursive descent parser is used to generate a syntax tree with positional tags and to mark operation priorities. Semantic role labeling is used to identify the functional intent of the topology nodes in the syntax tree, and a functional dependency graph is constructed based on the operation priorities. The physical constraints, temporal constraints, and operational constraints of the input and output of the standardized logical topology are extracted, and a constraint satisfaction problem model is formed by combining the functional dependency graph. In this model, the variables are logical nodes, and the constraints are parameter boundaries and functional dependencies. Based on the functional integrity of all logics under each basic function in the functional dependency graph and the constraint closure of the constraint satisfaction problem model forming a closed set, a backtracking search is performed on the syntax tree to extract indivisible logical atomic units. The security and liveness of the logical atomic units are verified. If the verification is successful, a unique hash identifier is generated for the logical atomic unit and attached to it. If the verification fails, an anomaly identifier is generated and attached to the logical atomic unit.

[0123] In this embodiment, the extended context-free grammar is a grammatical rule that adds nested structures and attribute constraints to the traditional context-free grammar. It is used to describe multi-level nested relationships in standardized logical topologies (such as logical units containing sub-units). For example, it defines rules. <logicunit> → <protection> | <control> | <protection> + <control>(This indicates that the logic unit can be composed of a protection unit, a control unit, or a combination of both), and additional attribute constraints are attached (such as...). <protection>Must include <currentcheck>Sub-units), specifically: define the nesting level (supporting 0-5 levels of nesting) through a grammar rule file (such as .g4), and clarify the inclusion relationship between parent and child units (such as an overcurrent protection unit must contain a current sampling sub-unit).

[0124] In this embodiment, the nesting rules of the standardized logical topology are rules that specify how logical units are nested and combined (such as the type, number, and order of sub-units). Specifically, the nesting rules for the backup automatic transfer control unit must include: <voltagecheck>(voltage detection) <loadcheck>(load detection) <switchcontrol>(Switch control) Three sub-units, and <voltagecheck>It must be located on the top layer (voltage must be detected first).

[0125] A recursive descent parser is a top-down syntax parsing tool that processes nested structures by recursively calling functions. It is suitable for parsing logical topologies described by extended context-free grammars. For example, when parsing an overcurrent protection unit (containing a current sampling subunit and a delay subunit), the parser first calls... <protection>The processing function is then recursively called. <currentcheck>and <delay>Sub-functions parse nested structures layer by layer, specifically: generating a parser based on ANTLR and configuring functions to correspond to grammar rules (such as parse_Protection()). <protection>(Rules), output the parsing results.

[0126] A syntax tree with position tags is a tree structure that records the position (row, column) of each node in the original topology expression. It is used to locate syntax errors. For example, the current sampling sub-unit node in the syntax tree is labeled [Line=5, Col=10], which means that the unit is in the 5th row and 10th column of the original expression. If there is a syntax error (such as missing parameters), it can be located accurately.

[0127] Operation priority is the rule for the execution order of logical operations (e.g., comparison operations take precedence over logical AND, and logical AND takes precedence over delay operations). For example, for (Ia>1.2Ie)&(T>50ms)→Trip, the priority is marked as: >(comparison)>&(logical AND)>→(causal), ensuring that the comparison is executed first, then the logical AND is executed, and finally the trip is triggered.

[0128] In this embodiment, semantic role labeling involves assigning functional roles (such as sampling, decision, and control) to the topological nodes of the syntax tree to clarify the functional intent of the nodes. For example, the semantic role of Node1 in the syntax tree is labeled as current sampling, the semantic role of Node2 is labeled as overcurrent decision, and the semantic role of Node3 is labeled as trip control. Specifically, based on the power domain vocabulary (including role labels such as sampling, decision, and control), the node text descriptions are classified using the BERT model, with a labeling accuracy of ≥95%.

[0129] The functional intent of a topology node is the specific function that the node undertakes in the logical topology (e.g., the intent of Node1 is to collect the current value of phase A and provide input for subsequent judgment). For example, the functional intent of Node2 (overcurrent judgment) is to compare the sampled current with the threshold and output the result of whether the limit is exceeded.

[0130] A functional dependency graph is a graph that uses directed edges to represent the functional dependencies between topological nodes (the direction of the edge indicates "who depends on whom"). The execution order is determined by combining the operation priority. For example, for sampling → decision → tripping, the edge in the functional dependency graph is Node1 (sampling) → Node2 (decision) → Node3 (tripping). The edge attribute labels the dependency type: hard dependency (the decision must depend on the sampling result, otherwise the function will fail). Specifically, based on the semantic role labeling results, the node that provides the input is pointed to the node that uses the input. The direction of the edge is determined by combining the operation priority (such as sampling before decision), and a directed acyclic graph (DAG) is generated.

[0131] Physical constraints are constraints on the range and accuracy of physical quantities of the logic topology inputs and outputs (related to hardware characteristics). For example, current input constraint: 0≤Ia≤63kA (accuracy≥0.2%), switch output constraint: duration of opening command ≥100ms.

[0132] Timing constraints: Constraints on the order and interval of execution of logical nodes (to ensure real-time performance). For example, "Node2 (decision) must start within 1ms after Node1 (sampling) is completed" and "Node3 (trip) must be executed within 50ms after Node2 (decision) outputs an over-limit signal".

[0133] Operational constraints are constraints on the parameter types, formats, and operation rules of logical operations (to ensure the legality of the operation). For example, in comparison operations, Ia and 1.2Ie must be of the same type (both are floating-point), and the time parameter of delay operations must be a positive integer (unit: ms).

[0134] The Constraint Satisfaction Problem (CSP) model is a mathematical model that includes "variables" and "constraints" to solve for variable assignments that satisfy all constraints (here, variables are logical nodes, and constraints are parameter boundaries and functional dependencies). For example, the variables are Node1 (sampling) and Node2 (decision); the constraints are: the output current of Node1 ≤ 63kA (physical constraint), Node2 starts within 1ms after Node1 (timing constraint), and Node2 depends on the output of Node1 (functional dependency). Specifically, logical nodes are used as CSP variables, and physical / timing / operational constraints and functional dependencies are used as CSP constraint conditions to construct a constraint matrix (rows = variables, columns = constraints, values ​​= whether they are satisfied).

[0135] Functional integrity means that in a functional dependency graph, all necessary logic nodes for a basic function (such as overcurrent protection) are included without any missing nodes (if any node is missing, the function will fail). For example, the functional integrity requirements for overcurrent protection are: it must include Node1 (current sampling), Node2 (threshold comparison), and Node3 (delay judgment). If Node3 is missing, the function of only acting when the limit is continuously exceeded cannot be implemented.

[0136] Constraint closure is the constraint satisfaction in a problem model where the input and output constraints of logic nodes form a closed set (input constraints cover the requirements of subsequent operations, and output constraints meet the input requirements of downstream nodes). For example, the output current range of Node1 (sampling) 0-63kA needs to cover the input range of Node2 (compare) 0-63kA, and the output (0 / 1) of Node2 needs to meet the input type (Boolean) of Node3 (delay), thus forming a closed constraint.

[0137] Backtracking search is a recursive trial-and-error algorithm used to find the smallest logical unit (indivisible) in a syntax tree that satisfies both functional integrity and constraint closure. For example, starting from the top-level node of the syntax tree, the search proceeds layer by layer downwards. If the current unit satisfies both functional integrity and constraint closure, it is marked as a candidate atomic unit; if not, the search backtracks to the previous level to adjust the search scope (e.g., adding / removing sub-units). Specifically, it combines CSP model pruning (excluding units that do not meet the constraints) and prioritizes searching units with lower nesting levels (ensuring the smallest possible size). The search terminates when the unit cannot be further split (splitting it would result in functional incompleteness or non-closure of constraints).

[0138] In this embodiment, security verification involves verifying that the logic atomic unit has no erroneous output under extreme conditions (such as no deadlock or contradictory instructions). For example, for the overcurrent determination atomic unit, it verifies whether the output is inactive (to avoid false activation) under contradictory conditions where the current is simultaneously ≤ and ≥ the threshold. It also verifies whether abnormal signals are output when there is a hardware fault (to avoid no response). Specifically, it uses a model checking tool (such as SPIN) to convert the unit logic into a Promela model, traverses all possible input states, and detects whether there are unsafe states (such as contradictory outputs).

[0139] Activity verification: Verify that the logic atomic unit will necessarily produce an output under valid input (no "dead wait" state). For example, for the overcurrent detection unit, verify whether it will necessarily output an over-limit signal when the current is continuously ≥ the threshold (to avoid failure to act when it should). Specifically, describe the activity attribute (such as eventually outputting a signal) through linear sequential logic (LTL) and use a model detector to prove that the attribute is valid.

[0140] A unique hash identifier is a unique string generated by a hash algorithm (such as SHA-256) for a verified logical atomic unit. It is associated with the unit's function, constraints, and structure and is used for identification and tamper prevention. For example, for a current sampling → threshold comparison unit, the hash identifier is 0x5f...a3, which is associated with its functional description, constraints, and structural information and stored in the terminal database.

[0141] Anomaly flags are generated for logic atomic units that fail verification (including error type, such as safety not met or activity missing) and are used for subsequent optimization. For example, if the overcurrent detection unit outputs an error signal when the current is 63kA, the anomaly flag is Error:Safety_Fail,Reason:Overflow_Output.

[0142] The beneficial effects of the above technical solution are: by extending grammar parsing, semantic annotation, constraint modeling, backtracking search and verification identifiers, the extracted logical atomic units simultaneously satisfy the requirements of functional integrity, constraint closure and security and reliability, thereby improving the functional integrity compliance rate of atomic units, and providing standardized and highly reliable basic logical units for subsequent physical quantity mapping and distributed collaboration.

[0143] This invention proposes a logic standardization processing method for distributed power distribution terminals, step 3 of which further includes:

[0144] Extract the static and dynamic attributes of the sampling channels and control loops that match the hardware interface in the power distribution terminal to construct a hardware resource ontology; parse the protocol frame structure and communication parameters related to the communication interface in the power distribution terminal to generate a protocol state machine; and match the physical quantity mapping relationship of the logical atom units based on the hardware resource ontology and the protocol state machine.

[0145] In this embodiment, the sampling channel is a physical channel in the hardware interface used to acquire electrical quantities (current, voltage, power, etc.), including signal conditioning circuits and AD conversion modules. Specifically, the channel parameters are read through terminal hardware configuration tools (such as debugging software provided by the manufacturer) or by parsing the channel definition table in the hardware manual. The control loop is a circuit in the hardware interface used to output control commands (opening, closing, regulation, etc.), including drive modules and protection circuits. For example, Trip_Circuit (trip circuit): trigger voltage 24VDC, maximum drive current 1A, action time 20-50ms, corresponding to physical interface DO_1.

[0146] Static properties are inherent properties of hardware (sampling channels, control loops) that do not change with the operating state.

[0147] Sampling channel static attributes: Range (0-63kA), accuracy class (0.2), resolution (16-bit), physical interface number (AI_0). Control loop static attributes: Trigger voltage (24V), rated current (1A), interface type (relay output). Dynamic attributes are the hardware properties that change with operating status or environment. Sampling channel dynamic attributes: Real-time sampled value (e.g., 10.5A), temperature drift coefficient (0.01% / ℃, varying with ambient temperature), noise level (≤5mV). Control loop dynamic attributes: Current status (open / close), number of actions (cumulative 1200 times), response time (currently 35ms, increasing with aging).

[0148] The hardware resource ontology is a knowledge base that uses a structured language (such as OWL) to describe the static and dynamic attributes of sampling channels and control loops, forming a unified description of attribute-value-constraint. For example, the description of Channel_0 in the ontology is: Sampling channel (ID=0, type=current, range=[0,63000]A, accuracy=0.2%, current temperature drift=0.008% / ℃).

[0149] In this embodiment, the protocol frame structure is a data frame format specified by the communication protocol, containing a frame header (synchronization word, address), a data segment (payload), and a frame trailer (checksum, end character). For example, the Modbus-RTU protocol frame structure is: [slave address (1 byte) + function code (1 byte) + data (1-252 bytes) + CRC checksum (2 bytes)]. For example, "010300000002840A" means "read registers 0000-0001 of slave 1". Specifically, communication data is captured by a message capture tool (such as Wireshark or serial port assistant), and the boundaries and meanings of the frame header, data segment, and frame trailer are analyzed in reverse.

[0150] Communication parameters are configuration parameters that control the operation of the communication interface, including baud rate, parity check, timeout, slave address, etc. For example, RS485_1 parameters: baud rate 9600bps, no parity check, 1 stop bit, slave address 0x02, timeout 500ms. Specifically, the parameters can be read through the terminal communication configuration interface or deduced by sending a probe message (such as the Modbus read device identifier command).

[0151] A protocol state machine is a mathematical model that describes the state transition rules during the operation of a communication protocol. It includes states such as Idle → Receive → Parse → Response → Idle and triggering conditions. For example, the Modbus protocol state machine is as follows: Idle state → [Received a frame that conforms to the format] → Receive state → [Verification passed] → Parse state → [Generate a response frame] → Send state → [Sending completed] → Idle state. If verification fails, it directly returns to the Idle state. Specifically, state transitions are described using state diagram tools (such as UML state diagrams) based on the protocol specification (such as the Modbus protocol document) or implemented as an executable model through code (such as Python's state machine library).

[0152] The physical quantity mapping relationship is the correspondence between the abstract physical quantity of the logical atomic unit (such as current I) and the actual physical quantity of the hardware interface (such as the AD value of the sampling channel) and the protocol data of the communication interface (such as the current field in the frame structure). For example, logical input current I → AD conversion value of hardware sampling channel "Channel_0" (AD value = I × 1000, where 1000 is the conversion coefficient).

[0153] The logic output trip signal is the DO_1 control bit in the communication protocol frame (a trip is indicated when bit 0 of the 5th byte in the frame is 1).

[0154] The matching logic establishes a correspondence rule between logical atomic units and physical quantities based on the hardware resource ontology and protocol state machine (ensuring that logical requirements are compatible with hardware / communication capabilities). For example, the OverCurrentCheck unit needs to match: Hardware: sampling channel range ≥ 1.2Ie (e.g., when Ie = 10kA, the channel range must be ≥ 12kA), accuracy ≥ 0.5%; Communication: the protocol frame contains a "current I" field (occupying 2 bytes, resolution 0.1A), supports real-time upload (update cycle ≤ 100ms), specifically:

[0155] Construct a mapping table: Record the correspondence between the input / output of the logic atomic unit and the hardware channel / protocol field (e.g., OverCurrentCheck.I → Channel_0.AD value); Compatibility verification: Verify whether the channel range and accuracy meet the logic requirements through the hardware resource body, and verify whether the communication parameters support real-time data transmission through the protocol state machine; Dynamic adjustment: If hardware aging causes the channel accuracy to decrease (e.g., from 0.1% to 0.8%), automatically update the conversion coefficient of the mapping table (e.g., adjust AD value = I × 1000 to AD value = I × 1005).

[0156] The beneficial effects of the above technical solution are: by constructing a hardware resource ontology and a protocol state machine, precise matching between logical atomic units and hardware interfaces and communication interfaces is achieved.

[0157] This invention proposes a logic standardization processing method for distributed power distribution terminals. Before constructing the hardware resource body, the method includes: inputting a standard signal to a hardware circuit that matches the hardware resource body and collecting the original value output by the hardware circuit; simultaneously, issuing a standard command to the control loop and recording the actual action time of the control loop; comparing and analyzing the original value with the standard value and fitting it using the least squares method to obtain a first calibration curve of the standard value; and simultaneously comparing and analyzing the actual action time with the upper and lower limit set trigger times and fitting it using the least squares method to obtain a double calibration curve of the set trigger times.

[0158] The trigger time for the upper and lower limits is adjusted based on the first calibration curve and the dual calibration curve;

[0159]

[0160] in, This is the first calibration curve; a k b k represents the slope and intercept of the first calibration curve; X represents the standard signal.

[0161] Using the intermediate threshold Rmid as the boundary, fit the upper boundary curve R fac,low and lower boundary curve R fac,high :

[0162] R fac,low =b low,m R ref +c low,m ;R fac,high =b high,m R ref +c lhigh,m Among them, b low,m c low,m

[0163] b represents the fitted slope and intercept of the fitted upper boundary curve; high,m c lhigh,m R represents the fitted slope and intercept of the fitted lower boundary curve; ref This represents the theoretical time for a standard trigger instruction; R fac This refers to the actual operating time of the control loop;

[0164] Construct the objective optimization function J to optimize the upper and lower limit trigger times of the control loop:

[0165] J = 0.6|R fac -R ref |+0.3|ΔV th +0.1N a ;

[0166] R low,min ≤R low +ΔR low ≤R low,max ,R high,min ≤R high +ΔR high ≤R high,max Among them, R low,min R low,max R high,min R high,max Two time safety boundaries based on the lower trigger time and two time safety boundaries based on the upper trigger time; ΔV th The threshold change is N. a Adjust the number of times to trigger the time; R low R high These are the original lower limit trigger time and the original upper limit trigger time, respectively; ΔR low ΔR high For the lower boundary trigger time adjustment amount and the upper boundary trigger time adjustment amount;

[0167] Based on the first calibration curve, the original value Yk is converted into a standardized physical quantity. where ∝T is the temperature compensation term; the update trigger threshold where f is the threshold-time mapping function; based on the standardized physical quantity and the updated trigger threshold, the update of the physical quantity in the hardware resource ontology is realized.

[0168] In this embodiment, the original value is the actual output of the hardware circuit, and the standard value is preset as the standard input. For example, when the input is 10 kA, the output is 998 (16-bit resolution).

[0169] In this embodiment, the linear relationship between the standard input and the actual output of the fitting hardware is fitted to correct the static deviation. The linear deviation of the hardware is the highest (such as the gain error of the signal conditioning circuit), and the least squares method can minimize the sum of the squared residuals to achieve the optimal linear approximation.

[0170] In this embodiment, R fac is the actual time taken for the control loop to execute the instruction. For example, after sending a trip instruction, the oscilloscope measures that the relay closing time is 25 ms.

[0171] In this embodiment, Rmid is used to divide the low-delay area R ref < Rmid, high-delay area R ref ≥ Rmid boundary, for example, 30 ms. The delay characteristic of the control loop is non-linear (the low-delay area is dominated by electromagnetic interference, and the high-delay area is dominated by mechanical inertia), and piecewise fitting is more accurate.

[0172] In this embodiment, R fac,low = b low,m R ref + c low,m is the theoretical-actual time relationship for fitting the low-delay area;

[0173] R fac,high = b high,m R ref + c lhigh,m is the theoretical-actual time relationship for fitting the high-delay area.

[0174] In this embodiment, the design of the weights in the target optimization function is to conform to the priority stratification of accuracy → stability → lifespan in the engineering scenario, and multi-objective balance is achieved through weighting.

[0175] In this embodiment, the time safety boundary limits the adjustment range of the trigger time. For example, the lower limit adjustment cannot be lower than 15 ms to avoid misoperation; it cannot be higher than 25 ms to ensure the response speed. Specifically: according to the hardware manual (such as the minimum reliable action time of the relay is 15 ms). <000046...Here, ΔT represents the deviation between the ambient temperature and the reference temperature. Since the hardware parameters drift with temperature (such as the temperature drift of the resistor causing AD sampling deviation), temperature compensation is required.

[0177] In this embodiment, the mapping function fits the nonlinear relationship between trigger time and threshold voltage using a dual-calibration curve (e.g., the longer the time, the higher the threshold needs to be to avoid false triggering).

[0178] The beneficial effects of the above technical solution are: by using a closed loop of hardware linear calibration → control time segmented calibration → multi-objective optimization → cross-physical quantity collaborative correction, the problem of insufficient calibration accuracy is solved, and a precise, stable and self-adaptive physical quantity reference is provided for the logic execution of distributed power distribution terminals.

[0179] This invention proposes a logic standardization processing method for distributed power distribution terminals, step 4 of which includes:

[0180] Collect the physical state, logical attributes, and environmental information of the power distribution terminal to construct a 12-dimensional state vector;

[0181] The change fields of the 12-dimensional state vector are identified using a hash difference algorithm;

[0182] Based on the logical interaction rules, a change vector for each changed field is constructed, and the set of abnormal attributes of the change vector is obtained.

[0183] Determine the coverage probability of each physical quantity in the physical quantity mapping relationship to each abnormal attribute in the abnormal attribute set, and construct a logical execution dependency graph;

[0184] The execution dependency graph is used to control the collaborative operation of distributed power distribution terminals.

[0185] In this embodiment, physical state refers to the operating parameters of the terminal hardware, reflecting resource usage and health.

[0186] Dimensional example (6 dimensions):

[0187] CPU load (1-dimensional, 0-100%): Terminal CPU real-time utilization is 65% (collected via the top command);

[0188] Memory usage (1D, 0-100%): 30% of memory remains (collected via the free command);

[0189] Sampling channel temperature (3D, °C): A / B / C phase current sampling channel temperatures are 45°C, 43°C, and 44°C (acquired via thermistor sensors);

[0190] Control loop voltage (1 dimension, V): Trip loop power supply voltage 24.2V (acquired via ADC module).

[0191] Logical attributes are the configuration and status of terminal logical functions, reflecting the validity of the logic.

[0192] Dimensional example (3D):

[0193] Protection Function Enable (1D, 0 / 1): Whether overcurrent protection is enabled (1) (enabled, read from register);

[0194] Trigger threshold (1-dimensional, such as phase A overcurrent threshold): 1.2Ie (Ie = 10kA, i.e. 12kA, resolved through configuration file);

[0195] Logical version (1-dimensional, version number): Protects the logic program version V2.1 (parsed through the file header).

[0196] Environmental information refers to the parameters of the power distribution network and natural environment where the terminal is located, reflecting external interference.

[0197] Dimensional example (3D):

[0198] Number of topology nodes (1-dimensional, integer): Number of nodes on the feeder to which the terminal belongs, 15 (obtained from the distribution network GIS system);

[0199] Ambient temperature (1-dimensional, °C): Temperature at the terminal installation location is 30 °C (collected via DHT11 sensor);

[0200] Electromagnetic interference (1D, dBμV): Nearby electromagnetic interference intensity 55 dBμV (acquired by EMI spectrum analyzer).

[0201] The 12-dimensional state vectors are combined in a fixed order, such as [65,30,45,43,44,24.2,1,12,V2.1,15,30,55], to achieve a full characterization of the state.

[0202] The hash differential algorithm reduces the amount of data transmission by comparing hash values ​​to locate fields with changes in status. Specifically, it involves hash calculation: generating a hash (e.g., 0x123...abc) from a 12-dimensional vector using SHA-256.

[0203] Historical comparison: Store the hash of the previous moment (e.g., 0x123...abd), and trigger differential if they are different;

[0204] Field location: Traverse the vector elements and find the changed value (e.g., CPU load changes from 65 to 70, corresponding to the change in the first dimension). For example, if the hash of the previous vector [65,30,...] is different from that of the current vector [70,30,...], the change in the first dimension (CPU load) is determined by difference, and the change value is +5.

[0205] The change vector is the numerical difference of the changed field (e.g., CPU load change +5).

[0206] The abnormal attribute set is a collection of abnormal types triggered by the change vector (e.g., if CPU load increases by 15 and then exceeds 80%, then it is {hardware overload}). Specifically, the rule engine matches the change value with the threshold to generate abnormal labels (e.g., if CPU load is 70 < 80, there is no overload; if CPU load is 80, hardware overload is triggered).

[0207] In this embodiment, the coverage probability is the suppression probability of a physical quantity on anomalies (range 0 to 1, the higher the value, the stronger the suppression ability). Specifically, a Bayesian network is trained based on historical data, such as P(hardware overload|normal current) = 0.99 (in 1000 data points, there are only 10 overloads when the current is normal).

[0208] Collaborative work involves multiple terminals synchronously executing logic based on a dependency graph to achieve global goals (such as fault isolation).

[0209] The beneficial effects of the above technical solution are: by using 12-dimensional vectors to fully perceive the state, hash differentials to accurately locate changes, and by combining anomaly rules and coverage probabilities to construct a dependency graph, a closed loop of distributed terminal state perception, anomaly prediction, and collaborative scheduling is realized, which significantly improves the real-time performance and reliability of the distribution network in dealing with complex operating conditions.

[0210] This invention proposes a logic standardization processing method for distributed power distribution terminals, which constructs a logic execution dependency graph, including:

[0211] For each anomalous attribute in the set of anomalous attributes, perform temporal and spatial feature extraction to obtain a combined feature vector;

[0212] Extract the range, accuracy, and hardware channel of physical quantities to construct static feature vectors. At the same time, collect ambient temperature, load rate, and electromagnetic interference in real time to generate dynamic feature vectors.

[0213] Historical correlation data between physical quantities and abnormal attributes are mined, and strong correlation rules are extracted using association rule mining to generate historical correlation feature vectors.

[0214] Based on a multi-layer perception mechanism, static feature vectors, dynamic feature vectors, and historical correlation feature vectors are integrated to output a 32-dimensional influence factor vector F.

[0215] Based on the current physical quantity Ft and the anomaly feature At of the combined anomaly vector, the coverage probability is inferred;

[0216] A logical execution dependency graph is constructed based on the coverage probability and the strength of logical dependencies between logical atomic units.

[0217] In this embodiment, time feature extraction describes the occurrence pattern of anomalies from a time dimension, including frequency (ft, number of occurrences per unit time), duration (dt, duration of a single anomaly), and interval distribution (it, time difference between adjacent anomalies). For example, a hardware overload anomaly occurs 3 times within 1 hour (ft = 3), each lasting 10 seconds (dt = 10), with intervals of 20 minutes and 25 minutes respectively (it = [1200, 1500], with an average of 1350). Specifically, a sliding time window (window length 100ms to 1s, step size 10ms) is used to segment the time series, and the frequency and duration are counted using Python's pandas.rolling, and the interval distribution is calculated using numpy.diff.

[0218] Spatial feature extraction characterizes the propagation characteristics of anomalies from the perspective of distribution network topology, including propagation path (ps1, the sequence of terminals / nodes from which the anomaly spreads), impact range (rs, the number of affected terminals), and spatial density (ps2, the proportion of affected terminals in the area). For example, a communication interruption anomaly propagates from terminal T1 to T2 and T3 (ps1 = [T1, T2, T3]), affecting 3 terminals (rs = 3). The feeder has a total of 5 terminals, so the spatial density ps2 = 3 / 5 = 0.6. Specifically, based on distribution network GIS topology data (terminal locations, feeder connection relationships), the anomaly propagation path is traced using a graph traversal algorithm (such as DFS), and the number of affected terminals and the proportion of the area are statistically analyzed.

[0219] In this embodiment, the combined feature vector generation fuses temporal features (3D: ft, dt, it) and spatial features (3D: ps1, rs, ps2), and generates a 64-dimensional quantized vector by weighting it through a spatiotemporal attention mechanism (STA) (ensuring that features of different anomalies can be compared). For example, the temporal feature vector is [3, 10, 1350], and the spatial feature vector is [[T1, T2, T3], 3, 0.6]. After STA weighting, the output is a 64-dimensional vector A = [0.82, 0.15, ..., 0.03] (attention weights highlight high-frequency, short-duration anomalies).

[0220] In this embodiment, the static feature vector (hardware inherent attribute) is a fixed attribute describing the physical quantity, including range ([min, max], the effective range of the physical quantity), accuracy (∈, the measurement error ratio), and hardware channel ID (unique identifier of the sampling / control channel). For example, the current sampling channel "AI_0": range [0, 63000]A (i.e., 0~63kA), accuracy ∈=0.2% (error ≤ 0.002 times the range), channel ID=1→static feature vector: [63000, 0.002, 1] (normalized to 0~1 to [1.0, 0.002, 0.1], a total of 10 dimensions). Specifically, the terminal hardware register is read (e.g., channel configuration is read via Modbus protocol) or the hardware manual provided by the manufacturer is parsed to extract parameters such as range, accuracy, and ID.

[0221] In this embodiment, the dynamic feature vector (real-time operating condition influence) is an attribute describing the change of physical quantities with the environment / operating state, including ambient temperature (Tenv, temperature at the terminal installation location), load rate (λ, hardware resource utilization rate), and electromagnetic interference (EMI, ambient electromagnetic noise intensity). For example, real-time monitoring: ambient temperature 30℃ (deviation from the reference 25℃ ΔT=5), CPU load rate 70%, electromagnetic interference → dynamic feature vector: [5,0.7,55] (3-dimensional, directly acquired or calculated), specifically: ambient temperature is acquired through a temperature sensor (such as DHT11), load rate is obtained through terminal system commands (such as top), and electromagnetic interference is measured through an EMI spectrum analyzer.

[0222] In this embodiment, the historical correlation data is a record of the historical correlation between physical quantities and abnormal attributes (e.g., "when the current value is > 1.1 times the rated value, the probability of hardware overload is 80%"). The data volume is ≥ 10. 5 To ensure statistical significance, for example, in a historical database of 100,000 records, when the current I > 1.1Ie (Ie = 10kA, i.e. 11kA), the "hardware overload" anomaly occurred 8,000 times (support 8%), of which 6,400 times were indeed overloads (confidence 80%).

[0223] In this embodiment, association rule mining (Apriori algorithm) extracts strong association rules from historical data, satisfying the following conditions: support ≥ 10% (the rule appears ≥ 10% of the time) and confidence ≥ 80% (the probability of an anomaly occurring after the rule is triggered ≥ 80%). For example, the rule: {I>1.1Ie}→{hardware overload} has a support of 12% (12,000 triggers), a confidence of 85% (10,200 actual overloads), and a lift of 1.2 (the probability of overload is 20% higher than in the random case).

[0224] In this embodiment, the historical association feature vector encodes the support, confidence, and lift of strong association rules into an 8-dimensional vector to characterize the historical association strength between physical quantities and anomalies. For example, the feature vector of the above rule is: [0.12, 0.85, 1.2, 0, ..., 0] (only the first 3 dimensions are valid, and the last 5 dimensions are filled with 0, for a total of 8 dimensions).

[0225] In this embodiment, the multilayer sensing mechanism employs a 3-layer fully connected neural network, fusing static features (10-dimensional), dynamic features (3-dimensional), and historical correlation features (8-dimensional) to output a 32-dimensional influence factor vector F, characterizing the comprehensive influence of physical quantities on anomalies. Specifically:

[0226] Input layer: 21-dimensional (10+3+8) → Hidden layer 1: 64-dimensional (ReLU activation) → Hidden layer 2: 32-dimensional (ReLU activation) → Output layer: 32-dimensional (Sigmoid normalization).

[0227] Training optimization:

[0228] Loss function: Mean Squared Error (MSE), optimizer: Adam (learning rate 0.001), trained with historical data (spatiotemporal features + physical features + association rules), convergence time ≤ 100 rounds, fusion error ≤ 5%.

[0229] The 32-dimensional influence factor vector F, for example, the fused vector: F = [0.82, 0.15, 0.03, ..., 0.01], the first dimension (0.82) represents the intensity of the influence of current on hardware overload, the higher the value, the easier it is for the current to trigger overload.

[0230] In this embodiment, Ft is a 32-dimensional influence factor vector of real-time physical quantities (such as the current current of 11.5kA, corresponding to the fusion vector after dynamic feature update), and At is a 64-dimensional combined feature vector of real-time anomalies (such as the spatiotemporal features of the current overload).

[0231] In this embodiment, the model structure of probabilistic inference is as follows: the time slice interval Δt = 50ms, the state transition matrix is ​​learned through the LSTM network (e.g., current increase → overload probability increase), and the nodes of adjacent time slices are associated through the transition matrix.

[0232] Probability Calculation: Variational inference (VI) is used to learn the conditional probability table (CPT). Given Ft and At, the coverage probability P(Ft→At) is inferred through the belief propagation (BP) algorithm. The inference time is ≤10ms and the accuracy is ≥90%. For example, if the current is 11.5kA (1.15Ie), the overload impact dimension in Ft is 0.85. The abnormal At is a high-frequency and short-duration one. The inferred coverage probability P = 0.88 (with an 88% probability, this current can cover the hardware overload abnormality).

[0233] In this embodiment, the logic dependency strength is the degree of functional dependency between logic atomic units (such as overcurrent protection depending on current sampling; the shorter the path and the stronger the functional correlation, the higher the strength, ranging from 0 to 1). For example, if the overcurrent protection unit directly depends on the current sampling unit, the dependency strength is 0.9 (path length 1, no intermediate units).

[0234] In this embodiment, the weighted directed dependency graph is constructed as follows:

[0235] Nodes: Logical atomic units (such as "overcurrent protection" and "load monitoring");

[0236] Edge weight: Edge weight = Coverage probability × Logical dependency strength (e.g., overcurrent protection → overload: 0.88 × 0.9 = 0.792), specifically: a directed graph is constructed using Python's networkx library, and acyclicity is verified through topological sorting (to avoid logical deadlock), resource constraints: CPU / memory usage ≤ 80%.

[0237] In this embodiment, such as Figure 2 The diagram shown is a logical execution dependency graph:

[0238] CS_A: Phase A current sampling unit, responsible for collecting the physical quantity of phase A current (hardware channel AI_0);

[0239] OC_A: Phase A overcurrent determination unit, which determines whether the current exceeds the threshold (1.2 times the rated current) based on the sampled value of CS_A;

[0240] TC_A: Phase A trip control unit, receives the judgment result of OC_A and outputs trip command.

[0241] CS_B: Phase B current sampling unit, which collects the physical quantity of phase B current (hardware channel AI_1);

[0242] OC_B: B-phase overcurrent determination unit, which determines overcurrent based on the sampled value of CS_B;

[0243] TC_B: B-phase trip control unit, receives the judgment result of OC_B and outputs trip command.

[0244] BZT: Backup automatic transfer trigger unit, which needs to receive the overcurrent judgment results of OC_A and OC_B simultaneously. The backup automatic transfer is activated when both phases are overcurrent.

[0245] CS_A→OC_A(0.96, covering HWO): Phase A current sampling provides input for overcurrent judgment, and the probability of covering the "Hardware Overload (HWO)" anomaly is 96% (that is, when the sampling is stable, the possibility of hardware overload is low).

[0246] OC_A→TC_A(0.92, covering COM): The overcurrent judgment result of phase A drives the trip control, and the coverage probability of "communication interruption (COM)" abnormality is 92% (that is, the possibility of communication interruption is low when the judgment result is transmitted).

[0247] OC_A→BZT(0.95, covering LOG): The overcurrent judgment result of phase A participates in the backup automatic transfer trigger, and the coverage probability of the "logic misjudgment (LOG)" anomaly is 95% (that is, the possibility of the judgment result being wrong is low).

[0248] The meanings of CS_B→OC_B (0.95, covering HWO), OC_B→TC_B (0.91, covering COM), and OC_B→BZT (0.94, covering LOG) for phase B paths are similar, but due to differences in hardware characteristics, the coverage probability is slightly lower than that for phase A.

[0249] The beneficial effects of the above technical solution are: through the entire process of quantifying anomalies with spatiotemporal features → characterizing physical quantities with static and dynamic features → mining patterns and probabilistic inferences from historical correlations → constructing a weighted dependency graph, deep correlation modeling of physical quantities and anomalies is realized, providing logical dependencies for the collaborative execution of distributed power distribution terminals.

[0250] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.< / protection> < / delay> < / currentcheck> < / protection> < / voltagecheck> < / switchcontrol> < / loadcheck> < / voltagecheck> < / currentcheck> < / protection> < / control> < / protection> < / control> < / protection> < / logicunit>

Claims

1. A method for logical standardization processing of a distributed power distribution terminal, characterized by, Comprising: Step 1: Obtain the original logic configuration of the core function of the power distribution terminal, wherein the original logic configuration contains private logic expressions, hardware interface definitions, and communication interface definitions; Step 2: Perform syntax normalization conversion on the private logic expressions, while extracting custom operators, composite variables, and operation relationships, and mapping the conversion results and extraction results to a preset standardized logic meta-linguistic set to generate a standardized logic topology expression describing the connection relationship of the logic units, wherein the standardized logic meta-linguistic set corresponds to the core function; Step 3: Perform lexical and syntactic analysis on the standardized logic topology expression, extract non-divisible logic atomic units, and match the physical quantity mapping relationship of the hardware interface and communication interface of the corresponding power distribution terminal; Step 4: Based on the logic interaction rules between multiple power distribution terminals and combined with the physical quantity mapping relationship, a logic execution dependency graph is constructed to realize the collaborative work of distributed power distribution terminals.

2. The method of claim 1, wherein the logic standardization process of the distributed power distribution terminal is characterized by, Step 2, comprising: Based on the lexical analyzer, recursively traverse and parse the private logic, identify and mark custom operators, composite variables, and operation relationships, and generate a syntax feature vector containing operator types, variable dimensions, and operation levels; Based on the power system domain ontology library, the semantic intention of the private logic is annotated, and the semantic annotation result is mapped to a standardized semantic vector, which is matched with the cosine similarity of the preset protection, control, and metering three function label library to preliminarily locate the meta-linguistic category to which the private logic belongs; Real-time record the scope, data type and value constraint of the composite variable, construct a hierarchical symbol table, wherein the scope includes global domain, local domain and cross-terminal shared domain, the hierarchical symbol table includes terminal level, logic unit level and meta-linguistic instance level, and the numerical value of the composite variable is uniformly mapped based on the range normalization algorithm; Map the syntax feature vector, the meta-linguistic category to which the private logic belongs, and the hierarchical symbol table to the preset standardized logic meta-linguistic set.

3. The method of claim 2, wherein the logic standardization process of the distributed power distribution terminal is characterized by, Step 2, further comprising: Based on the time sequence dependency relationship of the logical operation in the operation relationship, extract and mark the time sequence keywords, and construct a time sequence dependency chain; Based on the arbitration mechanism formed by the time sequence dependency chain, eliminate the many-to-one or one-to-many mapping conflicts of the private logic to the standardized logic meta-linguistic set, and generate a standardized logic topology expression describing the connection relationship of the logic units, wherein each meta-linguistic contains a function template, an interface specification, and a hardware adaptation matrix.

4. The method of claim 1, wherein the logic standardization process of the distributed power distribution terminal is characterized by, Step 3, comprising: Use the extended context-free grammar definition to define the nested rules of the standardized logic topology, and generate a syntax tree with position markers through the recursive descent parser, and mark the operation priority; Identify the function intention of the topology node of the syntax tree through semantic role labeling, and construct a function dependency graph combined with the operation priority; Extract the physical constraints, timing constraints, and operation constraints of the input and output of the standardized logic topology, and form a constraint satisfaction problem model combined with the function dependency graph, wherein the variables of the constraint satisfaction problem model are logic nodes, and the constraints are parameter boundaries and function dependencies; Based on the functional integrity of all the logic under each basic function in the function dependency graph and the constraint closure of the constraint satisfaction problem model forming a closed set, the syntax tree is backtracked to extract non-divisible logic atomic units; The security and activity of the logic atomic units are verified, and a unique hash identification of the logic atomic units is generated and attached to the logic atomic units when the verification is passed; If the verification fails, an abnormal identification is generated and attached to the logic atomic units.

5. The method of claim 4, wherein the logic standardization process of the distributed power distribution terminal is characterized by, Step 3 further comprises: Extracting the static attributes and dynamic attributes of the sampling channels and control loops in the power distribution terminal that match the hardware interface, and constructing a hardware resource ontology; Analyzing the protocol frame structure and communication parameters related to the communication interface in the power distribution terminal, and generating a protocol state machine; Based on the hardware resource ontology and the protocol state machine, the physical quantity mapping relationship of the logic atomic unit is matched.

6. The method of claim 5, wherein the logic standardization process of the distributed power distribution terminal is characterized by, Before constructing the hardware resource ontology, it includes: Inputting standard signals to the hardware circuit matched with the hardware resource ontology and collecting the original values output by the hardware circuit, at the same time, issuing standard instructions to the control loop and recording the actual action time of the control loop; Comparing and analyzing the original values with the standard values, and using the least squares method to fit to obtain the first calibration curve of the standard values; At the same time, the actual action time is compared and analyzed with the upper and lower limit setting trigger time, and the least squares fitting is used to obtain the double calibration curve of the setting trigger time; Adjusting the upper and lower limit setting trigger time based on the first calibration curve and the double calibration curve; wherein is a first calibration curve; a k , b k are the fitted slope, intercept of the first calibration curve; X is the standard signal; With the intermediate threshold Rmid as a boundary, the upper boundary curve R fac,low and the lower boundary curve R fac,high are fitted: R fac,low = b low,m R ref + c low,m ; R fac,high = b high,m R ref + c lhigh,m ; Wherein, b low,m , c low,m are the fitting slope and intercept of the fitted upper boundary curve; b high,m , c lhigh,m are the fitting slope and intercept of the fitted lower boundary curve; R ref is the theoretical time of the standard trigger instruction; R fac is the actual action time of the control loop; Constructing a target optimization function J to optimize the upper and lower limit trigger time of the control loop: J = 0.6 | R fac - R ref | +0.3 | ΔV th | +0.1 N a ; R low,min ≤R low +ΔR low ≤R low,max ,R high,min ≤R high +ΔR high ≤R high,max ; wherein R low,min , R low,max , R high,min , R high,max are two time safety boundaries based on a lower trigger time, two time safety boundaries based on an upper trigger time; ΔV th is a trigger threshold variation; N a is a trigger time adjustment number; R low , R high are an original lower trigger time, an original upper trigger time, respectively; ΔR low , ΔR high are a lower boundary trigger time adjustment, an upper boundary trigger time adjustment; converting the raw value Yk to a normalized physical quantity based on the first calibration curve wherein aT is a temperature compensation term; update trigger threshold Where f is the threshold-time mapping function; Based on the standardized physical quantity and the updated trigger threshold, the physical quantity in the hardware resource ontology is updated.

7. The method of claim 1, wherein the logic standardization process of the distributed power distribution terminal is characterized by, Step 4 includes: Collecting the physical state, logical attributes and environmental information of the power distribution terminal to construct a 12-dimensional state vector; Identifying the change field of the 12-dimensional state vector through the hash difference algorithm; Based on the logic interaction rule, the change vector of each change field is constructed, and the abnormal attribute set of the change vector is obtained; Determine the coverage probability of each physical quantity in the physical quantity mapping relationship to each abnormal attribute in the abnormal attribute set, and construct a logic execution dependency graph; Control the collaborative work of distributed power distribution terminals based on the execution dependency graph.

8. The method of claim 7, wherein the logic standardization process of the distributed power distribution terminal is characterized by, Constructing a logic execution dependency graph includes: Performing time feature extraction and spatial feature extraction on each abnormal attribute in the abnormal attribute set to obtain a combined feature vector; Extracting the range, accuracy and hardware channel of the physical quantity to construct a static feature vector, and simultaneously collecting the environmental temperature, load rate and electromagnetic interference in real time to generate a dynamic feature vector; Mining historical association data of physical quantities and abnormal attributes, and extracting strong association rules using association rule mining to generate a historical association feature vector; Based on the multi-layer perception mechanism, the static feature vector, dynamic feature vector and historical association feature vector are fused to output a 32-dimensional influence factor vector F; Based on the Ft of the current physical quantity and the abnormal feature At of the combined abnormal vector, the coverage probability is inferred. Based on the coverage probability and the logical dependency strength between the logical atomic units, a logical execution dependency graph is constructed. Based on the coverage probability and the logical dependency strength between the logical atomic units, a logical execution dependency graph is constructed.

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