Time schedule controller, display equipment, adjustment method and device of display equipment and storage medium

Abstract

The invention discloses a time schedule controller, a display device, an adjusting method and device of the display device and a storage medium, and belongs to the technical field of display. The time schedule controller comprises a built-in image generation module and a data selection module. The data selection module is used for stopping sending a first video signal to the display panel when the level of the first frame synchronization signal jumps from a first level to a second level, and sending a second video signal to the display panel when the level of the second frame synchronization signal jumps from a third level to a fourth level, and the display panel performs shutdown compensation based on the second video signal. Thus, the time schedule controller can start signal switching at the ending moment of the frame of video signal of the first video signal output by the main board, and complete signal switching at the starting moment of the frame of video signal of the second video signal generated by the time schedule controller.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a timing controller, display device, adjustment method and apparatus thereof, and storage medium. Background Technology

[0002] Organic light-emitting diode (OLED) display panels have good color saturation, contrast and response speed.

[0003] A timing controller is used in a display device. The display device includes a display panel, a timing controller, and a motherboard. The timing controller is used to receive a first video signal sent by the motherboard, decode the first video signal, and send it to the display panel to make the display panel display an image, or to perform power-off compensation based on the first video signal. Power-off compensation refers to detecting and compensating the threshold voltage of the driving transistor on the display panel.

[0004] However, due to the low stability of the first video signal, the compensation effect of the display panel is poor. Summary of the Invention

[0005] This application provides a timing controller, a display device, an adjustment method and apparatus thereof, and a storage medium. The technical solution is as follows:

[0006] According to one aspect of this application, a timing controller is provided for a display device, the display device including a display panel and a motherboard, the timing controller being electrically connected to the display panel and the motherboard respectively, the timing controller including a built-in image generation module and a data selection module, the motherboard being used to send a first video signal to the data selection module, and to send a power-off compensation signal to the built-in image generation module and the data selection module;

[0007] The built-in image generation module is electrically connected to the data selection module. The built-in image generation module is used to generate a second video signal after receiving the power-off compensation signal and send the second video signal to the data selection module. The second video signal includes a second frame synchronization signal.

[0008] The data selection module is electrically connected to the display panel. After receiving the power-off compensation signal, the data selection module is used to send the first video signal to the display panel. The first video signal includes a first frame synchronization signal so that the display panel displays the image based on the first video signal.

[0009] The data selection module is further configured to stop sending the first video signal to the display panel when the level of the first frame synchronization signal changes from the first level to the second level, and to send the second video signal to the display panel when the level of the second frame synchronization signal changes from the third level to the fourth level, so that the display panel performs shutdown compensation based on the second video signal.

[0010] Optionally, the first video signal further includes a first data enable signal, the first data enable signal including alternating blanking regions and active regions, and the display panel includes driving transistors;

[0011] The timing controller further includes a compensation conversion module, which is electrically connected to the data selection module. The compensation conversion module has a real-time detection mode, and in the real-time detection mode, the compensation conversion module is used to send a real-time detection signal to the display panel. The real-time detection signal is used to instruct the display panel to detect the mobility of the driving transistor.

[0012] The data selection module is further configured to detect whether the first data enable signal in the first video signal is in the valid area when transmitting the first video signal, and send a data valid signal to the compensation conversion module when the first data enable signal is in the valid area.

[0013] The compensation conversion module is used to turn off the real-time detection mode based on the valid data signal, so as to stop sending the real-time detection signal to the display panel.

[0014] Optionally, the built-in image generation module is used to immediately generate the second video signal upon receiving the power-off compensation signal;

[0015] The time when the level of the first frame synchronization signal changes from the first level to the second level has a first duration between the time when the level of the second frame synchronization signal changes from the third level to the fourth level.

[0016] Optionally, the data selection module is further configured to send an enable signal to the built-in image generation module when the level of the first frame synchronization signal changes from the first level to the second level;

[0017] The built-in image generation module is used to immediately generate the second video signal upon receiving the activation signal;

[0018] The moment when the level of the first frame synchronization signal changes from the first level to the second level coincides with the moment when the level of the second frame synchronization signal changes from the third level to the fourth level.

[0019] Optionally, the data selection module includes a comparison module and a gating module, wherein the comparison module is electrically connected to the motherboard and the gating module respectively;

[0020] The comparison module is used to generate a first indication signal and output the first indication signal to the gating module when it detects that the level of the first frame synchronization signal of the first video signal output by the motherboard reaches the second level.

[0021] The gating module is used to stop sending the first video signal to the display panel based on the first indication signal.

[0022] Optionally, the data selection module includes a comparison module and a gating module, wherein the comparison module is electrically connected to the built-in image generation module and the gating module, respectively;

[0023] The comparison module is used to generate a second indication signal and output the second indication signal to the gating module when it detects that the level of the second frame synchronization signal of the second video signal output by the built-in image generation module reaches the fourth level.

[0024] The gating module is used to send the second video signal to the display panel based on the second indication signal.

[0025] Optionally, the display device further includes a memory electrically connected to the timing controller. The memory is used to output a compensation completion signal, which is a signal generated by the memory when it receives a first detection value sent by the display panel. The first detection value is a first detection value obtained by the display panel during the power-off compensation process.

[0026] The data selection module is also used to send the second video signal to the display panel after receiving the compensation completion signal;

[0027] The data selection module is further configured to stop sending the second video signal to the display panel when the level of the second frame synchronization signal changes from the third level to the fourth level, and to send the first video signal to the display panel when the level of the first frame synchronization signal changes from the first level to the second level.

[0028] Optionally, the first video signal further includes a first data enable signal, the first data enable signal including alternating blanking regions and active regions, and the display panel includes driving transistors;

[0029] The timing controller further includes a compensation conversion module, which is electrically connected to the data selection module. The compensation conversion module has a real-time detection mode, and in the real-time detection mode, the compensation conversion module is used to send a real-time detection signal to the display panel. The real-time detection signal is used to instruct the display panel to detect the mobility of the driving transistor.

[0030] The data selection module is further configured to detect whether the first data enable signal in the first video signal is in the valid area when transmitting the first video signal, and send a data valid signal to the compensation conversion module when the first data enable signal is in the valid area.

[0031] The compensation conversion module is used to enable the real-time detection mode based on the valid data signal, so as to send the real-time detection signal to the display panel.

[0032] Optionally, the second video signal includes a first black screen signal and a third video signal;

[0033] The data selection module is further configured to send a first black screen signal to the display panel when the level of the second frame synchronization signal changes from the third level to the fourth level, wherein the duration of the first black screen signal is a second duration, so that the display panel displays a black screen of the second duration;

[0034] The data selection module is also used to send the third video signal to the display panel after sending the first black screen signal to the display panel, so that the display panel performs shutdown compensation based on the third video signal.

[0035] Optionally, the second video signal may further include a second black screen signal;

[0036] The data selection module is further configured to send a second black screen signal to the display panel when the compensation completion signal is received, wherein the duration of the second black screen signal is a second duration, so that the display panel displays a black screen of the second duration.

[0037] Optionally, the first video signal may further include a third black screen signal;

[0038] The data selection module is also used to send the third black screen signal to the display panel when the power-off compensation signal is received. The duration of the third black screen signal is the second duration, so that the display panel displays a black screen of the second duration.

[0039] Optionally, the second duration is the display duration of N frames, where N is an integer greater than or equal to 1.

[0040] According to another aspect of this application, a method for adjusting a display device is provided, applied in the aforementioned timing controller, the method comprising:

[0041] The system receives the first video signal and the power-off compensation signal sent by the motherboard, wherein the first video signal includes a first frame synchronization signal;

[0042] Based on the power-off compensation signal, the first video signal is sent to the display panel so that the display panel displays the image based on the first video signal and generates a second video signal, the second video signal including a second frame synchronization signal;

[0043] When the level of the first frame synchronization signal changes from the first level to the second level, the transmission of the first video signal to the display panel is stopped.

[0044] When the level of the second frame synchronization signal changes from the third level to the fourth level, the second video signal is sent to the display panel so that the display panel performs shutdown compensation based on the second video signal.

[0045] Optionally, the first video signal further includes a first data enable signal, which includes alternating blanking regions and active regions; the display panel includes a driving transistor; and the compensation conversion module has a real-time detection mode.

[0046] Before stopping the transmission of the first video signal to the display panel, the method further includes:

[0047] A real-time detection signal is sent to the display panel, the real-time detection signal being used to instruct the display panel to detect the mobility of the driving transistor;

[0048] Detect whether the first data enable signal in the first video signal is in the valid region;

[0049] In response to the first data enable signal being in the effective area, the real-time detection mode is turned off to stop sending the real-time detection signal to the display panel.

[0050] Optionally, based on the power-off compensation signal, a second video signal is generated, including:

[0051] Upon receiving the power-off compensation signal, the second video signal is immediately generated;

[0052] The time when the level of the first frame synchronization signal changes from the first level to the second level has a first duration between the time when the level of the second frame synchronization signal changes from the third level to the fourth level.

[0053] Optionally, based on the power-off compensation signal, a second video signal is generated, including:

[0054] The second video signal is generated immediately when the level of the first frame synchronization signal changes from the first level to the second level;

[0055] The moment when the level of the first frame synchronization signal changes from the first level to the second level coincides with the moment when the level of the second frame synchronization signal changes from the third level to the fourth level.

[0056] According to another aspect of this application, a display device is provided, including a motherboard, a display panel, and a timing controller, wherein the timing controller is electrically connected to the display panel and the motherboard respectively, and the timing controller is the timing controller described above.

[0057] According to another aspect of this application, an adjustment device for a display device is provided. The adjustment device for the display panel includes a processor and a memory. The memory stores at least one instruction, at least one program, code set, or instruction set. The at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by the processor to implement the adjustment method for the display device as described above.

[0058] According to another aspect of this application, a computer storage medium is provided, wherein at least one instruction, at least one program, code set, or instruction set is stored in the computer storage medium, wherein the at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by a processor to implement the above-described adjustment method for the display device.

[0059] According to another aspect of this application, a computer program product or computer program is provided, comprising computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the aforementioned adjustment method for the display device.

[0060] The beneficial effects of the technical solutions provided in this application include at least the following:

[0061] A timing controller including a built-in image generation module and a data selection module is provided. The data selection module stops sending a first video signal to the display panel when the level of the first frame synchronization signal transitions from a first level to a second level, and starts sending a second video signal to the display panel when the level of the second frame synchronization signal transitions from a third level to a fourth level, enabling the display panel to perform shutdown compensation based on the second video signal. Thus, the timing controller can begin signal switching at the end of a frame of the first video signal output from the motherboard and complete signal switching at the beginning of a frame of the second video signal generated by the timing controller. During signal switching, any frame of video signal sent to the display panel by the timing controller is a complete frame, avoiding display panel malfunctions caused by incomplete frame inputs due to signal switching. Furthermore, the video source of the display panel can be switched to the highly stable second video signal generated by the built-in image generation module, ensuring normal shutdown compensation. This solves the problem of poor compensation effect of the display panel in related technologies and improves the compensation effect of the display panel. Attached Figure Description

[0062] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0063] Figure 1 This is a schematic diagram of the structure of a display device provided in an embodiment of this application;

[0064] Figure 2 This is a signal switching timing diagram of a timing controller provided in an embodiment of this application;

[0065] Figure 3 This is a schematic diagram of another display device provided in an embodiment of this application;

[0066] Figure 4 This is a schematic diagram of a pixel circuit provided in an embodiment of this application;

[0067] Figure 5 This is a schematic diagram of a threshold voltage detection provided in an embodiment of this application;

[0068] Figure 6 It is a signal switching flowchart;

[0069] Figure 7 It is a signal switching timing diagram;

[0070] Figure 8 This is another signal switching timing diagram;

[0071] Figure 9 This is a signal switching timing diagram of another timing controller provided in this application;

[0072] Figure 10 This is a signal switching timing diagram of another timing controller provided in an embodiment of this application;

[0073] Figure 11 This is a schematic diagram of a detection compensation circuit provided in an embodiment of this application;

[0074] Figure 12 This is a signal switching flowchart provided in an embodiment of this application;

[0075] Figure 13 This is another signal switching flowchart provided in an embodiment of this application;

[0076] Figure 14 This is another signal switching flowchart provided in an embodiment of this application;

[0077] Figure 15 This is a flowchart of a display device adjustment method provided in an embodiment of this application;

[0078] Figure 16 This is a flowchart of another method for adjusting a display device provided in an embodiment of this application.

[0079] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0080] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0081] Please refer to Figure 1 The display device may include a display panel 11, a motherboard 12, and a timing controller 13 (TCON). The timing controller 13 is electrically connected to the display panel 11 and the motherboard 12. The timing controller 13 may include a built-in image generation module 131 and a data selection module 132. The motherboard 12 may be used to send a first video signal to the data selection module 132 and to send a power-off compensation signal to the built-in image generation module 131 and the data selection module 132.

[0082] The built-in image generation module 131 can be electrically connected to the data selection module 132. After receiving the power-off compensation signal, the built-in image generation module 131 generates a second video signal and sends it to the data selection module 132. The second video signal includes a second frame synchronization signal (Vertical Sync 2; abbreviated as VS2). The stability of the second video signal is stronger than that of the first video signal, meaning the second video signal is more stable than the first video signal, resulting in better power-off compensation for the display panel 11.

[0083] The data selection module 132 can be electrically connected to the display panel 11. The data selection module 132 can receive the first video signal and the power-off compensation signal output by the motherboard 12. After receiving the power-off compensation signal, the data selection module 132 is used to send the first video signal to the display panel 11. The first video signal includes the first frame synchronization signal (Vertical Sync 1; abbreviation: VS1) so that the display panel 11 displays the screen based on the first video signal.

[0084] Please refer to Figure 2 The data selection module 132 is also used to stop sending the first video signal to the display panel 11 when the level of the first frame synchronization signal VS1 changes from the first level to the second level (t2), and to send the second video signal to the display panel 11 when the level of the second frame synchronization signal VS2 changes from the third level to the fourth level (t3), so that the display panel 11 performs shutdown compensation based on the second video signal. Figure 2 The actual VS signal in the video signal actually sent by the timing controller 13 to the display panel 11 represents the frame synchronization signal.

[0085] The first video signal comprises multiple frames of video signal. When the level of the first frame synchronization signal VS1 changes from the first level to the second level, it can indicate the end of one frame of the first video signal or the beginning of another frame. In other words, the level change can be seen as a dividing point between two frames of the first video signal. Similarly, the second video signal comprises multiple frames of image signal. When the level of the second frame synchronization signal VS2 changes from the third level to the fourth level, it can indicate the end of one frame of the second video signal or the beginning of another frame. In other words, the level change can be seen as a dividing point between two frames of the second video signal.

[0086] If the timing controller 13 directly switches the signal that is being transmitted during the switching process from the first video signal to the second video signal, it may cause a frame of the first video signal to not be completely transmitted at the time of signal switching. That is, only a part of the signal of the first video signal is sent to the display panel 11. And if the transmission starts from the middle of a frame of the second video signal, that is, only a part of the signal of the second video signal is sent to the display panel 11, the two parts of the signal will be combined into a single frame of video signal. As a result, the amount of data of a frame of video signal received by the display panel 11 during signal switching may be more or less than the amount of data of a frame of video signal in the second video signal. This will cause the display panel 11 to receive abnormal video signals, making the operation of the display panel 11 disordered and affecting the compensation effect of the display panel 11 during power-off compensation.

[0087] Therefore, in this embodiment, after receiving the power-off compensation command, the timing controller 13 can start signal switching at the end of a frame of the first video signal output by the motherboard 12, and complete signal switching at the beginning of a frame of the second video signal generated by the timing controller 13. During the signal switching process, any frame of video signal sent by the timing controller 13 to the display panel 11 is a complete frame of video signal, which can avoid the problem of abnormal operation of the display panel 11 caused by an incomplete frame of video signal input to the display panel 11 due to signal switching. Furthermore, switching the video source of the display panel 11 to the second video signal with strong stability generated by the built-in image generation module 131 can ensure that the power-off compensation can be performed normally.

[0088] In summary, this application provides a timing controller including a built-in image generation module and a data selection module. The data selection module stops sending a first video signal to the display panel when the level of the first frame synchronization signal changes from a first level to a second level, and starts sending a second video signal to the display panel when the level of the second frame synchronization signal changes from a third level to a fourth level, enabling the display panel to perform shutdown compensation based on the second video signal. Thus, the timing controller can begin signal switching at the end of one frame of the first video signal output from the motherboard and complete signal switching at the beginning of one frame of the second video signal generated by the timing controller. During signal switching, any frame of video signal sent by the timing controller to the display panel is a complete frame, avoiding display panel malfunctions caused by incomplete frame input due to signal switching. Furthermore, the video source of the display panel can be switched to the highly stable second video signal generated by the built-in image generation module, ensuring normal shutdown compensation. This solves the problem of poor compensation effect of the display panel in related technologies and improves the compensation effect of the display panel.

[0089] It should be noted that the first level and the second level in the embodiments of this application can be two levels with different amplitudes, and the third level and the fourth level can be two levels with different amplitudes. The embodiments of this application do not limit the specific amplitudes of the first level, the second level, the third level and the fourth level.

[0090] Understandably, before receiving the power-off compensation signal, the data selection module 132 can receive the first video signal output by the motherboard 12 and transmit the first video signal to the display panel 11 so that the display panel 11 displays the image based on the first video signal. After receiving the power-off compensation signal, the data selection module 132 will not immediately switch signals. The data selection module 132 will continue to receive the first video signal output by the motherboard 12 and send the received first video signal to the display panel 11 until the level of the first frame synchronization signal VS1 in the first video signal changes from the first level to the second level, at which point it will stop sending the first video signal to the display panel 11.

[0091] The display panel 11 may include a driving transistor. In this embodiment, the power-off compensation is to detect the threshold voltage of the driving transistor by the display panel 11 to obtain a first detection value. The timing controller 13 can compensate the driving transistor according to the first detection value, which may be a voltage value.

[0092] It should be noted that the embodiments of this application do not limit the compensation method of the display panel 11 for power-off compensation based on the second video signal. Different structures of pixel circuits and detection compensation circuits can be set, and corresponding power-off compensation timing can be designed according to the structure of the pixel driving circuit and detection compensation circuit. The timing controller 13 drives the pixel circuit and detection compensation circuit to work according to the power-off compensation timing to obtain the corresponding first detection value, and then calculates the compensation gain value of the transistor to be driven based on the obtained first detection value.

[0093] In one exemplary implementation, such as Figure 2 As shown, the first video signal may include a first synchronization signal and a first data signal DATA1 (DA1). The first synchronization signal may include a first frame synchronization signal VS1, a first line synchronization signal (HS1), and a first data enable signal (DE1). In the accompanying drawings of this application embodiment, DA represents the DATA signal.

[0094] The second video signal may include a second synchronization signal and a second data signal DATA2 (DA2). The second synchronization signal may include a second frame synchronization signal VS2, a second line synchronization signal HS2, and a second data enable signal DE2. Since the built-in image generation module 131 uses the crystal oscillator on the timing controller 13 as the clock to generate the second video signal, the second video signal is very stable, and the signal width, the front shoulder value, and the back shoulder value can all be set according to the actual needs of power-off compensation.

[0095] Figure 2 The actual HS signal in the video signal actually sent by the timing controller 13 to the display panel 11 represents the line synchronization signal, and the actual DE signal represents the data enable signal in the video signal actually sent by the timing controller 13 to the display panel 11.

[0096] Please refer to Figure 3The display panel 11 may include a data signal driver 111, a scan signal driver 112, multiple data signal lines, multiple scan signal lines, multiple detection signal lines, and a pixel array (not shown in the figure). A timing controller 13 may be electrically connected to both the data signal driver 111 and the scan signal driver 112. The data signal driver 111 is electrically connected to multiple data signal lines and multiple detection signal lines, and the scan signal driver 112 is electrically connected to multiple scan signal lines. The pixel array may include multiple sub-pixels, and at least one sub-pixel may include a pixel circuit and a light-emitting device electrically connected to the pixel circuit. The pixel circuit may include at least one scan signal line, at least one data signal line, at least one detection signal line, and a light-emitting device. In an exemplary embodiment, the timing controller 13 may provide grayscale values ​​and control signals of specifications suitable for the data signal driver 111 to the data signal driver 111, and may provide clock signals, scan start signals, etc., of specifications suitable for the scan signal driver 112 to the scan signal driver 112.

[0097] The data signal driver 111 can generate a data voltage based on the received grayscale value and a control signal, and send the data voltage to the data signal line. For example, the data signal driver 111 can sample the grayscale value using a clock signal and apply the data voltage corresponding to the grayscale value to the data signal line on a pixel-by-pixel basis.

[0098] The scan signal driver 112 can generate a scan signal based on a received clock signal, a scan start signal, etc., and send the scan signal to the scan signal line. For example, the scan signal driver 112 can sequentially provide scan signals to the scan signal line. For example, the scan signal driver 112 can be configured as a shift register and can generate scan signals by sequentially transmitting the scan start signal to the next stage circuit under the control of a clock signal.

[0099] The pixel circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and output a corresponding current to the light-emitting device. The light-emitting device in each sub-pixel is connected to the pixel circuit of its respective sub-pixel, and the light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel circuit of its respective sub-pixel.

[0100] In one exemplary embodiment, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Please refer to [reference needed]. Figure 4The pixel circuit has a 3T1C structure, which can include 3 transistors (first transistor T1, second transistor T2 and third transistor T3), 1 storage capacitor C and 6 signal lines (data signal line D, first scan signal line G1, second scan signal line G2, detection signal line S, first power supply line VDD and second power supply line VSS).

[0101] In one exemplary embodiment, the first transistor T1 is a switching transistor, the second transistor T2 is a driving transistor, and the third transistor T3 is a compensation transistor. The first terminal of the storage capacitor C is electrically connected to the control terminal of the second transistor T2, and the second terminal of the storage capacitor C is electrically connected to the second terminal of the second transistor T2. The storage capacitor C is used to store the potential of the control terminal of the second transistor T2. The control terminal of the first transistor T1 is electrically connected to the first scan signal line G1, the first terminal of the first transistor T1 is electrically connected to the data signal line D, and the second terminal of the first transistor T1 is electrically connected to the control terminal of the second transistor T2. The first transistor T1, under the control of the first scan signal line G1, receives the data signal transmitted through the data signal line D, causing the control terminal of the second transistor T2 to receive the data signal. The control terminal of the second transistor T2 is electrically connected to the second terminal of the first transistor T1, the first terminal of the second transistor T2 is electrically connected to the first power supply line VDD, and the second terminal of the second transistor T2 is electrically connected to the first terminal (anode) of the light-emitting device. The second transistor T2, under the control of the data signal received at its control terminal, generates a corresponding current at its second terminal. The control electrode of the third transistor T3 is electrically connected to the second scan signal line G2, the first electrode of the third transistor T3 is electrically connected to the detection signal line S, and the second electrode of the third transistor T3 is electrically connected to the second electrode of the second transistor T2. The third transistor T3 is used to extract the threshold voltage Vth and mobility K of the second transistor T2 in response to the compensation timing, so as to compensate for the threshold voltage Vth. The second electrode (cathode) of the light-emitting device is connected to the second power supply line VSS.

[0102] In one exemplary embodiment, the light-emitting device may be an OLED, including a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together. The first electrode of the OLED is electrically connected to the second electrode of the second transistor T2, and the second electrode of the OLED is electrically connected to the second power line VSS. The OLED is used to emit light of corresponding brightness in response to the current of the second electrode of the second transistor T2.

[0103] In one exemplary embodiment, the first power line VDD continuously provides a high-level signal, while the second power line VSS provides a low-level signal. The first transistor T1 to the third transistor T3 can be either P-type or N-type transistors. Using the same type of transistor in the pixel driving circuit simplifies the manufacturing process, reduces the manufacturing difficulty of the display panel 11, and improves product yield.

[0104] During the use of the OLED display panel 11, the driving transistors experience characteristic drift due to stress from current, temperature, and illumination. This change manifests on the display panel 11 as image retention. Therefore, transistor compensation technology is needed to eliminate these image retentions. The driving transistors require compensation for two characteristic parameters: threshold voltage Vth and mobility K. The detection time for mobility K is relatively short, approximately several hundred microseconds. Therefore, mobility K detection can be performed either in the power-off state or during the real-time blank time. Each frame of the display device is divided into active time and blank time. During the active time, the display device uses pixel circuits to output and display normal data. During the blank time, real-time detection and compensation (RealTime Sense) is performed on the display panel 11.

[0105] Threshold voltage Vth detection requires a relatively long charging time; therefore, it is typically performed with the device powered off and the screen black. For an example, please refer to... Figure 4 and Figure 5 , Figure 5 The horizontal axis represents time (t / ms), and the vertical axis represents voltage (V). The threshold voltage Vth can be detected by charging the detection signal line with a fixed data voltage until the driving transistor T2 is turned off. The difference between the data voltage (Vdata; abbreviation: Vda) and the detection voltage (Vsense; abbreviation: Vse) on the detection signal line at this point is the Vth value of the driving transistor T2. This process can last approximately 30ms, therefore it cannot be performed while the display panel 11 is displaying normally. It is typically performed when the display device is powered off, i.e., when the display device is not displaying any image. It is understood that the power-off state in this embodiment can include a state where the display panel 11 does not display a normal image and displays a black screen; that is, in the power-off state, the display device may not be completely powered off, but simply not displaying normally.

[0106] When a display device performs power-off compensation, it needs to use three flag signals—frame synchronization signal (VS), line synchronization signal (HS), and data enable signal (DE)—to perform line-by-line charging detection. During power-off detection, if the video signal from the motherboard 12 (SOC board) is unstable, the corresponding flag signals will also exhibit fluctuations, signal loss, and periodic changes. These instabilities can cause errors in the source and gate control signals during power-off compensation, leading to malfunctions in the power-off compensation function. For example, this could result in abnormal display, or the detection of incorrect voltage values ​​leading to incorrect compensation data. Incorrect compensation data not only fails to achieve the desired compensation effect but may even worsen the display quality.

[0107] Please refer to Figure 6 A timing controller in the related technology has a display mode (SOC mode) and a built-in image mode. The timing controller outputs a first video signal in SOC mode and a second video signal in built-in image mode. One signal switching method involves directly switching the first video signal output by the motherboard to the second video signal generated by the local timing controller 13 before performing power-off compensation, so that the display panel can perform power-off compensation based on the second video signal.

[0108] However, in the signal switching methods described above, there is a high probability that the frequency, period, and length of the video marker signal (especially the DE signal) will change during the signal switching process. Please refer to [reference needed]. Figure 7 During signal switching, the following two situations may occur: Figure 7 As shown in the first case, the switching signal causes the DE and VS signals to shorten, such as Figure 7 As shown in the second scenario, the switching signal causes the DE and VS signals to become longer. In other words, the data signal driver can include multiple source ICs. When DE and VS become shorter, the scan time of one row of pixels also becomes shorter. This results in a decrease in the amount of data transmitted by the timing controller to at least one source IC. Since the source IC must receive a specific amount of data each time to output normally, this causes the source IC to malfunction. Similarly, when DE and HS become longer, the scan time of one row of pixels also becomes longer. This results in a increase in the amount of data transmitted by the timing controller to at least one source IC, also causing the source IC to malfunction.

[0109] Therefore, in this embodiment, when the level of the first frame synchronization signal VS1 changes from the first level to the second level (t2), the transmission of the first video signal to the display panel 11 is stopped, and when the level of the second frame synchronization signal VS2 changes from the third level to the fourth level (t3), the second video signal is transmitted to the display panel 11, so that the display panel 11 performs power-off compensation based on the second video signal. That is, after receiving the power-off compensation command, the timing controller 13 can start signal switching at the end of one frame of the first video signal output by the motherboard 12, and complete signal switching at the beginning of one frame of the second video signal generated by the timing controller 13. During the signal switching process, any frame of video signal sent by the timing controller 13 to the display panel 11 is a complete frame of video signal, which can avoid the problem of abnormal operation of the display panel 11 caused by an incomplete frame of video signal input to the display panel 11 due to signal switching.

[0110] Please refer to Figure 8 , Figure 8 This illustration demonstrates a situation where signal switching during real-time detection and compensation interrupts the real-time detection of the mobility of the driving transistor. Specifically, if the display panel is performing real-time mobility detection during signal switching, the detection process will be abnormally interrupted. The display panel may also include an analog-to-digital converter (ADC) electrically connected to the detection signal line (S). The ADC converts the voltage on the detection transistor acquired by the detection signal line (S) into digital data (the detected value) and sends this value to the timing controller. The ADC can be integrated into the source IC. Figure 8 In this circuit, the Sample (Sa) signal is a sampling signal sent by the timing controller to the analog-to-digital converter (ADC) to instruct the ADC to begin digital-to-analog conversion. The ADC-TX signal is a transmit signal output by the timing controller to the ADC to instruct the ADC to send the detected value to the memory after conversion. Due to signal switching, the timing controller only sent the Sample signal to the ADC and not the ADC-TX signal. This caused the digital data generated by the ADC in the Source IC after voltage conversion to fail to be sent to the memory, resulting in Source IC malfunction. Furthermore, this may also affect the real-time detection results, thereby impacting the real-time detection compensation effect of the display panel.

[0111] Please refer to Figure 2In an optional embodiment, the first video signal may further include a first data enable signal DE1, which includes alternating blanking regions and active regions. The display panel 11 includes driving transistors. The blanking regions of the first data enable signal DE1 correspond to the blank time of the first video signal, and the active regions of the first data enable signal DE1 correspond to the active display time of the first video signal.

[0112] The timing controller 13 also includes a compensation conversion module 133, which is electrically connected to the data selection module 132. The compensation conversion module 133 has a real-time detection mode. In this mode, it sends a real-time detection signal to the display panel 11, instructing the display panel 11 to detect the mobility of the driving transistors. The data selection module 132 is also used to detect whether a first data enable signal DE1 in the first video signal is in the valid region when transmitting the first video signal (t1), and to send a data valid signal to the compensation conversion module 133 when DE1 is in the valid region (t1). Based on the data valid signal, the compensation conversion module 133 disables the real-time detection mode to stop sending the real-time detection signal to the display panel 11.

[0113] Since the real-time detection and compensation of the display panel 11 is performed during the blank time of a frame, in this embodiment, the first video signal being transmitted can be detected before the data selection circuit stops sending the first video signal to the display panel 11. When the first data enable signal DE1 is in the valid region (t1), the compensation conversion module 133 is instructed to close the real-time detection mode. This allows the compensation conversion module 133 to stop sending the real-time detection signal to the display panel 11 when the first data enable signal DE1 is in the blanking region, i.e., to stop the real-time detection and compensation of the display panel 11. In other words, since the compensation conversion module 133 does not send a real-time detection signal to the display panel 11 during the valid display time of the first video signal, and the display panel 11 is not currently performing real-time detection and compensation, instructing the compensation conversion module 133 to close the real-time detection at t1 allows the display panel 11 to stop the real-time detection and compensation in advance. This avoids interruption of the real-time detection and compensation of the display panel 11, thereby preventing source IC malfunctions.

[0114] In one alternative implementation, please refer to Figure 2The built-in image generation module 131 can be used to immediately generate a second video signal upon receiving a power-off compensation signal. In this case, the rising edge of the second video signal is not synchronized with the rising edge of the first video signal, and for a period of time after the built-in image generation module 131 immediately generates the second video signal, the data selection module 132 continues to output the first video signal and does not output the second video signal.

[0115] There is a first duration between the moment (t2) when the level of the first frame synchronization signal VS1 changes from the first level to the second level and the moment (t3) when the level of the second frame synchronization signal VS2 changes from the third level to the fourth level. This first duration is less than the target duration, which is the sum of the duration of one frame of the first video signal and the duration of one frame of the second video signal.

[0116] For example, Figure 2 In stage 1 between t1 and t2, the timing controller 13 sends a first video signal to the display panel 11, and no real-time detection action is performed during this stage; in stage 2 between t2 and t3, the timing controller 13 does not send any video signal to the display panel 11; in stage 3 after t3, the timing controller 13 sends a second video signal to the display panel 11, and power-off compensation is performed during this stage.

[0117] In one alternative implementation, please refer to Figure 9 , Figure 9 The parallel signals are not shown to simplify the switching timing diagram. The data selection module 132 can also be used to send an enable signal to the built-in image generation module 131 when the level of the first frame synchronization signal VS1 changes from the first level to the second level. The built-in image generation module 131 is used to immediately generate a second video signal upon receiving the enable signal.

[0118] In this scenario, the first rising edge of the second video signal can be synchronized with the rising edge of the first video signal. In other words, the built-in image generation module 131 does not immediately generate the second video signal after receiving the power-off compensation signal. It only begins generating the second video signal after receiving the enable signal from the data selection module 132. At the moment the built-in image generation module 131 immediately generates the second video signal, the data selection circuit also stops outputting the first video signal and immediately outputs the second video signal.

[0119] The moment (t2) when the level of the first frame synchronization signal VS1 changes from the first level to the second level coincides with the moment (t3) when the level of the second frame synchronization signal VS2 changes from the third level to the fourth level.

[0120] Please refer to Figure 3 In an optional embodiment, the data selection module 132 may include a comparison module 1321 and a gating module 1322. The comparison module 1321 is electrically connected to the motherboard 12 and the gating module 1322, respectively. The comparison module 1321 generates a first indication signal and outputs it to the gating module 1322 when it detects that the level of the first frame synchronization signal VS1 of the first video signal output by the motherboard 12 reaches a second level. The gating module 1322 stops sending the first video signal to the display panel 11 based on the first indication signal. The second level can be a level indicating that the first video signal is in the frame completion stage. For example, when the second level reaches 3V, the comparison circuit can send the first indication signal to the gating module 1322 so that the gating module 1322 can respond promptly to changes in the first video signal output by the motherboard 12.

[0121] Please refer to Figure 3 In an optional embodiment, the data selection module 132 may include a comparison module 1321 and a gating module 1322. The comparison module 1321 is electrically connected to the built-in image generation module 131 and the gating module 1322, respectively. The comparison module 1321 may generate a second indication signal and output it to the gating module 1322 when it detects that the level of the second frame synchronization signal VS2 of the second video signal output by the built-in image generation module 131 reaches a fourth level. The gating module 1322 may send the second video signal to the display panel 11 based on the second indication signal. The fourth level may be the level indicating that the second video signal is at the beginning of a frame. For example, when the fourth level reaches 3V, the comparison circuit may send the second indication signal to the gating module 1322 so that the gating module 1322 can respond promptly to changes in the second video signal output by the built-in image generation module 131.

[0122] Please refer to Figure 3 and Figure 10 In an optional embodiment, the display device may further include a memory 14, which is electrically connected to a timing controller 13. The memory is used to output a compensation completion signal, which is a signal generated by the memory 14 when it receives a first detection value sent by the display panel 11. The first detection value is the first detection value obtained by the display panel 11 during the power-off compensation process.

[0123] The data selection module 132 is also used to send a second video signal to the display panel 11 after receiving the compensation completion signal; the data selection module 132 is also used to stop sending the second video signal to the display panel 11 when the level of the second frame synchronization signal VS2 jumps from the third level to the fourth level (t4), and to send a first video signal to the display panel 11 when the level of the first frame synchronization signal VS1 jumps from the first level to the second level (t5).

[0124] The display panel 11 includes a detection compensation circuit 113. The memory 14 can be configured to store the detection results of the detection compensation circuit 113. The memory 14 may also include a lookup table for storing the correspondence between the detection results and the compensation gain values. After power-off compensation is completed, normal display can continue, meaning it can switch back to the motherboard 12 (SOC) display mode to display normal video images. The switching process from the second video signal to the first video signal is similar to the switching process from the first video signal to the second video signal. After receiving the compensation completion signal, the timing controller 13 can start signal switching at the end of a frame of the second video signal generated by the timing controller 13, and complete signal switching at the beginning of a frame of the first video signal output by the motherboard 12.

[0125] During signal switching, the timing controller 13 sends a complete frame of video signal to the display panel 11. This avoids the problem of abnormal operation of the display panel 11 caused by an incomplete frame of video signal input to the display panel 11 due to signal switching.

[0126] For example, Figure 10 During phase 4, between t4 and t5, the timing controller 13 does not send a video signal to the display panel 11; after t5, the timing controller 13 sends a first video signal to the display panel 11, and during phase 5, between t5 and t6, it does not perform real-time detection of the display panel, and after t6, it performs real-time detection of the display panel.

[0127] In some exemplary implementations, such as Figure 3 and Figure 11 As shown, the detection compensation circuit 113 can be integrated into the source IC. The detection compensation circuit 113 is connected to the detection signal line S and is used to obtain the amount of charge flowing through the driven element within a preset detection time, so that the memory 14 can calculate the compensation gain value of the driven transistor based on the obtained amount of charge.

[0128] In some exemplary implementations, such as Figure 11As shown, the detection compensation circuit 113 includes a current integrator, a sampling switch, and an analog-to-digital converter connected in sequence. One end of the current integrator is connected to the detection signal line S, and the other end of the current integrator is connected to the first path terminal of the sampling switch. The second path terminal of the sampling switch is connected to the first terminal of the analog-to-digital converter, and the control terminal of the sampling switch receives the sampling signal. The second terminal of the analog-to-digital converter is electrically connected to the timing controller 13 and the memory 14.

[0129] In an optional embodiment, the first video signal further includes a first data enable signal DE1 (DE1), the first data enable signal DE1 includes alternating blanking regions and active regions, and the display panel 11 includes driving transistors.

[0130] The timing controller 13 also includes a compensation conversion module 133, which is electrically connected to the data selection module 132. The compensation conversion module 133 has a real-time detection mode. In the real-time detection mode, the compensation conversion module 133 is used to send a real-time detection signal to the display panel 11. The real-time detection signal is used to instruct the display panel 11 to detect the mobility of the driving transistor. The data selection module 132 is also used to detect whether the first data enable signal DE1 in the first video signal is in the valid region when the first data enable signal DE1 is in the valid region (t6), and send a data valid signal to the compensation conversion module 133 when the first data enable signal DE1 is in the valid region. The compensation conversion module 133 is used to enable the real-time detection mode based on the data valid signal so that it can send the real-time detection signal to the display panel 11.

[0131] Since the real-time detection compensation of the display panel 11 is performed during the blank time of a frame, in this embodiment, after the data selection circuit sends the first video signal to the display panel 11 again, the first video signal being transmitted can be detected. When the first data enable signal DE1 is in the valid region (t6), the compensation conversion module 133 is instructed to start the real-time detection mode, so that a real-time detection signal can be sent to the display panel 11 when the first data enable signal DE1 is in the blanking region, thereby enabling the display panel 11 to start the real-time detection compensation. That is, since the compensation conversion module 133 does not send a real-time detection signal to the display panel 11 when the first video signal is in the valid display time, and the display panel 11 is not currently performing a real-time detection compensation, instructing the compensation conversion module 133 to start the real-time detection mode at t6 can avoid the interruption of the real-time detection compensation of the display panel 11, thereby avoiding the source IC disorder.

[0132] In an optional implementation, the second video signal includes a first black screen signal and a third video signal. The data selection module 132 is further configured to send the first black screen signal to the display panel 11 when the level of the second frame synchronization signal VS2 changes from a third level to a fourth level. The duration of the first black screen signal is a second duration, so that the display panel 11 displays a black screen of the second duration. The data selection module 132 is also configured to send the third video signal to the display panel 11 after sending the first black screen signal, so that the display panel 11 performs shutdown compensation based on the third video signal.

[0133] In some exemplary embodiments, the second duration can be two frames of display time or one frame of display time. For example, the second duration can be 35ms. During the process of displaying a black screen for the second duration, the data voltage in the display panel 11 can be 0.

[0134] The timing controller 13 may further include a processing output module 135, which may include an image processing and compensation module 1351, a source drive control module (also known as a Source IC control module) 1352, and a gate drive control module (also known as a Gate IC / GOA control module) 1353. The display panel 11 includes a data signal driver 111 and a scan signal driver 112. The image processing and compensation module 1351 can perform image processing and uniformity compensation on the first video signal or the second video signal, and output the processed and compensated first video signal or second video signal to the source drive control module 1352 and the gate drive control module 1353.

[0135] The source drive control module 1352 can be used to generate source control signals and data signals according to the first video signal or the second video signal, and output them to the data signal driver 111; the gate drive control module 1353 can be used to generate gate control signals according to the first video signal or the second video signal, and output them to the scan signal driver 112.

[0136] Thus, the data selection module 132 can first send a first black screen signal to the processing output module 135, and the processing output module 135 then sends the processed first black screen signal to the display panel 11. During this process, the processing output module 135 can capture the signal parameters of the second video signal, which may include the width of the VS signal, the width of the DE signal, the front shoulder of the frame, the back shoulder of the frame, the frame pulse width, and the line pulse width, etc. This avoids the occasional detection anomaly caused by the data signal driver 111 not receiving a normal drive signal.

[0137] Optionally, the second video signal also includes a second black screen signal; the data selection module 132 is further configured to send the second black screen signal to the compensation conversion module 133 upon receiving the compensation completion signal, the second black screen signal having a duration of a second duration, so that the display panel 11 displays a black screen of the second duration. This eliminates residual charge on the display panel 11, preventing display ghosting after signal switching.

[0138] Optionally, the first video signal also includes a third black screen signal; the data selection module 132 is further configured to send the third black screen signal to the display panel 11 upon receiving the power-off compensation signal. The duration of the third black screen signal is the second duration, so that the display panel 11 displays a black screen of the second duration. In this way, residual charge on the display panel 11 can be eliminated, avoiding the problem of display ghosting on the display panel 11 after signal switching.

[0139] Please refer to Figure 3 In some exemplary embodiments, the motherboard 12 may include a television motherboard or a video signal generator. The timing controller 13 may also include a data decoding module 134, which receives the first video signal output by the motherboard 12 and decodes it. For example, the first video signal output by the motherboard 12 is a VBO (V-by-One) signal, a digital interface standard developed for image transmission. The first video signal after decoding by the data decoding module 134 includes a first synchronization signal and a first data signal DATA1. The first synchronization signal includes a first frame synchronization signal VS1, a first line synchronization signal HS1, and a first data enable signal DE1.

[0140] The third black screen signal can be generated by the data decoding module 134 or the motherboard 12. For example, the motherboard 12 is also used to send a power-off compensation signal to the data decoding module 134, and the data decoding module 134 is used to output the third black screen signal after receiving the power-off compensation signal.

[0141] Optionally, the second duration is the display duration of N frames, where N is an integer greater than or equal to 1.

[0142] In one optional embodiment, the compensation conversion module 133 is electrically connected to both the source drive control module 1352 and the gate drive control module 1353. The display panel 11 includes a data signal driver 111 and a scan signal driver 112. The source drive control module 1352 is electrically connected to the data signal driver 111, and the gate drive control module 1353 is electrically connected to the scan signal driver 112. The compensation conversion module 133 is used to receive a valid data signal output by the data selection module 132, generate a first shutdown signal based on the valid data signal, and send the first shutdown signal to both the source drive control module 1352 and the gate drive control module 1353. The source drive control module 1352 is used to stop sending real-time sensing signals to the data signal driver 111 according to the first shutdown signal. The gate drive control module 1353 is used to stop sending real-time sensing signals to the scan signal driver 112 according to the first shutdown signal.

[0143] In one optional embodiment, the compensation conversion module 133 has a power-off detection mode. In this mode, the compensation conversion module 133 sends a power-off detection signal to the display panel 11, which instructs the display panel 11 to detect the threshold voltage of the driving transistor. The data selection module 132 is also used to send a parameter acquisition completion signal to the compensation conversion module 133 after sending the first black screen signal.

[0144] The compensation conversion module 133 is used to acquire the completion signal based on the parameters, enable the power-off detection mode, and send the power-off detection signal to the display panel 11.

[0145] In one optional implementation, during the power-off operation phase of the display device, the motherboard 12 can determine whether it is necessary to perform power-off detection on the characteristic parameters in the display panel 11; when it is necessary to perform power-off detection on the characteristic parameters in the display panel 11, the timing controller 13 is instructed to perform the following power-off operation: perform power-off detection on the characteristic parameters in the display panel 11, obtain the detection value, and store it in the memory 14.

[0146] During the operation of the display device or the power-on phase, the motherboard 12 can instruct the timing controller 13 to adjust the characteristic parameters in the display panel 11 according to the detection time specified by the user.

[0147] In one exemplary implementation, please refer to Figure 2 and Figure 12During normal display, the timing controller checks for a power-off compensation command. At this time, the timing controller operates in normal display mode. When a power-off compensation command is received, a black screen is displayed for 35ms (more than two frames) in normal display mode to eliminate residual charge on the display panel. Then, at time t1, a switching signal command is issued to disable real-time detection of the display panel. At time t2, the motherboard signal is turned off (i.e., the first video signal is stopped). At time t3, the TCON signal is turned on (i.e., the second video signal is started), and the black screen is maintained for 35ms. After this, power-off compensation is performed on the display panel. Once compensation is complete, the power-off operation is executed.

[0148] In one exemplary implementation, please refer to Figure 9 and Figure 13 During normal display, the timing controller checks for a power-off compensation command. At this time, the timing controller operates in normal display mode. When a power-off compensation command is received, a black screen is displayed for 35ms (greater than two frames) in normal display mode to eliminate residual charge on the display panel. Then, at time t1, a switching signal command is issued to disable real-time detection of the display panel. At time t2, the motherboard signal is turned off (i.e., the first video signal is stopped), and at time t2, video signal generation begins and the TCON signal is enabled. This video signal is the second video signal; enabling the TCON signal means starting to send the second video signal, maintaining a black screen for 35ms. After this, power-off compensation is performed on the display panel. Once compensation is complete, a power-off operation is executed.

[0149] In one exemplary implementation, please refer to Figure 10 and Figure 14 After power-off compensation, the device can either be powered off or continue displaying. If the display device is set to power off directly, the power-off operation will be performed after compensation. If display continues, after power-off compensation, a black screen will be displayed for 35ms. Then, at time t4, the TCON signal will be turned off (i.e., the second video signal will stop being sent), and at time t5, the motherboard signal will be turned on (i.e., the first video signal will start being output). At time t6, the display validity period of the first video signal will begin (i.e., the valid display time), real-time detection will be enabled to start real-time detection of the display panel, and the device will enter normal display mode to display a normal video image. This signal switching process has no visible characteristics and will not be noticed by the user.

[0150] In summary, this application provides a timing controller including a built-in image generation module and a data selection module. The data selection module stops sending a first video signal to the display panel when the level of the first frame synchronization signal changes from a first level to a second level, and starts sending a second video signal to the display panel when the level of the second frame synchronization signal changes from a third level to a fourth level, enabling the display panel to perform shutdown compensation based on the second video signal. Thus, the timing controller can begin signal switching at the end of one frame of the first video signal output from the motherboard and complete signal switching at the beginning of one frame of the second video signal generated by the timing controller. During signal switching, any frame of video signal sent by the timing controller to the display panel is a complete frame, avoiding display panel malfunctions caused by incomplete frame input due to signal switching. Furthermore, the video source of the display panel can be switched to the highly stable second video signal generated by the built-in image generation module, ensuring normal shutdown compensation. This solves the problem of poor compensation effect of the display panel in related technologies and improves the compensation effect of the display panel.

[0151] Please refer to Figure 15 , Figure 15 This is a flowchart of a display device adjustment method provided in an embodiment of this application. This display device adjustment method can be applied to the timing controller in any of the above embodiments, and the method includes the following steps:

[0152] Step 201: Receive the first video signal and the power-off compensation signal sent by the motherboard. The first video signal includes the first frame synchronization signal.

[0153] Step 202: Based on the power-off compensation signal, send a first video signal to the display panel so that the display panel displays the image based on the first video signal and generates a second video signal, the second video signal including a second frame synchronization signal.

[0154] Step 203: When the level of the first frame synchronization signal changes from the first level to the second level, stop sending the first video signal to the display panel.

[0155] Step 204: When the level of the second frame synchronization signal changes from the third level to the fourth level, a second video signal is sent to the display panel so that the display panel performs shutdown compensation based on the second video signal.

[0156] Please refer to Figure 16 , Figure 16 This is a flowchart of another adjustment method for a display device provided in an embodiment of this application. This adjustment method for the display device can be applied to the timing controller in any of the above embodiments, and the method includes the following steps:

[0157] Step 301: Receive the first video signal and the power-off compensation signal sent by the motherboard. The first video signal includes the first frame synchronization signal.

[0158] The timing controller can send the first received video signal to the display panel so that the display panel can display the image.

[0159] Step 302: Based on the power-off compensation signal, send a first video signal to the display panel so that the display panel displays the image based on the first video signal and generates a second video signal, the second video signal including a second frame synchronization signal.

[0160] After receiving the power-off compensation signal, the timing controller continues to send the first video signal to the display panel to keep the display panel showing the image. The stability of the second video signal is better than that of the first video signal.

[0161] Step 303: Send a real-time detection signal to the display panel.

[0162] The real-time detection signal is used to instruct the display panel to detect the mobility of the driving transistors.

[0163] Step 304: Detect whether the first data enable signal in the first video signal is in the valid area.

[0164] The first data enable signal includes alternating blanking and active regions.

[0165] Step 305: In response to the first data enable signal being in the valid area, the real-time detection mode is turned off to stop sending real-time detection signals to the display panel.

[0166] Since the real-time detection and compensation of the display panel is performed during the blank time of a frame, in this embodiment, the first video signal being transmitted can be detected before the data selection circuit stops sending the first video signal to the display panel. When the first data enable signal is in the valid region (t1), the compensation conversion module is instructed to close the real-time detection mode. This allows the compensation conversion module to stop sending the real-time detection signal to the display panel when the first data enable signal is in the blanking region, effectively stopping the real-time detection and compensation of the display panel. In other words, since the compensation conversion module does not send a real-time detection signal to the display panel during the valid display time of the first video signal, and the display panel is not currently performing real-time detection and compensation, instructing the compensation conversion module to close the real-time detection at t1 allows the display panel to stop the real-time detection and compensation early, avoiding interruption of the real-time detection and compensation of the display panel and thus preventing source IC malfunctions.

[0167] Step 306: When the level of the first frame synchronization signal changes from the first level to the second level, stop sending the first video signal to the display panel.

[0168] The first video signal includes multiple video frames. When the level of the first frame synchronization signal changes from the first level to the second level, it can indicate the end of one video frame in the first video signal or the beginning of another video frame in the first video signal. That is, the level change can be regarded as the dividing point between two video frames in the first video signal.

[0169] Step 307: When the level of the second frame synchronization signal changes from the third level to the fourth level, a second video signal is sent to the display panel so that the display panel performs power-off compensation based on the second video signal.

[0170] The second video signal includes multiple frames of image signals. When the level of the second frame synchronization signal changes from the third level to the fourth level, it can indicate the end of one frame of the second video signal or the beginning of another frame of the second video signal. In other words, the level change can be regarded as the dividing point between two frames of the second video signal.

[0171] If the timing controller directly switches the signal while it is transmitting during the switching process from the first video signal to the second video signal, it may cause a frame of the first video signal to be sent before it is completely transmitted at the time of signal switching. That is, only a part of the frame of the first video signal is sent to the display panel. And if the transmission starts from the middle of a frame of the second video signal, that is, only a part of the frame of the second video signal is sent to the display panel, the two parts of the signal will be combined into a single frame of video signal. As a result, the amount of data in the frame of video signal received by the display panel during signal switching may be more or less than the amount of data in the frame of the second video signal. This will lead to the display panel receiving an abnormal video signal, causing the display panel to malfunction and affecting the compensation effect of the display panel during power-off compensation.

[0172] Therefore, in this embodiment, after receiving the power-off compensation command, the timing controller can begin signal switching at the end of a frame of the first video signal output from the motherboard, and complete signal switching at the beginning of a frame of the second video signal generated by the timing controller. During signal switching, any frame of video signal sent by the timing controller to the display panel is a complete frame of video signal, which avoids the problem of abnormal display panel operation caused by an incomplete frame of video signal input to the display panel due to signal switching. Furthermore, switching the video source of the display panel to the highly stable second video signal generated by the built-in image generation module ensures that power-off compensation can be performed normally.

[0173] Optionally, in step 302, generating the second video signal based on the power-off compensation signal can include the following two methods:

[0174] Method 1: Upon receiving the power-off compensation signal, immediately generate the second video signal.

[0175] There is a first duration between the moment when the level of the first frame synchronization signal jumps from the first level to the second level and the moment when the level of the second frame synchronization signal jumps from the third level to the fourth level.

[0176] Method 2: When the level of the synchronization signal of the first frame changes from the first level to the second level, the second video signal is generated immediately.

[0177] The moment when the level of the first frame synchronization signal jumps from the first level to the second level coincides with the moment when the level of the second frame synchronization signal jumps from the third level to the fourth level.

[0178] In summary, a method for adjusting a display device is provided. This method can be applied to a timing controller, which includes a built-in image generation module and a data selection module. The data selection module stops sending a first video signal to the display panel when the level of the first frame synchronization signal changes from a first level to a second level, and sends a second video signal to the display panel when the level of the second frame synchronization signal changes from a third level to a fourth level, so that the display panel performs shutdown compensation based on the second video signal. Thus, the timing controller can start signal switching at the end of one frame of the first video signal output from the motherboard and complete signal switching at the beginning of one frame of the second video signal generated by the timing controller. During signal switching, any frame of video signal sent by the timing controller to the display panel is a complete frame, avoiding display panel malfunctions caused by incomplete frames of video signal input to the display panel due to signal switching. Furthermore, the video source of the display panel can be switched to the highly stable second video signal generated by the built-in image generation module, ensuring that shutdown compensation can be performed normally. It can solve the problem of poor compensation effect of display panels in related technologies and improve the compensation effect of display panels.

[0179] According to another aspect of this application, a display device is provided, including a motherboard, a display panel, and a timing controller. The timing controller is electrically connected to both the display panel and the motherboard, and the timing controller is the timing controller described in any of the above embodiments. Optionally, the display device can be any product or component with display functionality, such as an AMOLED display device, a mobile phone, a tablet computer, a television, or a monitor.

[0180] According to another aspect of this application, an adjustment device for a display device is provided. The adjustment device for the display panel includes a processor and a memory. The memory stores at least one instruction, at least one program, code set, or instruction set. The at least one instruction, at least one program, code set, or instruction set is loaded and executed by the processor to implement the adjustment method of the display device as in any embodiment.

[0181] According to another aspect of this application, a computer storage medium is provided, which stores at least one instruction, at least one program, code set, or instruction set, wherein the at least one instruction, at least one program, code set, or instruction set is loaded and executed by a processor to implement the adjustment method of the display device in any embodiment.

[0182] According to another aspect of this application, a computer program product or computer program is provided, comprising computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the aforementioned adjustment method for the display device.

[0183] In this application, the terms "first," "second," "third," and "fourth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "multiple" means two or more, unless otherwise expressly defined.

[0184] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0185] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0186] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0187] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A timing controller, characterized in that, For a display device, the display device includes a display panel and a motherboard, the timing controller is electrically connected to the display panel and the motherboard respectively, the timing controller includes a built-in image generation module and a data selection module, the motherboard is used to send a first video signal to the data selection module, and to send a power-off compensation signal to the built-in image generation module and the data selection module; The built-in image generation module is electrically connected to the data selection module. The built-in image generation module is used to generate a second video signal after receiving the power-off compensation signal and send the second video signal to the data selection module. The second video signal includes a second frame synchronization signal. The data selection module is electrically connected to the display panel. After receiving the power-off compensation signal, the data selection module is used to send the first video signal to the display panel. The first video signal includes a first frame synchronization signal so that the display panel displays the image based on the first video signal. The data selection module is further configured to stop sending the first video signal to the display panel when the level of the first frame synchronization signal changes from the first level to the second level, and to send the second video signal to the display panel when the level of the second frame synchronization signal changes from the third level to the fourth level, so that the display panel performs shutdown compensation based on the second video signal.

2. The timing controller according to claim 1, characterized in that, The first video signal further includes a first data enable signal, which includes alternating blanking regions and active regions, and the display panel includes driving transistors; The timing controller further includes a compensation conversion module, which is electrically connected to the data selection module. The compensation conversion module has a real-time detection mode, and in the real-time detection mode, the compensation conversion module is used to send a real-time detection signal to the display panel. The real-time detection signal is used to instruct the display panel to detect the mobility of the driving transistor. The data selection module is further configured to detect whether the first data enable signal in the first video signal is in the valid area when transmitting the first video signal, and send a data valid signal to the compensation conversion module when the first data enable signal is in the valid area. The compensation conversion module is used to turn off the real-time detection mode based on the valid data signal, so as to stop sending the real-time detection signal to the display panel.

3. The timing controller according to claim 1, characterized in that, The built-in image generation module is used to immediately generate the second video signal upon receiving the power-off compensation signal; The time when the level of the first frame synchronization signal changes from the first level to the second level has a first duration between the time when the level of the second frame synchronization signal changes from the third level to the fourth level.

4. The timing controller according to claim 1, characterized in that, The data selection module is also used to send an enable signal to the built-in image generation module when the level of the first frame synchronization signal changes from the first level to the second level; The built-in image generation module is used to immediately generate the second video signal upon receiving the activation signal; The moment when the level of the first frame synchronization signal changes from the first level to the second level coincides with the moment when the level of the second frame synchronization signal changes from the third level to the fourth level.

5. The timing controller according to claim 1, characterized in that, The data selection module includes a comparison module and a gating module, wherein the comparison module is electrically connected to the motherboard and the gating module respectively; The comparison module is used to generate a first indication signal and output the first indication signal to the gating module when it detects that the level of the first frame synchronization signal of the first video signal output by the motherboard reaches the second level. The gating module is used to stop sending the first video signal to the display panel based on the first indication signal.

6. The timing controller according to claim 1, characterized in that, The data selection module includes a comparison module and a gating module, wherein the comparison module is electrically connected to the built-in image generation module and the gating module, respectively. The comparison module is used to generate a second indication signal and output the second indication signal to the gating module when it detects that the level of the second frame synchronization signal of the second video signal output by the built-in image generation module reaches the fourth level. The gating module is used to send the second video signal to the display panel based on the second indication signal.

7. The timing controller according to claim 1, characterized in that, The display device further includes a memory, which is electrically connected to the timing controller. The memory is used to output a compensation completion signal. The compensation completion signal is a signal generated by the memory when it receives a first detection value sent by the display panel. The first detection value is a first detection value obtained by the display panel during the power-off compensation process. The data selection module is also used to send the second video signal to the display panel after receiving the compensation completion signal; The data selection module is further configured to stop sending the second video signal to the display panel when the level of the second frame synchronization signal changes from the third level to the fourth level, and to send the first video signal to the display panel when the level of the first frame synchronization signal changes from the first level to the second level.

8. The timing controller according to claim 7, characterized in that, The first video signal further includes a first data enable signal, which includes alternating blanking regions and active regions, and the display panel includes driving transistors; The timing controller further includes a compensation conversion module, which is electrically connected to the data selection module. The compensation conversion module has a real-time detection mode, and in the real-time detection mode, the compensation conversion module is used to send a real-time detection signal to the display panel. The real-time detection signal is used to instruct the display panel to detect the mobility of the driving transistor. The data selection module is further configured to detect whether the first data enable signal in the first video signal is in the valid area when transmitting the first video signal, and send a data valid signal to the compensation conversion module when the first data enable signal is in the valid area. The compensation conversion module is used to enable the real-time detection mode based on the valid data signal, so as to send the real-time detection signal to the display panel.

9. The timing controller according to claim 1, characterized in that, The second video signal includes a first black screen signal and a third video signal; The data selection module is further configured to send a first black screen signal to the display panel when the level of the second frame synchronization signal changes from the third level to the fourth level, wherein the duration of the first black screen signal is a second duration, so that the display panel displays a black screen of the second duration; The data selection module is also used to send the third video signal to the display panel after sending the first black screen signal to the display panel, so that the display panel performs shutdown compensation based on the third video signal.

10. The timing controller according to claim 7, characterized in that, The second video signal also includes a second black screen signal; The data selection module is further configured to send a second black screen signal to the display panel when the compensation completion signal is received, wherein the duration of the second black screen signal is a second duration, so that the display panel displays a black screen of the second duration.

11. The timing controller according to claim 1, characterized in that, The first video signal also includes a third black screen signal; The data selection module is also used to send the third black screen signal to the display panel when the power-off compensation signal is received. The duration of the third black screen signal is the second duration, so that the display panel displays a black screen of the second duration.

12. The timing controller according to any one of claims 9 to 11, characterized in that, The second duration is the display duration of N frames, where N is an integer greater than or equal to 1.

13. A method for adjusting a display device, characterized in that, Applied in a timing controller as described in any one of claims 1 to 12, the method comprises: The system receives the first video signal and the power-off compensation signal sent by the motherboard, wherein the first video signal includes a first frame synchronization signal; Based on the power-off compensation signal, the first video signal is sent to the display panel so that the display panel displays the image based on the first video signal and generates a second video signal, the second video signal including a second frame synchronization signal; When the level of the first frame synchronization signal changes from the first level to the second level, the transmission of the first video signal to the display panel is stopped. When the level of the second frame synchronization signal changes from the third level to the fourth level, the second video signal is sent to the display panel so that the display panel performs shutdown compensation based on the second video signal.

14. The method according to claim 13, characterized in that, The first video signal further includes a first data enable signal, which includes alternating blanking regions and active regions. The display panel includes a driving transistor, and the compensation conversion module has a real-time detection mode. Before stopping the transmission of the first video signal to the display panel, the method further includes: A real-time detection signal is sent to the display panel, the real-time detection signal being used to instruct the display panel to detect the mobility of the driving transistor; Detect whether the first data enable signal in the first video signal is in the valid region; In response to the first data enable signal being in the effective area, the real-time detection mode is turned off to stop sending the real-time detection signal to the display panel.

15. The method according to claim 13, characterized in that, Based on the power-off compensation signal, a second video signal is generated, including: Upon receiving the power-off compensation signal, the second video signal is immediately generated; The time when the level of the first frame synchronization signal changes from the first level to the second level has a first duration between the time when the level of the second frame synchronization signal changes from the third level to the fourth level.

16. The method according to claim 13, characterized in that, Based on the power-off compensation signal, a second video signal is generated, including: The second video signal is generated immediately when the level of the first frame synchronization signal changes from the first level to the second level; The moment when the level of the first frame synchronization signal changes from the first level to the second level coincides with the moment when the level of the second frame synchronization signal changes from the third level to the fourth level.

17. A display device, characterized in that, It includes a motherboard, a display panel, and a timing controller, wherein the timing controller is electrically connected to the display panel and the motherboard respectively, and the timing controller is the timing controller according to any one of claims 1 to 12.

18. An adjustment device for a display device, characterized in that, The adjustment device for the display panel includes a processor and a memory, wherein the memory stores at least one instruction, at least one program, code set, or instruction set, and the at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by the processor to implement the adjustment method of the display device as described in any one of claims 13 to 16.

19. A computer storage medium, characterized in that, The computer storage medium stores at least one instruction, at least one program, code set, or instruction set, wherein the at least one instruction, the at least one program, the code set, or instruction set is loaded and executed by a processor to implement the adjustment method of the display device as described in any one of claims 13 to 16.

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