Trench gate MOS device and preparation method thereof

Abstract

The invention provides a trench gate MOS device and a preparation method thereof, the trench gate MOS device comprises a semiconductor structure, a shielding layer, a body region, a source region, a contact region, a trench structure, an injection region and a source / drain / gate, the semiconductor structure comprises a substrate, a drift region and a current transmission layer; the shielding layers arranged at intervals are located in the current transmission layer; the body region is positioned on the upper surface layers of the shielding layer and the current transmission layer; two ends of the source region are respectively positioned on the shielding layer and the current transmission layer; the contact regions are located between the adjacent source regions; the trench structure comprises a trench, a gate dielectric layer and a gate conductive layer, wherein the trench penetrates through the source region and the body region, and two side walls of the trench are positioned in the current transmission layer and the shielding layer; the upper surface of the injection region is flush with the bottom surface of the body region; and the source / drain / grid electrode is electrically connected with the corresponding region respectively. Through the combination of the shielding layer and the injection region, the channel density of the device is improved, the on-resistance of the device is reduced, and the ratio of Cgd / Cgs is reduced at the same time.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a trench gate MOS device and its fabrication method. Background Technology

[0002] Silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) are widely used in an increasing number of fields due to their excellent device performance, such as new energy vehicles, photovoltaics, and charging piles. The use of SiC MOSFETs can significantly increase the switching frequency of the system, thereby reducing the overall system's demand for inductive components, and consequently reducing the system's size, weight, and cost. At the same time, their low specific on-resistance and small switching losses can significantly improve the overall system efficiency.

[0003] Because of the low carrier mobility in the channel of SiC MOSFETs, the channel resistance accounts for a very large proportion of the overall device resistance, especially for SiC MOSFETs with voltage ratings below 1200V. To reduce the proportion of channel resistance, it is necessary to increase the carrier mobility in the channel or continuously reduce the cell size to increase the channel density. The most practical method is to increase the channel density. For planar gate SiC MOSFETs, since the drain, channel, source, and body contacts of their MOS structure are all located on the chip surface, it is difficult to further increase the channel density. However, trench gate SiC MOSFETs, by forming a channel in the vertical direction, have only the source and body contacts located on the chip surface, allowing the channel density to be increased by reducing the size of the source and body contacts.

[0004] However, for trench-gate SiC MOSFETs, the electric field strength of the oxide layer at the bottom of the trench gate cannot exceed 3 MV / cm, otherwise it will affect the reliability of the device, especially in high-temperature reverse bias (HTRB) experiments. Implanting a heavily doped P-type region at the bottom of the trench gate can effectively protect the oxide layer from the high electric field, such as... Figure 1The diagram shows a cross-sectional view of a trench-gate MOSFET, including a semiconductor structure 01, substrate 011, drift region 012, current transport layer 013, shielding layer 014, body region 015, source region 016, contact region 017, trench structure 2, trench 21, gate dielectric layer 022, polysilicon gate 023, interlayer dielectric layer 03, source 04, and drain 05. However, this method adds a JFET (junction field-effect transistor) resistor to the trench-gate SiC MOSFET, and the proportion of the JFET resistor gradually increases with the increase of channel density. To address this issue, Infineon Technologies introduced a semi-enclosed trench SiC MOSFET, which injects a high concentration of P-type regions into half of the bottom region of the gate oxide layer to protect the gate oxide layer. However, half of the channel does not participate in conduction, resulting in a lower channel density and consequently a relatively higher on-resistance of the device. Rohm introduced a dual-trench SiC MOSFET, which consists of a source trench and a gate trench. A P-type region is injected at the bottom of the source trench to prevent the gate oxide layer from being subjected to a high electric field intensity through the pinch-off effect. However, it requires an additional process to etch the source trench, resulting in a relatively low channel density and making it difficult to further increase the channel density.

[0005] Furthermore, as the switching frequency of SiC MOSFETs increases, in order to reduce the channel resistance of SiC MOSFETs, the threshold voltage of SiC MOSFETs is usually designed to be a low value (2V~4V). However, the large Cgd / Cgs ratio in SiC MOSFETs means that for SiC MOSFETs in half-bridge applications, the high dv / dt (rate of change of voltage between drain and source) in the upper MOSFET can cause the lower MOSFET to turn on incorrectly, resulting in large switching losses or even short circuits.

[0006] Therefore, there is an urgent need to find a trench gate MOS device that can reduce the channel density of the trench gate MOS device while reducing the ratio of the gate-drain parasitic capacitance Cgd to the gate-source parasitic capacitance Cgs. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a trench gate MOS device and its fabrication method, which solves the problems of low channel density and large ratio of gate-drain parasitic capacitance Cgd to gate-source parasitic capacitance Cgs in the prior art.

[0008] To achieve the above and other related objectives, the present invention provides a trench gate MOS device, comprising:

[0009] A semiconductor structure comprising a first conductivity type substrate, a first conductivity type drift region, and a first conductivity type current transport layer stacked sequentially.

[0010] Multiple second conductive type shielding layers are spaced apart, located in the current transmission layer and with their bottom surfaces higher than the bottom surfaces of the current transmission layer; the shielding layers are flush with the upper surface of the current transmission layer.

[0011] The second conductivity type body region is located on the upper surface of the shielding layer and the current transmission layer;

[0012] Multiple first conductivity type source regions are spaced apart and located on the upper surface of the body region. The two ends of the source regions along the arrangement direction of the shielding layer are respectively located above the shielding layer and the current transmission layer between two adjacent shielding layers.

[0013] The second type of conductive contact region is located in the body region between two adjacent source regions and is adjacent to the source regions;

[0014] A trench structure includes a trench, a gate dielectric layer, and a gate conductive layer. The trench penetrates the source region and the body region, and its bottom surface is spaced apart from the bottom surface of the body region by a predetermined distance. The two side walls of the bottom of the trench along the arrangement direction of the shielding layer are respectively located in the current transmission layer and the shielding layer. The gate dielectric layer covers the bottom surface and inner wall of the trench, and the gate conductive layer fills the trench.

[0015] The injection area is located at the bottom of the trench and its upper surface is flush with the bottom surface of the body area;

[0016] The device comprises a source, a gate, and a drain. The source is electrically connected to the source region and the contact region, the gate is electrically connected to the gate conductive layer, and the drain is electrically connected to the substrate.

[0017] Optionally, the doping concentration of the substrate is greater than the doping concentration of the drift region; the doping concentration of the current transport layer is greater than the doping concentration of the drift region.

[0018] Optionally, the thickness of the gate dielectric layer located at the bottom of the trench is greater than the thickness of the gate dielectric layer located on the inner wall of the trench.

[0019] Optionally, the injection region includes an adjacent first injection region and a second injection region, wherein the first injection region is located in the current transport layer at the bottom of the trench, and the second injection region is located in the shielding layer at the bottom of the trench.

[0020] Optionally, the conductivity type of the first injection region is the same as that of the current transport layer, and the conductivity type of the second injection region is the same as that of the first injection region.

[0021] Optionally, the conductivity type of the first injection region is the same as that of the current transport layer, and the conductivity type of the second injection region is opposite to that of the first injection region.

[0022] Optionally, the doping concentration of the second implantation region is lower than the doping concentration of the body region.

[0023] Optionally, the body region includes a first body region located on the upper surface of the current transport layer between two adjacent trenches and a second body region located on the upper surface of the shielding layer, wherein the doping concentration of the second body region is less than that of the first body region.

[0024] Optionally, the doping concentration of the first injection region is not less than the doping concentration of the current transport layer.

[0025] This invention also provides a method for fabricating a trench gate MOS device, comprising the following steps:

[0026] A semiconductor structure is provided, comprising a first conductivity type substrate, a first conductivity type drift region, and a first conductivity type current transport layer stacked sequentially.

[0027] A plurality of second conductive shielding layers are formed in the current transmission layer at intervals, wherein the upper surface of the shielding layer is flush with the upper surface of the current transmission layer and the bottom surface is higher than the bottom surface of the current transmission layer;

[0028] A second conductivity type body region is formed on the upper surface of the shielding layer and the current transmission layer, and a plurality of first conductivity type source regions are formed on the upper surface of the body region at intervals. The two ends of the source regions along the arrangement direction of the shielding layer are respectively located above the shielding layer and the current transmission layer between two adjacent shielding layers.

[0029] A second conductivity type contact region is formed in the body region between two adjacent source regions, the contact region being adjacent to the source region;

[0030] A trench is formed that penetrates the source region and the body region, with its bottom surface spaced a predetermined distance from the bottom surface of the body region. The two side walls of the bottom of the trench along the arrangement direction of the shielding layer are respectively located in the current transmission layer and the shielding layer.

[0031] An injection area with its upper surface flush with the bottom surface of the body region is formed at the bottom of the trench, and a gate dielectric layer covering the bottom surface and inner wall of the trench and a gate conductive layer filling the trench are formed. The trench, the gate dielectric layer and the gate conductive layer constitute a trench structure.

[0032] A source electrode is formed that is electrically connected to the source region and the contact region; a gate electrode is formed that is electrically connected to the gate conductive layer; and a drain electrode is formed that is electrically connected to the substrate.

[0033] As described above, the trench gate MOS device and its fabrication method of the present invention improve the device structure by extending the shielding layer to the direct below the trench on both sides of the trench structure arrangement direction, and providing a first injection region and a second injection region adjacent to each other at the bottom of the trench. The upper surfaces of the first injection region and the second injection region are flush with the lower surface of the body region, and the first injection region is located in the current transport layer, while the second injection region is located in the shielding layer. Through the combination of the shielding layer and the first and second injection regions, the gate dielectric layer at the bottom of the trench is protected, while the conductive channel density of the device is increased, the on-resistance of the device is reduced, and the ratio between the gate-drain parasitic capacitance Cgd and the gate-source parasitic capacitance Cgs of the device is reduced, thereby improving the switching speed of the device and reducing the risk of accidental turn-on during switching. Furthermore, by adjusting the ratio of the dimensions of the first injection region and the second injection region in the trench arrangement direction and the thickness of the first injection region and the second injection region, the ratio of the drain parasitic capacitance Cgd to the gate-source parasitic capacitance Cgs of the device can be further controlled. Furthermore, the combination of the injection region and the shielding layer can further reduce the size of the device, thereby further increasing the conductive channel density and reducing the on-resistance of the device, which has high industrial application value. Attached Figure Description

[0034] Figure 1 The diagram shows a cross-sectional view of a trench gate MOS device.

[0035] Figure 2 The diagram shown is a cross-sectional view of a trench gate MOS device according to the present invention.

[0036] Figure 3 The diagram shows another cross-sectional structure of the trench gate MOS device of the present invention.

[0037] Figure 4 Displayed as Figure 1 Middle trench gate MOS devices and Figure 3 The variation curves of gate-source parasitic capacitance Cgs and gate-drain parasitic capacitance Cgd of a trench gate MOS device.

[0038] Figure 5 The diagram shows a process flow chart of the method for fabricating the trench gate MOS device of the present invention.

[0039] Figure 6 The diagram shows a cross-sectional view of the semiconductor structure used in the fabrication method of the trench gate MOS device of the present invention.

[0040] Figure 7 The diagram shows a cross-sectional structure of the trench gate MOS device after the shielding layer is formed, as shown in the fabrication method of the present invention.

[0041] Figure 8 The diagram shows a cross-sectional view of the formed body region in the fabrication method of the trench gate MOS device of the present invention.

[0042] Figure 9 The diagram shows a cross-sectional structure after the contact region is formed, illustrating the fabrication method of the trench gate MOS device of the present invention.

[0043] Figure 10 The diagram shows a cross-sectional structure of the trench gate MOS device fabrication method of the present invention after trench formation.

[0044] Figure 11 The diagram shows a cross-sectional structure after the injection region is formed, which is a method for fabricating the trench gate MOS device of the present invention.

[0045] Figure 12 The diagram shows a cross-sectional structure after the formation of the gate conductive layer in the fabrication method of the trench gate MOS device of the present invention.

[0046] Explanation of icon numbers

[0047] 01 Semiconductor Structure

[0048] 011 Substrate

[0049] 012 Drift Zone

[0050] 013 Current Transport Layer

[0051] 014 Shielding layer

[0052] 015 Body Area

[0053] 016 Source Region

[0054] 017 Contact Area

[0055] 02 Trench Grid Structure

[0056] 021 Trench

[0057] 022 Gate dielectric layer

[0058] 023 Polysilicon gate

[0059] 03 Interlayer Dielectric Layer

[0060] 04 Source

[0061] 05 Drain

[0062] 1. Semiconductor Structure

[0063] 11 Substrate

[0064] 12 Drift Zones

[0065] 13 Current transport layer

[0066] 14 Shielding layer

[0067] 15 body areas

[0068] 151 First Body Area

[0069] 152 Second Body Area

[0070] 16 source regions

[0071] 17 Contact Area

[0072] 2. Trench Structure

[0073] 21. Trench

[0074] 22 Gate dielectric layer

[0075] 23 Gate conductive layer

[0076] 3. Injection area

[0077] 31 First Injection Zone

[0078] 32 Second Injection Zone

[0079] 4 Interlayer dielectric layer

[0080] 5 Source poles

[0081] 6 Drain Detailed Implementation

[0082] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0083] Please see Figures 2 to 12 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0084] Example 1

[0085] This embodiment provides a trench gate MOS device, such as Figure 2 and Figure 3The diagrams shown are a cross-sectional view of one trench gate MOS device and another, respectively. The trench gate MOS device includes a semiconductor structure 1, a second conductivity type shielding layer 14, a second conductivity type body region 15, a first conductivity type source region 16, a second conductivity type contact region 17, a trench structure 2, an injection region 3, a source 5, a gate (not shown), and a drain 6. The semiconductor structure 1 includes a first conductivity type substrate 11, a first conductivity type drift region 12, and a first conductivity type current transport layer 13 stacked sequentially. Multiple spaced shielding layers 14 are located within the current transport layer 13, with their bottom surfaces higher than the bottom surfaces of the current transport layer 13. The shielding layers 14 are flush with the upper surface of the current transport layer 13. The body region 15 is located on the upper surface of the shielding layers 14 and the current transport layer 13. The source region 16 is located on the upper surface of the body region 15, and the source region 16 is divided into two parts along the arrangement direction of the shielding layers 14. The contact area 17 is located above the shielding layer 14 and the current transmission layer 13 between two adjacent shielding layers 14; the contact area 17 is located in the body region 15 between two adjacent source regions 16 and is adjacent to the source region 16; the trench structure 2 includes a trench 21, a gate dielectric layer 22 and a gate conductive layer 23, the trench 21 penetrates the source region 16 and the body region 15 and the bottom surface of the trench 21 is spaced apart from the bottom surface of the body region 15 by a predetermined distance, and the bottom of the trench 21 is along the shielding layer 14. The two sidewalls of the 4-axis arrangement are respectively located in the current transmission layer 13 and the shielding layer 14. The gate dielectric layer 22 covers the bottom surface and inner wall of the trench 21, and the gate conductive layer 23 fills the trench 21. The injection region 3 is located at the bottom of the trench 21 and its upper surface is flush with the bottom surface of the body region 15. The source 5 is electrically connected to the source region 16 and the contact region 17. The gate is electrically connected to the gate conductive layer 23, and the drain 6 is electrically connected to the substrate 11.

[0086] Specifically, the first conductivity type includes either N-type or P-type, and the second conductivity type includes either N-type or P-type, with the first conductivity type and the second conductivity type being opposite in nature. In this embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0087] As an example, the doping concentration of the substrate 11 is greater than the doping concentration of the drift region 12; the doping concentration of the current transport layer 13 is greater than the doping concentration of the drift region 12.

[0088] Specifically, the contact type between the substrate 11 and the drain 6 is an ohmic contact. While ensuring device performance, the size, shape, thickness, and doping concentration of the substrate 11 can be selected according to actual conditions and are not limited here. The thickness here refers to the distance between the upper and lower surfaces of the substrate 11.

[0089] Specifically, while ensuring device performance, the thickness and doping concentration of the drift region 12 can be selected according to actual conditions and are not limited here; the thickness and doping concentration of the current transport layer 13 can also be selected according to actual conditions and are not limited here. Here, thickness refers to the distance between the bottom surface of the drift region 12 and the top surface of the current transport layer 13.

[0090] Specifically, while ensuring device performance, the distance between the bottom surface of the shielding layer 14 and the bottom surface of the current transmission layer 13 can be selected according to the actual situation and is not limited here; the size, shape and doping concentration of the shielding layer 14 can be selected according to the actual situation and are not limited here; the spacing between two adjacent shielding layers 14 can be selected according to the actual situation and is not limited here.

[0091] Specifically, while ensuring device performance, the doping concentration and thickness of the body region 15 can be selected according to actual conditions, and are not limited here. The thickness here refers to the distance between the bottom surface of the body region 15 and the top surface of the body region 15.

[0092] Specifically, the contact type between the source region 16 and the source electrode 5 is an ohmic contact. While ensuring device performance, the doping concentration and thickness of the source region 16 can be selected according to actual conditions and are not limited here. The distance between two source regions 16 adjacent to the trench 21 can be selected according to actual conditions and is not limited here. The thickness here refers to the distance between the bottom surface of the source region 16 and the top surface of the source region 16 (i.e., the top surface of the semiconductor structure 1).

[0093] Specifically, while ensuring device performance, the opening size and shape of the trench 21 can be selected according to actual conditions and are not limited here; the distance between the bottom surface of the trench 21 and the bottom surface of the body region 15 can be selected according to actual conditions and are not limited here; the distance between the bottom surface of the trench 21 and the bottom surface of the carrier storage layer 13 can be selected according to actual conditions and are not limited here.

[0094] As an example, the thickness of the gate dielectric layer 22 located at the bottom of the trench 21 is greater than the thickness of the gate dielectric layer 22 located on the inner wall of the trench 21.

[0095] Specifically, while ensuring device performance, the thickness of the gate dielectric layer 22 located at the bottom of the trench 21 can be selected according to the actual situation, and is not limited here; the thickness of the gate dielectric layer 22 located on the inner wall of the trench 21 can be selected according to the actual situation, and is not limited here.

[0096] Specifically, the gate dielectric layer 22 is made of silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

[0097] Specifically, the gate conductive layer 23 fills the trench 21, and the gate dielectric layer 22 wraps around the sidewalls and bottom surface of the gate conductive layer 23.

[0098] Specifically, the material of the gate conductive layer 23 includes polycrystalline silicon or other suitable conductive materials.

[0099] Specifically, by setting the injection area 3, the shielding layer 14 is ensured to protect the bottom of the trench structure 2, while the trench structure 2 forms conductive channels on both sides along its arrangement direction, thereby increasing the density of conductive channels in the device.

[0100] As an example, the injection region 3 includes an adjacent first injection region 31 and a second injection region 32, the first injection region 31 being located in the current transmission layer 13 at the bottom of the trench 21, and the second injection region 32 being located in the shielding layer 14 at the bottom of the trench 21.

[0101] As an example, the conductivity type of the first injection region 31 is the same as that of the current transport layer 13, and the conductivity type of the second injection region 32 is the same as that of the first injection region 31, that is, the conductivity type of both the first injection region 31 and the second injection region 32 is the first conductivity type.

[0102] Specifically, the conductivity type of the first injection region 31 and the second injection region 32 is the same as that of the current transport layer 13. The current transport layer 13, the first injection region 31, the body region 15 above the first injection region 31, and the source region 16 constitute a gate-controlled conductive path on one side of the trench structure 2. The current transport layer 13, the first injection region 31, the second injection region 32, the body region 15 above the second injection region 32, and the source region 16 constitute a gate-controlled conductive path on the other side of the trench structure 2. The trench structure 2 controls the formation of conductive channels in the body region 15 adjacent to the trench structure 2.

[0103] Specifically, when the second injection region 32 and the current transport layer 13 have the same conductivity type, the conductive channel in the gate-controlled conductive path formed by the first injection region 31, the second injection region 32, the body region 15 and the source region 16 is formed only in the body region 15, which can relatively reduce the channel resistance of the gate-controlled conductive path.

[0104] As an example, the conductivity type of the first injection region 31 is the same as that of the current transport layer 13, and the conductivity type of the second injection region 32 is opposite to that of the first injection region 31, that is, the conductivity type of the first injection region 31 is the first conductivity type, and the conductivity type of the second injection region 32 is the second conductivity type.

[0105] Specifically, the first injection region 31 has a first conductivity type, and the second injection region 32 has a second conductivity type. The current transport layer 13, the first injection region 31, the body region 15 above the first injection region 31, and the source region 16 constitute a gate-controlled conductive path on one side of the trench structure 2. The trench structure 2 controls the formation of a conductive channel in the body region 15 adjacent to the trench structure 2 on this side. The current transport layer 13, the first injection region 31, the second injection region 32, the body region 15 above the second injection region 32, and the source region 16 constitute a gate-controlled conductive path on the other side of the trench structure 2. The trench structure 2 controls the formation of a conductive channel in the second injection region 32 and the body region 15 adjacent to the trench structure 2 on this side.

[0106] As an example, when the doping concentration of the second implantation region 32 is less than the doping concentration of the body region 15, that is, when the conductivity type of the first implantation region 31 is the first conductivity type and the conductivity type of the second implantation region 32 is the second conductivity type, the doping concentration of the second implantation region 32 is less than the doping concentration of the body region 15.

[0107] Specifically, when the conductivity types of the first injection region 31 and the second injection region 32 are opposite, the second injection region 32 and the body region 15 adjacent to the injection region constitute a conductive channel region for forming the device, thereby increasing the threshold voltage for forming the conductive channel. By reducing the doping concentration of the second injection region 32, the threshold voltage for forming the conductive channel can be reduced, so as to facilitate the control of the conductive channels in the two conductive paths by the same trench structure 2.

[0108] As an example, the body region 15 includes a first body region 151 located on the upper surface of the current transport layer 13 between two adjacent trenches 21 and a second body region 152 located on the upper surface of the shielding layer 14. The doping concentration of the second body region 152 is less than that of the first body region 151. That is, when the conductivity type of the second injection region 32 is the same as that of the shielding layer 14 and the second body region 152, the doping concentration of the second body region 152 can also be less than that of the first body region 151.

[0109] Specifically, when the doping type of the second implantation region 32 is the same as that of the shielding layer 14 and the second body region 152, in the gate-controlled conductive path formed by the first implantation region 31, the second implantation region 32, the second body region 152 above the second implantation region 32, and the source region 16, the threshold voltage of the conductive path is relatively increased because the conductive channel of the conductive path is formed in the second implantation region 32 and the second body region 152. By reducing the doping concentration of the second body region 152, the threshold voltage of the conductive channel formed in the conductive path can be reduced, so as to facilitate the control of the conductive channels in the two conductive paths by the same trench structure 2.

[0110] As an example, the doping concentration of the first implantation region 31 is not less than the doping concentration of the current transport layer 13. That is, regardless of whether the doping type of the second implantation 32 is the first conductivity type or the second conductivity type, the doping concentration of the first implantation region 31 is greater than or equal to the doping concentration of the current transport layer 13, so as to reduce the on-resistance of the device. In this embodiment, the doping concentration range of the first implantation region 31 is 1×10⁻⁶. 16 cm -3 ~5×10 17 cm -3 .

[0111] Specifically, the device also includes an interlayer dielectric layer 4 covering the upper surfaces of the semiconductor structure 1 and the trench structure 2. The interlayer dielectric layer 4 also includes a source contact hole and a gate contact hole that penetrate the interlayer dielectric layer 4. The bottom surface of the source contact hole exposes the contact region 17 and the source region 16, and the bottom surface of the gate contact hole exposes the gate conductive layer 23.

[0112] Specifically, while ensuring device performance, the thickness of the interlayer dielectric layer 4 can be selected according to actual conditions and is not limited here; the opening size and shape of the source contact hole can be selected according to actual conditions and are not limited here; the opening size and shape of the gate contact hole can be selected according to actual conditions and are not limited here.

[0113] Specifically, the source electrode 5 is made of titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, or other suitable conductive materials; the gate electrode is made of titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, or other suitable conductive materials; and the drain electrode 6 is made of titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, or other suitable conductive materials.

[0114] Specifically, such as Figure 4 As shown, Figure 1 Middle trench gate MOS devices and Figure 3The curves showing the variation of gate-source parasitic capacitance Cgs and gate-drain parasitic capacitance Cgd of a trench gate MOS device (curve A is...) Figure 3 The gate-source parasitic capacitance Cgs of a trench gate MOS device is shown by curve B. Figure 1 The gate-source parasitic capacitance Cgs of a trench gate MOS device, curve C is Figure 3 The gate-drain parasitic capacitance Cgd of a trench gate MOS device is shown by curve D. Figure 1 The gate-drain parasitic capacitance Cgd of a trench gate MOS device, where, Figure 1 and Figure 3 The cell width of all devices is 5 μm, and the doping concentration and thickness of the substrate are both 1.0 × 10⁻⁶. 19 cm -3 The doping concentration and thickness of the drift region are both 8.0 × 10⁻⁶ and 2 μm, respectively. 15 cm -3 The doping concentration and thickness of the current transport layer are both 6.0 × 10⁻⁶ μm and 10 μm, respectively. 16 cm -3 The doping concentration, bottom depth, and width of the shielding layer are all 5×10⁻⁶ and 2μm, respectively. 17 cm -3 The thicknesses are 1.8 μm and 3 μm, and the doping concentration and thickness of the bulk region are both 2.0 × 10⁻⁶. 17 cm -3 The doping concentration and thickness of the source region are both 1.0 × 10⁻⁷ μm and 0.7 μm, respectively. 19 cm -3 The parameters of the trench structure are the same as those of 0.2 μm, and the thicknesses of the gate dielectric layer on the trench sidewall and the gate dielectric layer at the bottom of the trench are 50 nm and 100 nm, respectively. Figure 3 The doping concentration of the first implantation region of the first conductivity type is 1.0 × 10⁻⁶. 17 cm -3 The width along the trench alignment direction is 0.3 μm, and the thickness is 0.2 μm (distance between the bottom and top surfaces). The doping concentration of the second implantation region of the second conductivity type is 2.0 × 10⁻⁶. 17 cm -3 The width along the trench alignment direction is 0.8 μm, and the thickness is 0.2 μm (distance between the bottom and top surfaces). As can be seen from the figure, as the voltage between the source and drain of the device increases, Figure 1 The gate-source parasitic capacitance Cgs of the device is always less than Figure 3 The gate-source parasitic capacitance Cgs of the device. Figure 1 The gate-drain parasitic capacitance Cgd of the device is always greater than Figure 3 The gate-drain parasitic capacitance Cgd of the device. Figure 3 The ratio between Cgd and Cgs of the device is Figure 1One-sixth of the ratio between Cgd and Cgs in the device. Figure 3 The switching speed of the device is significantly improved, while the risk of accidental activation during the switching process is reduced.

[0115] Specifically, through the combination of the injection region 3 and the shielding layer 14, in the device withstand voltage device, as the voltage between the drain 6 and the source 5 increases, the current transport layer 13 and the first injection region 31 located between the shielding layers 14 are gradually depleted. After the current transport layer 13 and the first injection region 31 between the shielding layers 14 are depleted, as the voltage between the drain 6 and the source 5 further increases, the voltage in the device will be borne by the shielding layer 14 and the current transport layer 13 below the shielding layer 14, avoiding the gate dielectric layer 22 from being threatened by a high electric field. Moreover, as the depth of the trench structure 2 extending into the shielding layer 14 becomes shallower, the electric field strength experienced by the gate dielectric layer 22 becomes smaller.

[0116] Specifically, by combining the injection region 3 with the shielding layer 14, the cell size of the device can be further reduced, while the density of conductive channels in the device can be increased, thereby reducing the on-resistance of the device and improving its performance.

[0117] Specifically, by adjusting the dimensions of the first injection region 31 and the second injection region 32, the ratio between the gate-drain parasitic capacitance and the gate-source parasitic capacitance of the device can be adjusted. The wider the width of the first injection region 31, the larger the gate-drain parasitic capacitance Cgd of the device, and the stronger the maximum electric field strength that the gate dielectric layer 21 can withstand. The thicker the first injection region 31, the larger the gate-source parasitic capacitance Cgd of the device, and the stronger the maximum electric field strength that the gate dielectric layer 21 can withstand. The wider the width of the second injection region 32 and the narrower the width of the first injection region 31, the larger the gate-source parasitic capacitance Cgs of the device, and the smaller the gate-drain parasitic capacitance Cgd of the device. Therefore, the value of Cgd / Cgs of the device can be adjusted by adjusting the width of the first injection region 31 and the second injection region 32.

[0118] In this embodiment, the trench gate MOS device extends the shielding layer 14 along the two sidewalls of the trench structure 2 to the bottom of the trench structure 2. A first injection region 31 and a second injection region 32, with their upper surfaces flush with the bottom surface of the body region 15 and located in the current transport layer 13 and the shielding layer 14 respectively, are formed at the bottom of the trench structure 2. This allows the first injection region 31, the body region 15, and the source region 16 to form a gate-controlled conductive path. The first injection region 31, the second injection region 32, the body region 15, and the source region... The 16th layer forms another gate-controlled conductive path, protecting the gate dielectric layer 21 at the bottom of the trench structure 2 in the device while increasing the density of the conductive channel, reducing the on-resistance of the device, decreasing the ratio of the gate-drain parasitic capacitance Cgd to the gate-source parasitic capacitance Cgs, improving the switching speed of the device, and reducing the risk of accidental activation during switching. Furthermore, by adjusting the ratio and thickness of the first injection region 31 and the second injection region 32 along the arrangement direction of the trench structure 2, the ratio of the drain parasitic capacitance Cgd to the gate-source parasitic capacitance Cgs can be further controlled. In addition, this structure, through the combination of the injection region 3 and the shielding layer 14, can further reduce the size of the device, thereby further increasing the conductive channel density and further reducing the on-resistance of the device.

[0119] Example 2

[0120] This embodiment provides a method for fabricating a trench gate MOS device, such as... Figure 5 The diagram shown is a process flow chart of the fabrication method of the trench gate MOS device, including the following steps:

[0121] S1: Provide a semiconductor structure comprising a first conductivity type substrate, a first conductivity type drift region and a first conductivity type current transport layer stacked sequentially;

[0122] S2: A plurality of second conductive shielding layers are formed in the current transmission layer at intervals, wherein the upper surface of the shielding layer is flush with the upper surface of the current transmission layer and the bottom surface is higher than the bottom surface of the current transmission layer;

[0123] S3: A second conductivity type body region is formed on the upper surface of the shielding layer and the current transmission layer, and a plurality of first conductivity type source regions are formed on the upper surface of the body region at intervals. The two ends of the source regions along the arrangement direction of the shielding layer are respectively located above the shielding layer and the current transmission layer between two adjacent shielding layers.

[0124] S4: A second conductive contact region is formed in the body region between two adjacent source regions, the contact region being adjacent to the source region;

[0125] S5: A trench is formed that penetrates the source region and the body region and whose bottom surface is spaced apart from the bottom surface of the body region by a predetermined distance. The two side walls of the bottom of the trench along the arrangement direction of the shielding layer are respectively located in the current transmission layer and the shielding layer.

[0126] S6: An injection area with its upper surface flush with the bottom surface of the body region is formed at the bottom of the trench, and a gate dielectric layer covering the bottom surface and inner wall of the trench and a gate conductive layer filling the trench are formed. The trench, the gate dielectric layer and the gate conductive layer constitute a trench structure.

[0127] S7: Form a source electrode electrically connected to the source region and the contact region, form a gate electrode electrically connected to the gate conductive layer, and form a drain electrode electrically connected to the substrate.

[0128] Please see Figures 6 to 7 The steps S1 and S2 are performed as follows: a semiconductor structure 1 is provided, comprising a first conductivity type substrate 11, a first conductivity type drift region 12 and a first conductivity type current transport layer 13 stacked sequentially; a plurality of second conductivity type shielding layers 14 are formed in the current transport layer 11 at intervals, wherein the upper surface of the shielding layer 14 is flush with the upper surface of the current transport layer 13 and the bottom surface is higher than the bottom surface of the current transport layer 13.

[0129] Specifically, such as Figure 6 The diagram shown is a cross-sectional view of the semiconductor structure 1. The substrate 11 is made of silicon carbide or other suitable semiconductor materials.

[0130] Specifically, the substrate 11 is a process platform for epitaxially growing the drift region 12. The current transport layer 13 can be epitaxially grown on the upper surface of the drift region 12, or it can be formed on the upper surface of the drift region 12 by ion implantation. When the current transport layer 13 is formed on the upper surface of the drift region 12 by ion implantation, multiple ion implantations are required on the upper surface of the drift region 12 to ensure the uniformity of the doping concentration of the current transport layer 13.

[0131] Specifically, such as Figure 7 The diagram shows a cross-sectional view of the shielding layer 14 after its formation. The method for forming the shielding layer 14 includes ion implantation or other suitable methods. In this embodiment, the shielding layer 14 is formed by forming a patterned masking layer on the upper surface of the semiconductor structure 1, followed by high-energy ion implantation based on the patterned masking layer. The masking layer is typically a SiN layer, and the patterned masking layer is obtained by photolithography on the SiN layer.

[0132] Specifically, the shielding layer 14 has an inverted doping distribution, that is, the doping concentration of the shielding layer 14 gradually decreases from the upper surface of the shielding layer 14 to the bottom surface of the shielding layer 14, so that the PN junction formed between the shielding layer 14 and the current transport layer 13 below the shielding layer 14 is wider, thereby improving the voltage withstand capability of the device.

[0133] Specifically, while ensuring device performance, the depth and size of the shielding layer 14 can be selected according to actual conditions, and are not limited here. The depth here refers to the distance between the upper surface of the shielding layer 14 (the upper surface of the semiconductor structure 1) and the lower surface of the shielding layer 14.

[0134] Please see again Figures 8 to 10 The following steps are executed: Steps S3, S4, and S5 are performed: A second conductivity type body region 15 is formed on the upper surface of the shielding layer 14 and the current transmission layer 13, and a plurality of spaced first conductivity type source regions 16 are formed on the upper surface of the body region 15. The two ends of the source regions 16 along the arrangement direction of the shielding layer 14 are respectively located above the shielding layer 14 and the current transmission layer 13 between two adjacent shielding layers 14; A second conductivity type contact region 17 is formed in the body region 15 between two adjacent source regions 16, and the contact region 17 is adjacent to the source region 16; A trench 21 is formed that penetrates the source region 16 and the body region 15 and whose bottom surface is spaced apart from the bottom surface of the body region 15 by a predetermined distance. The two side walls of the bottom of the trench 21 along the arrangement direction of the shielding layer 14 are respectively located in the current transmission layer 13 and the shielding layer 14.

[0135] Specifically, the body region 15 includes a first body region 151 located on the upper surface of the current transmission layer 13 between two adjacent trenches 21 and a second body region 152 located on the upper surface of the shielding layer 14, wherein the doping concentration of the second body region 152 is less than that of the first body region 151.

[0136] Specifically, the method for forming the first body region 151 includes ion implantation or other suitable methods; the method for forming the second body region 152 includes ion implantation or other suitable methods.

[0137] Specifically, such as Figure 8The diagram shows a cross-sectional view of the body region 15 after its formation. While ensuring device performance, the first body region 151 and the second body region 152 can be formed simultaneously, meaning they have the same doping concentration. Alternatively, they can be formed step-by-step. When the first body region 151 and the second body region 152 are formed step-by-step, the doping concentration of the first body region 151 is not less than the doping concentration of the second body region 152. The dimensions of the step-by-step formed first body region 151 and second body region 152 can be selected based on actual conditions and are not limited here.

[0138] Specifically, the method for forming the source region 16 includes ion implantation or other suitable methods.

[0139] Specifically, such as Figure 9 The diagram shown is a cross-sectional view of the contact region 17 after it has been formed. The method for forming the contact region 17 includes ion implantation or other suitable methods.

[0140] Specifically, after forming the body region 15, the source region 16, and the contact region 17, the process further includes an activation step for the doped ions. For example, the doped ions in the ion-implanted region can be activated by annealing.

[0141] Specifically, such as Figure 10 The diagram shows a cross-sectional view of the trench 21 after it has been formed. The formation of the trench 21 includes the following steps: forming a patterned masking layer on the upper surface of the semiconductor structure 1, and forming the trench 21 based on the patterned masking layer.

[0142] Specifically, the masking layer includes a hard mask layer and a photoresist layer. First, the photoresist layer is patterned, and then an etching process is used to transfer the pattern onto the hard mask layer, thus achieving patterning of the entire masking layer. The method for forming the patterned photoresist layer is the commonly used photoresist coating, drying, exposure, and development process, which will not be described in detail here. The hard mask layer is also a commonly used hard mask material in photolithography, which will not be described in detail here.

[0143] Specifically, the method for forming the trench 21 based on the masking layer includes dry etching, wet etching, or other suitable methods.

[0144] Specifically, while ensuring device performance, the distance between the sidewall of the trench 21 in the current transmission layer 13 and the sidewall of the shielding layer 14 below the trench 21 adjacent to the sidewall can be selected according to actual conditions, and is not limited here; the distance between the sidewall of the trench 21 in the shielding layer 14 and the sidewall of the shielding layer 14 below the trench 21 adjacent to the sidewall can be selected according to actual conditions, and is not limited here.

[0145] Please see Figures 11 to 12 Then, perform steps S6 and S7: form an injection region 3 at the bottom of the trench 21 with its upper surface flush with the bottom surface of the body region 15, and form a gate dielectric layer 22 covering the bottom surface and inner wall of the trench 21 and a gate conductive layer 23 filling the trench 21. The trench 21, the gate dielectric layer 22 and the gate conductive layer 23 constitute the trench structure 2; form a source electrode 5 electrically connected to the source region 16 and the contact region 17, form a gate electrode electrically connected to the gate conductive layer 23, and form a drain electrode 6 electrically connected to the substrate 11.

[0146] Specifically, such as Figure 11 The diagram shows a cross-sectional view of the injection region 3 after its formation. The injection region 3 includes a first injection region 31 and a second injection region 32 that are adjacent to each other. The first injection region 31 is located in the current transmission layer 13 at the bottom of the trench 21, and the second injection region 32 is located in the shielding layer 14 at the bottom of the trench 21.

[0147] Specifically, the doping concentration of the first injection region 31 is not less than the doping concentration of the current transport layer 13. Preferably, the doping concentration of the first injection region 31 is greater than the doping concentration of the current transport layer 13, so as to reduce the on-resistance of the device.

[0148] Specifically, the method for forming the first implantation region 31 includes ion implantation or other suitable methods; the method for forming the second implantation region 32 includes ion implantation or other suitable methods.

[0149] Specifically, when the conductivity type of the first implantation region 31 and the second implantation region 32 is the same as that of the current transport layer 13, the first implantation region 31 and the second implantation region 32 can be formed simultaneously or in stages. The doping concentration of the first implantation region 31 can be the same as or different from that of the second implantation region 32. In this embodiment, the photoresist layer in the masking layer is first removed, leaving only the hard mask layer. Ion implantation and annealing are then performed based on the hard mask layer in a direction perpendicular to the bottom of the trench 21 to simultaneously form the first implantation region 31 and the second implantation region 32. After the implantation region 32 is formed, the remaining hard mask layer is removed.

[0150] Specifically, the first injection region 31 has the same conductivity type as the current transport layer 13, the second injection region 32 has the same conductivity type as the shielding layer 14, and when the doping concentrations of the first body region 151 and the second body region 152 are the same, the doping concentration of the second injection region 32 is less than that of the body region 15, so as to reduce the threshold voltage of the gate-controlled conductive path formed by the first injection region 31, the second injection region 32, the body region 15 and the source region 16, thereby reducing the channel resistance of the device.

[0151] Specifically, the first injection region 31 has the same conductivity type as the current transport layer 13, the second injection region 32 has the same conductivity type as the shielding layer 14, and the doping concentration of the second body region 152 is lower than that of the first body region 151. By reducing the doping concentration of the second injection region 32 and the second body region 152, the threshold voltage of the gate-controlled conductive path formed by the first injection region 31, the second injection region 32, the second body region 152 and the source region 16 can be adjusted to make the threshold voltage of the conductive path even lower, thereby reducing the channel resistance of the device.

[0152] Specifically, the method for forming the gate dielectric layer 22 includes thermal oxidation, chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0153] Specifically, the thickness of the gate dielectric layer 22 located on the inner wall of the trench 21 is less than the thickness of the gate dielectric layer 22 located at the bottom of the trench 21.

[0154] Specifically, such as Figure 12 The diagram shown is a cross-sectional view of the gate conductive layer 23 after its formation. The method for forming the gate conductive layer 23 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0155] Specifically, after forming the gate conductive layer 23 and before forming the source electrode 5 and the gate electrode, the process further includes forming an interlayer dielectric layer 4 covering the upper surfaces of the semiconductor structure 1 and the trench structure 2.

[0156] Specifically, the method for forming the interlayer dielectric layer 4 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0157] Specifically, after forming the interlayer dielectric layer 4 and before forming the source electrode 5 and the gate electrode, the process further includes forming a source contact hole and a gate contact hole that penetrate the interlayer dielectric layer 4. The bottom surface of the source contact hole exposes the source region 16 and the contact region 17, and the bottom surface of the gate contact hole exposes the gate conductive layer 23.

[0158] Specifically, such as Figure 2 and Figure 3 The figures show two cross-sectional structural diagrams: one after the drain 6 is formed, and the other after the drain 6 is formed. The source 5 fills the source contact hole, and the gate fills the gate contact hole. The method for forming the source 5 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods. The method for forming the gate includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods. The method for forming the drain 6 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0159] Specifically, by forming the trench 21 at the junction of the shielding layer 14 and the current transmission layer 13, the two sidewalls of the trench 21 along the trench arrangement direction are respectively located in the current transmission layer 13 and the shielding layer 14, and the injection region 3 is formed at the bottom of the trench 21. This not only increases the channel density of the device, but also prevents the gate dielectric layer 21 at the bottom of the trench structure 2 from being subjected to high voltage during the device withstand voltage test, reduces the on-resistance of the device, and allows for further reduction in the size of the device.

[0160] Specifically, by adjusting the doping type, doping concentration, size ratio along the trench 21 arrangement direction of the second injection region 32 in the injection region 3 to the first injection region 31 and the thickness, the ratio between the gate-drain parasitic capacitance Cgd and the gate-source parasitic capacitance Cgs of the device can be reduced, thereby improving the switching speed of the device and improving the performance of the device.

[0161] The method for fabricating the trench gate MOS device in this embodiment extends the shielding layer 14 along the two sidewalls of the trench structure 2 to the bottom of the trench structure 2, and forms a first injection region 31 and a second injection region 32 at the bottom of the trench 21, the upper surface of which is flush with and adjacent to the lower surface of the body region 15. The first injection region 31 is located in the current transport layer 13, and the second injection region 32 is located in the shielding layer 14. This method increases the conductive channel density of the device, reduces the on-resistance of the device, and reduces the ratio between the gate-drain parasitic capacitance Cgd and the gate-source parasitic capacitance Cgs of the device.

[0162] In summary, the trench gate MOS device and its fabrication method of the present invention improve the device structure by extending the shielding layer along both sides of the trench arrangement direction to directly below the trench. A first injection region and a second injection region are provided at the bottom of the trench, with their upper surfaces flush with and adjacent to the lower surface of the body region. The first injection region is located in the current transport layer, and the second injection region is located in the shielding layer. Through the combination of the shielding layer and the first and second injection regions, the gate dielectric layer at the bottom of the trench structure is protected while simultaneously increasing the conductive channel density of the device, reducing the on-resistance, and decreasing the ratio between the gate-drain parasitic capacitance Cgd and the gate-source parasitic capacitance Cgs. This improves the switching speed of the device and reduces the risk of accidental activation during switching. Furthermore, by adjusting the ratio of the first and second injection regions along the trench arrangement direction and the thickness of the first and second injection regions, the ratio of the drain parasitic capacitance Cgd to the gate-source parasitic capacitance Cgs can be further controlled. Furthermore, by combining the injection region with the shielding layer, the device size can be further reduced, thereby increasing the conductive channel density and reducing the on-resistance. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0163] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A trench gate MOS device, characterized in that, include: A semiconductor structure comprising a first conductivity type substrate, a first conductivity type drift region, and a first conductivity type current transport layer stacked sequentially. Multiple second conductive type shielding layers are spaced apart, located in the current transmission layer and with their bottom surfaces higher than the bottom surface of the current transmission layer; the shielding layers are flush with the upper surface of the current transmission layer. The second conductivity type body region is located on the upper surface of the shielding layer and the current transmission layer; Multiple first conductivity type source regions are spaced apart and located on the upper surface of the body region. The two ends of the source regions along the arrangement direction of the shielding layer are respectively located above the shielding layer and the current transmission layer between two adjacent shielding layers. The second type of conductive contact region is located in the body region between two adjacent source regions and is adjacent to the source regions; A trench structure includes a trench, a gate dielectric layer, and a gate conductive layer. The trench penetrates the source region and the body region, and its bottom surface is spaced apart from the bottom surface of the body region by a predetermined distance. The two side walls of the bottom of the trench along the arrangement direction of the shielding layer are respectively located in the current transmission layer and the shielding layer. The gate dielectric layer covers the bottom surface and inner wall of the trench, and the gate conductive layer fills the trench. The injection area is located at the bottom of the trench and its upper surface is flush with the bottom surface of the body area; The device comprises a source, a gate, and a drain. The source is electrically connected to the source region and the contact region, the gate is electrically connected to the gate conductive layer, and the drain is electrically connected to the substrate.

2. The trench gate MOS device according to claim 1, characterized in that: The doping concentration of the substrate is greater than that of the drift region; the doping concentration of the current transport layer is greater than that of the drift region.

3. The trench gate MOS device according to claim 1, characterized in that: The thickness of the gate dielectric layer located at the bottom of the trench is greater than the thickness of the gate dielectric layer located on the inner wall of the trench.

4. The trench gate MOS device according to claim 1, characterized in that: The injection region includes an adjacent first injection region and a second injection region, wherein the first injection region is located in the current transmission layer at the bottom of the trench, and the second injection region is located in the shielding layer at the bottom of the trench.

5. The trench gate MOS device according to claim 4, characterized in that: The conductivity type of the first injection region is the same as that of the current transport layer, and the conductivity type of the second injection region is the same as that of the first injection region.

6. The trench gate MOS device according to claim 4, characterized in that: The conductivity type of the first injection region is the same as that of the current transport layer, and the conductivity type of the second injection region is opposite to that of the first injection region.

7. The trench gate MOS device according to claim 6, characterized in that: The doping concentration of the second implantation region is less than that of the body region.

8. The trench gate MOS device according to claim 6, characterized in that: The body region includes a first body region located on the upper surface of the current transport layer between two adjacent trenches and a second body region located on the upper surface of the shielding layer, wherein the doping concentration of the second body region is less than that of the first body region.

9. The trench gate MOS device according to any one of claims 5 or 6, characterized in that: The doping concentration of the first injection region is not less than the doping concentration of the current transport layer.

10. A method for fabricating a trench gate MOS device, characterized in that, Includes the following steps: A semiconductor structure is provided, comprising a first conductivity type substrate, a first conductivity type drift region, and a first conductivity type current transport layer stacked sequentially. A plurality of second conductive shielding layers are formed in the current transmission layer at intervals, wherein the upper surface of the shielding layer is flush with the upper surface of the current transmission layer and the bottom surface is higher than the bottom surface of the current transmission layer; A second conductivity type body region is formed on the upper surface of the shielding layer and the current transmission layer, and a plurality of first conductivity type source regions are formed on the upper surface of the body region at intervals. The two ends of the source regions along the arrangement direction of the shielding layer are respectively located above the shielding layer and the current transmission layer between two adjacent shielding layers. A second conductivity type contact region is formed in the body region between two adjacent source regions, the contact region being adjacent to the source region; A trench is formed that penetrates the source region and the body region, with its bottom surface spaced a predetermined distance from the bottom surface of the body region. The two side walls of the bottom of the trench along the arrangement direction of the shielding layer are respectively located in the current transmission layer and the shielding layer. An injection area with its upper surface flush with the bottom surface of the body region is formed at the bottom of the trench, and a gate dielectric layer covering the bottom surface and inner wall of the trench and a gate conductive layer filling the trench are formed. The trench, the gate dielectric layer and the gate conductive layer constitute a trench structure. A source electrode is formed that is electrically connected to the source region and the contact region; a gate electrode is formed that is electrically connected to the gate conductive layer; and a drain electrode is formed that is electrically connected to the substrate.

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