Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The device comprises a semiconductor layer; a well region in the semiconductor layer; the source region is located in the well region; the gate dielectric layer is located on the semiconductor layer; the plurality of gate conductors are positioned on the gate dielectric layer; the grid connecting part is respectively connected with the grid conductors, the grid connecting part is provided with a plurality of holes, and each hole increases the equivalent resistance by reducing the cross sectional area of the grid connecting part, so that the plurality of equivalent resistors are respectively connected in series on a conduction path of the corresponding grid conductor and the grid connecting part; by adjusting the number, the distribution density and the arrangement mode of the holes, the uniformity of resistance between cells at different positions can be realized, so that the switching speed is balanced, and the internal oscillation is reduced.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor device manufacturing, and more specifically, to semiconductor devices and methods of manufacturing the same. Background Technology

[0002] In the field of power semiconductor devices, silicon carbide (SiC) is a preferred material for applications in high-voltage, high-frequency, and high-temperature environments due to its wide bandgap, high breakdown field strength, high thermal conductivity, and high saturation drift velocity. Silicon carbide-based metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used in new energy vehicles, smart grids, and industrial motor drives due to their excellent performance. However, due to the high-frequency operating characteristics of silicon carbide MOSFETs, they are susceptible to parasitic inductance and capacitance during switching, leading to gate oscillation. This oscillation can not only cause false turn-on but also lead to localized breakdown due to energy concentration, thereby affecting the stability and reliability of the system.

[0003] To suppress gate oscillations, a gate resistor is typically connected in series on the gate lead outside the device to reduce oscillation energy through damping; alternatively, a separate gate resistor is placed outside the device's gate bus. However, neither of these methods fully considers the characteristics of silicon carbide MOSFET devices, which consist of multiple parallel cells. Due to the differences in cell layout, a uniform gate resistor design would lead to inconsistent switching speeds of cells at different locations, thus introducing new gate oscillation problems within the device. Therefore, there is an urgent need for a gate structure that can uniformly distribute resistance based on the characteristics of parallel cells to effectively suppress internal oscillations and improve overall device performance. Summary of the Invention

[0004] This disclosure provides a semiconductor device and a method for manufacturing the same, aiming to solve the gate oscillation problem caused by uneven gate resistance distribution in the prior art.

[0005] According to one aspect of the present disclosure, a semiconductor device is provided, comprising: Semiconductor layer; The well region is located within the semiconductor layer; The source region is located within the well region; A gate dielectric layer is located on the semiconductor layer; Multiple gate conductors are located on the gate dielectric layer; and The gate connection portion is connected to the plurality of gate conductors respectively, so as to connect the plurality of gate conductors in parallel. The gate connection portion has multiple openings, each of which increases its equivalent resistance by reducing the cross-sectional area of ​​the gate connection portion, so that the multiple equivalent resistances are respectively connected in series in the conduction path of the corresponding gate conductor and the gate connection portion.

[0006] Optionally, it also includes: The first wiring layer is located on the gate connection portion and is in contact with the gate connection portion. The opening is located between the first wiring layer and the gate conductor, and is not covered by the first wiring layer.

[0007] Optionally, the plurality of gate conductors are strip-shaped and arranged in parallel. At least a portion of the gate connection extends along the arrangement direction of the plurality of gate conductors and is connected to at least one end of the plurality of gate conductors.

[0008] Optionally, at least a portion of the first wiring layer extends continuously along the arrangement direction. Alternatively, the first wiring layer may include multiple spaced conductive portions, spaced apart along the arrangement direction.

[0009] Optionally, the gate connection portion is connected to the ends on both sides of the plurality of gate conductors, and the openings and the first wiring layer are symmetrically distributed with respect to the plurality of gate conductors.

[0010] Optionally, it also includes: The second wiring layer is located on top of the first wiring layer and is connected to the first wiring layer.

[0011] Optionally, the opening is filled with insulating material.

[0012] Optionally, the number and distribution density of the plurality of openings are set according to the target equivalent resistance value to achieve resistance uniformity between the gate conductor and the gate connection at different locations.

[0013] Optionally, the plurality of openings are arranged in a uniformly spaced manner so that the equivalent resistance between each gate conductor and the gate connection portion is consistent.

[0014] Optionally, the gate conductor and the gate connection portion are located on the same layer.

[0015] According to another aspect of the present disclosure, a method for manufacturing a semiconductor device is provided for forming the semiconductor device as described above.

[0016] One of the above technical solutions has the following beneficial effects: This semiconductor device reduces its cross-sectional area by setting multiple openings on the gate connection portion (equivalent to the gate bus) to increase the equivalent resistance (gate resistance), and connects these equivalent resistances in series between the corresponding gate conductor and the gate connection portion. By adjusting the number, distribution density, and arrangement of the openings, the uniformity of the resistance between cells at different locations can be achieved, thereby balancing the switching speed and reducing internal oscillations.

[0017] Furthermore, the openings in the gate connection portion can be formed using photolithography and filled with insulating materials such as silicon oxide to maintain structural stability. The arrangement of the first and second wiring layers further optimizes the current path, ensuring that the path length of the current reaching each gate conductor is the same, thereby ensuring that the equivalent resistances connected in series in each path do not interfere with each other.

[0018] Furthermore, the symmetrical distribution design of the apertures and gate conductors, as well as the structure where the gate conductors and interconnects are located in the same layer, both contribute to simplifying the manufacturing process and improving process compatibility. The technical solution disclosed herein, through refined resistor distribution design, significantly improves the stability and reliability of silicon carbide power devices under high-frequency operating conditions, while also providing a flexible implementation path for the adjustability of the gate resistor. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some embodiments of this disclosure, and are not intended to limit this disclosure.

[0020] Figure 1 A three-dimensional structural schematic diagram of a semiconductor device according to a first embodiment of the present disclosure is shown; Figure 2 It shows Figure 1 A top-view structural diagram; Figure 3 It shows along Figure 2 A schematic diagram of the cross-sectional structure cut by line AA; Figure 4 It shows along Figure 2 A schematic diagram of the cross-sectional structure intercepted by the middle BB line; Figure 5 A schematic diagram of the structure of a semiconductor device according to a second embodiment of the present disclosure is shown. Detailed Implementation

[0021] The present disclosure will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. For simplicity, a semiconductor structure obtained after several steps can be depicted in a single figure.

[0022] It should be understood that when describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that there are other layers or regions between it and another layer or region. Furthermore, if the device is flipped, that layer or region will be located "below" or "under" another layer or region.

[0023] To describe a situation where it is directly above another layer or another area, this article will use expressions such as "directly above" or "above and adjacent to".

[0024] Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without following these specific details.

[0025] This disclosure may be presented in various forms, as will be described below. Figures 1 to 4 Describe some examples where, to more clearly illustrate the positional relationships of the various parts in a semiconductor device, Figure 1 , Figure 2 and Figure 4 The interlayer dielectric layer is not shown.

[0026] like Figures 1 to 4 As shown, the power semiconductor device of the first embodiment of this disclosure includes: a semiconductor layer 110, a plurality of well regions 120, a plurality of source regions 130, a gate dielectric layer 140, a gate layer 150, an interlayer dielectric layer 103, a first wiring layer 160, a second wiring layer 170, and a back conductive layer 180.

[0027] Semiconductor layer 110 includes a substrate 111 and an epitaxial layer 112, with the epitaxial layer 112 located on the substrate 111. Multiple well regions 120 are located in the epitaxial layer 112, and multiple source regions 130 are located in their respective well regions 120. The material of semiconductor layer 110 includes silicon, silicon carbide, or other semiconductor materials. The substrate 111, epitaxial layer 112, and source regions 130 are doped with either P-type or N-type materials, and the well regions 120 are doped with either P-type or N-type materials.

[0028] The semiconductor device in this embodiment can be a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated-gate bipolar transistor (IGBT). For example, a drain contact region can be formed in the substrate 111, and the conductivity type of the drain contact region can be set to P-type or N-type accordingly. However, this embodiment is not limited to this. Those skilled in the art can make other settings for the conductivity type of each region in the semiconductor layer 110 as needed to make the semiconductor device a MOSFET or an IGBT. Other settings can also be made for the components of the semiconductor layer 110 as needed. For example, the semiconductor layer 110 may only include the substrate 111 and not the epitaxial layer 112, and the well region 120 may be formed directly in the substrate 101.

[0029] A gate dielectric layer 140 covers the surface of the epitaxial layer 112, and its material may be an insulating material such as silicon dioxide, silicon nitride, or aluminum oxide. A gate layer 150 is located on the gate dielectric layer 140 and includes a plurality of gate conductors 151 and a gate connection portion 152. The material of the gate layer 150 includes polysilicon or other conductive materials. The plurality of gate conductors 151 are strips extending along the X-axis direction, and are arranged in parallel and spaced apart from each other along the Y-axis direction. At least a portion of the gate connection portion 152 extends along the Y-axis direction and is connected to at least one end of the plurality of gate conductors 151, thereby connecting the plurality of gate conductors 151 in parallel, wherein the gate connection portion 152 is equivalent to a gate bus. In some specific embodiments, the gate connection portion 152 partially surrounds the plurality of gate conductors 151 and is connected to the ends of the plurality of gate conductors 151 on both sides respectively. However, the embodiments disclosed herein are not limited thereto, and those skilled in the art can make other arrangements of the shape and arrangement of the gate conductors 151 as needed.

[0030] In this embodiment, the gate connection portion 152 has a plurality of openings 102. Each opening 102 increases its equivalent resistance R by reducing the cross-sectional area of ​​the gate connection portion 152, so that the plurality of equivalent resistances R are respectively connected in series in the conduction path between the corresponding gate conductor 151 and the gate connection portion 152, such as... Figure 2 The dashed arrows indicate the conductive paths leading to different gate conductors 151. The number and distribution density of the multiple openings 102 are set according to the target equivalent resistance value to achieve uniformity of resistance R between the gate conductors 151 and the gate connection portion 152 at different locations. In some specific embodiments, the multiple openings 102 are arranged in a uniformly spaced manner to ensure that the equivalent resistance R between each gate conductor 151 and the gate connection portion 152 is consistent.

[0031] like Figure 3 As shown, the opening 102 can penetrate the gate connection portion 152. In some other embodiments, it may not penetrate the gate connection portion 152. For example, the depth of the opening 102 is 10%-90% of the thickness of the gate connection portion 152.

[0032] Further reference Figures 1 to 4 An interlayer dielectric layer 103 covers the gate layer 150 and fills each opening 102. The material of the interlayer dielectric layer 103 is, for example, silicon oxide or other insulating materials. A first wiring layer 160 is located in the interlayer dielectric layer 103 and contacts the gate connection portion 152. The opening 102 is located between the first wiring layer 160 and the gate conductor 151 along the X-axis. A second wiring layer 170 is located on the interlayer dielectric layer 103 and connected to the first wiring layer 160. The materials of the first wiring layer 160 and the second wiring layer 170 are metals, such as aluminum. The resistance of the first wiring layer 160 and the second wiring layer 170 is negligible compared to the polysilicon gate connection portion 152.

[0033] In this embodiment, the first wiring layer 160 partially surrounds the plurality of first gate conductors 151, and a portion of the first wiring layer 160 extends continuously along the Y-axis. The openings 102 and the first wiring layer 160 are symmetrically distributed with respect to the plurality of gate conductors 151. The back conductive layer 180 is located on the back side of the substrate 111 and can serve as a drain electrode. See further details. Figure 2 and Figure 4 When each gate conductor 151 receives the gate voltage through the conductive path, the region of the well region 120 near the gate dielectric layer 140 is inverted, making the doping type of this region the same as that of the source region 130. At this time, the power device is turned on, and in each cell 10, a doping pattern is formed as shown in the diagram. Figure 4 The source-drain conductive path is indicated by the dashed arrow.

[0034] In some other embodiments, the first wiring layer 160 may also be configured as a plurality of spaced conductive portions 160a, spaced apart along the Y-axis direction, such as... Figure 5As shown, the symmetrical distribution of the apertures 102 in the connection path between the first wiring layer 160 and the gate conductor 151 effectively balances the current distribution. Since the gate conductors 151 are arranged parallel along the Y-axis, and the first wiring layer 160 forms independent current channels with each gate conductor 151 through spaced conductive portions 160a, this structural design ensures that the equivalent resistance R of each channel is determined solely by the geometric parameters of the corresponding aperture 102. When the distribution density of the apertures 102 remains consistent along the Y-axis, the difference in the driving current path length of each gate conductor 151 is significantly reduced, thereby avoiding resistance fluctuations caused by different path lengths. Furthermore, by controlling the depth of the apertures 102 within a specific range (e.g., 10%-90%) of the thickness of the gate connection portion 152, precise control of the equivalent resistance R can be achieved without compromising the overall conductivity of the gate connection portion 152. This layered resistance design retains the process compatibility of polysilicon materials while ensuring efficient transmission of external driving signals through the metallic properties of the wiring layer (such as the low resistance of aluminum).

[0035] In terms of manufacturing method, the semiconductor device of this disclosure embodiment can be formed by the following steps: First, on a polysilicon layer forming a gate conductor 151 and a gate connection portion 152, a pattern of openings 102 is defined using a photolithography process. Then, openings 102 with a predetermined depth are formed in the gate connection portion 152 using a dry etching or wet etching process. Next, an insulating material (such as silicon oxide) is deposited in the openings 102, and a smooth surface of the interlayer dielectric layer 103 is formed using a chemical mechanical polishing (CMP) process. After depositing a metal layer on the interlayer dielectric layer 103, a conductive portion 160a of a first wiring layer 160 is formed using another photolithography step, and a second wiring layer 170 is constructed using a metal deposition and etching process. It is worth noting that when it is necessary to adjust the equivalent resistance R, this can be achieved by modifying the distribution parameters of the openings 102 on the photomask without changing the original structure of the gate connection portion 152. This resistance control method based on the same layer structure, compared with the traditional approach of adding resistors separately on the outside or at the bus end, not only reduces the number of process steps, but also reduces the influence of parasitic parameters through structural integration design, thereby achieving better oscillation suppression under high-frequency operating conditions.

Claims

1. A semiconductor device, comprising: Semiconductor layer; The well region is located within the semiconductor layer; The source region is located within the well region; A gate dielectric layer is located on the semiconductor layer; Multiple gate conductors are located on the gate dielectric layer; as well as The gate connection portion is connected to the plurality of gate conductors respectively; The gate connection portion has multiple openings.

2. The semiconductor device according to claim 1, further comprising: The first wiring layer is located on the gate connection portion and is in contact with the gate connection portion. The opening is located between the first wiring layer and the gate conductor, and is not covered by the first wiring layer.

3. The semiconductor device according to claim 2, wherein, The plurality of gate conductors are strip-shaped and arranged in parallel. At least a portion of the gate connection extends along the arrangement direction of the plurality of gate conductors and is connected to at least one end of the plurality of gate conductors.

4. The semiconductor device according to claim 3, wherein, At least a portion of the first wiring layer extends continuously along the arrangement direction. Alternatively, the first wiring layer may include multiple spaced conductive portions, spaced apart along the arrangement direction.

5. The semiconductor device according to claim 2, wherein, The gate connection portion is connected to the ends on both sides of the plurality of gate conductors, and the openings and the first wiring layer are symmetrically distributed with respect to the plurality of gate conductors.

6. The semiconductor device according to any one of claims 2 to 5, further comprising: The second wiring layer is located on top of the first wiring layer and is connected to the first wiring layer.

7. The semiconductor device according to any one of claims 1 to 5, wherein, The opening is filled with insulating material.

8. The semiconductor device according to any one of claims 1 to 5, wherein, The multiple openings are arranged in a uniformly spaced manner.

9. The semiconductor device according to any one of claims 1 to 5, wherein, The gate conductor and the gate connection portion are located on the same layer.

10. A method for manufacturing a semiconductor device, for forming the semiconductor device as described in any one of claims 1 to 9.

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