Wafer bonding method, manufacturing method of gate-all-around transistor and product
By improving wafer bonding quality through chemical mechanical polishing and surface activation techniques, the fabrication process of all-around gate transistors is simplified, costs are reduced, and electrical performance is improved, solving the problems of high cost and long cycle time in existing technologies.
Patent Information
- Application Number
- CN202511559189.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-29
- Publication Date
- 2026-02-13
AI Technical Summary
Existing all-around gate transistors are limited by wafer bonding quality and fabrication processes, resulting in high costs and long production cycles, making it difficult to effectively suppress short-channel effects and improve electrical performance.
Chemical mechanical polishing and surface activation techniques are used to treat the wafer bonding surface. High-density Si-OH bonds are formed by activating the surface with plasma or solution, and annealing is combined to improve the bonding strength and area. Wet etching process is used to ensure full contact between the gate dielectric and the channel, simplifying the fabrication process.
It improves wafer bonding quality, reduces process costs and cycle time, and enhances transistor gate control capability and electrical performance.
Smart Images
Figure CN121531937A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to the technical field of semiconductor material and device processes, and in particular to a wafer bonding method, a manufacturing method of a gate-all-around transistor and a product. BACKGROUND
[0002] As the size of transistors gradually approaches its physical limit, Moore's Law gradually fails. Wafer bonding technology is one of the key technologies to overcome Moore's Law, and has important applications in silicon-based photonic integration, microelectronic device manufacturing, micro-electro-mechanical system packaging and many other fields. Wafer bonding technology includes various bonding methods, among which direct bonding is widely used in the manufacture of XOI substrates and some micro-electro-mechanical system devices due to its high bonding strength, good thermal stability, and the absence of an intermediate layer. For direct bonding, the wafer surface needs to be hydrophilic first, so that water molecules are adsorbed to form a hydrophilic surface with a high density of hydroxyl groups. Then, the donor wafer and the support wafer are attached at room temperature, so that the surface hydroxyl groups are initially combined through hydrogen bonds. Subsequently, annealing treatment is needed to convert the hydrogen bonds into firm covalent bonds, achieving permanent bonding. This process is accompanied by the generation of water molecules, and the reaction equation is as follows: X-OH + OH-X → X-O-X + H2O.
[0003] With the development of transistor technology, when the channel length of a planar transistor is shortened to below 20 nm, a serious short channel effect occurs, i.e., the gate cannot effectively control the opening and closing of the channel. This will cause the leakage current of the transistor to increase, the power consumption to rise, and the on-off state to be blurred. Gate-all-around field effect transistors (GAAFET) are a new type of structure transistor that can suppress the short channel effect. By using a nanowire or nanosheet structure that can be completely surrounded by gate material from all sides as the channel, it achieves superior electrostatic control, higher drive current, lower power consumption and more flexible threshold voltage regulation. However, existing gate-all-around transistors are limited by wafer bonding quality and manufacturing process, and are costly and have a long manufacturing cycle. SUMMARY
[0004] In view of the above problems, the present disclosure provides a wafer bonding method, a manufacturing method of a gate-all-around transistor and a product, which are used to at least partially solve the above technical problems.
[0005] This disclosure provides a wafer bonding method, comprising: providing a semiconductor material donor wafer and a support wafer; forming a first dielectric layer on the support wafer; forming a second dielectric layer on one side of the semiconductor material donor wafer to be bonded to the support wafer; performing chemical mechanical polishing on the first dielectric layer to form a first bonding surface; performing chemical mechanical polishing on the second dielectric layer to form a second bonding surface; and bonding the support wafer to the semiconductor material donor wafer through the first bonding surface and the second bonding surface.
[0006] According to embodiments of this disclosure, the semiconductor material donor wafer includes one of elemental semiconductors, semiconductor alloys, semiconductor single crystal wafers, semiconductor epitaxial wafers, and epitaxial wafers with prefabricated device structures; the material of the first dielectric layer includes one or more of SiO2, Si3N4, and Al2O3, and the thickness of the first dielectric layer is 300 nm-600 nm; the material of the second dielectric layer includes one or more of SiO2, Si3N4, and Al2O3, and the thickness of the second dielectric layer is 300 nm-600 nm.
[0007] According to embodiments of this disclosure, chemical mechanical polishing uses an abrasive slurry containing an abrasive agent, which includes one or more of diamond, corundum, SiC, B4C, and quartz, with a particle size of 40 nm-200 nm. During chemical mechanical polishing, a first cleaning solution is used to clean the first bonding surface and the second bonding surface. The first cleaning solution includes one or more of ammonia, hydrogen peroxide, and commercial cleaning solutions, and the cleaning method includes one or more of brushing and ultrasonic cleaning, with a cleaning time of 30 min-60 min. The surface roughness of the first bonding surface and the second bonding surface is less than 0.5 nm. Before bonding the support wafer to the semiconductor material donor wafer through the first bonding surface and the second bonding surface, a second cleaning solution is used to clean the first bonding surface and the second bonding surface. The second cleaning solution includes one or more of acetone, ethanol, and deionized water, and the cleaning method includes ultrasonic cleaning, with a cleaning time of 5 min-10 min.
[0008] According to embodiments of this disclosure, bonding a support wafer to a semiconductor material donor wafer via a first bonding surface and a second bonding surface includes: surface activation of the first and second bonding surfaces using plasma or a solution; pre-bonding the support wafer to the semiconductor material donor wafer via the activated first and second bonding surfaces; and annealing after pre-bonding to complete the bonding between the support wafer and the semiconductor material donor wafer. The plasma includes one or more of oxygen plasma, nitrogen plasma, and argon plasma; the solution includes one or more of sulfuric acid-hydrogen peroxide solution and ammonia-hydrogen peroxide solution; the annealing temperature is 200°C-400°C, and the annealing time is 120 min-300 min.
[0009] Another aspect of this disclosure provides a wafer bonding product, including: a silicon substrate, a bonding dielectric layer, and a bonding material layer, wherein the wafer bonding product is fabricated using the wafer bonding method of this disclosure.
[0010] Another aspect of this disclosure provides a method for fabricating an all-around gate transistor, comprising: providing a semiconductor material donor wafer and a support wafer; forming a first dielectric layer on the support wafer; forming a second dielectric layer on one side of the semiconductor material donor wafer to be bonded to the support wafer; performing chemical mechanical polishing on the first dielectric layer to form a first bonding surface; performing chemical mechanical polishing on the second dielectric layer to form a second bonding surface; bonding the support wafer to the semiconductor material donor wafer through the first bonding surface and the second bonding surface; and removing portions of non-target semiconductor material layers from the semiconductor material donor wafer. The process involves: dividing the substrate to obtain an XOI substrate; thinning the target semiconductor material layer in the semiconductor material donor wafer; defining the source, drain, and channel regions of the transistor on the thinned XOI substrate; separating and suspending the channel region from the buried oxide layer to obtain a semi-finished transistor; depositing a gate dielectric layer on the semi-finished transistor and defining the gate region and depositing gate metal; performing ion implantation on the semi-finished transistor with deposited gate metal and annealing to activate the implanted ions; opening holes in the source and drain regions of the ion-implanted semi-finished transistor and depositing source and drain electrodes to obtain a fully all-around gate transistor.
[0011] According to embodiments of this disclosure, a target semiconductor material layer in a semiconductor material donor wafer is thinned using dry etching or wet etching. Dry etching includes one or more of chemical mechanical polishing, mechanical grinding, reactive ion etching, and inductively coupled plasma etching. Wet etching includes etching using a solution that chemically reacts with the target semiconductor material layer. The thickness of the thinned target semiconductor material layer is 10 nm to 50 nm.
[0012] According to embodiments of this disclosure, electron beam lithography is used to define the source region, drain region, and channel region of a transistor on a thinned XOI substrate. The area of the source region and the facet of the drain region are (5 μm × 5 μm) - (30 μm × 30 μm). The length of the channel region is 300 nm - 500 nm, and the width is 30 nm - 50 nm. Dry etching or wet etching is used to remove the target semiconductor layer in the semiconductor material donor wafer outside the defined region. Dry etching includes one or more of reactive ion etching and inductively coupled plasma etching. Wet etching includes etching with a solution that chemically reacts with the target semiconductor material layer. An etching solution is used to separate and suspend the channel region from the buried oxide layer. The etching solution includes one or more of hydrofluoric acid solution and buffered oxide etching solution.
[0013] According to embodiments of this disclosure, an atomic layer deposition (ALD) is used to deposit a gate dielectric layer on a semi-finished transistor. The gate dielectric layer is made of one or more of SiO2, Al2O3, Y2O3, ZrO2, and HfO2, and has a thickness of 3 nm to 10 nm. Electron beam lithography (EBL) is used to define the gate region. One or more of ALD, sputtering, chemical vapor deposition (CVD), and electron beam evaporation (EBBE) are used to deposit a gate metal. The gate metal is made of one or more of TiN, Ni, Au, W, and Al. Implanted ions include one or more of B, P, and Ga. EBL is used to define the opening positions of the source and drain regions. An etchant is used to etch the opening positions to form openings. The etchant includes one or more of hydrofluoric acid solution and buffered oxide etchant. EBBE is used to deposit source and drain electrodes. The source and drain electrodes are made of one or more of Ni and Al.
[0014] Another aspect of this disclosure provides a gate-all-around transistor, which is fabricated using the methods of this disclosure.
[0015] The wafer bonding method, the fabrication method of the all-around gate transistor, and the product disclosed herein have at least the following technical advantages:
[0016] By activating the bonding surface using plasma or solution, a large number of Si-OH bonds are generated on the sample surface, which greatly improves the surface hydrophilicity, enhances the quality of wafer bonding, ensures that the bonding strength meets the requirements of subsequent processes, and increases the bonding area.
[0017] By using wet etching, the gate dielectric, gate metal, and channel are fully contacted, which improves the gate control capability of the transistor, simplifies the fabrication process of all-around gate transistors, reduces process costs and cycle time, and enhances the electrical performance of the transistor. Attached Figure Description
[0018] The foregoing contents, as well as other objects, features, and advantages of this disclosure, will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:
[0019] Figure 1 A schematic flowchart of a wafer bonding method according to an embodiment of the present disclosure is shown.
[0020] Figure 2 A flowchart illustrating a method for fabricating a gate-all-around transistor according to an embodiment of the present disclosure is shown schematically.
[0021] Figure 3 The schematic diagram illustrates the structure of a silicon-based epitaxial germanium-tin wafer and a thermally oxidized silicon wafer according to embodiments of the present disclosure;
[0022] Figure 4A schematic diagram of the GeSnOI fabrication process according to an embodiment of the present disclosure is shown.
[0023] Figure 5 The schematic diagram illustrates the fabrication process of a large drive current all-around gate transistor according to an embodiment of the present disclosure.
[0024] Figure 6 The illustration schematically depicts a wafer bonding product and a gate-all-around transistor according to an embodiment of the present disclosure. Detailed Implementation
[0025] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.
[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.
[0027] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.
[0028] Figure 1 A schematic flowchart of a wafer bonding method according to an embodiment of the present disclosure is shown.
[0029] like Figure 1 As shown, the wafer bonding method of this embodiment may include operations S1 to S3.
[0030] In operation S1, a semiconductor material donor wafer and a support wafer are provided. A first dielectric layer is formed on the support wafer, and a second dielectric layer is formed on the side of the semiconductor material donor wafer to be bonded to the support wafer.
[0031] In operation S2, the first dielectric layer is chemically and mechanically polished to form a first bonding surface, and the second dielectric layer is chemically and mechanically polished to form a second bonding surface.
[0032] In operation S3, the support wafer is bonded to the semiconductor material donor wafer through the first bonding surface and the second bonding surface.
[0033] In some embodiments, semiconductor material donor wafers include, but are not limited to, elemental semiconductors (such as Si, Ge, etc.) and semiconductor alloys (such as Si...). 1-x Ge x Ge 1-x Sn x Si 1-x-y Ge x Sn y It is one of the following: semiconductor single crystal wafer, semiconductor epitaxial wafer, and epitaxial wafer with prefabricated device structure.
[0034] In some embodiments, the material of the first dielectric layer includes, but is not limited to, one or more of SiO2, Si3N4, Al2O3, etc., and the thickness of the first dielectric layer can be 300 nm-600 nm.
[0035] The material of the second dielectric layer includes, but is not limited to, one or more of SiO2, Si3N4, Al2O3, etc., and the thickness of the second dielectric layer is 300 nm-600 nm.
[0036] In some embodiments, chemical mechanical polishing may use an abrasive slurry containing an abrasive, which may include one or more of diamond, corundum (Al2O3), SiC, B4C, quartz (SiO2), etc., and the particle size of the abrasive may be 40 nm-200 nm.
[0037] During chemical mechanical polishing, a first cleaning solution can be used to clean the first and second bonding surfaces. The first cleaning solution may include one or more of ammonia, hydrogen peroxide, or commercial cleaning solutions, and the cleaning method may include one or more of brushing or ultrasonic cleaning, with a cleaning time of 30-60 minutes.
[0038] The surface roughness (RMS) of the first bonding surface and the second bonding surface needs to be less than 0.5 nm, and preferably less than 0.3 nm.
[0039] In some embodiments, before bonding the support wafer to the semiconductor material donor wafer through the first bonding surface and the second bonding surface, the first bonding surface and the second bonding surface are cleaned with a second cleaning solution. The second cleaning solution includes one or more of acetone, ethanol, and deionized water. The cleaning method includes ultrasonic cleaning, and the cleaning time is 5 min to 10 min.
[0040] In some embodiments, bonding the support wafer to the semiconductor material donor wafer via the first bonding surface and the second bonding surface may include: surface activation of the first bonding surface and the second bonding surface using plasma or solution; pre-bonding the support wafer to the semiconductor material donor wafer via the activated first bonding surface and the activated second bonding surface; and annealing after pre-bonding to enhance the bonding strength, thereby completing the bonding between the support wafer and the semiconductor material donor wafer.
[0041] After activation, pre-bonding can be performed at room temperature. The plasma includes, but is not limited to, one or more of oxygen plasma, nitrogen plasma, and argon plasma; the solution includes, but is not limited to, one or more of sulfuric acid hydrogen peroxide solution and ammonia hydrogen peroxide solution; the annealing temperature is 200 ℃-400 ℃, and the annealing time is 120 min-300 min.
[0042] Figure 2 A flowchart illustrating a method for fabricating a fully all-around gate transistor according to an embodiment of the present disclosure is shown.
[0043] like Figure 2 As shown, the fabrication method of the all-around gate transistor in this embodiment may include operations S1 to S9.
[0044] In operation S1, a semiconductor material donor wafer and a support wafer are provided. A first dielectric layer is formed on the support wafer, and a second dielectric layer is formed on the side of the semiconductor material donor wafer to be bonded to the support wafer.
[0045] In operation S2, the first dielectric layer is chemically and mechanically polished to form a first bonding surface, and the second dielectric layer is chemically and mechanically polished to form a second bonding surface.
[0046] In operation S3, the support wafer is bonded to the semiconductor material donor wafer through the first bonding surface and the second bonding surface.
[0047] In operation S4, the portion of the non-target semiconductor material layer in the semiconductor material donor wafer is removed to obtain the XOI substrate.
[0048] In operation S5, the target semiconductor material layer in the semiconductor material donor wafer is thinned.
[0049] In operation S6, the source region, drain region, and channel region of the transistor are defined on the thinned XOI substrate, and the channel region is separated from the buried oxide layer and suspended to obtain a semi-finished transistor.
[0050] In operation S7, a gate dielectric layer is deposited on the semi-finished transistor, and the gate region is defined and the gate metal is deposited.
[0051] In operation S8, ion implantation is performed on the semi-finished transistor with deposited gate metal, and annealing is performed to activate the implanted ions.
[0052] In operation S9, holes are made in the source and drain regions of the ion-implanted semi-finished transistor, and source and drain electrodes are deposited to obtain a gate-all-around transistor.
[0053] It should be noted that the specific implementation details of operations S1 to S3 can be found in the aforementioned wafer bonding method implementation section, and will not be repeated here.
[0054] In some embodiments, the target semiconductor material layer in the semiconductor material donor wafer is thinned using dry etching or wet etching. Dry etching includes one or more of chemical mechanical polishing, mechanical polishing, reactive ion etching, and inductively coupled plasma etching. Wet etching involves etching with a solution that chemically reacts with the target semiconductor material layer, such as using hydrochloric acid-hydrogen peroxide solution to thin the germanium layer. The thickness of the thinned target semiconductor material layer is 10 nm to 50 nm.
[0055] In some embodiments, electron beam lithography (EBL) is used to define the source (S) region, drain (D) region, and channel region of the transistor on the thinned XOI substrate. The area of the source region and the facet of the drain region are (5 μm × 5 μm) to (30 μm × 30 μm), and the length of the channel region is 300 nm to 500 nm, and the width is 30 nm to 50 nm.
[0056] In some embodiments, dry etching or wet etching is used to remove the target semiconductor layer in the semiconductor material donor wafer outside the defined region. Dry etching includes one or more of reactive ion etching and inductively coupled plasma etching, while wet etching involves etching with a solution that chemically reacts with the target semiconductor material layer. An etching solution is used to separate and suspend the channel region from the buried oxide layer. The etching solution includes one or more of hydrofluoric acid solution and buffered oxide etching solution.
[0057] In some embodiments, an atomic layer deposition method is used to deposit a gate dielectric layer on a semi-finished transistor. The material of the gate dielectric layer includes one or more of SiO2, Al2O3, Y2O3, ZrO2, HfO2, etc., and the thickness is 3 nm-10 nm.
[0058] Electron beam lithography is used to define the gate region. One or more of the following methods are employed to deposit the gate metal: atomic layer deposition, sputtering, chemical vapor deposition, and electron beam evaporation. The gate metal material can be one or more of TiN, Ni, Au, W, and Al. The thickness of the deposited gate metal is related to subsequent ion implantation; it is necessary to ensure that the gate metal is thick enough to prevent implanted ions from entering the channel region.
[0059] The implanted ions include one or more of B, P, Ga, etc. The annealing time and temperature are related to the type, dose, and energy of the implanted ions, and the annealing atmosphere can be nitrogen. For example, when the implanted ion type is B and the dose is 1E15 cm⁻¹... -2 When the energy is 10 keV, the annealing time can be 3 min and the temperature can be 400 ℃.
[0060] In some embodiments, electron beam lithography is used to define the aperture locations of the source and drain regions, and an etching solution is used to etch the aperture locations to form apertures. The etching solution includes one or more of hydrofluoric acid solution and buffered oxide etching solution. Electron beam evaporation is used to deposit source and drain electrodes. The materials of the source and drain electrodes include one or more of Ni, Al, etc. The area of the source and drain electrodes should not be larger than the area of the source and drain regions.
[0061] To illustrate the above methods and products more clearly, a specific example is provided below.
[0062] Germanium-tin-on-insulator (GeSnOI) wafers are an important material platform in the fields of microelectronics and optoelectronics, exhibiting higher carrier mobility than germanium-on-insulator (GeOI).
[0063] Figure 3 The schematic diagram illustrates the structure of a silicon-based epitaxial germanium-tin wafer and a thermally oxidized silicon wafer according to embodiments of the present disclosure.
[0064] like Figure 3 As shown, GeSnOI can be obtained by bonding a silicon-based epitaxial germanium-tin wafer to a thermally oxidized silicon wafer.
[0065] Figure 4 A schematic diagram of the GeSnOI fabrication process according to an embodiment of the present disclosure is shown.
[0066] like Figure 4 As shown in Figure S1, a semiconductor material donor wafer and a support wafer are provided. A first dielectric layer is disposed on the support wafer, and a second dielectric layer is disposed on the side of the semiconductor material donor wafer to be bonded to the support wafer.
[0067] The supporting wafer is a silicon wafer with a thermally oxidized layer. The thermally oxidized silicon wafer is obtained by forming a 500 nm first dielectric layer SiO2 layer on the surface of the silicon wafer through a thermal oxidation method.
[0068] The semiconductor material donor wafer is a silicon substrate on which a germanium buffer layer and a germanium-tin material layer are epitaxially grown sequentially. A second dielectric layer, SiO2, is deposited on the surface of the germanium-tin material layer. The silicon substrate is 500 μm thick, the germanium buffer layer is 800 nm thick, the germanium-tin material layer is 800 nm thick, and the second dielectric layer, SiO2, is deposited on the surface of the germanium-tin material layer using chemical vapor deposition, and has a thickness of 500 nm.
[0069] S2, perform chemical mechanical polishing on the first dielectric layer to form a first bonding surface, and perform chemical mechanical polishing on the second dielectric layer to form a second bonding surface.
[0070] The surfaces of the first and second SiO2 dielectric layers were polished using a chemical mechanical polishing (CMP) system. During polishing, a quartz polishing slurry with a particle size of 80 nm was uniformly sprayed onto the polishing pad, and the polishing time was approximately 1 minute. After polishing, the surface roughness of both the first and second SiO2 dielectric layers was less than 0.5 nm, forming qualified first and second bonding surfaces.
[0071] S3, the support wafer and the semiconductor material donor wafer are bonded together through the first bonding surface and the second bonding surface.
[0072] The first and second bonding surfaces were cleaned sequentially with acetone, ethanol, and deionized water using ultrasonic cleaning for 10 minutes each. After cleaning, the two bonding surfaces were activated using oxygen plasma at a power of 300 W for 120 seconds. Following activation, the bonding surfaces were then contacted with deionized water to adsorb water molecules and form a bonding surface with a high density of hydroxyl groups. Subsequently, the two wafers were pre-bonded together. The pre-bonded wafers were annealed at 200 °C for 5 hours to achieve higher bonding strength.
[0073] S4, remove the portion of the non-target semiconductor material layer in the semiconductor material donor wafer, such as the buffer layer on the epitaxial layer.
[0074] The removal method can be either dry etching or wet etching. For example, the silicon substrate of the donor wafer is thinned to approximately 50 μm using mechanical polishing, and then the remaining silicon substrate is etched using a tetramethylammonium hydroxide (TMAH) solution under 80 °C water bath heating. Subsequently, an 800 nm germanium buffer layer is etched using inductively coupled plasma to obtain the complete GeSnOI.
[0075] Compared to transistors with germanium as the channel material, transistors with germanium-tin as the channel material achieve a larger drive current due to their higher carrier mobility, thus improving the transistor's electrical characteristics.
[0076] Figure 5 The schematic diagram illustrates a structural diagram corresponding to the fabrication process of a large drive current all-around gate transistor according to an embodiment of the present disclosure.
[0077] like Figure 5 As shown, GeSnOI substrates are prepared based on steps S1 to S4 of the above wafer bonding method.
[0078] S5, thinning the target semiconductor material layer in the semiconductor material donor wafer.
[0079] Based on the aforementioned GeSnOI, the thickness of the germanium-tin material layer was reduced from 800 nm to approximately 300 nm using inductively coupled plasma etching. Subsequently, a chemical mechanical polishing (CMP) device was used to further reduce the thickness of the germanium-tin material layer to approximately 50 nm. During polishing, a diamond polishing slurry with a particle size of 30 nm was uniformly sprayed onto the polishing pad to prevent a drastic increase in the surface roughness of the germanium-tin material layer.
[0080] S6 defines the source, drain, and channel regions of the transistor on the thinned GeSnOI substrate and suspends the channel region from the buried oxide layer.
[0081] Using electron beam lithography, source, drain, and channel regions are defined on the GeSnOI surface through exposure and development. Inductively coupled plasma (ICP-PAP) etching is then used to remove the germanium-tin material outside the defined regions until it is completely removed, isolating different transistors on the same GeSnOI. A buffered oxide etchant is then used to remove part of the buried oxide layer beneath the germanium-tin material layer, separating and suspending the channel region from the buried oxide layer, resulting in a semi-finished transistor.
[0082] S7 deposits a gate dielectric layer on the semi-finished transistor and defines the gate (G) region and deposits gate metal.
[0083] Using atomic layer deposition (ALD), an approximately 5 nm thick layer of Al₂O₃ is deposited on the surface of the aforementioned semi-finished transistor as the gate dielectric. Electron beam lithography (EBL) is used to define the gate region through exposure and development. Using sputtering, an approximately 80 nm thick layer of TiN is deposited in the gate electrode region as the gate electrode, while simultaneously filling it with gate metal.
[0084] S8 performs ion implantation on the semi-finished transistor after depositing gate metal and anneals it to activate the implanted ions.
[0085] Ions of type B were implanted into the aforementioned semi-finished transistor at a dose of 1E15 cm⁻¹. -2The implantation energy was 10 keV. The gate metal was used as a barrier layer for ion implantation to prevent implanted ions from entering the channel, thereby reducing the control capability of the metal gate. Subsequently, the semi-finished transistor was subjected to rapid thermal annealing at 300 °C for 3 min to activate the implanted ions.
[0086] S9 involves creating openings in the source and drain regions of the semi-finished transistor after ion implantation, and depositing source and drain electrodes.
[0087] Using electron beam lithography, the source and drain electrode positions are defined in the source and drain regions of the aforementioned semi-finished transistor through exposure and development. The oxide on the germanium-tin material layer at the source and drain electrode positions is removed using a buffered oxide etchant. Subsequently, a 50 nm thick layer of Ni is deposited using electron beam evaporation to serve as the source and drain electrodes. At this point, the all-around gate transistor with a germanium-tin channel material is fabricated.
[0088] Based on the wafer bonding method described above, embodiments of this disclosure also provide a wafer bonding product. Based on the fabrication method described above, embodiments of this disclosure also provide a gate-all-around transistor with good switching characteristics and driving performance.
[0089] Figure 6 The illustration schematically depicts a wafer bonding product and a gate-all-around transistor according to an embodiment of the present disclosure.
[0090] like Figure 6 As shown, the wafer bonding product includes a silicon substrate, a bonding dielectric layer, and a bonding material layer, and is fabricated using the wafer bonding method described above. Specific details are not elaborated here.
[0091] A gate-all-around transistor includes complete source, drain, and channel regions, as well as gate dielectric and gate metal. The gate-all-around transistor is fabricated by the method described above, which will not be repeated here.
[0092] Those skilled in the art will understand that the methods provided in the embodiments of this disclosure are not limited to the fabrication of GeSnOI and related transistors, but can also be applied to other semiconductor materials to obtain the same material structure or device structure as in the embodiments described above.
[0093] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.
[0094] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.
Claims
1. A wafer bonding method, characterized in that, include: A semiconductor material donor wafer and a support wafer are provided, a first dielectric layer is formed on the support wafer, and a second dielectric layer is formed on one side of the semiconductor material donor wafer to be bonded to the support wafer; The first dielectric layer is chemically and mechanically polished to form a first bonding surface, and the second dielectric layer is chemically and mechanically polished to form a second bonding surface; The support wafer is bonded to the semiconductor material donor wafer through the first bonding surface and the second bonding surface.
2. The method according to claim 1, characterized in that, The semiconductor material donor wafer includes one of the following: elemental semiconductor, semiconductor alloy, semiconductor single crystal wafer, semiconductor epitaxial wafer, and epitaxial wafer with prefabricated device structure; The material of the first dielectric layer includes one or more of SiO2, Si3N4, and Al2O3, and the thickness of the first dielectric layer is 300 nm-600 nm. The material of the second dielectric layer includes one or more of SiO2, Si3N4, and Al2O3, and the thickness of the second dielectric layer is 300 nm-600 nm.
3. The method according to claim 1, characterized in that, The chemical mechanical polishing uses an abrasive slurry containing an abrasive, which includes one or more of diamond, corundum, SiC, B4C, and quartz, and the particle size of the abrasive is 40 nm to 200 nm. During the chemical mechanical polishing process, a first cleaning solution is used to clean the first bonding surface and the second bonding surface. The first cleaning solution includes one or more of ammonia water, hydrogen peroxide, and commercial cleaning solutions. The cleaning method includes one or more of brushing and ultrasonic cleaning. The cleaning time is 30 min to 60 min. The surface roughness of the first bonding surface and the second bonding surface is less than 0.5 nm. Before bonding the support wafer to the semiconductor material donor wafer through the first bonding surface and the second bonding surface, the first bonding surface and the second bonding surface are cleaned with a second cleaning solution. The second cleaning solution includes one or more of acetone, ethanol, and deionized water. The cleaning method includes ultrasonic cleaning, and the cleaning time is 5 min to 10 min.
4. The method according to claim 1, characterized in that, The bonding of the support wafer to the semiconductor material donor wafer via the first bonding surface and the second bonding surface includes: The first and second bonding surfaces are surface activated using plasma or solution. The support wafer and the semiconductor material donor wafer are pre-bonded using the activated first bonding surface and the activated second bonding surface; After pre-bonding is completed, annealing is performed to complete the bonding between the support wafer and the semiconductor material donor wafer; The plasma includes one or more of oxygen plasma, nitrogen plasma, and argon plasma; the solution includes one or more of sulfuric acid hydrogen peroxide solution and ammonia hydrogen peroxide solution. The annealing temperature is 200 ℃-400 ℃, and the annealing time is 120 min-300 min.
5. A wafer bonding product, characterized in that, include: The wafer bonding product comprises a silicon substrate, a bonding dielectric layer, and a bonding material layer, and is fabricated using the wafer bonding method described in any one of claims 1 to 4.
6. A method for fabricating a gate-all-around transistor, characterized in that, include: A semiconductor material donor wafer and a support wafer are provided, a first dielectric layer is formed on the support wafer, and a second dielectric layer is formed on one side of the semiconductor material donor wafer to be bonded to the support wafer; The first dielectric layer is chemically and mechanically polished to form a first bonding surface, and the second dielectric layer is chemically and mechanically polished to form a second bonding surface; The support wafer is bonded to the semiconductor material donor wafer through the first bonding surface and the second bonding surface; Remove the portion of the non-target semiconductor material layer from the semiconductor material donor wafer to obtain the XOI substrate; The target semiconductor material layer in the semiconductor material donor wafer is thinned, and the source region, drain region and channel region of the transistor are defined on the thinned XOI substrate. The channel region is separated from the buried oxide layer and suspended to obtain a semi-finished transistor. A gate dielectric layer is deposited on the semi-finished transistor, and a gate region is defined and a gate metal is deposited. Ion implantation is performed on the semi-finished transistor with deposited gate metal, and annealing is performed to activate the implanted ions; By creating openings in the source and drain regions of the ion-implanted semi-finished transistor and depositing source and drain electrodes, a fully all-around gate transistor is obtained.
7. The method according to claim 6, characterized in that, The target semiconductor material layer in the semiconductor material donor wafer is thinned by dry etching or wet etching; the dry etching includes one or more of chemical mechanical polishing, mechanical polishing, reactive ion etching, and inductively coupled plasma etching; the wet etching includes etching with a solution that has a chemical reaction with the target semiconductor material layer. The thickness of the target semiconductor material layer after thinning is 10 nm-50 nm.
8. The method according to claim 6, characterized in that, Electron beam lithography is used to define the source region, drain region, and channel region of the transistor on the thinned XOI substrate. The area of the source region and the facet of the drain region are (5 μm × 5 μm) - (30 μm × 30 μm). The length of the channel region is 300 nm - 500 nm and the width is 30 nm - 50 nm. The target semiconductor layer in the semiconductor material donor wafer outside the defined region is removed by dry etching or wet etching. The dry etching includes one or more of reactive ion etching and inductively coupled plasma etching. The wet etching includes etching with a solution that has a chemical reaction with the target semiconductor material layer. An etching solution is used to separate and suspend the channel region from the buried oxide layer. The etching solution includes one or more of hydrofluoric acid solution and buffered oxide etching solution.
9. The method according to claim 6, characterized in that, A gate dielectric layer is deposited on the semi-finished transistor using atomic layer deposition. The material of the gate dielectric layer includes one or more of SiO2, Al2O3, Y2O3, ZrO2, and HfO2, and the thickness is 3nm-10nm. Electron beam lithography is used to define the gate region, and one or more of atomic layer deposition, sputtering, chemical vapor deposition, and electron beam evaporation are used to deposit the gate metal. The gate metal material is one or more of TiN, Ni, Au, W, and Al. The implanted ions include one or more of B, P, and Ga; Electron beam lithography is used to define the opening positions of the source and drain regions, and an etching solution is used to etch the opening positions to form openings. The etching solution includes one or more of hydrofluoric acid solution and buffered oxide etching solution. Source and drain electrodes are deposited using electron beam evaporation. The materials of the source and drain electrodes include one or more of Ni and Al.
10. A gate-all-around transistor, characterized in that, The all-around gate transistor is manufactured using the method described in any one of claims 6 to 9.
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CN121908616A