Semiconductor device and method of manufacturing the same

Abstract

This application discloses a semiconductor device and its manufacturing method. The semiconductor device includes a first region and a second region. The second region contains a plurality of transistors. Each transistor includes: a semiconductor layer and a source region and a drain region, the source region and drain region being located in the semiconductor layer and close to its surface; a second gate dielectric layer located on the surface of the semiconductor layer; a gate conductor located on the second gate dielectric layer; a second sidewall located on the side surface of the gate conductor on the second gate dielectric layer; and a plurality of conductive channels respectively connected to the source region, drain region, gate conductor, and second sidewall as lead-out structures. The second sidewall includes a field plate, and the conductive channels of the field plate are connected to the conductive channels of the drain region. This application improves the breakdown voltage of the device without increasing the channel on-resistance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] Power management chips (PMICs) contain CMOS (Complementary Metal-Oxide-Semiconductor) devices, which are divided into low-to-medium voltage devices (the second region) and ultra-high voltage devices (the first region). These two parts have different requirements for the gate dielectric layer thickness due to their different functions. Figure 1 As shown, during the formation of gate dielectric layers of different thicknesses, a 2E mask can be used to block the ultra-high voltage device portion, preventing exposure and etching, while the medium and low voltage device portion is exposed and etched. This process involves two gate dielectric layer material depositions and one gate dielectric layer material etch-back, forming a thick gate dielectric layer for the ultra-high voltage device portion and a thin gate dielectric layer for the medium and low voltage device portion.

[0003] In power management chips (PMICs), the breakdown voltage and on-resistance are the most important electrical parameters. Performance improvements aim for low on-resistance and high withstand voltage. These parameters are directly related to the thickness of the gate dielectric layer. A thicker gate dielectric layer effectively enhances electric field tolerance, helping ultra-high voltage devices achieve high breakdown voltages, but it increases gate capacitance and carrier penetration resistance. A thinner gate dielectric layer reduces carrier transport barriers, meeting the low on-resistance requirements of medium- and low-voltage devices, but its thinner insulation layer limits the breakdown voltage. The core goal of performance improvement is to achieve a dual optimization of low on-resistance and high withstand voltage. However, the inherent characteristics of gate dielectric layer thickness make low on-resistance and high withstand voltage contradictory, making it difficult to achieve both simultaneously.

[0004] Currently used techniques to improve withstand voltage, such as reducing the channel ion implantation concentration and increasing the channel length, all lead to obstruction of the carrier transport path, which in turn increases the on-resistance and further restricts the improvement of the overall performance of the device. Summary of the Invention

[0005] In view of the above problems, this application provides a semiconductor device and a method for manufacturing the same, which aims to further improve the voltage withstand capability of the device without increasing the channel on-resistance.

[0006] According to a first aspect of the present invention, a semiconductor device is provided, comprising a first region and a second region, wherein the second region comprises a plurality of transistors, each transistor comprising: a semiconductor layer and a source region and a drain region, the source region and the drain region being located in the semiconductor layer and close to a surface; a second gate dielectric layer being located on a surface of the semiconductor layer; a gate conductor being located on the second gate dielectric layer; a second sidewall being located on the second gate dielectric layer on a side surface of the gate conductor; and a plurality of conductive channels being respectively connected to the source region, the drain region, the gate conductor and the second sidewall as lead-out structures, wherein the second sidewall comprises a field plate, and the conductive channels of the field plate are connected to the conductive channels of the drain region.

[0007] Optionally, the material of the second sidewall includes oxide-nitride-polysilicon.

[0008] Optionally, the material of the second sidewall includes oxide-nitride-polysilicon-metal silicide.

[0009] Optionally, the plurality of conductive channels include: a first conductive channel connected to the source region; a second conductive channel connected to the gate conductor; a third conductive channel connected to the drain region; a fourth conductive channel connected to the field plate of the second sidewall; and a fifth conductive channel connecting the third conductive channel and the fourth conductive channel.

[0010] According to a second aspect of the present invention, a method for manufacturing a semiconductor device is provided, the semiconductor device comprising a first region and a second region, the method comprising: forming a first gate dielectric layer and a second gate dielectric layer on a semiconductor layer, the first gate dielectric layer being located on the semiconductor layer of the first region and the second gate dielectric layer being located on the semiconductor layer of the second region; forming a plurality of gate conductors on the first gate dielectric layer and the second gate dielectric layer; forming a first sidewall on a semiconductor structure, the first sidewall being located on a side surface of the gate conductors; forming a second sidewall by etching back the first sidewall of the second region; forming a source region and a drain region in the semiconductor layer; and forming a plurality of conductive channels respectively connected to the source region, the drain region, the gate conductors and the second sidewall, wherein the second sidewall includes a field plate and the conductive channels of the field plate are connected to the conductive channels of the drain region.

[0011] Optionally, the step of forming a first sidewall on the semiconductor structure includes: sequentially depositing a third oxide layer, a nitride layer, and a fourth oxide layer on the semiconductor structure; and etching back the third oxide layer, nitride layer, and fourth oxide layer to remove the third oxide layer, nitride layer, and fourth oxide layer from a portion of the surface of the first gate dielectric layer, a portion of the surface of the second gate dielectric layer, and the surface of the gate conductor, wherein the remaining third oxide layer, nitride layer, and fourth oxide layer at the side surface of the gate conductor forms the first sidewall.

[0012] Optionally, the step of forming the second sidewall after etching back the first sidewall of the second region includes: using a mask to etch back the first sidewall in the second region to remove the fourth oxide layer in the first sidewall; depositing a polysilicon layer on the surface of the semiconductor structure; and etching back the polysilicon layer to remove the polysilicon layer on the surface of the first gate dielectric layer, the surface of the second gate dielectric layer, the surface of the first sidewall, and the surface of the gate conductor, wherein the oxide-nitride layer at the sidewall of the second region and the remaining polysilicon layer constitute the second sidewall.

[0013] Optionally, between the steps of forming the source and drain regions in the semiconductor layer and forming a plurality of conductive channels respectively connected to the source and drain regions, the gate conductor and the second sidewall, the method further includes: forming metal silicides on the surface of the gate conductor and the surface of the second sidewall.

[0014] Optionally, the step of forming a first gate dielectric layer and a second gate dielectric layer on the semiconductor layer includes: forming a first oxide layer on the semiconductor layer and removing the first oxide layer in a second region using a photomask; forming a second oxide layer on the first oxide layer and the semiconductor layer, wherein the first oxide layer in the first region and the second oxide layer constitute the first gate dielectric layer, and the second oxide layer in the second region constitutes the second gate dielectric layer.

[0015] Optionally, the same mask is used in the step of removing the first oxide layer in the second region and in the step of etching back the first sidewall in the second region.

[0016] The unexpected technical effect of this application is:

[0017] According to the semiconductor device of the present invention, the structure of the second sidewall in the second region is improved from the traditional oxygen-nitrogen-oxygen material structure to an oxygen-nitrogen-polysilicon material structure. The polysilicon layer in the second sidewall serves as a field plate, and the third conductive channel leads out the drain of the semiconductor device. The fourth conductive channel leads out the polysilicon of the second sidewall in the second region, and the third and fourth conductive channels in the second region are connected by a fifth conductive channel. This realizes the connection between the field plate and the drain of the second sidewall in the transistor of the second region, which not only optimizes the electric field distribution of the channel between the source and drain terminals below the field plate and increases the withstand voltage of the device, but also does not increase the size of the semiconductor device.

[0018] Furthermore, forming metal silicides on the polysilicon surface of the upper surface of the gate conductor and the second sidewall can not only reduce interfacial stress, but also reduce the resistance of the gate conductor and the second sidewall surface, thereby improving the performance of the semiconductor device.

[0019] Furthermore, during the semiconductor device manufacturing process, gate dielectric layers of different thicknesses are formed in the first and second regions using a photomask. In subsequent steps, the same photomask can be used to etch the outer oxide layer in the first sidewall of the second region, facilitating the subsequent formation of the oxygen-nitrogen-polysilicon (-metal polysilicon) material structure of the second sidewall. By reusing the same photomask, no additional photomasks are required during the manufacturing process, reducing the cost of device manufacturing. Attached Figure Description

[0020] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0021] Figure 1 A schematic diagram of the structure of a semiconductor device in the prior art is shown;

[0022] Figure 2 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention is shown;

[0023] Figure 3 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown;

[0024] Figures 4a to 4m Cross-sectional views of each stage of a method for manufacturing a semiconductor device according to an embodiment of the present invention are shown;

[0025] Figure 5 An embodiment of the present invention is shown. Figure 4g Corresponding electron microscope image;

[0026] Figures 6a to 6c An embodiment of the present invention is shown. Figure 4g , Figure 4i , Figure 4k The corresponding magnified view of a part of the device. Detailed Implementation

[0027] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. The present application may be presented in various forms, some of which will be described below.

[0028] This application may be presented in various forms, some of which will be described below.

[0029] Figure 2 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention is shown.

[0030] Semiconductor device 100 may be, for example, a power management integrated circuit (PMIC), but is not limited thereto; it may also be an N-channel logic field-effect transistor (NLDJFET), an AC-DC integrated chip, a BCD transistor (Bipolar-CMOS-DMOS), etc. In this embodiment, semiconductor device 100 is, for example, a power management chip, and the technical solution will be described accordingly below.

[0031] like Figure 2 As shown, the semiconductor device 100 includes a first region and a second region. The first region includes, for example, multiple ultra-high voltage devices, and the second region includes, for example, multiple medium- and low-voltage devices. Specifically, the semiconductor device 100 includes a semiconductor layer 110, multiple first doped regions 112 and multiple second doped regions 113 located in and near the surface of the semiconductor layer 110, a first gate dielectric layer 122 located in the first region of the semiconductor layer 110, a second gate dielectric layer 121 located in the second region of the semiconductor layer 110, a second gate structure located on the second gate dielectric layer 121, a first gate structure located on the first gate dielectric layer 122, and an insulating layer on the gate dielectric layer and the gate structure. Figure 2 (Not shown in the diagram) and multiple conductive channels penetrating the insulating layer and connected to the gate structure. Multiple first doped regions 112 located in the first region of the semiconductor layer 110 serve as the source and drain regions of multiple transistor devices in the first region of the semiconductor device 100, and multiple second doped regions 113 located in the second region of the semiconductor layer 110 serve as the source and drain regions of multiple transistor devices in the second region of the semiconductor device 100. The multiple conductive channels are respectively connected to the source region, drain region, and gate structure to serve as lead-out structures.

[0032] The semiconductor layer 110 may be composed of any one of a doped semiconductor substrate, a doped well region, and a doped epitaxial semiconductor layer. For example, for an N-type MOSFET, the semiconductor layer 110 is P-type doped; for a P-type MOSFET, the semiconductor layer 110 is N-type doped.

[0033] In this embodiment, multiple first doped regions 112 are located, for example, in the semiconductor layer 110 of the first region of the semiconductor device 100, and multiple second doped regions 113 are located, for example, in the semiconductor layer 110 of the second region of the semiconductor device 100. The first doped regions 112 and the second doped regions 113 serve as the source and drain regions of transistors in the first and second regions, respectively. The semiconductor layer 110 of the first region is, for example, of a first doping type, and the first doped regions 112 are, for example, of a second doping type. The semiconductor layer 110 of the second region is, for example, of a second doping type, and the second doped regions 113 are, for example, of a first doping type. However, this is not a limitation, and corresponding settings can be made according to the actual device. The first doping type and the second doping type are opposite doping types; the first doping type is, for example, one of N-type and P-type, and the second doping type is the other of N-type and P-type.

[0034] The semiconductor device 100 is divided into two regions based on the different voltage ratings of the transistors. The required thickness of the gate dielectric layer differs for the transistors in each region. In this embodiment, for example, the voltage rating of the transistors in the first region is higher than that in the second region; therefore, the thickness of the first gate dielectric layer 122 in the first region is greater than the thickness of the second gate dielectric layer 121 in the second region. The first gate dielectric layer 122 and the second gate dielectric layer 121 are used to isolate the active region from the gate structure in the semiconductor device 100. The gate dielectric layer is, for example, composed of silicon oxide.

[0035] In the first region, the first gate structure includes a gate conductor 131 and a first sidewall 132, with the first sidewall 132 located on the side surface of the gate conductor 131. In the second region, the second gate structure includes a gate conductor 131 and a second sidewall 135. The gate conductor 131 is, for example, composed of doped polysilicon, and a layer of metal silicide may be included on the upper surface of the gate conductor 131. The first sidewall 132 and the second sidewall 135 have different compositions. Specifically, the first sidewall 132 is a three-layer material structure of oxide-nitride-oxide (ONO), while the second sidewall 135 includes a field plate, which is a three-layer material structure of oxide-nitride-polysilicon (ON-poly), with the polysilicon layer serving as the field plate. Furthermore, the second sidewall 135 can also be a four-layer material structure of oxide-nitride-polysilicon-metal silicide (ON-poly-polycide), where the metal silicide is obtained, for example, by metallizing the polysilicon in the third layer of the second sidewall 135. In this case, the field plate is, for example, a polysilicon layer and a metal silicide layer. The first gate dielectric layer 122 and the second gate dielectric layer 121 are located between the gate structure and the semiconductor layer 110, and are used to isolate the active region in the semiconductor layer 110 from the gate conductor 131.

[0036] Furthermore, both the first and second regions include multiple conductive channels that penetrate the insulating layer, used to lead the source region, drain region, and gate conductor 131 of the transistor to the surface of the insulating layer. The multiple conductive channels include a first conductive channel 143, a second conductive channel 142, and a third conductive channel 141. The first conductive channel 143, for example, is connected to a portion of the first doped region 112 and a portion of the second doped region 113, which constitute the source region. The second conductive channel 142 is connected to the gate conductor 131. The third conductive channel 141 is connected to another portion of the first doped region 112 and another portion of the second doped region 113, which constitute the drain region. Additionally, if the surface of the gate conductor 131 has metal silicide, the second conductive channel 142 is connected to the metal silicide on the upper surface of the gate conductor 131. Furthermore, the second region also includes a fourth conductive channel 144 and a fifth conductive channel 145. The fourth conductive channel 144 is connected to the polysilicon or metal silicide on the surface of the second sidewall 135, i.e., the fourth conductive channel 144 is connected to the field plate of the second sidewall 135. The fifth conductive channel 145 is used to connect the third conductive channel 141 and the fourth conductive channel 144, so that the field plate in the second sidewall 135 in the second region is electrically connected to the second doped region 113, which serves as the drain region. This adjusts the channel current distribution between the source and drain regions below the field plate, thereby improving the device performance. In this embodiment, the multiple conductive channels are, for example, made of a metallic material.

[0037] Figure 3 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown; Figures 4a to 4m Cross-sectional views of each stage of a method for manufacturing a semiconductor device according to an embodiment of the present invention are shown; Figure 5 An embodiment of the present invention is shown. Figure 4g Corresponding electron microscope image; Figures 6a to 6c An embodiment of the present invention is shown. Figure 4g , Figure 4i , Figure 4k A magnified view of the corresponding device. (Reference) Figures 3 to 6c The method for manufacturing the semiconductor device of this application includes:

[0038] Step S110: A first oxide layer is formed on the semiconductor layer, and the first oxide layer in the second region is removed by a photomask.

[0039] like Figure 4a As shown, the method begins with semiconductor layer 110. In this step, a deposition process, such as physical vapor deposition or chemical vapor deposition, is used to deposit an oxide on the surface of semiconductor layer 110 to form a first oxide layer 123.

[0040] Furthermore, an etching process, such as dry etching (including ion milling, plasma etching, reactive ion etching, laser ablation), or wet etching or vapor phase etching, is employed to etch back the first oxide layer 123 of the second region using a mask 101, thereby exposing the surface of the semiconductor layer 110 in the second region and retaining only the first oxide layer 123 of the first region. Figure 4b and Figure 4c As shown.

[0041] In this embodiment, since the transistor devices in the first region and the second region have different requirements for the thickness of the gate dielectric layer, in this step, the surface of the semiconductor layer 110 in the first region has a first oxide layer 123 of a certain thickness, while the surface of the semiconductor layer 110 in the second region does not have a first oxide layer 123.

[0042] When etching back the first oxide layer 123 in the second region, the mask 101 used is, for example, a double-layer mask. In one embodiment, photolithography is used, where one layer of the double-layer mask is a photoresist layer (PR) that can block the entire surface of the semiconductor layer 110, and the other layer is an opaque 2E mask that blocks the surface of the first region of the semiconductor layer 110, thus preventing the first oxide layer 123 in the first region from being etched during the etching process. The mask of the present invention is not limited to this; any mask that can achieve the same purpose in other etching methods can be used.

[0043] Step S120: Form a second oxide layer on the semiconductor layer and the first oxide layer.

[0044] In this step, a deposition process, such as physical vapor deposition or chemical vapor deposition, is used to deposit oxides on the surfaces of the semiconductor layer 110 and the first oxide layer 123 to form a first gate dielectric layer 122 in the first region and a second gate dielectric layer 121 in the second region, as shown below. Figure 4d As shown.

[0045] In this embodiment, the material of the second oxide layer is the same as that of the first oxide layer 123, for example, a high-K material. Due to the presence of the first oxide layer 123 in the first region, after the second oxide layer is deposited, the thickness of the first gate dielectric layer 122 in the first region is greater than the thickness of the second gate dielectric layer 121 in the second region.

[0046] Step S130: A plurality of gate conductors are formed on the gate dielectric layer of the first region and the second region.

[0047] In this step, a deposition process, such as physical vapor deposition or chemical vapor deposition, is used to deposit polysilicon material on the surface of the semiconductor layer 110. After patterning and etching the polysilicon material, multiple gate conductors 131 are formed. Figure 4e As shown.

[0048] In this embodiment, the polysilicon material forming the gate conductor 131 is, for example, a doped polysilicon material.

[0049] Step S140: Form a third oxide layer, a nitride layer, and a fourth oxide layer on the surface of the semiconductor structure.

[0050] In this step, deposition processes, such as physical vapor deposition and chemical vapor deposition, are used to sequentially deposit oxide, nitride, and oxide on the surface of the semiconductor structure to form a third oxide layer 102, a nitride layer 103, and a fourth oxide layer 104, as shown below. Figure 4f As shown.

[0051] The semiconductor structure is, for example, an intermediate structure of a semiconductor device that has not completed all the steps. Here, the semiconductor structure refers to a structure having a semiconductor layer 110, a first gate dielectric layer 122, a second gate dielectric layer 121, and a plurality of gate conductors 131.

[0052] In this embodiment, both the first and second regions have a plurality of gate conductors 131, and the deposited third oxide layer 102, nitride layer 103 and fourth oxide layer 104 are conformal to maintain the same shape as the surfaces of the plurality of gate conductors 131.

[0053] Step S150: Etch back the third oxide layer, nitride layer and fourth oxide layer to form a first sidewall at the side surface of the gate conductor.

[0054] In this step, an etching process, such as dry etching (including ion milling, plasma etching, reactive ion etching, laser ablation), or wet etching or vapor phase etching, is used to etch back the third oxide layer 102, nitride layer 103, and fourth oxide layer 104. This removes the third oxide layer 102, nitride layer 103, and fourth oxide layer 104 from the upper surface of the gate conductor 131, a portion of the upper surface of the first gate dielectric layer 122, and a portion of the upper surface of the second gate dielectric layer 121, leaving only the third oxide layer 102, nitride layer 103, and fourth oxide layer 104 on the side surface of the gate conductor 131. The remaining third oxide layer 102, nitride layer 103, and fourth oxide layer 104 form a first sidewall 132 on the side surface of the gate conductor 131. Figure 4g , Figure 5 As shown, Figure 6a yes Figure 4g A magnified view of a portion of the image.

[0055] In this embodiment, the first sidewall 132 is a three-layer structure of oxygen-nitrogen-oxygen (ONO), and the side surface of the first sidewall 132 is an arc surface. The upper end of the arc surface is located near the upper surface of the gate conductor 131, and the lower end is in contact with the surface of the gate dielectric layer.

[0056] Step S160: Remove the fourth oxide layer in the first sidewall of the second region using a mask template.

[0057] In this step, an etching process, such as dry etching (including ion milling, plasma etching, reactive ion etching, laser ablation), or wet etching or vapor phase etching, is used to etch back the fourth oxide layer 104 in the first sidewall 132 of the second region through a mask 101. This removes the fourth oxide layer 104 from the first sidewall 132 of the second region, exposing the surface of the nitride layer 103. Figure 4h and Figure 4i and Figure 6b As shown.

[0058] In this embodiment, after removing the fourth oxide layer 104 of the first sidewall 132 in the second region, the sidewall in the second region becomes an oxide-nitride (ON) bilayer structure. Furthermore, the mask 101 used in removing the fourth oxide layer 104 in the second region is the same as the mask used in step S110 when removing the first oxide layer 123 on the surface of the semiconductor layer 110 in the second region, thereby eliminating the need for one etching mask and reducing costs.

[0059] Step S170: Deposit a polycrystalline silicon layer on the surface of the semiconductor structure.

[0060] In this step, a deposition process, such as physical vapor deposition or chemical vapor deposition, is used to deposit a polycrystalline silicon layer 105 on the surface of the semiconductor structure. Figure 4j As shown.

[0061] In this embodiment, a polysilicon layer 105 covers the surface of the semiconductor structure, so that a polysilicon layer 105 also covers the surface of the nitride layer 103 on the sidewall of the second region.

[0062] Step S180: Etch back the polysilicon layer to expose the first sidewall of the first region and form the second sidewall in the second region.

[0063] In this step, an etching process, such as dry etching (including ion milling, plasma etching, reactive ion etching, laser ablation), or wet etching or vapor phase etching, is used to etch back the polysilicon layer 105 to expose the first sidewall 132 in the first region and form the second sidewall 135 in the second region. Figure 4k As shown, Figure 6c yes Figure 4k A magnified view of a portion of the image.

[0064] In this embodiment, when the polysilicon layer 105 is etched back, the removal speed of the polysilicon layer 105 deposited there is slow due to the surface shape of the sidewall in the second region. As a result, after the polysilicon layer 105 in other regions is removed to expose the surface of the first gate dielectric layer 122, the upper surface of the gate conductor 131, the first sidewall 132 in the first region, and the surface of the first gate dielectric layer 122 and the upper surface of the gate conductor 131 in the second region, there is still a portion of the polysilicon layer 105 on the surface of the nitride layer 103 of the sidewall in the second region, thereby forming the second sidewall 135 of the oxide-nitride-polysilicon three-layer structure in the second region.

[0065] Step S190: Ion implantation is performed on the semiconductor layer to form source and drain regions in the semiconductor layer, and metal silicide is formed on the surface of the gate conductor and the surface of the second sidewall.

[0066] In this step, an ion implantation process is used to form a first doped region 112 and a second doped region 113 in the semiconductor layer 110 corresponding to the first sidewall 132 and the second sidewall 135, and a silicide process is used to convert the exposed polysilicon surfaces in the first and second regions into metal silicides 106. Figure 4l As shown.

[0067] In this embodiment, the semiconductor layer 110 is doped with a first doping type and a second doping type using an ion implantation process to form a first doped region 112 and a second doped region 113. The first doped region 112 can serve as the source and drain regions of multiple transistors in the first region of the semiconductor device 100, and the second doped region 113 can serve as the source and drain regions of multiple transistors in the second region of the semiconductor device 100. Optionally, the first doping type is, for example, N-type doping, and the second doping type is, for example, P-type doping. N-type doping particles can be, for example, phosphorus, arsenic, antimony, etc.; P-type doping particles can be, for example, boron, germanium, indium, etc.

[0068] Furthermore, during the process of converting polysilicon into metal silicides, the exposed surfaces of the polysilicon can react with metal raw materials (such as titanium, cobalt, nickel, etc.) to generate metal silicides. Specifically, metal silicides are formed on the upper surface of the gate conductor 131 in the first region, the upper surface of the gate conductor 131 in the second region, and the side surface of the polysilicon layer in the second sidewall of the second region.

[0069] Step S200: Deposit an insulating layer and form a first conductive channel to a fifth conductive channel through the insulating layer.

[0070] In this step, a deposition process, such as physical vapor deposition or chemical vapor deposition, is used to deposit an insulating material on the surface of the semiconductor structure to form an insulating layer (not shown in the figure). Then, an etching process is used to form a first conductive channel 143, a second conductive channel 142, a third conductive channel 141, a fourth conductive channel 144, and a fifth conductive channel 145 penetrating the insulating layer. Figure 4m As shown.

[0071] In this embodiment, the first conductive channel 143 is, for example, a conductive channel of the source region, the third conductive channel 141 is, for example, a conductive channel of the drain region, and the second conductive channel 142 is, for example, a conductive channel of the gate conductor 131. The bottoms of the first conductive channel 143 and the third conductive channel 141 also penetrate the gate dielectric layer and contact the first doped region 112 and the second doped region 113 in the semiconductor layer 110 to form lead-out conductive channels for the source and drain regions of the transistor.

[0072] Furthermore, the second region also includes a fourth conductive channel 144 and a fifth conductive channel 145. The bottom of the fourth conductive channel 144 is in contact with the surface of the polysilicon or metal silicide portion of the second sidewall 135, while the fifth conductive channel 145 is located on the surface of the insulating layer and is used to connect the third conductive channel 141 and the fourth conductive channel 144 in the second region, so that the field plate of the second sidewall 135 is connected to the drain region, thereby optimizing the channel current distribution between the source region and the drain region below the field plate.

[0073] According to the semiconductor device of the present invention, the structure of the second sidewall in the second region is improved from the traditional oxygen-nitrogen-oxygen material structure to an oxygen-nitrogen-polysilicon material structure. The polysilicon layer in the second sidewall serves as a field plate, and the third conductive channel leads out the drain of the semiconductor device. The fourth conductive channel leads out the polysilicon of the second sidewall in the second region, and the third and fourth conductive channels in the second region are connected by a fifth conductive channel. This realizes the connection between the field plate and the drain of the second sidewall in the transistor of the second region, which not only optimizes the electric field distribution of the channel between the source and drain terminals below the field plate and increases the withstand voltage of the device, but also does not increase the size of the semiconductor device.

[0074] Furthermore, forming metal silicides on the polysilicon surface of the upper surface of the gate conductor and the second sidewall can not only reduce interfacial stress, but also reduce the resistance of the gate conductor and the second sidewall surface, thereby improving the performance of the semiconductor device.

[0075] Furthermore, during the semiconductor device manufacturing process, gate dielectric layers of different thicknesses are formed in the first and second regions using a photomask. In subsequent steps, the same photomask can be used to etch the outer oxide layer in the first sidewall of the second region, facilitating the subsequent formation of the oxygen-nitrogen-polycrystalline silicon (-metal silicide) material structure of the second sidewall. By reusing the same photomask, no additional photomasks are required during the manufacturing process, reducing the cost of device manufacturing.

[0076] As described above, these embodiments of this application do not exhaustively cover all details, nor do they limit the application to merely the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor device comprising a first region and a second region, the second region comprising a plurality of transistors, each of the transistors comprising: A semiconductor layer and source and drain regions, wherein the source and drain regions are located in the semiconductor layer and close to the surface; A second gate dielectric layer is located on the surface of the semiconductor layer; A gate conductor is located on the second gate dielectric layer; The second sidewall is located on the second gate dielectric layer on the side surface of the gate conductor, and the second sidewall is a structure comprising at least three layers including oxide-nitride-polysilicon; as well as Multiple conductive channels are respectively connected to the source and drain regions, the gate conductor, and the second sidewall to serve as lead-out structures. In this configuration, the polycrystalline silicon layer in the second sidewall is a field plate, and the conductive channels of the field plate are connected to the conductive channels of the drain region.

2. The semiconductor device according to claim 1, wherein, The material of the second sidewall includes oxide-nitride-polysilicon-metal silicide.

3. The semiconductor device according to claim 1 or 2, wherein, The plurality of conductive channels include: A first conductive channel is connected to the source region; A second conductive channel is connected to the gate conductor; A third conductive channel is connected to the drain region; The fourth conductive channel is connected to the field plate of the second side wall; The fifth conductive channel connects the third conductive channel and the fourth conductive channel.

4. A method for manufacturing a semiconductor device, the semiconductor device comprising a first region and a second region, the manufacturing method comprising: A first gate dielectric layer and a second gate dielectric layer are formed on a semiconductor layer, wherein the first gate dielectric layer is located on the semiconductor layer in a first region and the second gate dielectric layer is located on the semiconductor layer in a second region; A plurality of gate conductors are formed on the first gate dielectric layer and the second gate dielectric layer; A first sidewall is formed on the semiconductor structure, the first sidewall being located on the side surface of the gate conductor; The second sidewall is formed by etching back the first sidewall of the second region; Source and drain regions are formed in the semiconductor layer; as well as Multiple conductive channels are formed that are respectively connected to the source and drain regions, the gate conductor, and the second sidewall. The second sidewall includes a field plate, and the conductive channels of the field plate are connected to the conductive channels of the drain area.

5. The manufacturing method according to claim 4, wherein, The steps for forming a first sidewall on a semiconductor structure include: A third oxide layer, a nitride layer, and a fourth oxide layer are sequentially deposited on the semiconductor structure. The third oxide layer-nitride layer-fourth oxide layer is etched back to remove the third oxide layer-nitride layer-fourth oxide layer from a portion of the surface of the first gate dielectric layer, a portion of the surface of the second gate dielectric layer, and the surface of the gate conductor. The remaining third oxide layer-nitride layer-fourth oxide layer at the side surface of the gate conductor forms a first sidewall.

6. The manufacturing method according to claim 5, wherein, The steps of forming the second sidewall after etching back the first sidewall of the second region include: A mask template is used to etch back the first sidewall in the second region to remove the fourth oxide layer in the first sidewall; Deposit a polycrystalline silicon layer on the surface of a semiconductor structure; The polysilicon layer is etched back to remove the polysilicon layer on the surface of the first gate dielectric layer, the surface of the second gate dielectric layer, the surface of the first sidewall, and the surface of the gate conductor. The oxide-nitride layer at the sidewall of the second region and the remaining polysilicon layer form the second sidewall.

7. The manufacturing method according to claim 6, wherein, Between the steps of forming source and drain regions in the semiconductor layer and forming a plurality of conductive channels respectively connected to the source and drain regions, the gate conductor, and the second sidewall, the method further includes: Metal silicides are formed on the surface of the gate conductor and the surface of the second sidewall.

8. The manufacturing method according to claim 6, wherein, The steps of forming a first gate dielectric layer and a second gate dielectric layer on the semiconductor layer include: A first oxide layer is formed on the semiconductor layer, and the first oxide layer in the second region is removed using a photomask. A second oxide layer is formed on the first oxide layer and the semiconductor layer, wherein the first oxide layer and the second oxide layer in the first region constitute the first gate dielectric layer, and the second oxide layer in the second region constitutes the second gate dielectric layer.

9. The manufacturing method according to claim 8, wherein, The same mask is used in the step of removing the first oxide layer in the second region and in the step of etching back the first sidewall in the second region.

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