Electronic device having power transistor including buried shield and gap region and method of making same

Abstract

An electronic device may include a buried shield (426) and a gap region (452). The electronic device may include a body contact region (1826), a deep body region (1046), or both. The deep body region may be separated from the gap interval and does not cause RSP reduction. The combination of the body contact region and the deep body region may form a stepped conductive structure to couple the buried shield and the source terminal to each other. In one implementation, a body contact region, a deep body region, or another p-type doped region may be spaced from a gate member (2930) by at least a minimum distance to improve long term reliability of a gate dielectric layer (2814). When designing an electronic device, the minimum distance may be applied as a design rule.

Description

Technical Field

[0001] This disclosure relates to electronic devices and methods, and more specifically to electronic devices having power transistors including buried shielding and gap regions, and methods for fabricating the same. Background Technology

[0002] Transistors can be designed to operate at relatively high voltages and high currents. Some semiconductor materials, such as single-crystal Si, may not be able to operate at such high voltages and currents, or may require complex designs to withstand the high voltages and currents during operation. Wide-bandgap semiconductors, such as SiC, can be used in transistors that operate at high voltages and high currents. Power transistors can have relatively high electric fields in the region near the main surface of the substrate. Scaling transistors to smaller sizes while maintaining acceptable drain-to-source punch-through voltages and long-term gate dielectric reliability can be challenging. Further improvements in power transistors are expected. Attached Figure Description

[0003] The accompanying drawings illustrate specific embodiments by way of example, but the embodiments are not limited to the drawings.

[0004] Figure 1 The illustration includes a cross-sectional view of a portion of a workpiece, which includes a substrate comprising a semiconductor substrate material and a semiconductor layer.

[0005] Figure 2 Including the mask components that form the buried shield mask. Figure 1 A top-view illustration of this part of the workpiece.

[0006] Figures 3 to 6 This includes the deep portion after the formation of the buried shield and source region. Figure 2 A cross-sectional view of the workpiece.

[0007] Figure 7 Including after the formation of the deep body mask Figures 3 to 6 A top-view illustration of this part of the workpiece.

[0008] Figures 8 to 11 This includes the formation of the deep host region, removal of the deep host mask, and the formation of the carrier distribution layer and carrier accumulation region. Figure 7 A cross-sectional view of the workpiece.

[0009] Figures 12 to 15 Including the shallow portions following the formation of the main region and the source region. Figures 8 to 11 A cross-sectional view of the workpiece.

[0010] Figure 16 Including after the formation of the main contact mask Figures 12 to 15A top-view illustration of this part of the workpiece.

[0011] Figures 17 to 20 Including after the formation of the main contact area and the removal of the main contact mask. Figure 16 A cross-sectional view of the workpiece.

[0012] Figure 21 Including after the formation of the gate trench mask Figures 17 to 20 A top-view illustration of the workpiece.

[0013] Figures 22 to 25 This includes patterning the substrate to define the gate trench and removing the gate trench mask. Figure 21 A cross-sectional view of the workpiece.

[0014] Figure 26 This includes the mask components after forming the gate dielectric layer, gate conductive layer, and gate mask. Figures 22 to 25 A top-view illustration of the workpiece.

[0015] Figures 27 to 30 Including after the formation of the gate component and the removal of the mask component of the gate mask. Figure 26 A cross-sectional view of the workpiece.

[0016] Figure 31 include Figures 27 to 30 A top-view illustration of a portion of the workpiece to illustrate the minimum distance between the body contact area and the gate component.

[0017] Figure 32 include Figures 27 to 30 A perspective view of the workpiece corresponding to a portion of a unit cell.

[0018] Figure 33 Including after forming the interlayer dielectric layer and the contact mask. Figures 27 to 30 A top-view illustration of the workpiece.

[0019] Figures 34 to 37 Including after removing the contact mask and after forming the source extremum Figure 33 A cross-sectional view of the workpiece.

[0020] Figure 38 The illustration includes a cross-sectional view of a transistor structure to illustrate majority carrier flow from the source region to the semiconductor layer via the gap region.

[0021] Those skilled in the art will recognize that the elements in the accompanying drawings are shown for purposes of brevity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be enlarged relative to other elements to aid in an understanding of specific embodiments of the inventive concept. Detailed Implementation

[0022] The following description, in conjunction with the accompanying drawings, is provided to aid in understanding the teachings disclosed herein. The following description will focus on specific implementations of the teachings. This focus is provided to aid in describing the teachings and should not be construed as limiting the scope or applicability of the teachings. However, other implementations may be adopted based on the teachings disclosed in this application.

[0023] As used in this specification, length and width are measured along or parallel to the main surface of the substrate or semiconductor layer. Depth, height, and thickness are measured in a direction perpendicular to the main surface of the substrate or semiconductor layer.

[0024] The term "electrical coupling" is intended to refer to the connection, link, or association of two or more electronic components, circuits, systems, or any combination of the following: (1) at least one electronic component, (2) at least one circuit, or (3) at least one system, in such a way that a signal (e.g., a current, voltage, or optical signal) can be transferred partially or completely from one to the other. A subset of "electrical coupling" may include an electrical connection between two electronic components. In a circuit diagram, a node corresponds to an electrical connection between electronic components. Thus, an electrical connection is a specific type of electrical coupling; however, not all electrical couplings are electrical connections. Other types of electrical coupling include capacitive coupling, resistive coupling, and inductive coupling.

[0025] The terms "horizontal," "lateral," and their variations refer to directions along or parallel to the main surface of the substrate or semiconductor layer, while the terms "vertical," "height," "depth," and their variations refer to directions perpendicular to the main surface of the substrate or semiconductor layer. Two objects laterally offset may be at the same or different heights.

[0026] The term "metal" or any variation thereof is intended to refer to materials including elements in any of Groups 1 through 12, or in Groups 13 through 16, along or below the lines defined by atomic numbers 13 (Al), 31 (Ga), 50 (Sn), 51 (Sb), and 84 (Po). Neither Si nor Ge are metals.

[0027] The terms "normal operation" and "normal operating conditions" refer to the conditions under which an electronic component or device is designed to operate. These conditions can be obtained from datasheets or other information regarding voltage, current, capacitance, resistance, or other electrical conditions. Therefore, normal operation does not include operating an electronic component or device outside its design limits.

[0028] The terms "overlapping," "underlapping," and variations thereof refer to at least a portion of a region or other feature positioned along a vertical line perpendicular to the plane defined by the main surface. Components or features that are overlapped or underlapped may or may not be in physical contact with each other.

[0029] The term "power transistor" is intended to refer to a transistor with a drain-to-source breakdown voltage (BV) of at least 400V. DS ) transistors.

[0030] Unless explicitly stated otherwise, the boundary between a relatively heavy doped region or layer and an adjacent, relatively light doped region or layer with the same conductivity type is the location where the dopant concentration between these regions or layers is 1.1 times higher than the peak dopant concentration of the relatively light doped region or layer.

[0031] The terms “on,” “overlay,” and “above” can be used to indicate that two or more elements are in direct physical contact with each other. However, “above” can also mean that two or more elements are not in direct contact with each other. For example, “above” can mean that one element is on top of another element, but the elements are not in contact with each other and there may be another element or one other element between the two elements.

[0032] The terms “comprising,” “including,” “having,” “containing,” or any other variations thereof are intended to cover non-exclusive inclusion. For example, a method, article, or apparatus that includes a list of features is not necessarily limited to those features, but may include other features not expressly listed or inherent to such a method, article, or apparatus. Furthermore, unless expressly stated to the contrary, “or” means inclusive or, not exclusive, or. For example, condition A or B is satisfied by any of the following: A is true (or exists) and B is false (or does not exist); A is false (or does not exist) and B is true (or exists); and both A and B are true (or exist).

[0033] Furthermore, the use of "a" or "an" when describing elements, components, or other features described herein is merely for convenience and to give a general meaning regarding the scope of the inventive concept. The description should be considered to include one (a), at least one (a), or the singular form includes the plural form and vice versa, unless the opposite is explicitly stated. For example, when describing a single item herein, "more than one" may be used instead of "single item." Similarly, in cases where more than one item is described herein, "single item" may be used instead of "more than one item."

[0034] The use of the terms "about," "approximately," or "basically" is intended to indicate that the value of a parameter is close to the specified value or position. However, slight differences can prevent the value or position from being exactly as specified. Therefore, from the ideal goal of being exactly as described, a difference of up to ten percent (10%) for the value (and up to twenty percent (20%) for the semiconductor doping concentration) is a reasonable difference.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which these inventive concepts pertain. Materials, methods, and examples are illustrative only and are not intended to be limiting. Where not described herein, many details regarding specific materials and processing actions are conventional and can be found in textbooks and other sources in the semiconductor and electronics fields.

[0036] An electronic device may include a buried shield electrically coupled to a body contact region and a defined gap region. The electronic device may include a deep body region spaced apart from the gap region, such that a good conduction state specific resistance R can be maintained. SP The combination of the main contact area and the deep main area can form a stepped conductive structure.

[0037] The most common p-type dopant used in SiC is Al, while the most common p-type dopant used in Si is B. The presence of Al near the gate dielectric layer, where too much Al migrates, can pose reliability problems. These problems are not a concern with B. Besides Al, reliability issues can also extend to one or more other metallic elements with an atomic number of at least 13.

[0038] In one specific implementation, one or more relatively heavily doped regions may be located at a minimum distance from the gate element. (For now, please refer to the following text.) Figure 31 and Figure 32 The gate member 2930 may include a gate electrode 2934 and an intermediate portion 2936. The dashed line 3230 indicates the minimum distance that a relatively heavily doped p-type region should be spaced from the gate member. Figure 31 The minimum distance along the main surface of the substrate is illustrated, and Figure 32 This illustrates the minimum distance extending from the host surface into the substrate. As described later in this specification, design rules regarding the minimum distance can be triggered by a threshold dopant concentration. The minimum distance may or may not vary with dopant concentration. Relatively higher dopant concentrations can result in a larger minimum distance compared to relatively lower dopant concentrations. These concepts are better understood with reference to the accompanying drawings and the following description.

[0039] In one aspect, an electronic device may include: a substrate defining a gate trench having sidewalls and extending from a main surface of the substrate to a depth of the gate trench, wherein the substrate includes a semiconductor layer having a first conductivity type; a body region having a second conductivity type opposite to the first conductivity type; a body contact region having the second conductivity type; a buried shield having the second conductivity type and a peak dopant concentration, wherein the buried shield is stacked below the gate trench; a deep body region having the second conductivity type and a peak dopant concentration, wherein the peak dopant concentration of the deep body region is greater than the peak dopant concentration of the buried shield; a gate dielectric layer located within the gate trench; and a gate member including a portion extending into the gate trench. In a direction perpendicular to the main surface, the deep body region may be located between the body region and the buried shield, and the body region may be spaced apart from the gate member along a portion of the sidewall of the gate trench and by the gate dielectric layer. The gate member may not be stacked on top of the body contact region, and the gate member may be stacked on top of the deep body region and separated from the deep body region by the body region.

[0040] In another aspect, an electronic device may include: a substrate defining a gate trench extending from a main surface of the substrate to a depth of the gate trench, wherein the substrate includes a semiconductor layer having a first conductivity type; a body contact region having a second conductivity type opposite to the first conductivity type; a buried shield having a second conductivity type and a peak dopant concentration, wherein the buried shield is stacked below the gate trench; a gap region having a first conductivity type, wherein the gap region is at least partially defined by the buried shield; and a deep body region having a second conductivity type and a peak dopant concentration. The body contact region, the buried shield, and the deep body region are electrically coupled to each other, the deep body region may not be stacked above the gap region, the deep body region may be spaced apart from the main surface of the substrate, and the peak dopant concentration of the deep body region may be greater than the peak dopant concentration of the buried shield.

[0041] In another aspect, a method of forming an electronic device may include determining a minimum distance between a gate member and a doped region within a SiC material, wherein the doped region has a dopant that is a metallic element with an atomic number of at least 13, and the doped region has a minimum distance of 5 × 10⁻⁶. 18 atoms / cm 3 The peak dopant concentration. The method may further include forming a buried shield within a SiC layer of a substrate, wherein the SiC layer has a first conductivity type and the buried shield has a second conductivity type opposite to the first conductivity type; forming a host region within the SiC layer, wherein the host region has a second conductivity type and less than 5 × 10⁻⁶. 18 atoms / cm 3The peak dopant concentration; forming a host contact region within the SiC layer, wherein the host contact region has a second conductivity type and at least 5 × 10⁻⁶. 18 atoms / cm 3 The peak dopant concentration is determined, and the body contact region is electrically coupled to the buried shield; the substrate is patterned to define a gate trench having sidewalls and extending from the main surface of the substrate to the depth of the gate trench; and a gate member is formed, the gate member including a portion extending into the gate trench. The gate member may be spaced apart from the body region by a body distance less than a minimum distance, and spaced apart from the body contact region by a body contact distance of at least a minimum distance.

[0042] In the following description, the doped layer and doped region are described with respect to dopant concentration and depth, as well as vertical position (in a direction perpendicular to the main surface), length, and width (along the main surface or in a plane parallel to the main surface). Those skilled in the art will be able to perform simulations to determine the dose and energy to be used during doping to achieve the doped layer and doped region in the final device.

[0043] Figure 1 The diagram includes a cross-sectional view of a portion of workpiece 200, which includes a substrate 220. This substrate may include a semiconductor substrate material 232 and a semiconductor layer 234. The semiconductor substrate material 232 may be a single-crystal semiconductor wafer, a semiconductor-on-insulator (SOI) wafer, etc. The semiconductor substrate material 232 and the semiconductor layer 234 may include a wide-bandgap semiconductor material, and in a particular embodiment, SiC is the semiconductor material within the semiconductor layer 234, and is the semiconductor material within at least that portion of the semiconductor substrate material 232 that contacts the semiconductor layer 234. In one embodiment, SiC may be a 3C, 4H, or 6H polytype.

[0044] The semiconductor material within the semiconductor substrate 232 can be the drain region of a power transistor and has at least 1×10⁻⁶ Ω·cm. 18 atoms / cm 3 The dopant concentration. In a specific implementation, the dopant concentration may be at least 1 × 10⁻⁶. 19 atoms / cm 3 This ensures ohmic contact with the drain electrode subsequently attached to or formed along the back-side main surface 222. The semiconductor substrate material 232 may have a maximum of 2 × 10⁻⁶ ohms. 21 atoms / cm 3 The peak dopant concentration. The semiconductor material within the semiconductor substrate 232 can be n-type doped or p-type doped. The majority carriers of the power transistor can be electrons, and the semiconductor material can be n-type doped. In this specification, the n-type dopant can be N or P, and the p-type dopant can be Al.

[0045] Semiconductor layer 234 can be epitaxially grown and doped during or after growth. Semiconductor layer 234 can have a thickness ranging from 4.0 μm to 20.0 μm. Semiconductor layer 234 can have the same conductivity type as the semiconductor material within semiconductor substrate material 232. In one embodiment, semiconductor layer 234 is n-type doped. Semiconductor layer 234 can be a drift region of a power transistor and has a lower dopant concentration compared to the semiconductor material within semiconductor substrate material 232. The average dopant concentration of semiconductor layer 234 can be 2 × 10⁻⁶. 15 atoms / cm 3 Up to 4×10 16 atoms / cm 3 Within the range. Before any further doping, such as for the host region or source region, the average dopant concentration of semiconductor layer 234 is referred to herein as the original dopant concentration of semiconductor layer 234.

[0046] One or more epitaxial layers may be grown between the semiconductor substrate material 232 and the semiconductor layer 234. These additional layers can serve a variety of functions, including providing a transition buffer at the start of epitaxial growth, isolating crystal defects from the semiconductor layer 234, or improving stability under high-current operation (i.e., improving the safe operating region). In these foregoing cases, the additional layers typically have a higher doping concentration than the semiconductor layer 234, resulting in lower resistivity due to their higher doping concentration, and providing little additional benefit in terms of blocking voltage.

[0047] Figure 2The image includes a top view of a buried shielding mask, which includes mask member 306. Mask member 306 corresponds to the location where the gap region will be formed. In the finished power transistor structure, electrons can flow through the gap region when the power transistor is turned on. In this specification, some masks will be described as hard masks, such as the buried shielding mask described here. Other masks will be described as photoresist masks. In a hard mask, a pattern is first defined in a photoresist, and then the pattern is transferred to an underlying mask layer by etching. This mask layer comprises a single or multiple films made of oxides, nitrides, polycrystalline silicon, or similar materials. This type of mask is called a hard mask because it can withstand higher processing temperatures than photoresist, which is often required when performing ion implantation into SiC. The need for high-temperature ion implantation (e.g., above room temperature, or 20°C to 25°C) increases with both the energy and the dose of the implanted material. Depending on the injection conditions, photoresist masks and hard masks can sometimes be used interchangeably. Therefore, the use of photoresist masks or hard masks in this specification is for illustrative purposes only and should not be construed as limiting the invention.

[0048] The power transistor being formed comprises many unit cells, wherein one of the unit cells 300 is in Figure 2 The identifier is in the middle. Many other unit cells exist, but are not listed here. Figure 2 The unit cells immediately to the right, left, above, and below unit cell 300 are mirror images of unit cell 300. Locations not covered by masking member 306 will be injected to form a buried shield.

[0049] Figures 3 to 6 A cross-sectional view of the workpiece 200, including a portion of the substrate 220, after the formation of the buried shield 426 and the deep portion 436 of the source region. Figure 3 It is along Figure 2 Section line A in the middle, Figure 4 It is along Figure 2 Section line B in the middle, Figure 5 It is along Figure 2 Section line C in the middle, and Figure 6 It is along Figure 2 Section line D in the middle.

[0050] In this specification, doping of each layer or region may be performed as a single ion implantation or as multiple ion implantations, wherein each ion implantation is performed at an energy different from one or more other ion implantations within the multiple ion implantations. After reading this specification, those skilled in the art will be able to determine, for each dopant (e.g., N (n-type), P (n-type), or Al (p-type)), the number, dose, and energy of ion implantations to achieve the desired doping depth and dopant concentration profile.

[0051] refer to Figures 3 to 6 The buried shield mask may include a relatively thin oxide layer 472, a polysilicon layer 474, and a relatively thick oxide layer 476. Of these three layers, the semiconductor layer 234 is closest to the relatively thin oxide layer 472 and furthest from the relatively thick oxide layer 476. The relatively thin oxide layer 472 may have a thickness ranging from 10 nm to 90 nm. In the same or different embodiments, the polysilicon layer 474 may have a thickness ranging from 30 nm to 300 nm. In the same or further different embodiments, the relatively thick oxide layer 476 may have a thickness ranging from 0.9 μm to 4.0 μm. The polysilicon layer 474 and the relatively thick oxide layer 476 may be patterned to form the mask member 306, and the relatively thin oxide layer 472 may remain unpatterned during implantation. The relatively thin oxide layer 472 may help reduce the likelihood of implantation channel effects within the single-crystal SiC when doping to form the buried shield 426. Furthermore, for SiC, higher doses of implantation can be performed at elevated temperatures to reduce implantation damage. Hard masks allow for ion implantation temperatures that conventional photoresist materials may not be able to withstand.

[0052] The buried shield 426 helps shield the subsequently formed gate electrode from the drain voltage of the power transistor and can be used to limit or reduce the saturation current of the power transistor during a short-circuit event. For some applications such as motor drives and traction inverters, the ability to survive short-circuit events on the order of several microseconds can be important. Limiting this current during a short-circuit event extends the lifespan of the power transistor. The mid-height line 424 is a case where half the thickness of the buried shield 426 is above the mid-height line 424 and the other half is below the mid-height line 424.

[0053] Compared to semiconductor layer 234, buried shield 426 has the opposite conductivity type. In one embodiment, buried shield 426 may be p-type doped. The peak dopant concentration of buried shield 426 may be the same as or different from the peak dopant concentration of the subsequently formed host region. In the same or different embodiments, the peak dopant concentration of buried shield 426 may be 8 × 10⁻⁶. 17 atoms / cm3 Up to 4.5×10 18 atoms / cm 3 Within the range. In the same or other specific implementations, the peak dopant concentration of the buried shield 426 may be located at a height ranging from 0.3 micrometers to 0.9 micrometers below the main surface 226.

[0054] Under normal operating conditions, the buried shield 426 may not be fully depleted during reverse bias. However, unlike the subsequently formed body region, which may affect the threshold voltage of the subsequently formed transistor, fewer electrical characteristics of the power transistor may depend on the buried shield 426. Therefore, the buried shield 426 may have a higher dopant concentration than the subsequently formed body region.

[0055] Compared to a source region excluding the deep portion 436, the deep portion 436 of the source region helps maintain a relatively low resistance in the source region. Relative to Figures 12 to 15 The shallow portion of the subsequently formed source region, described in more detail, essentially occupies the entire cell array of the power transistor. Unlike the shallow portion of the source region, the mask member 306 prevents the formation of the deep portion 436 across the entire cell array.

[0056] The deep portion 436 may have the same conductivity type as the semiconductor layer 234. In one specific embodiment, the deep portion 436 may be n-type doped. The deep portion 436 may have at least 5 × 10⁻⁶ Ω·cm. 18 atoms / cm 3 The peak dopant concentration. In one specific implementation, the deep portion 436 may have a peak dopant concentration of at least 1 × 10⁻⁶. 19 atoms / cm 3 The peak dopant concentration is set to ensure low resistance within the source region. In the same or different specific implementations, the peak dopant concentration can be up to 5 × 10⁻⁶. 20 atoms / cm 3 This allows for the formation of subsequently formed main contact regions, and these subsequently formed main contact regions are partially anti-doped with deep portions 436. In the same or different embodiments, the deep portions 436 may extend from the main surface 226 to a depth in the range of 0.1 micrometers to 0.4 micrometers. Figures 3 to 6 In the specific embodiment illustrated, the deep portions 436 are spaced apart and do not contact the main surface 226.

[0057] Ion implantation scattering allows some of the dopants in each of the deep portion 436 and the buried shield 426 to extend laterally beneath a portion of the mask member 306. The buried shield 426 can extend further beneath the mask member 306 than the deep portion 436 because the implantation energy for forming the buried shield 426 can be greater than that for forming the deep portion 436. Therefore, the buried shield 426 can be fully stacked beneath the deep portion 436.

[0058] The gap region 452 (between the dashed lines in the figure) is a region whose conductivity type corresponds to the majority carrier type of the power transistor (e.g., n-type when the majority carriers are electrons, or p-type when the majority carriers are holes), and is at least partially defined by the buried shield 426. The deep portion 436 of the source region does not extend into or overlap with any or all of the gap regions in the gap region 452. From a plan view, the gap region 452 has a conductivity type corresponding to the majority carrier type of the power transistor (e.g., n-type when the majority carriers are electrons, or p-type when the majority carriers are holes), and is at least partially defined by the buried shield 426. Figure 2 The shape of the mask member 306. Each gap region in the gap region 452 may have a length and a width, wherein the length is greater than the width. The width of the gap region 452 is in the range of 0.4 micrometers to 3.0 micrometers, as measured in a direction parallel to the main surface 226 and perpendicular to the depth of the gate trench subsequently formed. The unit cell 300 may include portions of two different gap regions 452.

[0059] In another embodiment, when the buried shield mask is a hard mask, a spacer can be formed along the mask member 306 after implantation of the buried shield 426 and before implantation of the deep portion 436 of the source region. The spacer can be formed by depositing any material described for the hard mask, followed by anisotropic etching such that a portion of the deposited film remains along the sidewalls of the hard mask. When subsequent implantation of the deep portion 436 of the source region is performed, the edge of the implanted region can be further spaced from the gap region 452 by a distance approximately equal to the width of the spacer along the substrate of the spacer. This spacer can be removed simultaneously with the removal of the hard mask.

[0060] In another specific implementation, different masks can be used to form the buried shield 426 and the deep portion 436 of the source region. (Similar to...) Figures 3 to 6 Compared to the illustrated specific implementation, the deep portion 436 may extend laterally further away from, closer to, or laterally into the gap region 452. The deep portion 436 does not span the entire extension of any or all gap regions 452. Drain-to-source breakdown voltage (BV) DS The improvement can be achieved by extending the deep portion 436 of the entire length of any or all gap regions not across gap region 452. (See reference...) Figures 3 to 6 From a top view, because the deep portion 436 occupies a smaller area, the BV... DSIt can only be increased to a certain extent, and further reduction of the area occupied by the deep portion 436 will not significantly increase BV. DS However, as the area continues to decrease, the resistance attributable to the source region may increase. Therefore, the area of ​​the deep portion 436 can only be reduced to BV. DS There was no further significant increase. After reading this specification, a technician will be able to run simulations to determine the acceptable BV of the power transistor occupied by the deep portion 436. DS The area of ​​the source resistance value.

[0061] After the buried shield 426 and the deep portion 436 of the source region are formed, the mask member 306 and any sidewall spacers can be removed. The relatively thin oxide layer 472 may or may not be removed at this point in the process.

[0062] A mask (not shown) is formed over workpiece 200. The active region of the transistor structure of the power transistor being formed is exposed. The mask covers the areas of the electronic components and circuitry outside the active region of the transistor structure. The doping concentration of the surface portion of semiconductor layer 234 is enhanced to form a structure as shown in the image. Figures 8 to 11 The illustrated carrier distribution layer 936 and carrier accumulation region 938.

[0063] Figure 8 Is along such Figure 7 The illustrated section line A, Figure 9 Is along such Figure 7 The illustrated section line B, Figure 10 Is along such Figure 7 The illustrated section line C, and Figure 11 Is along such Figure 7 The illustrated profile D shows that the formation of the carrier distribution layer 936 and the carrier accumulation region 938 can be performed in any order relative to each other.

[0064] The gap region 452 may include the portion between the carrier distribution layer 936 and the carrier accumulation region 938 located between portions of the buried shield 426. (As shown relative to...) Figure 38 In more detail, majority carriers can flow along the following path: through carrier accumulation region 938, around buried shield 426 into gap region 452, through carrier distribution layer 936, and into semiconductor layer 234. At least a portion of carrier distribution layer 936 may overlap with carrier accumulation region 938. In one embodiment, part or all of carrier distribution layer 936 may overlap with carrier accumulation region 938.

[0065] The boundary between the carrier distribution layer 936 and the carrier accumulation region 938 can be at any height within the unit cell 300, between the highest and lowest heights of the buried shield 426. In a particular embodiment, the boundary between the carrier distribution layer 936 and the carrier accumulation region 938 can be at or near the mid-height line 424.

[0066] On a relative basis, the peak dopant concentration of the buried shield 426 may be greater than the peak dopant concentration of each of the carrier distribution layer 936 and the carrier accumulation region 938. The peak dopant concentration of the carrier distribution layer 936 may be the same as or less than the peak dopant concentration of the carrier accumulation region 938.

[0067] The carrier accumulation region 938 facilitates the flow of majority carriers from the channel region of the transistor structure of the power transistor to the gap region 452. The carrier accumulation region 938 may be located between the subsequently formed body region and the buried shield 426. The carrier accumulation region 938 may extend at least partially within the gap region 452. The carrier accumulation region 938 may extend across all gap regions within the gap region 452 of the active region of the power transistor.

[0068] In one embodiment, the entire buried shield 426 overlaps with a portion of the carrier accumulation region 938; however, the buried shield 426 does not overlap with the entire carrier accumulation region 938. In the same or different embodiments, for a transistor structure array of power transistors, the buried shield 426 overlaps with at least 10% of the carrier accumulation region 938. As the overlap increases, the survivability in short-circuit events is improved. Therefore, the overlap can be at least 40% or at least 70%. When the overlap becomes too large, R... SP It may become higher than expected. In the same or different embodiments, the buried shield 426 overlaps with at most 99%, at most 98%, or at most 95% of the carrier accumulation region 938. In any of the foregoing or different embodiments, the buried shield 426 overlaps with the carrier accumulation region 938 in the range of 70% to 95%.

[0069] Under normal operating conditions, carrier accumulation region 938 may be completely depleted during reverse bias. In one specific implementation, carrier accumulation region 938 may be completely depleted when any or all of the gap regions 452 are not completely depleted.

[0070] In the finished device, the carrier accumulation region 938 may be located at a height of at least 0.3 micrometers below the main surface 226, and at a height of at most 1.5 micrometers below the main surface 226. The carrier accumulation region 938 may have a thickness (measured in the Z direction) in the range of 0.2 micrometers to 0.5 micrometers.

[0071] The peak dopant concentration in the carrier accumulation region 938 can reach 2 × 10⁻⁶. 17 atoms / cm 3 Up to 4×10 18 atoms / cm 3 Within the range. In the same or different specific implementations, the carrier accumulation region 938 may have a dopant concentration gradient, wherein the dopant concentration of the carrier accumulation region 938 at a location closer to the carrier distribution layer 936 is less than the dopant concentration of the carrier accumulation region 938 at different locations closer to the main surface 226.

[0072] The carrier distribution layer 936 can facilitate the redistribution of majority carriers along the flow path from the carrier accumulation region 938 through the gap region 452 to the semiconductor layer 234. The carrier distribution layer 936 may extend into the gap region 452. In one embodiment, the entirety of the buried shield 426 may overlap with a portion of the carrier distribution layer 936; however, the buried shield 426 does not overlap with the entirety of the carrier distribution layer 936. In the same or different embodiments, for a transistor structure array of power transistors, the buried shield 426 overlaps with at least 10% of the carrier distribution layer 936 located below the mid-height line 424. As the overlap increases, the ability to survive short-circuit events is improved. Therefore, the overlap can be at least 40% or at least 70%. When the overlap becomes too large, R SP It may become higher than expected. In the same or different embodiments, the buried shield 426 is superimposed on at most 99%, at most 98%, or at most 95% of the carrier distribution layer 936. In any of the foregoing or different embodiments, the buried shield 426 is superimposed on the carrier distribution layer 936 in the range of 70% to 95%.

[0073] The carrier distribution layer 936 has the same conductivity type as the semiconductor layer 234. When the majority carriers are electrons, the carrier distribution layer 936 can be n-type doped. Under normal operating conditions, the carrier distribution layer 936 may be completely depleted during reverse bias.

[0074] The carrier distribution layer 936 may have a peak dopant concentration greater than the average dopant concentration of the semiconductor layer 234. In one specific embodiment, the peak dopant concentration may be less than an order of magnitude higher than the average dopant concentration of the semiconductor layer 234. The carrier distribution layer 936 may have a peak dopant concentration of 4 × 10⁻⁶. 16 atoms / cm 3 Up to 8×10 17 cm 3 The peak dopant concentration is within a certain range. The peak dopant concentration of the carrier distribution layer 936 can be located at a height of 0.7 μm to 2.0 μm below the main surface 226.

[0075] In a specific implementation, the dopant concentration of the carrier distribution layer 936 may have a dopant concentration gradient, wherein the dopant concentration of the carrier distribution layer 936 at a location closer to the carrier accumulation region 938 is greater than the dopant concentration of the carrier distribution layer 936 at different locations closer to the semiconductor substrate material 232.

[0076] After the carrier distribution layer 936 and the carrier accumulation region are formed, the mask can be removed.

[0077] Figure 7 A top view including a deep body mask 800. The deep body mask 800 can be formed, and the deep body mask defines an opening 806 for a deep body region. The deep body mask 800 is stacked on top of a gap region 452. The gap region 452 is... Figure 7 The dashed lines in the diagram are used to illustrate the positional relationship between the gap region 452 and the opening 806, in order to provide a better understanding of this relationship.

[0078] The deep body mask 800 can have a shape that is different from the previous one. Figure 2 The mask component 306 described herein may have the same or different composition. In one embodiment, the deep body mask 800 may be made of an oxide layer similar to the relatively thick oxide layer 476 previously described, and therefore, the relatively thin oxide layer 472, polysilicon layer 474, or both may or may not be present. In another embodiment, the deep body mask 800 may be made of a photoresist.

[0079] Figures 8 to 11 This includes a cross-sectional view of the workpiece 200 after the deep body region 1046 has been formed and the deep body mask 800 has been removed. The deep body region 1046 electrically couples the buried shield 426 and the subsequently formed body contact area to each other. In one embodiment, the deep body region 1046 physically contacts the buried shield 426. The deep body region 1046 is spaced apart from and not located at the main surface 226. The deep body region 1046 is spaced apart from the gap regions 452 and does not extend into or overlap with these gap regions. The deep body region 1046 may extend to any depth within the buried shield 426. In one embodiment, the deep body region 1046 may extend from the main surface 226 to a depth in the range of 0.4 micrometers to 0.9 micrometers.

[0080] Each deep main body region 1046 may have a length and a width, wherein the length is greater than the width. The length of the deep main body region 1046 is along a line in the Y direction. Each gap region 452 may have a length and a width, wherein the length is greater than the width. The length of the gap region 452 is along a line in the X direction. The line in the X direction may be substantially orthogonal to the line in the Y direction. In one embodiment, the line in the X direction is perpendicular to the line in the Y direction at a 90° angle. + / -5 The angles intersect.

[0081] The deep body region 1046 has the same conductivity type as the buried shield 426. In one embodiment, the dopant used for the deep body region 1046 may include a p-type dopant, which is a metallic element with an atomic number of at least 13. In a particular embodiment, the p-type dopant is Al. The deep body region 1046 may have a higher peak dopant concentration than the peak dopant concentration of the carrier accumulation region 938 and the buried shield 426. The peak dopant concentration of the deep body region 1046 may or may not have a lower peak dopant concentration than the peak dopant concentration of the deep portion 436 of the source region. In the same or other different embodiments, the deep body region 1046 may have at least 5 × 10⁻⁶. 18 atoms / cm 3 Or at least 1×10 19 atoms / cm 3 The peak dopant concentration. In any of the foregoing or different embodiments, the peak dopant concentration may be at most 1 × 10⁻⁶. 20 atoms / cm 3 .

[0082] A body mask (not shown) may be formed over the main surface 226 of semiconductor layer 234. The active region of the transistor structure of the power transistor being formed is exposed. The mask covers portions of the electronic components and circuitry outside the active region of the transistor structure. The body mask is used when forming the body region 1346 and the shallow portion 1356 of the source region.

[0083] refer to Figures 12 to 15 Doping can be performed to form the host region 1346 and the shallow portion of the source region 1356. Figure 12 Is along such Figure 7 The illustrated section line A, Figure 13 Is along such Figure 7 The illustrated section line B, Figure 14 Is along such Figure 7 The illustrated section line C, and Figure 15 Is along such Figure 7 The illustrated profile D shows that the formation of the main body region 1346 and the shallow portion 1356 of the source region can be performed in any order relative to each other.

[0084] The body region 1346 includes the channel region of the transistor structure of a power transistor. The body region 1346 has a conductivity type opposite to any or more of the semiconductor layer 234, the carrier distribution layer 936, or the carrier accumulation region 938. In one embodiment, the body region 1346 may be p-type doped. The buried shield 426 is spaced apart from the body region 1346 by at least a portion of the carrier accumulation region 938. In a direction perpendicular to the main surface 226, the body region 1346 is located between any or all of the deep body regions 1046 and the main surface 226. The body region 1346 may be stacked below the source region (including the shallow portion 1356 and the deep portion 436). A portion of the body region 1346 is not stacked below the deep portion 436 of the source region. The body region 1346 may be stacked above the carrier accumulation region 938. In one embodiment, the buried shield is spaced apart from the body region 1346 by the carrier accumulation region 938.

[0085] The peak dopant concentration in the main region 1346 is greater than the average dopant concentration of the semiconductor layer 234, the carrier distribution layer 936, or both. In one specific embodiment, the peak dopant concentration is 8 × 10⁻⁶. 17 atoms / cm 3 Up to 4.5×10 18 atoms / cm 3 The peak dopant concentration of the body region 1346 can be located at a height ranging from 0.1 μm to 0.6 μm below the main surface 226. Unlike the carrier distribution layer 936 and the carrier accumulation region 938, the body region 1346 may not be fully depleted during reverse bias under normal operating conditions. These depletion conditions of the carrier distribution layer 936 and the carrier accumulation region 938 can be used to determine their maximum dopant concentration for a given device geometry, and the depletion condition of the body region 1346 can be used to determine lower values ​​of the dopant concentration for a given device geometry.

[0086] The source region of a power transistor may include a shallow portion 1356 and a deep portion 436. The shallow portion 1356 may have the same conductivity type as the deep portion 436 of the source region, the carrier accumulation region 938, or the carrier distribution layer 936. In one embodiment, the shallow portion 1356 may be n-type doped. Compared to the portion of the source region that includes both the deep portion 436 and the shallow portion 1356, the shallow portion 1356 is thinner (as measured in the Z direction).

[0087] The shallow portion 1356 may stack on top of the gap region 452. The shallow portion 1356 does not extend as far into the substrate as the deep portion 436. Therefore, the body region 1346 is locally thicker where it stacks on top of the gap region 452 and locally thinner where it stacks below the deep portion 436 of the source region. In one embodiment, the centerline 1452 may pass through the center of the narrowest width of the gap region 452, wherein the centerline 1452 is perpendicular to the main surface 226. The width may be measured at or near the mid-height line 424. The centerline 1452 may pass through the shallow portion 1356 of the source region but not through the deep portion 436 of the source region. Based on simulations, the breakdown mechanism can occur by drain-to-source punch-through at the gap region 452 in a direction generally along or parallel to the centerline 1452, because the body region 1346 is exposed to the highest potential during reverse bias compared to other regions and layers. The main body region 1346 is locally thicker where it overlaps with the gap region 452, and this allows for BV (bulk volume). DS The case of the entire superposition of any or all gap regions above the deep portion 436 and the gap region 452.

[0088] In one embodiment, the shallow portion 1356 may extend from the main surface 226 to a depth of up to 75%, up to 65%, or up to 55% of the lowest height of the deep portion 436. In the same or different embodiments, the shallow portion 1356 may extend from the main surface 226 to a depth of at least 20%, up to 25%, or up to 30% of the lowest height of the deep portion 436. In any one or both embodiments, the shallow portion 1356 may extend from the main surface 226 to a depth ranging from 20% to 75%, 25% to 65%, or 30% to 55% of the lowest height of the deep portion 436. The shallow portion 1356 may extend from the main surface 226 to a depth ranging from 0.05 micrometers to 0.3 micrometers.

[0089] The peak dopant concentration of the shallow portion 1356 can be any of the peak dopant concentrations previously described relative to the deep portion 436. In one specific implementation, the shallow portion 1356 and the deep portion 436 may have the same peak dopant concentration or different peak dopant concentrations.

[0090] After forming the main body area 1346 and the shallow portion 1356, the main body mask can be removed.

[0091] Figure 16 A top view including a body contact mask 1700. The body contact mask 1700 can be formed, and the body contact mask defines an opening 1706 for a body contact region. The body contact mask 1700 is stacked on top of a shallow portion 1356 of the source region. The body contact mask 1700 may have a shape similar to the one previously described. Figure 2The composition of the mask component 306 may be the same as or different from that described. In one embodiment, the body contact mask 1700 may be made of an oxide layer similar to the relatively thick oxide layer 476 previously described, and therefore, the relatively thin oxide layer 472, the polysilicon layer 474, or both may be present or absent. In another embodiment, the body contact mask 1700 may be made of a photoresist.

[0092] Figures 17 to 20 A cross-sectional view of the workpiece 200 after the main contact area 1826 is formed and the main contact mask 1700 is removed. Figure 17 It is along Figure 16 Section line A in the middle, Figure 18 It is along Figure 16 Section line B in the middle, Figure 19 It is along Figure 16 Section line C in the middle, and Figure 20 It is along Figure 16 Section line D in the middle. The main contact area 1826 is formed in Figure 16 Below the opening 1706 of the main body contact mask 1700.

[0093] The body contact area 1826 can be electrically connected to the subsequently formed source terminal. The deep body area 1046 allows the resistance drop between the subsequently formed source terminal and the buried shield 426 via the body contact area 1826 to be less than if the deep body area 1046 were not present. In addition, the body contact area 1826 can be stacked on top of the gap area 452.

[0094] The main contact area 1826, the main body area 1346, the buried shield 426, and the deep main body area 1046 may be electrically coupled to each other. In one embodiment, the main contact area 1826 may be electrically connected to the main body area 1346, the buried shield 426, and the deep main body area 1046. Any or all of the main contact areas 1826 may be in physical contact. Figure 19 The deep main body region 1046 is illustrated. The main body contact region 1826, which is partially superimposed on the deep main body region 1046, forms a stepped conductive structure.

[0095] In another embodiment, any or all of the deep body regions 1046 may be spaced apart from and not in contact with the body contact regions 1826. In one embodiment, no portion of the deep body regions 1046 overlaps with the body contact regions 1826. If any or all of the body contact regions 1826 are spaced apart from their nearest deep body regions 1046, the distance between such body contact regions 1826 and their nearest deep body regions 1046 should be relatively small compared to a relatively large distance to allow for a smaller resistance drop between the source terminal and the buried shield 426. As used herein, the distance between the first object and the second object corresponds to the distance between a first point on the first object closest to the second object and a second point on the second object closest to the first object. In a particular embodiment, the distance between any or all of the body contact regions 1826 and their nearest deep body regions 1046 may be at most 0.5 micrometers, at most 0.2 micrometers, or at most 0.1 micrometers.

[0096] The main contact region 1826 can physically contact and extend through the shallow portion 1356 and the deep portion 436 of the source region, and therefore, the lowest height of the main contact region 1826 can be located below the lowest height of the deep portion 436 of the source region within the active region of the power transistor. At locations spaced apart from the main contact region 1826, the shallow portion 1356 of the source region does not overlap with the deep portion 436 of the source region. In such cases... Figure 19 In the specific implementation illustrated, the main contact area 1826 does not extend to the buried shielding component 426.

[0097] The main contact region 1826 has the same conductivity type as the main body region 1346 and the buried shield 426. In one embodiment, the main contact region 1826 may include a p-type dopant, which is a metallic element with an atomic number of at least 13. In a particular embodiment, the p-type dopant is Al. The main contact region 1826 may have a higher peak dopant concentration than the shallow portion 1356 and the deep portion 436 of the source region. In the same or different embodiments, the peak dopant concentration of the main contact region 1826 may be greater than the peak dopant concentration of the deep main body region 1046. The main contact region 1826 may have at least 1 × 10⁻⁶ 19 atoms / cm 3 The peak dopant concentration can be up to 2 × 10⁻⁶. 21 atoms / cm 3 The peak dopant concentration. In one specific embodiment, the host contact region 1826 extends from the host surface 226 to a depth in the range of 0.3 micrometers to 0.7 micrometers.

[0098] Annealing can be performed to activate the dopant relative to the previously described doping operation. Prior to annealing, a graphite capping layer can be formed over the workpiece to protect the SiC surface from sublimation, pitting, and other forms of surface roughening during annealing. In one embodiment, the graphite capping layer can have a thickness ranging from 1.5 micrometers to 5.0 micrometers. The capping layer can be deposited in the form of a photoresist and decomposes into a layer primarily composed of carbon during subsequent annealing. Annealing can be performed at 1500 °C. C to 1800 Immersion times ranging from 10 to 60 minutes are performed at temperatures within the range of C. During annealing, dopants within the workpiece may not diffuse significantly, and therefore, the doped layers and doped regions essentially retain their original shape and location. In one embodiment, annealing can be performed in an inert environment.

[0099] As described below, annealing can be performed before or after the formation of the gate trench. Annealing can be performed before the formation of the gate dielectric layer because the material within the gate dielectric layer may not withstand the temperatures required for annealing. After reading this specification, those skilled in the art will be able to determine where in the process flow annealing should be performed.

[0100] Many doping operations have been described previously. The order in which doping operations are performed after the formation of semiconductor layer 234 can be varied. For example, doping of the host contact region 1826, such as doping of the carrier distribution layer 936, carrier accumulation region 938, host region 1346, and shallow and deep portions 1356 and 436 of the source region, can be performed before many other doping operations described previously. Therefore, doping operations can be performed in many different orders before any annealing is performed. In another embodiment, another annealing can be performed after some, but not all, doping operations. Any doping operation performed before another annealing may not be performed after another annealing, and any doping operation performed after another annealing may not be performed before another annealing.

[0101] Figure 21 A top view of a gate trench mask 2200 above workpiece 200. The gate trench mask 2200 defines a gate trench opening 2204 for defining a gate trench. The gate trench opening 2204 may be in the form of a strip having a length in the Y direction. The gate trench mask 2200 may have the same or different composition as previously described relative to the buried shield mask. In one embodiment, the gate trench mask 2200 may be made of an oxide layer similar to the relatively thick oxide layer 476 previously described, and therefore, a relatively thin oxide layer 472, a polysilicon layer 474, or both may or may not be present. In another embodiment, the gate trench mask 2200 may be made of a photoresist.

[0102] Figure 21 Some features are illustrated below to aid in understanding the layout. The gate trench mask 2200 is stacked on top of a portion of the shallow portion 1356 of the source region and the body contact region 1826. The gate trench opening 2204 exposes a portion of the shallow portion 1356 of the source region. The body contact region 1826 is illustrated with dashed lines. The shallow portion 1356 of the source region and the body contact region 1826 may be located at the main surface 226 (in...). Figures 22 to 25 (marked in the middle).

[0103] Figures 22 to 25 A cross-sectional view of the workpiece 200 after defining the gate trench 2404 and removing the gate trench mask 2200. Figure 26 It is along Figure 21 Section line A in the middle, Figure 23 It is along Figure 21 Section line B in the middle, Figure 24 It is along Figure 21 Section line C in the middle, and Figure 25 It is along Figure 21 Section line D in the middle.

[0104] The substrate beneath the gate trench opening 2204 of the gate trench mask 2200 is etched to define a gate trench 2404 extending from the main surface 226 to the depth of the gate trench. (Reference) Figure 23 and Figure 25 The gate trench 2404 may extend from the main surface 226 through the body region 1346 and the shallow portion 1356 and deep portion 436 of the source region, and at least extend to the carrier accumulation region 938. At least a portion of the shallow portion 1356 and deep portion 436 of the source region, the body region 1346 and the carrier accumulation region 938 may be along the sidewalls of the gate trench 2404.

[0105] In one embodiment, the gate trench 2404 may extend through the carrier accumulation region 938 and into the buried shield 426, such as Figure 23 and Figure 25As illustrated. The channel length of the transistor structure of the power transistor may correspond to the thickness of the body region 1346 along the sidewall of the gate trench 2404. The buried shield 426 may be stacked under at least a portion of the body region 1346 and the gate trench 2404. In the same or different embodiments, the gate trench 2404 does not extend completely through the buried shield 426. In the same or more specific embodiments, the gate trench 2404 is spaced apart from and not in physical contact with (1) a portion of the carrier distribution layer 936 below the buried shield 426, (2) the underlying semiconductor layer 234, or both (1) and (2). In any of the embodiments, the depth of the gate trench 2404 may be in the range of 0.3 micrometers to 1.1 micrometers. In another embodiment, the bottom of the gate trench 2404 may be located up to 0.05 micrometers below the top of the carrier accumulation region 938. In any of the foregoing or different specific embodiments, the buried shield 426 may be stacked under at least a portion of the body region 1346 and the gate trench 2404.

[0106] The width of the gate trench 2404 corresponds to the width of the gate trench 2404. Figure 21 The width of the gate trench opening 2204 is measured in the X direction. The widths of the gate trenches 2404 may be the same or different from each other. In one embodiment, the depth of the gate trench 2404 may be in the range of 0.1 micrometers to 0.9 micrometers. After defining the gate trench 2404, the gate trench mask 2200 can be removed.

[0107] If the previously described annealing is not performed before defining the gate trench 2404, annealing may be performed after defining the gate trench 2404. Annealing may be performed before forming the gate dielectric layer 2814. When annealing is performed after defining the gate trench 2404, the graphite capping layer may fill or at least partially fill the gate trench 2404.

[0108] For reference only Figures 27 to 30 The gate dielectric layer 2814 may be formed along the exposed surface of the workpiece 200 (including the sidewalls and bottom of the gate trench 2404) and over the shallow portion 1356 of the source region and the body contact region 1826 along the main surface 226. In one embodiment, the gate dielectric layer 2814 is spaced apart from and does not physically contact the gap regions 452. The gate dielectric layer 2814 may comprise oxide or oxynitride. In one embodiment, the gate dielectric layer 2814 may have a thickness in the range of 20 nm to 150 nm.

[0109] After forming the gate dielectric layer 2814, a gate conductive layer may be deposited over the gate dielectric layer 2814. The gate conductive layer may comprise a single film or multiple films, wherein any film within the single film or multiple films may comprise a doped semiconductor layer, an elemental metal (a metal that is not part of an alloy and not part of a compound, such as W, Cu, Al, etc.), a metal alloy (e.g., TiW, Al-1wt% Cu, etc.), or a conductive metal compound (e.g., a conductive metal silicide or a conductive metal nitride). The gate conductive layer may have a thickness sufficient to fill the gate trench 2404. In a particular embodiment, the gate conductive layer may be n-type doped polysilicon.

[0110] Figure 26 A top view of the gate mask above workpiece 200. The gate mask is formed after the gate dielectric layer 2814 and the gate conductive layer are formed. The gate mask includes a gate mask member 2704 for defining the gate component. The gate mask member 2704 may be in the form of a strip having a length in the X direction. The gate mask may have the same or different composition as previously described relative to the buried shield mask. In one embodiment, the gate mask member 2704 may be made of an oxide layer similar to the relatively thick oxide layer 476 previously described, and therefore, the relatively thin oxide layer 472, the polysilicon layer 474, or both may or may not be present. In another embodiment, the gate mask member 2704 may be made of a photoresist.

[0111] Figure 26 Some features are shown in the examples to help understand the layout. Figure 26 The entire workpiece illustrated is covered by a gate conductive layer, and a portion of the gate conductive layer is covered by a gate mask component 2704. The gate conductive layer is stacked on top of the shallow portion 1356 of the source region, the body contact region 1826, and the gate trench 2404. The shallow portion 1356 of the source region and the body contact region 1826 may be located at the main surface 226 (in...). Figures 27 to 30 (Marked in the middle). Gate mask component 2704 is not in the gap region 452 (not in the middle). Figure 26 (Example shown) Overlapping, and from the top view, located between gaps 452.

[0112] Figures 27 to 30 A cross-sectional view of workpiece 200 after etching the gate conductive layer to form gate member 2930 and removing gate mask member 2704. Figure 27 It is along Figure 26 Section line A in the middle, Figure 28 It is along Figure 26 Section line B in the middle, Figure 29 It is along Figure 26 Section line C in the middle, and Figure 30 It is along Figure 26Section line D in the middle.

[0113] Etching can be performed to remove portions of the gate conductive layer covering the gap region 452, portions of the shallow portion 1356 of the source region, and the body contact region 1826, all outside the gate trench, to form the gate member 2930. The gate member 2930 may include a gate electrode 2934 as a portion extending into the gate trench 2404 and an intermediate portion 2936 outside the gate trench 2404. Etching can be performed as a timed etching or using endpoint detection and over-etching. Endpoint detection can occur when the gate dielectric layer 2814 is exposed. Over-etching can be performed to recess a portion of the gate electrode 2934 into the gate trench 2404 to reduce the gate-to-source capacitance C. GS The height of the upper surface of the recessed portion along the gate electrode is not lower than the lowest point of the source region along its corresponding gate trench 2404. Compared to the absence of the deep portion 436 of the source region, there is more process margin for the recess of the gate electrode when both the deep portion 436 and the shallow portion 1356 of the source region are adjacent to the gate trench 2404. Since the gate electrode should at least partially overlap the source region to effectively control the threshold voltage, the presence of the deep portion 436 of the source region improves the threshold voltage control and manufacturability of the device. In another embodiment, a relatively high C GS This is acceptable, and the gate electrode 2934 may not be recessed within the gate trench 2404.

[0114] like Figures 27 to 30 As illustrated, a gate dielectric layer 2814 is located between the gate member 2930 and the sidewalls and bottom of the main surface 226 and the gate trench 2404. The gate member 2930 can be spaced apart from the body region 1346 and the buried shield 426 via the gate dielectric layer 2814. The gate member 2930 can be stacked on any or all widths of the deep body region 1046. The distance between any or all gate members of the gate member 2930 and their nearest body contact region 1826 can be greater than the thickness of the gate dielectric layer 2814. Along a direction perpendicular to the main surface 226, the gate dielectric layer 2814, the body region 1346, and the shallow portion 1356 of the source region are disposed between the deep body region 1046 and the gate member 2930 stacked on such deep body region 1046.

[0115] After etching the gate conductive layer to form the gate member 2930, the gate mask member 2704 is removed. If required or desired, when the gate member 2930 includes doped polysilicon, a silicide process can be performed on the silicide-exposed surface of the gate member 2930.

[0116] Figure 31A top view including a portion of workpiece 200, which includes a shallow portion 1356 of the source region, a body contact region 1826, and a gate member 2930. The gate member 2930 includes a middle portion 2936 and extends into a gate trench 2404 (not shown in the image). Figure 31 Gate electrode 2934 (marked in the middle). The body contact region 1826 and gate member 2930 are at least spaced apart by a minimum distance illustrated by dashed line 3230. Gate dielectric layer 2814 covers the shallow portion 1356 of the source region and the body contact region 1826, but not... Figure 31 Examples are provided to simplify the understanding of minimum distance.

[0117] Metal elements with an atomic number of at least 13 (such as Al) can cause reliability issues relative to the gate dielectric layer 2814. Some metal elements can be used as p-type dopants in semiconductor materials. While many atoms of a metal element are within the semiconductor lattice, others may not be part of the lattice or may have detached from it. During repeated application of the gate voltage while switching multiple power transistors, metal atoms not within the lattice may migrate into the gate dielectric layer 2814. As more metal atoms migrate into the gate dielectric layer 2814, the likelihood of gate dielectric failure increases.

[0118] When the peak dopant concentration of the p-type region or layer is low, the risk of gate dielectric failure is relatively small. For example, the p-type region or layer may have a peak dopant concentration of 1 × 10⁻⁶. 16 atoms / cm 3 The dopant concentration is approximately 1 ppm, and the dopant within the p-type region or layer can constitute about 1 ppm of atoms within the p-type region or layer. As the peak dopant concentration increases, the number of metal atoms within the p-type region or layer also increases. At 1 × 10⁻⁶... 19 atoms / cm 3 At peak dopant concentrations, dopants can form approximately 0.1% of p-type regions or layers on an atomic basis. Therefore, the likelihood of gate dielectric failure may increase significantly.

[0119] The minimum distance between the p-type doped region or layer and the gate component can be used to reduce the likelihood of premature gate dielectric failure due to the migration of atoms of a metal element with an atomic number of at least 13 into the gate dielectric layer 2814. When the minimum distance becomes too large, the unit cell may become too large, which is undesirable. In one embodiment, the minimum distance may be at most 0.9 micrometers, at most 0.7 micrometers, or at most 0.5 micrometers. The minimum distance may be at least 0.1 micrometers. Other values ​​of the minimum distance may be greater than or less than those listed. The minimum distance may be greater than the thickness of the gate dielectric layer 2814.

[0120] The minimum distance can be a fixed value or a value that varies with the peak dopant concentration. Regarding a fixed value, a minimum distance can be used when the peak dopant concentration is equal to or greater than a threshold. For example, if the peak dopant concentration is less than a threshold, a minimum distance design rule may not be used. Equal to or greater than a threshold (e.g., 5 × 10⁻⁶) 18 atoms / cm 3 If the peak dopant concentration is 1 × 10⁻⁶, then the minimum distance is 0.4 micrometers. In another specific embodiment, the minimum distance can vary with the dopant concentration and increases with increasing peak dopant concentration. For example, when the peak dopant concentration is 1 × 10⁻⁶, the minimum distance can be 0.4 micrometers. 19 atoms / cm 3 At this point, the minimum distance can be 0.2 micrometers, and the peak dopant concentration is 1×10⁻⁶. 20 atoms / cm 3 At that time, the minimum distance can be 0.3 micrometers, and when the peak dopant concentration is 1×10 21 atoms / cm 3 At that time, the minimum distance can be 0.4 micrometers.

[0121] In another specific implementation, the minimum distance may include a first value corresponding to a threshold of peak dopant concentration and an additional value for increasing the peak dopant concentration. As a non-limiting example, the threshold for peak dopant concentration may be 5 × 10⁻⁶. 18 atoms / cm 3 Below this value, there is no minimum distance, or the minimum distance is set to 0. Equal to or greater than 5 × 10 18 atoms / cm 3 The minimum distance can then be calculated based on the value in Formula 1 below.

[0122] D calc =(log(value of PDC) –log(1x10) 18 )) ×0.15 micrometers, (Formula 1) Among them, D calc It is the calculated distance, and The value of PDC does not include units (atoms / cm). 3 The peak dopant concentration.

[0123] When the peak dopant concentration is 1×10 20 atoms / cm 3 hour, D calc =(log(1×10 20 )–log(1x10 18 )) ×0.15 micrometers = (20-18) ×0.15 micrometers = 0.30 micrometers.

[0124] Different formulas can be used to calculate distances. After reading this manual, technicians will be able to determine the formula that best suits their specific application needs or requirements.

[0125] During implementation, due to variations that occur during manufacturing, the minimum distance may not be exactly the calculated distance. Therefore, the minimum distance can be + / - 10% of the calculated distance. In the example above, the minimum distance could be in the range of 0.27 micrometers to 0.33 micrometers.

[0126] The previous description was based on a minimum distance that is the same in all directions. Alternatively, the minimum distance may have a horizontal component in the direction along the main surface and a vertical component in the direction perpendicular to the main surface. The horizontal component may be the same as or different from the vertical component. For example, a common variation in manufacturing is the misalignment of photomask layers. In this case, it may be more appropriate to add a fixed number of misalignments to the previously calculated value. For example, suppose the misalignment tolerance between two mask layers is 0.20 micrometers. Then, in the example above, the horizontal component of the minimum distance could be increased to 0.50 micrometers (or 0.45 to 0.55 micrometers to allow for certain manufacturing tolerances) to accommodate the worst-case mask misalignment. When considering mask misalignment, the minimum distance for the horizontal spacing can also be different from that for the vertical spacing, because the horizontal spacing may be affected by mask misalignment, while the vertical spacing may be affected by variations in ion implantation depth, but not by photomask misalignment. Therefore, the vertical component of the minimum distance could be kept at 0.3 micrometers (or 0.27 to 0.33 micrometers to allow for certain manufacturing tolerances).

[0127] When designing power transistors, a minimum distance can be implemented as a design rule. The design must still comply with other design rules. For example, the body region 1346 may have a peak dopant concentration below a threshold to trigger the minimum distance. Within unit cell 300, the distance between the body region 1346 and the gate electrode 2934 is not zero because if the body region 1346 is electrically shorted to any gate electrode in the gate electrode 2934, the transistor will not operate correctly. Therefore, even if the peak dopant concentration of the body region 1346 does not trigger the minimum distance rule or is assigned a value of 0 micrometers, another design rule requires an appropriately thick gate dielectric layer 2814 between the body region 1346 and the gate electrode 2934.

[0128] Methods for forming electronic devices may include implementing design rules during simulation and fabrication of masks for the electronic devices. The methods may include determining a minimum distance between a gate component and a doped region within the SiC material. The doped region has a dopant that is a metallic element with an atomic number of at least 13, and the doped region has a minimum distance of 5 × 10⁻⁶. 18 atoms / cm 3The peak dopant concentration. The host contact region, deep host region, or another p-type doped region or layer may be formed such that it is spaced from the gate member by at least a minimum distance.

[0129] Most of the description in this paper uses SiC as the semiconductor substrate material and Al as the p-type dopant. Minimum distance is applicable to compound semiconductor substrate materials such as SiC, SiGe, III-V semiconductor materials and II-VI semiconductor materials, and to other p-type dopant elements as metallic elements with atomic numbers greater than Al (13).

[0130] The minimum distance can extend in all directions and is not limited to the XY plane. The minimum distance can extend into the substrate (Z direction). Figure 32 It also includes a perspective view of a portion of the workpiece 200 at this point in the process. Figure 32 The view in the diagram corresponds to unit cell 300. Gate dielectric layer 2814 runs along the main surface 226 of workpiece 200 and the sidewalls of gate trench 2404. Deep body region 1046 is spaced from gate member 2930 by at least a minimum distance (dashed line 3230). Figure 32 The gate member 2930 includes a gate electrode 2934 within a gate trench 2404 and an intermediate portion 2936 outside the gate trench 2404. A portion of the body contact region 1826 is located in the corner. A deep body region 1046 is seen along its length on the right front side of the illustration. A portion of the shallow portion 1356 and the deep portion 436 of the source region overlap with the deep body region 1046. The deep portion 436 of the source region does not overlap with the gap region 452.

[0131] refer to Figures 33 to 37 An interlayer dielectric (ILD) layer 3610 may be formed above the workpiece 200, and a contact mask 3400 may be formed above the ILD layer 3610, the contact mask including a contact opening 3406. Figures 34 to 37 A cross-sectional view of workpiece 200 after the formation of source end 3526. Figure 34 It is along Figure 33 Section line A in the middle, Figure 35 It is along Figure 33 Section line B in the middle, Figure 36 It is along Figure 33 Section line C in the middle, and Figure 37 It is along Figure 33 Section line D in the middle.

[0132] The ILD layer 3610 may comprise a single film or multiple films. Any one or more films within the single or multiple films may comprise oxides, nitrides, or oxynitrides. Any one or more films within the single or multiple films may be doped or undoped with boron, phosphorus, etc. The ILD layer 3610 may be deposited to a thickness ranging from 0.5 micrometers to 3.0 micrometers. A planarization process can be performed such that the uppermost surface of the ILD layer 3610 is along a plane. The planarization process can be performed using chemical mechanical polishing or resist etching-back processes.

[0133] exist Figure 33 In this configuration, contact mask 3400 defines contact openings 3406 that expose a portion of the ILD layer 3610. Contact mask 3400 may be made of photoresist. Contact openings 3406 are superimposed on portions of the shallow source region 1356 and the body contact region 1826. Figure 33 In the diagram, portions of, but not all, of the main contact region 1826 and the shallow portion 1356 of the source region are marked. Contact opening 3406 may be spaced apart from gate member 2930. Contact mask 3400 may include portions exposing gate member 2930 (not shown in the diagram). Figure 33 Other openings (as illustrated in the example), wherein such openings are located along workpiece 200 as shown in the example. Figures 33 to 37 Outside the illustrated view, the ILD layer 3610 is etched to expose a shallow portion 1356 of the source region, a portion of the body contact region 1826, and a portion of the gate member 2930. After etching, the contact mask 3400 is removed.

[0134] A conductive layer is deposited above the ILD layer 3610 and within contact openings extending through the ILD layer 3610 to contact the shallow portion 1356 of the source region, the body contact region 1826, and the gate member 2930. The conductive layer may include one or more films, each comprising a conductive material. In one embodiment, the conductive material may include a doped semiconductor material, an elemental metal (a metal that is not part of a compound or alloy), a metal alloy, or a conductive metal compound. Non-limiting examples of conductive materials may include doped polycrystalline silicon (n-type or p-type), W, WN, Ti, Ta, TiW, Al-1wt% Cu, Ni, Cu, Au, Pt, conductive metal nitrides (e.g., WN, TiN, TaN, etc.), conductive metal silicides (NiSi, TiSi2, CoSi2, PtSi, etc.), etc. In one embodiment, the conductive layer may be deposited to a thickness ranging from 0.7 micrometers to 5.0 micrometers.

[0135] A photoresist mask is formed above the conductive layer, and the conductive layer is patterned to form... Figures 34 to 37The source terminal 3526 and the gate terminal (not shown) are shown. The source terminal 3526 physically contacts the shallow portion 1356 of the source region and the body contact region 1826. In one embodiment, an ohmic contact is formed between the source terminal 3526 and the shallow portion 1356 of the source region and the body contact region 1826. The gate terminal may physically contact the gate member 2930.

[0136] If desired or desired, a passivation layer (not shown) may be formed over the ILD layer 3610, the source terminal 3526, and the gate terminal. The passivation layer may comprise one or more films of insulating material. In a particular embodiment, the passivation layer comprises polyimide coated and patterned to expose portions of the source terminal 3526 and the gate terminal. A metal layer may be disposed on the reverse side of the workpiece, which is the drain terminal and physically contacts the semiconductor substrate material 232.

[0137] Figure 38 A cross-sectional view including a portion of a unit cell adjacent to one of the gap regions 452, illustrating majority carrier flow within the transistor structure. The portion of the workpiece above the main surface 226 is removed to improve understanding of the power transistor's characteristics. A body contact region 1826 and a deep body region 1046 are present, but... Figure 38 This is not visible in the image. The flow of majority carriers is illustrated with arrows. For an n-channel transistor, the majority carriers are electrons, and for a p-channel transistor, the majority carriers are holes.

[0138] In the finished device and when the power transistor is in the ON state, majority carriers flow along the following path: from the shallow portion 1356 and deep portion 436 of the source region, through the channel region adjacent to the sidewall of the gate trench 2404, which is the main region 1346, into the carrier accumulation region 938, through the gap region 452 into the carrier distribution layer 936, through the semiconductor layer 234, and through the semiconductor substrate material 232 (not in the semiconductor layer 234). Figure 38 (as shown in the example), and enters the drain terminal (not shown) of the power transistor.

[0139] Most carriers flow substantially vertically (in the Z direction) through the channel region, and... Figure 38 The arrow extending through the main body region 1346 and into the carrier accumulation region 938 is illustrated in the diagram. After entering the carrier accumulation region 938, the majority carriers flow substantially laterally (in the X direction) between the main body region 1346 and the buried shield 426, and... Figure 38 The arrow in the carrier accumulation region 938 is used as an example. Although Figure 38Includes an arrow exemplified in the X direction passing through the center of the carrier accumulation region 938, but the majority of carriers are not limited to flowing only along the center of the carrier accumulation region 938. At least some of the majority of carriers may flow through the carrier accumulation region 938 at locations outside the center of the carrier accumulation region 938.

[0140] The majority carriers entering the interstitial region then flow substantially vertically (in the Z direction) through the interstitial region 452 and into the carrier distribution layer 936. Although Figure 38 Includes a single arrow exemplified in the Z direction passing through the center of gap region 452, but the majority carriers are not limited to flowing only along the center of gap region 452. At least some of the majority carriers may flow through gap region 452 at locations outside the center of gap region 452.

[0141] Compared to transistor structures in which the carrier distribution layer 936 is confined only to the gap region 452 or in which the carrier distribution layer 936 is replaced by the semiconductor layer 234 (which extends into the gap region 452 and physically contacts the carrier accumulation region 938), the carrier distribution layer 936 helps to distribute the majority of carriers more evenly in the semiconductor layer 234.

[0142] After entering the carrier distribution layer 936, at least some of the majority carriers can flow substantially laterally (in the X direction) below the buried shield 426, and Figure 38 The image is illustrated by a double-headed arrow extending within the carrier distribution layer 936. The majority carriers can then flow from the carrier distribution layer 936 to the semiconductor layer 234, illustrated by a vertical arrow (in the Z direction) extending from the double-headed arrow within the carrier distribution layer 936 to the semiconductor layer 234. Although Figure 38 This includes a double-headed arrow, illustrated in the X direction, passing through the center of the carrier distribution layer 936, but the majority of carriers are not limited to flowing only along the center of the carrier distribution layer 936 in the X direction. At least some of the majority of carriers may flow through the carrier distribution layer 936 at locations outside the center of the carrier distribution layer 936. (See reference...) Figure 38 The majority carrier flow from the carrier distribution layer 936 to the semiconductor layer 234 is illustrated in the Z direction by a relatively thin arrow. The majority carriers can be present in both the semiconductor layer 234 and the semiconductor substrate material 232 (not shown in the image). Figure 38 (Example) It flows basically in the vertical direction.

[0143] exist Figure 38 In the middle, the deep portion 436 of the source region does not overlap with the gap region 452 and is laterally spaced from the gap region 452. The shallow portion 1356 of the source region extends across the entire width of the gap region 452, as shown... Figure 38As illustrated, compared to the channel region at gate trench 2404 in the transistor structure, the body region 1346 is locally thicker above the gap region 452. For example... Figure 38 The illustrated combination of the shallow portion 1356 and the deep portion 436 of the source region allows for an acceptablely low source contact resistance and a relatively high drain-to-source punch-through voltage because the body region 1346 is thicker above the gap region 452. If the deep portion 436 of the source region were to extend across the entire gap region 452, the power transistor would have a relatively low drain-to-source punch-through voltage.

[0144] Many different benefits can be seen in different specific implementations of the concepts described herein. These specific implementations have at least one of the benefits described herein, but not all benefits need to be seen in all specific implementations.

[0145] Compared to a non-existent deep body region 1046, a deep body region 1046 allows for lower resistance between the source terminal 3526 and the buried shield 426. Lower resistance allows the buried shield 426 to have a closer proximity to the source voltage V. S The potential. The deep main body region 1046 can be separated from the gap region 452, and therefore R SP It will not be adversely affected by the deep body region 1046. The deep body region 1046 eliminates the need for a deep body contact region that aligns with the body contact region 1826. Such a deep body contact region would extend through the gap region 452 and reduce the area of ​​these gap regions, and adversely affect R. SP .

[0146] p-type dopant can be a metallic element with an atomic number of at least 13. If a sufficient amount of p-type dopant accumulates within the gate dielectric layer 2814, the gate dielectric layer 2814 may fail. To improve long-term gate dielectric reliability, p-type regions and layers with relatively high peak dopant concentrations (such as the body contact region 1826 and the deep body region 1046) can be spaced at a minimum distance from the gate member 2930. The high peak dopant concentration in these regions will reduce the resistance to the buried shield 426 to below the resistance that would be achievable if the dopant concentration in these regions had to be reduced to maintain gate dielectric reliability. The minimum distance can be a fixed distance or can vary depending on the peak dopant concentration of a particular p-type doped region or layer. When the peak dopant concentration is below a threshold concentration, a minimum distance may not be required.

[0147] Many different aspects and embodiments are possible. Some of those aspects and embodiments are described below. Upon reading this specification, those skilled in the art will recognize that those aspects and embodiments are merely illustrative and do not limit the scope of the inventive concept. Embodiments may be made according to any one or more of the embodiments listed below.

[0148] Specific Implementation 1. An electronic device may include a substrate defining a gate trench having sidewalls and extending from a main surface of the substrate to a depth of the gate trench, wherein the substrate includes a semiconductor layer having a first conductivity type. The electronic device may further include a body region having a second conductivity type opposite to the first conductivity type; a body contact region having the second conductivity type; a buried shield having the second conductivity type and a peak dopant concentration, wherein the buried shield is stacked below the gate trench; a deep body region having the second conductivity type and a peak dopant concentration, wherein the peak dopant concentration of the deep body region is greater than the peak dopant concentration of the buried shield; a gate dielectric layer located within the gate trench; and a gate member including a portion extending into the gate trench. In a direction perpendicular to the main surface, the deep body region may be located between the body region and the buried shield, the body region may be spaced apart from the gate member along a portion of the sidewall of the gate trench and through the gate dielectric layer. The gate member may not be stacked on top of the body contact area, and the gate member may be stacked on top of the deep body region and spaced apart from the deep body region through the body region.

[0149] Specific implementation 2. The electronic device according to specific implementation 1, wherein each of the main contact region and the deep main region includes a dopant, the dopant being a metallic element with an atomic number of at least 13.

[0150] Specific implementation 3. The electronic device according to specific implementation 2, wherein the semiconductor layer is a SiC layer.

[0151] Specific implementation 4. The electronic device according to specific implementation 1 further includes a gap region having the first conductivity type and being at least partially defined by the buried shield.

[0152] Specific implementation 5. The electronic device according to specific implementation 4 further includes a carrier accumulation region having the first conductivity type, wherein the carrier accumulation region spans the entire extension of the gap region and is located between the body region and the buried shield.

[0153] Specific Implementation 6. The electronic device according to Specific Implementation 5 further includes a carrier distribution layer, the carrier distribution layer having the first conductivity type, wherein the gap region includes a portion of the carrier distribution layer and the carrier accumulation region.

[0154] Specific implementation 7. The electronic device according to specific implementation 6, wherein the buried shielding is stacked on the carrier distribution layer.

[0155] Specific Implementation 8. An electronic device may include a substrate defining a gate trench extending from a main surface of the substrate to a depth of a gate trench, wherein the substrate includes a semiconductor layer having a first conductivity type. The electronic device may further include a body contact region having a second conductivity type opposite to the first conductivity type; a buried shield having the second conductivity type and a peak dopant concentration, wherein the buried shield is stacked below the gate trench; a gap region having the first conductivity type, wherein the gap region is at least partially defined by the buried shield; and a deep body region having the second conductivity type and a peak dopant concentration. The body contact region, the buried shield, and the deep body region may be electrically coupled to each other, the deep body region may not be fully stacked above the gap region, the deep body region may be spaced apart from the main surface of the substrate, and the peak dopant concentration of the deep body region may be greater than the peak dopant concentration of the buried shield.

[0156] Specific Embodiment 9. The electronic device according to Specific Embodiment 8 further includes a body region having the second conductivity type and along the sidewall of the gate trench; a gate dielectric layer located within the gate trench, wherein the gate dielectric layer has a thickness; and a gate member including a portion extending into the gate trench. The gate member is spaced apart from the body region by the gate dielectric layer, spaced apart from the body contact region by a body contact distance greater than the thickness of the gate dielectric layer, and spaced apart from the deep body region by a deep body distance greater than the thickness of the gate dielectric layer.

[0157] Specific implementation 10. The electronic device according to specific implementation 9 further includes a source region having the first conductivity type, wherein the gate dielectric layer, the source region, and the body region are disposed between the deep body region and the gate member along a direction perpendicular to the main surface.

[0158] Specific implementation 11. The electronic device according to specific implementation 10, wherein the source region includes a shallow portion and a deep portion, wherein the shallow portion overlaps with the gap region and the deep portion does not overlap with the gap region.

[0159] Specific Implementation 12. The electronic device according to Specific Implementation 8, wherein, viewed in plan view, the deep body region has a length and a width, wherein the length is greater than the width, and the length of the deep body region is along a first line; the gap region has a length and a width, wherein the length is greater than the width, and the length of the gap region is along a second line. The first line and the second line are at a 90° angle. + / -5 The angles intersect.

[0160] Specific Implementation 13. A method of forming an electronic device may include determining a minimum distance between a gate member and a doped region within a compound semiconductor material, wherein the doped region has a dopant, the dopant being a metallic element with an atomic number of at least 13, and the doped region having a minimum distance of 5 × 10⁻⁶. 18 atoms / cm 3 The peak dopant concentration. The method may further include forming a buried shield within a compound semiconductor layer of a substrate, wherein the compound semiconductor layer has a first conductivity type and the buried shield has a second conductivity type opposite to the first conductivity type; forming a host region within the compound semiconductor layer, wherein the host region has the second conductivity type and less than 5 × 10⁻⁶. 18 atoms / cm 3 The peak dopant concentration; forming a host contact region within the compound semiconductor layer, wherein the host contact region has the second conductivity type and at least 5 × 10⁻⁶. 18 atoms / cm 3 The peak dopant concentration is determined, and the body contact region is electrically coupled to the buried shield; the substrate is patterned to define a gate trench having sidewalls and extending from the main surface of the substrate to a gate trench depth; and a gate member is formed, the gate member including a portion extending into the gate trench. The gate member may be spaced from the body region by a body distance less than the minimum distance, and spaced from the body contact region by a body contact distance of at least the minimum distance.

[0161] Specific Implementation 14. The method according to Specific Implementation 13 further includes forming a deep body region, the deep body region having the second conductivity type and at least 5 × 10 18 atoms / cm 3 The peak dopant concentration. The gate member is separated from the deep body region by a deep body distance, which is at least the minimum distance.

[0162] Specific embodiment 15. The method according to specific embodiment 13 further includes forming a deep host region within the compound semiconductor layer, wherein the deep host region has the second conductivity type and at least 5 × 10 18 atoms / cm 3 The peak dopant concentration. In a direction perpendicular to the main surface, the main body region is located between the deep main body region and the main surface, the gate member is stacked on top of the deep main body region, and the gate member is spaced from the deep main body region by a deep main body distance, which is at least the minimum distance.

[0163] Specific implementation 16. The method according to specific implementation 15, wherein the buried shield at least partially defines a gap region having the first conductivity type, and the deep body region is spaced apart from the gap region and does not overlap with or extend into the gap region.

[0164] Specific embodiment 17. The method according to specific embodiment 13 further includes forming a current accumulation region having the first conductivity type. The buried shield: has a density of less than 5 × 10⁻⁶. 18 atoms / cm 3 The peak dopant concentration is separated from the main body region by the current accumulation region and from the gate member by a distance less than the minimum distance.

[0165] Specific implementation 18. The method according to specific implementation 13, wherein determining the minimum distance is performed such that the minimum distance varies with the peak dopant concentration of the doped region.

[0166] Specific implementation 19. The method according to specific implementation 18, wherein for the peak dopant concentration having a first value, the minimum distance is a first distance, and for the peak dopant concentration having a second value, the minimum distance is a second distance, wherein the first distance is different from the second distance, and the first value is different from the second value.

[0167] Specific implementation 20. According to the method of specific implementation 13, wherein determining the minimum distance includes a horizontal component along the main surface and a vertical component in a direction perpendicular to the main surface.

[0168] Specific implementation 21. The method according to specific implementation 20, wherein the horizontal component is different from the vertical component.

[0169] Specific implementation 22. The method according to specific implementation 20 or 21, wherein the horizontal component is the same as the vertical component.

[0170] It should be noted that not all activities described in the general description or examples above are required; some specific activities may not be necessary, and one or more additional activities may be performed in addition to those described. Furthermore, the order in which the activities are listed is not necessarily the order in which they are performed.

[0171] The beneficial effects, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, these beneficial effects, advantages, solutions to problems, and any features that may lead to or make more apparent any beneficial effect, advantage, or solution should not be construed as key, necessary, or essential features of any or all claims.

[0172] The description and illustrations of the specific embodiments described herein are intended to provide a general understanding of the structure of various embodiments. The description and illustrations are not intended to be an exhaustive and comprehensive description of all elements and features of devices and systems using the structures or methods described herein. Individual embodiments may also be provided in combination within a single embodiment; conversely, various features described in the context of a single embodiment for simplicity may also be provided individually or in any sub-combination. Furthermore, references to values ​​expressed as ranges include all values ​​within that range. Many other embodiments will be apparent only to those skilled in the art upon reading this specification. Other embodiments may be used and derived from this disclosure, such that structural substitutions, logical substitutions, or other changes can be made without departing from the scope of this disclosure. Therefore, this disclosure should be considered exemplary and not restrictive.

Claims

1. An electronic device, the electronic device comprising: A substrate (200) defining a gate trench (2404) having sidewalls and extending from a main surface (226) of the substrate to a depth of the gate trench, wherein the substrate includes a semiconductor layer (234) having a first conductivity type. The main body region (1346) has a second conductivity type opposite to the first conductivity type; The main contact area (1826) has the second conductivity type; A buried shield (426) having the second conductivity type and peak dopant concentration, wherein the buried shield is stacked under the gate trench; A deep body region (1046) having the second conductivity type and a peak dopant concentration, wherein the peak dopant concentration of the deep body region is greater than the peak dopant concentration of the buried shield; A gate dielectric layer (2814) is located within the gate trench; and Gate member (2930), the gate member including a portion extending into the gate trench. in: In a direction perpendicular to the main surface, the deep main body region is located between the main body region and the buried shielding component. The body region is spaced from the gate member along a portion of the sidewall of the gate trench and through the gate dielectric layer. The gate component does not overlap with the body contact area, and The gate member is stacked on top of the deep body region and is spaced apart from the deep body region by the body region.

2. The electronic device of claim 1, wherein each of the body contact region and the deep body region comprises a dopant, the dopant being a metallic element with an atomic number of at least 13.

3. The electronic device according to claim 2, wherein the semiconductor layer is a SiC layer.

4. The electronic device according to claim 1, further comprising: The gap region (452) has the first conductivity type and is at least partially defined by the buried shield.

5. The electronic device according to claim 4, further comprising: Carrier accumulation region (938) having the first conductivity type, wherein the carrier accumulation region extends across the entire gap region and is located between the body region and the buried shield.

6. The electronic device according to claim 5, further comprising: A carrier distribution layer (936) having the first conductivity type, wherein the gap region includes a portion of the carrier distribution layer and a portion of the carrier accumulation region.

7. The electronic device according to claim 6, wherein the buried shield is stacked on top of the carrier distribution layer.

8. An electronic device, the electronic device comprising: A substrate (200) defining a gate trench (2404) extending from the main surface of the substrate to a gate trench depth, wherein the substrate includes a semiconductor layer (234) having a first conductivity type. The main contact area (1826) has a second conductivity type opposite to the first conductivity type; A buried shield (426) having the second conductivity type and peak dopant concentration, wherein the buried shield is stacked under the gate trench; A gap region (452) having the first conductivity type, wherein the gap region is at least partially defined by the buried shield; and Deep host region (1046), the deep host region having the second conductivity type and peak dopant concentration, wherein: The main contact area, the buried shielding component, and the deep main body area are electrically coupled to each other. The deep main body region does not overlap with all of the gap regions. The deep body region is spaced apart from the main surface of the substrate, and The peak dopant concentration in the deep body region is greater than the peak dopant concentration in the buried shield.

9. The electronic device according to claim 8, further comprising: Body region (1346), the body region having the second conductivity type and along the sidewall of the gate trench; A gate dielectric layer (2814) is located within the gate trench, wherein the gate dielectric layer has a thickness; and Gate member (2930), the gate member including a portion extending into the gate trench, wherein the gate member: The gate dielectric layer is separated from the body region. A body contact distance is separated from the main body contact area, and the main body contact distance is greater than the thickness of the gate dielectric layer, and The deep body region is separated from the deep body region by a deep body distance, which is greater than the thickness of the gate dielectric layer.

10. The electronic device according to claim 9, further comprising: Source regions (436 and 1356) having the first conductivity type, wherein the gate dielectric layer, the source regions, and the body region are disposed between the deep body region and the gate member along a direction perpendicular to the main surface.

11. The electronic device of claim 10, wherein the source region comprises a shallow portion (1356) and a deep portion (436), wherein the shallow portion overlaps the gap region and the deep portion does not overlap the gap region.

12. The electronic device according to claim 8, wherein, viewed from a plan view: The deep body region has a length and a width, wherein the length is greater than the width, and the length of the deep body region is along a first line. The gap region has a length and a width, wherein the length is greater than the width, and the length of the gap region follows a second line. The first line and the second line are at a 90° angle. + / -5 The angles intersect.

13. A method of forming an electronic device, the method comprising: Determine the minimum distance (3230) between the gate component and the doped region within the compound semiconductor material, where: The doped region has a dopant, which is a metallic element with an atomic number of at least 13, and The doped region has at least 5 × 10 18 atoms / cm 3 Peak dopant concentration; A buried shield (426) is formed within a compound semiconductor layer (234) of a substrate (220), wherein the compound semiconductor layer has a first conductivity type and the buried shield has a second conductivity type opposite to the first conductivity type; A host region (1346) is formed within the compound semiconductor layer, wherein the host region has the second conductivity type and the peak dopant concentration is less than 5 × 10⁻⁶. 18 atoms / cm 3 ; A main contact region (1826) is formed within the compound semiconductor layer, wherein the main contact region has the second conductivity type and at least 5 × 10 18 atoms / cm 3 The peak dopant concentration, and the main contact area is electrically coupled to the buried shield; The substrate is patterned to define a gate trench (2404) having sidewalls and extending from the main surface of the substrate to a depth of the gate trench; and A gate member (2930) is formed, the gate member including a portion extending into the gate trench, wherein the gate member: The distance between the main body area and the main body area is less than the minimum distance, and The contact area between the contact area and the main body is separated by a contact distance, which is at least the minimum distance.

14. The method according to claim 13, further comprising: A deep body region (1046) is formed, the deep body region having the second conductivity type and at least 5 × 10 18 atoms / cm 3 The peak dopant concentration, where: The gate member is separated from the deep body region by a deep body distance, which is at least the minimum distance.

15. The method according to claim 13, further comprising: A deep host region (1046) is formed within the compound semiconductor layer, wherein the deep host region has the second conductivity type and at least 5 × 10 18 atoms / cm 3 The peak dopant concentration, where: In a direction perpendicular to the main surface, the main body region is located between the deep main body region and the main surface. The gate component is stacked on top of the deep body region, and The gate member is separated from the deep body region by a deep body distance, which is at least the minimum distance.

16. The method of claim 15, wherein the buried shield at least partially defines a gap region (452) having the first conductivity type, and the deep body region is spaced apart from the gap region and does not overlap with or extend into the gap region.

17. The method according to claim 13, further comprising: Forming a current accumulation region (2930) having the first conductivity type, wherein the buried shield: With less than 5×10 18 atoms / cm 3 The peak dopant concentration, Separated from the main body area by the current accumulation region, and A distance less than the minimum distance between the gate member and the gate member.

18. The method of claim 13, wherein determining the minimum distance is performed such that the minimum distance varies with the peak dopant concentration of the doped region.

19. The method of claim 18, wherein for a peak dopant concentration having a first value, the minimum distance is a first distance, and for a peak dopant concentration having a second value, the minimum distance is a second distance, wherein the first distance is different from the second distance, and the first value is different from the second value.

20. The method of claim 13, wherein determining the minimum distance comprises a horizontal component along the main surface and a vertical component in a direction perpendicular to the main surface.

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