A low on-resistance mosfet power device and a method for manufacturing the same

Abstract

The application belongs to the technical field of semiconductor, and provides a MOSFET power device with low on-resistance and a preparation method thereof. The MOSFET power device with low on-resistance comprises a semiconductor substrate, an N-type drift region, a P-type well region, a P-type doped region, a source doped region, a source, a gate, a gate dielectric layer and a drain. When the voltage of the gate of the MOSFET power device exceeds the threshold voltage, the channels formed by the positions of the P-type doped region and the P-type well region in contact with the gate dielectric layer are all turned on, and then the MOSFET power device starts to work. Since the on-resistance of the P-type doped region is small, the MOSFET power device can have a small on-resistance when working, so that the MOSFET power device can have a large threshold voltage while reducing the on-resistance of the MOSFET power device.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a MOSFET power device with low on-resistance and its fabrication method. Background Technology

[0002] With the increasing integration of integrated circuits, MOSFET power devices are frequently used in the design of high-voltage power integrated circuits due to their outstanding advantages such as high voltage resistance, large drive current, high output power, and good switching characteristics. They are especially prevalent in high-voltage power amplifiers. An important parameter of MOSFET power devices is their on-resistance. In practical applications, on-resistance is a crucial parameter closely related to performance, and its magnitude is closely related to the maximum output power of the LDMOS.

[0003] For high-performance power devices, in addition to a high threshold voltage, the lowest possible on-resistance is also required. On-resistance always decreases with increasing drift region doping concentration, while the relationship between threshold voltage and drift region doping concentration is often complex. Therefore, we need to optimize the relationship between threshold voltage and on-resistance, minimizing on-resistance while maintaining a certain threshold voltage to obtain the maximum possible output power.

[0004] This shows that existing LDMOS devices cannot achieve a balance between threshold voltage and on-resistance. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides a MOSFET power device with low on-resistance and its fabrication method, aiming to solve the problem that existing LDMOS devices cannot achieve a balance between threshold voltage and on-resistance.

[0006] A first aspect of this application provides a low on-resistance MOSFET power device, the low on-resistance MOSFET power device comprising:

[0007] Semiconductor substrate;

[0008] An N-type drift region is disposed on the front side of the semiconductor substrate;

[0009] A P-type well region is disposed on the N-type drift region;

[0010] A P-type doped region is disposed on the P-type well region;

[0011] The source doped region is in contact with the P-type doped region;

[0012] The source electrode is in contact with the source doped region and the P-type doped region.

[0013] Gate;

[0014] A gate dielectric layer is disposed between the gate and the N-type drift region, the P-type well region, the P-type doped region, and the source doped region;

[0015] The drain is located on the back side of the semiconductor substrate.

[0016] In one embodiment, the N-type drift region has an "L"-shaped structure, and the P-type trap region is located on the horizontal portion of the N-type drift region.

[0017] In one embodiment, the P-type well region has an "L"-shaped structure; wherein the P-type doped region and the source doped region are both located on the horizontal portion of the P-type well region.

[0018] In one embodiment, the source doped region is located in the middle of the P-type doped region to divide the P-type doped region into a first P-type doped unit and a second P-type doped unit; wherein the gate dielectric layer is in contact with the second P-type doped unit.

[0019] In one embodiment, the width of the first P-type doped unit is greater than the width of the second P-type doped unit.

[0020] In one embodiment, the gate dielectric layer is disposed on the source doped region, the P-type doped region, the P-type well region, and the N-type drift region.

[0021] In one embodiment, the N-type drift region has an "L"-shaped structure, the P-type well region is disposed on the vertical portion of the N-type drift region, and the gate dielectric layer is disposed on the horizontal portion of the N-type drift region.

[0022] In one embodiment, the P-type doped region has an "L"-shaped structure, and the source doped region is located on the horizontal portion of the P-type doped region.

[0023] In one embodiment, the gate dielectric layer has a concave structure, and the gate metal layer is disposed within the concave area of ​​the gate dielectric layer.

[0024] A second aspect of this application provides a method for fabricating a low on-resistance MOSFET power device, comprising:

[0025] An N-type drift region is formed on the front side of the semiconductor substrate;

[0026] A P-type well region is formed on the N-type drift region;

[0027] A P-type doped region is formed on the P-type well region;

[0028] A source doped region is formed; wherein the source doped region is in contact with the P-type doped region;

[0029] A gate dielectric layer, a gate, and a source are formed; wherein the gate dielectric layer is disposed between the gate and the N-type drift region, the P-type well region, the P-type doped region, and the source doped region; the source is in contact with the source doped region and the P-type doped region;

[0030] A drain electrode is formed on the back side of the semiconductor substrate.

[0031] The beneficial effects of this application embodiment compared with the prior art are as follows: The conduction channel is composed of a P-type doped region and a P-type well region. When the gate voltage of the MOSFET power device exceeds the threshold voltage, the channels formed by the P-type doped region and the P-type well region in contact with the gate dielectric layer are turned on, and the MOSFET power device starts to work. Since the conduction resistance of the P-type doped region is small, the MOSFET power device can have a small conduction resistance when working. Since the P-type well region can maintain a high threshold voltage, the MOSFET power device can have a large threshold voltage when working. Thus, the MOSFET power device can have a large threshold voltage while reducing the conduction resistance of the MOSFET power device. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the structure of a low on-resistance MOSFET power device provided in one embodiment of this application. Figure 1 ;

[0033] Figure 2 This is a schematic diagram of the structure of a low on-resistance MOSFET power device provided in one embodiment of this application. Figure 2 ;

[0034] Figure 3 This is a schematic diagram of the fabrication steps of a low on-resistance MOSFET power device provided in one embodiment of this application;

[0035] Figure 4 This is a schematic diagram of the N-type drift region sequentially formed according to an embodiment of this application;

[0036] Figure 5 This is a schematic diagram of the formation of a P-type well region provided in one embodiment of this application;

[0037] Figure 6 This is a schematic diagram of the formation of a P-type doped region provided in one embodiment of this application;

[0038] Figure 7 This is a schematic diagram of the formation of the source doped region provided in one embodiment of this application;

[0039] Figure 8This is a schematic diagram of the formation of the gate dielectric layer, the gate, and the source according to an embodiment of this application;

[0040] Figure 9 This is a schematic diagram of the drain electrode after formation according to an embodiment of this application;

[0041] Figure 10 This is a schematic diagram of the formation of an N-type drift region, a P-type well region, a P-type doped region, and a source doped region provided in another embodiment of this application;

[0042] Figure 11 This is a schematic diagram of the formation of the gate dielectric layer and the gate as provided in another embodiment of this application. Detailed Implementation

[0043] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0044] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0045] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0046] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means one or more, unless otherwise explicitly specified.

[0047] In this application specification, references to "one embodiment," "some embodiments," or "embodiment" mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," "in a particular embodiment," "in a particular application," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. Furthermore, in one or more embodiments, specific features, structures, or characteristics may be combined in any suitable manner.

[0048] With the increasing integration of integrated circuits, MOSFET power devices are frequently used in the design of high-voltage power integrated circuits due to their outstanding advantages such as high voltage resistance, large drive current, high output power, and good switching characteristics. They are especially prevalent in high-voltage power amplifiers. An important parameter of MOSFET power devices is their on-resistance. In practical applications, on-resistance is a crucial parameter closely related to performance, and its magnitude is closely related to the maximum output power of the LDMOS.

[0049] For high-performance power devices, in addition to a high threshold voltage, the lowest possible on-resistance is also required. On-resistance always decreases with increasing drift region doping concentration, while the relationship between threshold voltage and drift region doping concentration is often complex. Therefore, we need to optimize the relationship between threshold voltage and on-resistance, minimizing on-resistance while maintaining a certain threshold voltage to obtain the maximum possible output power.

[0050] This shows that existing LDMOS devices cannot achieve a balance between threshold voltage and on-resistance.

[0051] To address the technical problem of the inability to balance threshold voltage and on-resistance in LDMOS devices, embodiments of this application provide a low-on-resistance MOSFET power device, as referenced above. Figure 1 As shown, the low on-resistance MOSFET power device includes: a semiconductor substrate 10, an N-type drift region 20, a P-type well region 30, a P-type doped region 40, a source doped region 50, a source 60, a gate dielectric layer 70, a gate 80, and a drain 90.

[0052] Specifically, the N-type drift region 20 is disposed on the front side of the semiconductor substrate 10. The P-type well region 30 is disposed on the N-type drift region 20. The P-type doped region 40 is disposed on the P-type well region 30. The source doped region 50 is in contact with the P-type doped region 40. The source 60 is in contact with the source doped region 50 and the P-type doped region 40. The gate dielectric layer 70 is disposed between the gate 80 and the N-type drift region 20, the P-type well region 30, the P-type doped region 40, and the source doped region 50. The drain 90 is disposed on the back side of the semiconductor substrate 10.

[0053] In this embodiment, a P-type doped region 40 is disposed on a P-type well region 30, and a source doped region 50 is in contact with the P-type doped region 40. Specifically, a rectangular P-type doped region 40 can be formed on the P-type well region 30 by epitaxy, and then N-type silicon carbide material is doped at the middle position of the P-type doped region 40 to form the source doped region 50.

[0054] In this embodiment, a gate dielectric layer 70 is disposed between the gate 80 and the N-type drift region 20, the P-type well region 30, the P-type doped region 40, and the source doped region 50. It is understood that the gate dielectric layer 70 is used to isolate the gate 80 from the N-type drift region 20, the P-type well region 30, the P-type doped region 40, and the source doped region 50. For example, the gate 80 is isolated from the N-type drift region 20, from the P-type well region 30, from the P-type doped region 40, and from the source doped region 50 by the gate dielectric layer 70. This operation ensures that when the MOSFET power device is operating, a conduction channel is formed at the locations of the P-type doped region 40 and the P-type well region 30 that are in contact with the gate dielectric layer 70 (see...). Figure 1 (Dashed line diagram) This design allows the on-resistance to be composed of the P-type doped region 40 and the P-type well region 30 connected in series. Since the P-type doped region 40 is heavily doped with P-type ions, its on-resistance is relatively low. In this embodiment, by setting the on-resistance to be composed of the P-type doped region 40 and the P-type well region 30 connected in series, the on-resistance of the MOSFET power device can be reduced.

[0055] In this embodiment, the conduction channel is composed of a P-type doped region 40 and a P-type well region 30. The concentration of P-type ions in the P-type well region 30 is relatively small. For example, the concentration of P-type ions in the P-type well region 30 is at least two orders of magnitude smaller than the concentration of P-type ions in the P-type doped region 40. This allows the P-type well region 30 to maintain a high threshold voltage. Even if the voltage of the gate 80 of the MOSFET power device causes the P-type doped region 40 to form a channel, the P-type well region 30 does not conduct. This allows the device to remain off. Therefore, this embodiment of the application can enable the MOSFET power device to have a large threshold voltage while reducing conduction.

[0056] In this embodiment, when the voltage of the gate 80 of the MOSFET power device exceeds the threshold voltage, causing the channels formed by the P-type doped region 40 and the P-type well region 30 in contact with the gate dielectric layer 70 to be turned on, the MOSFET power device starts to work. Since the on-resistance of the P-type doped region 40 is small, the MOSFET power device can have a small on-resistance when working. Since the P-type well region 30 can maintain a high threshold voltage, the MOSFET power device can have a large threshold voltage when working. Thus, the on-resistance of the MOSFET power device is reduced while the MOSFET power device can have a large threshold voltage.

[0057] In one embodiment, the semiconductor substrate 10 can be made of N-type SiC. N-type SiC can be formed by heavily doping SiC with N-type ions.

[0058] In one embodiment, the material of the N-type drift region 20 can be N-type SiC material.

[0059] In one embodiment, the P-type well region 30 can be formed by doping with P-type material.

[0060] In one embodiment, the P-type doped region 40 can be formed by doping with P-type material.

[0061] In one embodiment, the material of the source doped region 50 can be an N-type SiC material.

[0062] In one embodiment, the material of the gate dielectric layer 70 may be silicon oxide.

[0063] In one embodiment, the source 60, drain 90, and gate 80 can all be made of metal.

[0064] In one embodiment, reference Figure 1 As shown, the N-type drift region 20 has an "L"-shaped structure, which includes a horizontal part and a vertical part. The P-type trap region 30 is located on the horizontal part of the N-type drift region 20.

[0065] Specifically, the N-type drift region 20 has an "L"-shaped structure, the gate dielectric layer 70 is in contact with the vertical portion of the N-type drift region 20, and the P-type well region 30 is located on the horizontal portion of the N-type drift region 20. It should be noted that the maximum thickness of the P-type well region 30 is the same as the thickness of the vertical portion of the N-type drift region 20, so that the upper surface of the P-type well region 30 is flush with the upper surface of the N-type drift region 20.

[0066] In one embodiment, reference Figure 1 As shown, the P-type well region 30 has an "L"-shaped structure; wherein, the P-type doped region 40 and the source doped region 50 are both located on the horizontal part of the P-type well region 30.

[0067] In this embodiment, the upper surfaces of the P-type doped region 40 and the source doped region 50 are flush with the upper surface of the P-type well region 30, thus forming a rectangle with the P-type doped region 40, the source doped region 50, and the P-type well region 30. The gate dielectric layer 70 contacts the upper surfaces of the source doped region 50, the P-type doped region 40, the P-type well region 30, and the N-type drift region 20, respectively. When the voltage of the gate 80 exceeds the threshold voltage, causing the channels formed by the P-type doped region 40 and the P-type well region 30 in contact with the gate dielectric layer 70 to conduct, the MOSFET power device starts to operate. Because the on-resistance of the P-type doped region 40 is small, the MOSFET power device can have a small on-resistance during operation. Because the P-type well region 30 can maintain a high threshold voltage, the MOSFET power device can have a large threshold voltage during operation. Thus, the on-resistance of the MOSFET power device is reduced while a large threshold voltage is achieved.

[0068] In one embodiment, reference Figure 1 As shown, the source doped region 50 is located in the middle of the P-type doped region 40, so as to divide the P-type doped region 40 into a first P-type doped unit 41 and a second P-type doped unit 42; wherein, the gate dielectric layer 70 is in contact with the second P-type doped unit 42.

[0069] In this embodiment, reference Figure 1 As shown, the second P-type doped cell 42 is located on the horizontal portion of the P-type well region 30, and the second P-type doped cell 42 is in contact with the vertical portion of the P-type well region 30. The upper surface of the second P-type doped cell 42 is in contact with the gate dielectric layer 70. In this operation, when the voltage of the gate 80 exceeds the threshold voltage, the channel between the second P-type doped cell 42 and the vertical portion of the P-type well region 30 is turned on. Because the on-resistance of the second P-type doped cell 42 is small, the on-resistance of the MOSFET power device can be reduced. Furthermore, since the conduction channel is also composed of the vertical portion of the P-type well region 30, the vertical portion of the P-type well region 30 can have a larger threshold voltage. Thus, even if the channel of the second P-type doped region 40 is turned on, the device remains off because the vertical portion of the P-type well region 30 is not yet turned on. This allows the MOSFET power device to have a larger threshold voltage while reducing on-state voltage.

[0070] In one embodiment, reference Figure 1 As shown, the width of the first P-type doped unit 41 is greater than the width of the second P-type doped unit 42.

[0071] Specifically, the first P-type doped unit 41 is used to connect the voltage of the P-type well region 30 to 0V, and the second P-type doped unit 42 is used to reduce the on-resistance of the MOSFET power device. By setting the width of the first P-type doped unit 41 to be greater than the width of the second P-type doped unit 42, it is easier to connect the voltage of the P-type well region 30 to 0V, and the on-resistance of the power device can be reduced, thereby improving the overall performance of the power device.

[0072] In one embodiment, reference Figure 1 As shown, the gate dielectric layer 70 is disposed on the source doped region 50, the P-type doped region 40, the P-type well region 30, and the N-type drift region 20.

[0073] In this embodiment, by setting the gate dielectric layer 70 on the source doped region 50, the P-type doped region 40, the P-type well region 30, and the N-type drift region 20, the gate dielectric layer 70 isolates the gate 80 from the source doped region 50, the P-type doped region 40, the P-type well region 30, and the N-type drift region 20. This improves the stability of the MOSFET power device.

[0074] In one embodiment, reference Figure 2 As shown, the N-type drift region 20 has an "L"-shaped structure, the P-type well region 30 is disposed on the vertical part of the N-type drift region 20, and the gate dielectric layer 70 is disposed on the horizontal part of the N-type drift region 20.

[0075] In this embodiment, the gate dielectric layer 70 is disposed on the horizontal portion of the N-type drift region 20, and the gate dielectric layer 70 is used to isolate the gate 80 from the N-type drift region 20, the P-type well region 30, the P-type doped region 40, and the source doped region 50. It is understood that the thickness of the gate dielectric layer 70 is the sum of the thickness of the vertical portion of the N-type drift region 20, the thickness of the P-type well region 30, and the thickness of the P-type doped region 40, and the upper surface of the gate dielectric layer 70 is flush with the upper surface of the P-type doped region 40. Thus, when the voltage of the gate 80 exceeds the threshold voltage, causing the channels formed by the P-type doped region 40 and the P-type well region 30 in contact with the gate dielectric layer 70 to be turned on, the MOSFET power device begins to operate. Because the on-resistance of the P-type doped region 40 is small, the MOSFET power device can have a small on-resistance when it is working. Because the P-type well region 30 can maintain a high threshold voltage, the MOSFET power device can have a large threshold voltage when it is working. Thus, the on-resistance of the MOSFET power device is reduced while the MOSFET power device can have a large threshold voltage.

[0076] In one embodiment, reference Figure 2As shown, the P-type doped region 40 has an "L"-shaped structure, which has a horizontal part and a vertical part. The source doped region 50 is located on the horizontal part of the P-type doped region 40.

[0077] Specifically, the upper surface of the source doped region 50 is flush with the upper surface of the P-type doped region 40, so that the source doped region 50 and the P-type doped region 40 form a rectangle. The source 60 is located on the upper surface of the source doped region 50 and the upper surface of the P-type doped region 40, and is in contact with the source doped region 50 and the P-type doped region 40 respectively.

[0078] In one embodiment, reference Figure 2 As shown, the gate dielectric layer 70 has a concave structure, and the gate metal layer 80 is disposed in the concave groove of the gate dielectric layer 70.

[0079] In this embodiment, the gate dielectric layer 70 has a concave structure. The bottom of the gate dielectric layer 70 is in contact with the N-type drift region 20, and the first concave wall of the gate dielectric layer 70 is in contact with the N-type drift region 20, the P-type well region 30, the P-type doped region 40, and the source doped region 50. By setting the gate dielectric layer 70 to a concave structure, complete isolation between the gate 80 and the N-type drift region 20, the P-type well region 30, the P-type doped region 40, and the source doped region 50 is achieved, thereby improving the stability of the MOSFET power device.

[0080] This application also provides a method for fabricating a low on-resistance MOSFET power device, referencing... Figure 3 As shown, it includes steps S10 to S60.

[0081] Step S10 includes: referencing Figure 4 As shown, an N-type drift region 20 is formed on the front side of the semiconductor substrate 10.

[0082] Specifically, an N-type drift region 20 is formed on the front side of the semiconductor substrate 10 by epitaxy.

[0083] In one specific application embodiment, the semiconductor substrate 10 is made of N-type SiC material, which is formed by doping N-type ions into the SiC material.

[0084] In one specific application embodiment, the doping concentration of N-type ions in the semiconductor substrate 10 is 1 to 9 × 10⁻⁶. 19 / cm -3 .

[0085] In one specific application embodiment, the thickness of the semiconductor substrate 10 is 200um to 400um.

[0086] In one specific application embodiment, the doping concentration of N-type ions in the N-type drift region 20 is 1 to 9 × 10⁻⁶. 17 / cm -3 .

[0087] In one specific application embodiment, the thickness of the N-type drift region 20 is 400um to 600um.

[0088] Step S20 includes: referencing Figure 5 As shown, a P-type well region 30 is formed on the N-type drift region 20.

[0089] Specifically, the P-type well region 30 can be etched into the N-type drift region 20 by etching, or the P-type well region 30 can be made by implanting phosphorus ion impurities and annealing on the left side of the N-type drift region 20.

[0090] In one specific application embodiment, the doping concentration of the P-type well region 30 is 1 to 9 × 10⁻⁶. 16 / cm -3 .

[0091] In one specific application embodiment, the depth of the P-type well region 30 is 100um to 200um.

[0092] Step S30 includes: referencing Figure 6 As shown, a P-type doped region 40 is formed on the P-type well region 30.

[0093] Specifically, a P-type doped region 40 can be fabricated by implanting phosphorus ion impurities and annealing on the upper left side of the P-type well region 30.

[0094] In one specific application embodiment, the doping concentration of the P-type doped region 40 is 1 to 9 × 10⁻⁶. 19 / cm -3 .

[0095] In one specific application embodiment, the depth of the P-type doped region 40 is 50 μm to 100 μm.

[0096] In one specific application embodiment, the P-type doped ion can be a magnesium ion.

[0097] Step S40 includes: referencing Figure 7 As shown, a source doped region 50 is formed; wherein, the source doped region 50 is in contact with the P-type doped region 40.

[0098] For details, please refer to Figure 7 As shown, the source doped region 50 is fabricated by doping N-type SiC material at the middle position of the P-type doped region 40.

[0099] In one specific application embodiment, the doping concentration of the source doped region 50 is 1 to 9*10⁻⁶. 19 / cm -3 .

[0100] In one specific application embodiment, the depth of the source doped region 50 is the same as the depth of the P-type doped region 40.

[0101] Step S50 includes: referencing Figure 8 As shown, a gate dielectric layer 70, a gate 80, and a source 60 are formed; wherein, the gate dielectric layer 70 is disposed between the gate 80 and the N-type drift region 20, the P-type well region 30, the P-type doped region 40, and the source doped region 50; the source 60 is in contact with the source doped region 50 and the P-type doped region 40.

[0102] Specifically, the source 60 is formed by depositing corresponding metal materials over the source doped region 50 and the P-type doped region 40.

[0103] In this embodiment, a gate dielectric layer 70 can be formed epitaxially in the N-type drift region 20, P-type well region 30, P-type doped region 40 and source doped region 50, and then a gate 80 can be formed on the gate dielectric layer 70.

[0104] In one specific embodiment, the source electrode 60 can be any one of gold, silver, platinum, palladium, iridium, etc.

[0105] In one specific embodiment, the material of the gate dielectric layer 70 can be any one of HfO2, Al2O3, ZrO2, HfSiO, HfSiON, HfTaO, and HfZrO.

[0106] In one specific embodiment, the material of the gate dielectric layer 70 may be silicon dioxide.

[0107] In one specific embodiment, the gate 80 can be made of a metallic material.

[0108] Step S60 includes: referencing Figure 9 As shown, a drain 90 is formed on the back side of the semiconductor substrate 10.

[0109] In this embodiment, the position of the drain 90 is determined on the back side of the semiconductor substrate 10 by means of a mask, and the corresponding metal material is deposited to form the drain 90.

[0110] In one embodiment, when it is necessary to make Figure 2 When designing a low on-resistance MOSFET power device, the method is as follows: (Refer to...) Figure 10 As shown, an N-type drift region 20, a P-type well region 30, a P-type doped region 40, and a source doped region 50 are sequentially epitaxially formed on a semiconductor substrate 10. (Reference) Figure 11As shown, the position of the gate dielectric layer 70 is determined by masking above and to the right of the P-type doped region 40. Trenches of the gate dielectric layer 70 are etched and filled with a suitable material, such as silicon dioxide, to form the gate dielectric layer 70. Then, the position of the gate 80 is determined by masking on the silicon dioxide. Trenches of the gate 80 are etched and filled with a suitable metal to form the gate 80. The gate 80 can be a metal material, a polysilicon material, or a metal material. Then, the source 60 and drain 90 are deposited. Following this operation, when the voltage of the gate 80 exceeds the threshold voltage, causing the channels formed by the P-type doped region 40 and the P-type well region 30 in contact with the gate dielectric layer 70 to conduct, the MOSFET power device begins to operate. Because the on-resistance of the P-type doped region 40 is small, the MOSFET power device can have a small on-resistance during operation. Because the P-type well region 30 can maintain a high threshold voltage, the MOSFET power device can have a large threshold voltage during operation. Thus, while reducing the on-resistance of the MOSFET power device, it can also achieve a large threshold voltage.

[0111] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0112] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A MOSFET power device with low on-resistance, characterized in that, The low on-resistance MOSFET power device includes: Semiconductor substrate; An N-type drift region is disposed on the front side of the semiconductor substrate; A P-type well region is disposed on the N-type drift region; A P-type doped region is disposed on the P-type well region; The source doped region is in contact with the P-type doped region; The source electrode is in contact with the source doped region and the P-type doped region. Gate; A gate dielectric layer is disposed between the gate and the N-type drift region, the P-type well region, the P-type doped region, and the source doped region; The drain electrode is located on the back side of the semiconductor substrate; The N-type drift region has an "L"-shaped structure, and the P-type well region is located on the horizontal portion of the N-type drift region. The P-type well region also has an "L"-shaped structure. The P-type doped region and the source doped region are both located on the horizontal portion of the P-type well region.

2. The low on-resistance MOSFET power device as described in claim 1, characterized in that, The source doped region is located in the middle of the P-type doped region to divide the P-type doped region into a first P-type doped unit and a second P-type doped unit; wherein the gate dielectric layer is in contact with the second P-type doped unit.

3. The low on-resistance MOSFET power device as described in claim 2, characterized in that, The width of the first P-type doped unit is greater than the width of the second P-type doped unit.

4. The low on-resistance MOSFET power device as described in claim 2, characterized in that, The gate dielectric layer is disposed on the source doped region, the P-type doped region, the P-type well region, and the N-type drift region.

5. The low on-resistance MOSFET power device as described in claim 1, characterized in that, The N-type drift region has an "L"-shaped structure, the P-type well region is located on the vertical part of the N-type drift region, and the gate dielectric layer is located on the horizontal part of the N-type drift region.

6. The low on-resistance MOSFET power device as described in claim 4, characterized in that, The P-type doped region has an "L"-shaped structure, and the source doped region is located on the horizontal part of the P-type doped region.

7. The low on-resistance MOSFET power device as described in claim 4, characterized in that, The gate dielectric layer has a concave structure, and the gate metal layer is disposed in the groove of the gate dielectric layer.

8. A method for fabricating a low on-resistance MOSFET power device as described in any one of claims 1-7, characterized in that, include: An N-type drift region is formed on the front side of the semiconductor substrate; A P-type well region is formed on the N-type drift region; A P-type doped region is formed on the P-type well region; A source doped region is formed; wherein the source doped region is in contact with the P-type doped region; A gate dielectric layer, a gate, and a source are formed; wherein the gate dielectric layer is disposed between the gate and the N-type drift region, the P-type well region, the P-type doped region, and the source doped region; the source is in contact with the source doped region and the P-type doped region; A drain electrode is formed on the back side of the semiconductor substrate.

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