Techniques for selecting processor frequency

Abstract

The disclosure relates to techniques for selecting processor frequencies. Apparatuses, systems, and techniques for selecting processing unit frequencies. In at least one embodiment, an operating frequency of the one or more integrated circuits is dynamically adjusted based at least in part on a dynamically measured maximum throughput of the one or more integrated circuits.

Description

Technical Field

[0001] At least one embodiment relates to improving the processing resources of one or more processing units. For example, at least one embodiment relates to a processor or computing system for increasing the design frequency of a graphics processing unit using the various novel techniques described herein. Background Technology

[0002] Limiting user programs to a single design frequency of the GPU can lead to underutilization of computing resources. GPU performance can be improved by customizing the design frequency for user programs. Attached Figure Description

[0003] Figure 1 An example of a system for selecting the design frequency of a processing unit according to at least one embodiment is shown;

[0004] Figure 2 An example of a process for selecting the design frequency of a processing unit according to at least one embodiment is shown;

[0005] Figure 3 An example of a process for selecting the design frequency of a processing unit according to at least one embodiment is shown;

[0006] Figure 4 An example of selecting the design frequency of a processing unit according to at least one embodiment is shown;

[0007] Figure 5 An example of a processor having a module for selecting the design frequency of a processing unit according to at least one embodiment is shown;

[0008] Figure 6 An example of a block diagram according to at least one embodiment is shown, illustrating a driver and / or runtime that includes one or more libraries to provide one or more application programming interfaces (APIs);

[0009] Figure 7 An exemplary data center according to at least one embodiment is shown;

[0010] Figure 8 A processing system according to at least one embodiment is shown;

[0011] Figure 9 A computer system according to at least one embodiment is shown;

[0012] Figure 10 A system according to at least one embodiment is shown;

[0013] Figure 11 An exemplary integrated circuit according to at least one embodiment is shown;

[0014] Figure 12 A computing system according to at least one embodiment is shown;

[0015] Figure 13 An APU according to at least one embodiment is shown;

[0016] Figure 14 A CPU according to at least one embodiment is shown;

[0017] Figure 15 An exemplary accelerator integration slice according to at least one embodiment is shown;

[0018] Figures 16A-16B An exemplary graphics processor according to at least one embodiment is shown;

[0019] Figure 17A A graphics core according to at least one embodiment is shown;

[0020] Figure 17B A GPGPU according to at least one embodiment is shown;

[0021] Figure 18A A parallel processor according to at least one embodiment is shown;

[0022] Figure 18B A processing cluster according to at least one embodiment is shown;

[0023] Figure 18C A graphics multiprocessor according to at least one embodiment is shown;

[0024] Figure 19 A graphics processor according to at least one embodiment is shown;

[0025] Figure 20 A processor according to at least one embodiment is shown;

[0026] Figure 21 A processor according to at least one embodiment is shown;

[0027] Figure 22 A graphics processor core according to at least one embodiment is shown;

[0028] Figure 23 A PPU according to at least one embodiment is shown;

[0029] Figure 24 A GPC according to at least one embodiment is shown;

[0030] Figure 25 A streaming multiprocessor according to at least one embodiment is illustrated;

[0031] Figure 26 A software stack of a programming platform according to at least one embodiment is shown;

[0032] Figure 27 The illustration shows an embodiment according to at least one of the embodiments. Figure 26 The CUDA implementation of the software stack;

[0033] Figure 28 The illustration shows an embodiment according to at least one of the embodiments. Figure 26 The ROCm implementation of the software stack;

[0034] Figure 29 The illustration shows an embodiment according to at least one of the embodiments. Figure 26 The OpenCL implementation of the software stack;

[0035] Figure 30 Software supported by a programming platform according to at least one embodiment is shown;

[0036] Figure 31 The illustration shows an embodiment of at least one of the following: Figure 26-29 Compiled code executed on the programming platform;

[0037] Figure 32 The illustration shows an embodiment of at least one of the following: Figure 26-29 More detailed coding is performed on the programming platform;

[0038] Figure 33 This illustrates the transformation of source code before compilation, according to at least one embodiment;

[0039] Figure 34A A system configured to compile and execute CUDA source code using different types of processing units, according to at least one embodiment, is shown;

[0040] Figure 34B The diagram illustrates a configuration, according to at least one embodiment, to compile and execute using a CPU and a CUDA-enabled GPU. Figure 34A The system of CUDA source code;

[0041] Figure 34C The diagram illustrates a configuration, according to at least one embodiment, to compile and execute using a CPU and a GPU with CUDA disabled. Figure 34A The system of CUDA source code;

[0042] Figure 35 The diagram illustrates a method according to at least one embodiment. Figure 34C An example kernel converted by the CUDA to HIP conversion tool;

[0043] Figure 36 A more detailed description is provided according to at least one embodiment. Figure 34C GPUs without CUDA enabled;

[0044] Figure 37 This illustrates how threads of an exemplary CUDA grid, according to at least one embodiment, are mapped to... Figure 36 Different computational units;

[0045] Figure 38 This illustrates how to migrate existing CUDA code to data-parallel C++ code according to at least one embodiment; and

[0046] Figure 39 Components of a system for accessing a large language model according to at least one embodiment are shown. Detailed Implementation

[0047] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of at least one embodiment. However, those skilled in the art will understand that the inventive concept can be practiced without one or more of these specific details.

[0048] In at least one embodiment, the technique described herein relates to comparing sensor data of the processor while executing a user program with sensor data of the processor while executing a benchmark program at the same frequency to determine how much the processor's frequency can be increased while executing the user program. In at least one embodiment, the benchmark program is designed for worst-case scenarios of the processor, such that at a certain frequency, any user program will produce the same or fewer errors. The benchmark program can be run to record sensor data from the processor's sensors, and when the user program runs, the processor can use the sensor data to adjust the frequency based on the difference between the recorded sensor data and the recorded sensor data.

[0049] In at least one embodiment, one or more circuits may be used to dynamically adjust the operating frequency of one or more integrated circuits, at least in part, based on the maximum throughput of dynamically measured data of the one or more integrated circuits. In at least one embodiment, the operating frequency may be the design frequency of the one or more integrated circuits, and / or the maximum permissible set frequency of the one or more integrated circuits, for executing one or more user programs. In at least one embodiment, the operating frequency may be as follows: Figure 1The design frequency shown is 104. In at least one embodiment, the one or more integrated circuits may include any processing unit, such as a graphics processing unit (“GPU”), a central processing unit (“CPU”), or other parallel processing unit (“PPU”). In at least one embodiment, the one or more integrated circuits may be as follows: Figure 1 The processing unit 102 shown. In at least one embodiment, the dynamic adjustment may refer to setting different design frequencies for different user applications or programs. In at least one embodiment, the maximum throughput may refer to the state where the one or more integrated circuits have a maximum clock delay, exceeding which an error may occur. In at least one embodiment, the maximum throughput may be dynamically measured by a critical path monitor. In at least one embodiment, the maximum throughput may be dynamically measured in one or more critical paths. In at least one embodiment, the maximum throughput may be indicated by a trim setting in one or more critical path monitors. In at least one embodiment, the maximum throughput is obtained by comparing data collected during benchmark program execution with data collected during user program execution.

[0050] In at least one embodiment, one or more circuits may be used to select the frequency of the processing unit based at least in part on a comparison of two or more sets of data collected while running two or more applications on the processing unit. In at least one embodiment, the selected frequency may be the design frequency or the maximum permissible set frequency of the processing unit. In at least one embodiment, a critical path monitor (CPM) included in the processing unit may be used to collect two or more sets of data. In at least one embodiment, the two or more applications may include a reference application and at least one user application. In at least one embodiment, the reference application corresponds to a reference frequency for benchmarking, while the user application corresponds to a user frequency for updating and / or setting the design frequency of the processing unit. In at least one embodiment, the comparison between the two or more sets of data indicates a change in the processing unit's design frequency by identifying the distance of the user application from a fault compared to the reference application. In at least one embodiment, the two or more sets of data are collected from one or more critical paths of the processing unit. In at least one embodiment, different frequencies may be selected for different applications.

[0051] In at least one embodiment, one or more circuits may acquire two or more passing trims of the processing unit, calculate two or more frequencies based on comparisons between the two or more passing trims, and calculate a change in the design frequency of the processing unit based on comparisons between the two or more frequencies. In at least one embodiment, the two or more passing trims include a first passing trim, a second passing trim, and a third passing trim, for example, according to... Figure 2 Those described. In at least one embodiment, the two or more frequencies may include a first frequency and a second frequency, for example, according to... Figure 2 Those described.

[0052] In at least one embodiment, the technical effect is achieved by enabling the customization of performance-related strategies to allow specific applications to better utilize the processing unit. In at least one embodiment, the user is enabled to optimize the voltage-frequency (“VF”) curve of the processing unit for the application. In at least one embodiment, the proposed technique improves power efficiency by achieving higher performance per watt. Examples of various embodiments are now provided with reference to the accompanying drawings for further description.

[0053] Figure 1 An example of a system 100 for selecting the design frequency of a processing unit according to at least one embodiment is shown. In at least one embodiment, such as Figure 1 The system shown is executed using one or more systems, processors, or communication devices. In at least one embodiment, system 100 may include a processing unit 102 having a design frequency 104 and a frequency determination module 110. In at least one embodiment, processing unit 102 may be one or more graphics processing units (“GPUs”), central processing units (“CPUs”), or other parallel processing units (“PPUs”).

[0054] In at least one embodiment, the processing unit 102 may include a design frequency 104. In at least one embodiment, the design frequency 104 represents the maximum frequency at which the processing unit 102 can operate while running an application or program. In at least one embodiment, the design frequency 104 may be defined as a voltage-frequency (VF) curve, a fixed value, or any other form. In at least one embodiment, the design frequency 104 indicates the performance of the processing unit 102 relative to the application. In at least one embodiment, a higher design frequency 104 indicates better performance of the processing unit 102. In at least one embodiment, if the design frequency 104 is set too high for an application, it may cause problems when running the application, such as instability, crashes, data loss, overhitting, and / or other issues. In at least one embodiment, setting the design frequency 104 incurs associated hardware and software costs, and these costs increase with the number of applications running on the processing unit 102. Therefore, conventionally, the design frequency 104 is either limited to worst-case applications or has only a few values ​​stored in a bucket for several groups of applications, making it impossible to customize for individual applications. For example, conventionally, the design frequency 104 might be set to 1870MHz for all applications running on the processing unit 102, even if some applications run at higher frequencies without problems; this is possible, and even ideal. In at least one embodiment, the design frequency 104 is set or initialized based on a worst-case application. In at least one embodiment, the worst-case application could be a sparse HMMA, or any other application / program. In at least one embodiment, the design frequency 104 can be set or initialized using Modular Diagnostic Software (MODS) testing or any other method. In at least one embodiment, the design frequency 104 is set or initialized based on a reference application 106 running on the processing unit 102. In at least one embodiment, the techniques presented herein can be used to improve, update, or customize the design frequency 104 for other applications, such as user application 108.

[0055] In at least one embodiment, a reference application 106 and one or more user applications 108 may run on the processing unit 102. In at least one embodiment, the reference application 106 is used to set or initialize the design frequency 104. In at least one embodiment, running the reference application 106 on the processing unit 102 may be the worst-case scenario in terms of the performance of the processing unit 102. In at least one embodiment, the processing unit 102 may operate normally at the lowest frequency when running the reference application 106 compared to running other applications. In at least one embodiment, the design frequency of the user application 108 may be higher than the design frequency of the reference application 106. In at least one embodiment, the user application 108 may be any program or application created or provided by the user to run on the processing unit 102. In at least one embodiment, the reference application 106 and / or the user application 108 are created using Unified Computing Device Architecture (CUDA) instructions or any other parallel computing environment.

[0056] In at least one embodiment, reference application 106 and / or user application 108 are input to or processed by frequency determination module 110. In at least one embodiment, frequency determination module 110 may be located inside or coupled to processing unit 102. In at least one embodiment, frequency determination module 110 may also be located outside processing unit 102. In at least one embodiment, frequency determination module 110 determines one or more actual frequencies of processing unit 102 when processing unit 102 is running one or more applications. In at least one embodiment, frequency determination module 110 determines reference frequency 112 based on reference application 106. In at least one embodiment, frequency determination module 110 determines user frequency 114 based on user application 108. In at least one embodiment, frequency determination module 110 uses data collected by critical path monitor (CPM) to calculate frequencies. In at least one embodiment, CPM refers to replicas of critical paths in processing unit 102. In at least one embodiment, CPM may be logic cells and / or circuit chains of different voltage types located at multiple locations in a silicon chip. In at least one embodiment, the CPM indicates a path with a voltage frequency limiter that has minimum relaxation across multiple stress vectors on the processing unit 102. In at least one embodiment, the CPM has a trimmer to change its clock delay. In at least one embodiment, the CPM displays an error bit when a setup failure occurs. In at least one embodiment, the frequency determination module 110 determines the frequency based on comparing the minimum passing trim of the processing unit 102 under different conditions, where the minimum passing trim is defined as the last trim exceeding which the CPM indicates an error. In at least one embodiment, the frequency determination module 110 performs... Figure 2 and / or Figure 3 Some or all of the steps shown. For example, the frequency determination module 110 can perform the following steps: Figure 2 Steps 202-210 are shown. For example, the rate determination module 110 can perform actions such as... Figure 3 Steps 302-306 are shown. For a more detailed discussion of how the frequency determination module 110 works, please refer to [reference needed]. Figure 2 and Figure 3 The description.

[0057] In at least one embodiment, the frequency determination module 110 may calculate a reference frequency 112 and / or a user frequency 114 for both the reference application 106 and the user application 108. In at least one embodiment, multiple values ​​for the reference frequency 112 and / or the user frequency 114 may be calculated for multiple critical paths. In at least one embodiment, the reference frequency 112 indicates the actual frequency of the processing unit 102 when running the worst-case application after minimum pass-through fine-tuning of the CPM. In at least one embodiment, the user frequency 114 indicates the actual frequency of the processing unit 102 when running the user application 108 after minimum pass-through fine-tuning of the CPM. In at least one embodiment, considering that the reference application 106 represents the worst-case scenario for the processing unit 102, and therefore the processing unit 102 is utilized to a greater extent, the user application 108 may be able to sustain more CPM fine-tuning or more clock delays in the critical path than the reference application 106. Therefore, the user frequency 114 may be lower than the reference frequency 112 because more fine-tuning has been performed on the user application 108.

[0058] In at least one embodiment, a reference frequency 112 and a user frequency 114 are compared to determine a frequency difference 116. In at least one embodiment, the frequency difference 116 represents the percentage decrease from the reference frequency 112 to the user frequency 114. In at least one embodiment, if the user frequency 114 is higher than the reference frequency 112, the frequency difference 116 can be set to zero. In at least one embodiment, multiple values ​​of the frequency difference 116 are calculated for multiple critical paths, and a representative value is selected or calculated to represent all paths of the processing unit 102, wherein the representative value may be the average of the multiple values, the maximum value among the multiple values, the minimum value among the multiple values, the sum of the multiple values, and / or variations thereof.

[0059] In at least one embodiment, frequency difference 116 is used to update the design frequency 104 of user application 108 117. In at least one embodiment, frequency difference 116 indicates the percentage or rate by which the design frequency 104 can be increased. In at least one embodiment, update 117 can be performed for one or more user applications to obtain one or more updated design frequencies. For example, if the original design frequency of the processing unit is 2000MHz, and a first frequency difference of 5% is calculated for a first user application, the design frequency of the first user application can be increased by 5% to 2100MHz; if a second frequency difference of 10% is calculated for a second user application, the design frequency of the second user application can be increased by 10% to 2200MHz.

[0060] Figure 2An example of a process 200 for selecting a design frequency for a processing unit according to at least one embodiment is shown. In at least one embodiment, part or all of process 200 (or any other process described herein, or variations and / or combinations thereof) is executed under the control of one or more computer systems configured with computer-executable instructions and is implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more application programs) that is jointly executed on one or more processors by hardware, software, or a combination thereof. In at least one embodiment, the code is stored in the form of a computer program on a computer-readable storage medium containing a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some of the computer-readable instructions that can be used to execute process 200 are not stored using only transient signals (e.g., propagation of transient electrical or electromagnetic transmission). In at least one embodiment, the non-transitory computer-readable medium does not necessarily contain non-transitory data storage circuitry (e.g., buffers, caches, and queues) within a transient signal transceiver. In at least one embodiment, process 200 is executed at least partially on a computer system (e.g., a computer system described elsewhere in this disclosure). In at least one embodiment, process 200 may be executed by a processor using a neural network. In at least one embodiment, one or more operations performed as part of process 200 may be performed in a manner different from... Figure 2 Various sequences and combinations of execution are shown, including parallel execution.

[0061] In at least one embodiment, in step 202, a first pass-through fine-tuning is obtained while the processing unit is in an idle state. In at least one embodiment, the first pass-through fine-tuning is the number of fine-tunings that can be performed on CPM without causing problems when the processing unit is in an idle state. In at least one embodiment, an idle state refers to a state where the processing unit is not actively processing computational tasks or running applications or programs. In at least one embodiment, the first pass-through fine-tuning can be represented by a non-positive integral. In at least one embodiment, the processing unit can be any suitable processing unit or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, or PPUs. In at least one embodiment, the processing unit can be as follows: Figure 1 The processing unit 102 shown.

[0062] In at least one embodiment, in step 204, a second pass-through is obtained while the first application is running on the processing unit. In at least one embodiment, the second pass-through is the number of tweaks that can be performed on CPM without causing problems while the first application is running on the processing unit. In at least one embodiment, the second pass-through can be represented by a non-positive integer. In at least one embodiment, the absolute value of the second pass-through is less than the absolute value of the first pass-through. In at least one embodiment, the first application is the worst-case application of the processing unit. In at least one embodiment, the first application is as follows: Figure 1 The reference application 106 is shown.

[0063] In at least one embodiment, in step 206, a first frequency is calculated at least in part based on a first difference between the first pass trim in step 202 and the second pass trim in step 204. In at least one embodiment, the first difference represents how much less latency can be set on the CPM compared to an idle state when the processing unit is executing a first application. In at least one embodiment, the first difference is used to generate the first frequency. This is possible because clock frequency is proportional to voltage, and dynamic voltage scaling is closely related to frequency scaling. For example, a higher clock frequency requires a higher voltage, and vice versa. Each significant clock domain on the processing unit has its own dedicated clock source, called a Noise Aware Frequency Lock Loop (NAFLL). When an application (e.g., the first application) is running on the processing unit, noise events are generated, and due to the NAFLL, the frequency during operation reacts to these voltage noise events and oscillates, which are captured by the CPM. Therefore, the frequency can be associated with the pass trim, and the first frequency can be determined based on the first difference in the pass trim. In at least one embodiment, the first frequency is a reference frequency 112, as referenced Figure 1 As described.

[0064] In at least one embodiment, a third pass-through is obtained in step 208 when the second application is running on the processing unit. In at least one embodiment, the third pass-through refers to the number of times the CPM can be fine-tuned without causing problems while the processing unit is running the second application. In at least one embodiment, the third pass-through can be represented by a non-positive integer. In at least one embodiment, the absolute value of the third pass-through is less than the absolute value of the first pass-through. In at least one embodiment, the absolute value of the third pass-through is not less than the absolute value of the second pass-through. In at least one embodiment, the second application is a user application to be run on the processing unit. In at least one embodiment, the second application is as follows: Figure 1 The user application 108 described.

[0065] In at least one embodiment, in step 210, the second frequency is calculated at least in part based on a second difference between the first fine-tuning in step 202 and the third fine-tuning in step 208. In at least one embodiment, the second difference represents how much less latency can be set on CPM compared to an idle state when the processing unit is executing the second application. In at least one embodiment, the second difference is used to generate the second frequency. In at least one embodiment, the same or similar calculations or processes as in step 206 can be performed in step 210. In at least one embodiment, the second frequency is as follows: Figure 1 The described user frequency is 114.

[0066] In at least one embodiment, in step 212, a change in the design frequency of the processing unit is calculated based on a third difference between the first frequency in step 206 and the second frequency in step 210. In at least one embodiment, the third difference is a frequency decrease or reduction from when the processing unit is running a first application to when the processing unit is running a second application. In at least one embodiment, the third difference is expressed as a percentage and / or ratio. In at least one embodiment, the third difference is as follows: Figure 1 The described frequency difference is 116. In at least one embodiment, the design frequency is as follows: Figure 1 The design frequency 104 is described. In at least one embodiment, the change in the design frequency refers to increasing the value by a percentage and / or ratio indicated by the third difference. In at least one embodiment, the design frequency of the processing unit for the second application may be increased by the third difference such that the second frequency in step 210 matches the first frequency, since the first frequency in step 206 is the maximum frequency at which the processing unit can perform.

[0067] In at least one embodiment, in step 214, steps 202-212 are repeated for the next critical path in the CPM. In at least one embodiment, for each of the multiple critical paths in the CPM, a first pass adjustment, a second pass adjustment, a first difference, a first frequency, a third pass adjustment, a second difference, a second frequency, a third difference, and / or a design frequency change are obtained. In at least one embodiment, the final design frequency change can be calculated by finding the average, minimum, maximum, and / or other representative values ​​of the design frequency changes for all critical paths calculated in step 212.

[0068] Figure 3 An example of a process 300 for selecting a design frequency for a processing unit according to at least one embodiment is shown. In at least one embodiment, part or all of process 300 (or any other process described herein, or variations and / or combinations thereof) is executed under the control of one or more computer systems configured with computer-executable instructions and is implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more application programs) that is jointly executed on one or more processors by hardware, software, or a combination thereof. In at least one embodiment, the code is stored in the form of a computer program on a computer-readable storage medium containing a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some of the computer-readable instructions that can be used to execute process 300 are not stored using only transient signals (e.g., propagation of transient electrical or electromagnetic transmission). In at least one embodiment, the non-transitory computer-readable medium does not necessarily contain non-transitory data storage circuitry (e.g., buffers, caches, and queues) within a transient signal transceiver. In at least one embodiment, process 300 is executed at least partially on a computer system (e.g., a computer system described elsewhere in this disclosure). In at least one embodiment, process 300 may be executed by a processor using a neural network. In at least one embodiment, one or more operations performed as part of process 300 may be performed in a manner different from... Figure 3 Various sequences and combinations of execution are shown, including parallel execution.

[0069] In at least one embodiment, in step 302, the reference frequency is acquired when the reference application is run on the processing unit. In at least one embodiment, the processing unit may be as follows: Figure 1 The processing unit 102 described. In at least one embodiment, the reference application may be as described in... Figure 1 The reference application 106 is described. In at least one embodiment, the reference application may be as described in... Figure 2The first application described. In at least one embodiment, the reference frequency may be as follows: Figure 1 The reference frequency 112 is described. In at least one embodiment, the reference frequency may be as follows: Figure 2 The first frequency described.

[0070] In at least one embodiment, in step 304, the user frequency is acquired while running a user application on the processing unit. In at least one embodiment, the processing unit may be as follows: Figure 1 The processing unit 102 described. In at least one embodiment, the user application may be as described in... Figure 1 The user application 108 described. In at least one embodiment, the user application may be as described in... Figure 2 The second application described. In at least one embodiment, the user frequency can be as follows: Figure 1 The user frequency 114 is described. In at least one embodiment, the user frequency can be as follows: Figure 2 The second frequency described.

[0071] In at least one embodiment, in step 306, the reference frequency obtained in step 302 is compared with the user frequency obtained in step 304. In at least one embodiment, in step 308, a determination is made based on the comparison result in step 306. If the user frequency is not less than the reference frequency, process 300 ends. If the user frequency is less than the reference frequency, step 310 is executed.

[0072] In at least one embodiment, in step 310, a change to the design frequency of the processing unit is applied based on the difference between the reference frequency and the user frequency. In at least one embodiment, the difference may be as follows: Figure 1 The described frequency difference is 116. In at least one embodiment, the difference can be as follows: Figure 2 The third difference described. In at least one embodiment, the design frequency can be as follows: Figure 1 The design frequency 104 is described. In at least one embodiment, a change to the design frequency can be as follows: Figure 2 The described change to the design frequency. In at least one embodiment, the design frequency is changed only if the user frequency obtained in step 304 is less than the reference frequency obtained in step 306. In at least one embodiment, process 300 can be performed for each of the multiple critical paths in the CPM.

[0073] Figure 4An example of selecting the design frequency of a processing unit according to at least one embodiment is shown. In at least one embodiment, HMMAsparsePWM can be as follows: Figure 1 The reference application 106, and / or as per [reference] Figure 2 The first application, and / or as per [the provided text] Figure 3 The reference application is described above. BERT, RN50, and DMMA can be as follows: Figure 1 The user application 108, and / or as per [the provided text] Figure 2 The second application, and / or as per [relevant regulations] Figure 3 The user application described. In at least one embodiment, in path 1 ( Figure 4 In Table 400, second row, the idle passing trim of -23 can be achieved as follows: Figure 2 The first described method involves fine-tuning. In at least one embodiment, the HMMA of -5 can be fine-tuned as follows: Figure 2 The second, as described, involves fine-tuning. In at least one embodiment, the 2628MHz frequency can be as follows: Figure 1 The reference frequency 112 described, and / or as per [reference] Figure 2 The first frequency described, and / or as per [the description] Figure 3 The reference frequency described. In at least one embodiment, a BERT of -8 can be fine-tuned as described in... Figure 2 The third method described is through fine-tuning. In at least one embodiment, the 2461MHz frequency can be as follows: Figure 1 The described user frequency is 114, and / or as per... Figure 2 The second frequency described, and / or as per [the description] Figure 3 The user frequency described. In at least one embodiment, the 6.33% decrease may be as follows: Figure 1 The described frequency difference is 116, and / or as per... Figure 2 The third difference described, and / or as per [the description] Figure 3 The difference between the described reference frequency and the user frequency. In at least one embodiment, the predicted BERT Fmax of 1988MHz is an updated or modified design frequency, which may be as follows: Figure 1 The design frequency 104 after update 117 is described, and / or as per [the description]. Figure 2 and / or Figure 3 The described application design frequency is 104 after the design frequency change. In at least one embodiment, the above parameters are calculated for path 2, such as... Figure 4As shown, the same parameters were calculated for each of the 30 paths in the CPM. The final design frequency of the user application BERT is the average of all 30 updated design frequencies. It can be seen that this frequency increased from 1870MHz to 1996MHz, listed as "Predicted Average" at the bottom of Table 400. In other words, when a user uses the same processing unit tested in Table 400 with a design frequency or maximum allowable set frequency of 1870MHz, the user can increase that design frequency to 1996MHz for better performance.

[0074] Figure 5 An example of a processor 500 having a module for selecting the design frequency of a processing unit is shown according to at least one embodiment. In at least one embodiment, the processor 500 executes one or more processes, such as those described above. Figures 1 to 4 This describes the process for selecting the design frequency of the processing unit.

[0075] In at least one embodiment, processor 500 includes one or more processors, such as combined Figures 13 to 25 The processor described. In at least one embodiment, processor 500 is any suitable processing unit or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, or PPUs. In at least one embodiment, processor 500 includes a processing module 502 and a frequency determination module 504. In at least one embodiment, processing module 502 and frequency determination module 504 are part of processor 500 (e.g., Figure 5 As shown in the example), or it may be part of one or more other processors. In at least one embodiment, the processing module 502 and the frequency determination module 504 are distributed across multiple processors, which communicate via a bus, network, by writing to shared memory, or any suitable communication process (e.g., in conjunction with...). Figures 13 to 25 (The described communication process) is used for communication.

[0076] In at least one embodiment, the processing module 502 includes circuitry that enables all or part of an application or program to run, for example... Figure 1 The reference application 106 and / or user application 108 are shown. In at least one embodiment, the frequency determination module 504 includes circuitry for selecting, calculating, and / or determining the frequency of the processing unit, for example... Figures 1 to 4 As shown. In at least one embodiment, the frequency determination module 504 may be as follows: Figure 1 The frequency determination module 110 is described. For example, in at least one embodiment, the frequency determination module 504 can perform operations to achieve... Figure 3 Steps 302-310 and / or shown Figure 4 Steps 202-214 are shown.

[0077] Figure 6 A block diagram example of a driver and / or runtime comprising one or more libraries to provide one or more application programming interfaces (APIs) is shown according to at least one embodiment. In at least one embodiment, software program 602 is a software module. In at least one embodiment, software program 602 comprises one or more software modules. In at least one embodiment, one or more software modules are as follows: Figure 5 The following description is provided in a non-exclusive manner. In at least one embodiment, one or more APIs 610 are software instruction sets that, if executed, cause one or more processors to perform one or more computational operations. In at least one embodiment, one or more APIs 610 are distributed or otherwise provided as part of one or more libraries 606, runtimes 604, drivers 604, and / or any other software and / or executable code groups further described herein. In at least one embodiment, one or more APIs 610 perform one or more computational operations in response to a call to software program 602. In at least one embodiment, software program 602 is a collection of software code, commands, instructions, or other text sequences for instructing a computing device to perform one or more computational operations and / or to invoke one or more other instruction sets (e.g., API 610 or API function 612) to perform. In at least one embodiment, the functionality provided by one or more APIs 610 includes software function 612, such as a software function that can be used to accelerate one or more portions of software program 602 using one or more parallel processing units (PPUs) (e.g., graphics processing units (GPUs)).

[0078] In at least one embodiment, API 610 is a hardware interface to one or more circuits for performing one or more computational operations. In at least one embodiment, the one or more software APIs 610 described herein are implemented as one or more circuits for performing combined... Figures 1 to 4 One or more techniques are described. In at least one embodiment, one or more software programs 602 include instructions that, if executed, cause one or more hardware devices and / or circuits to perform a combination. Figures 1 to 4 One or more technologies are further described.

[0079] In at least one embodiment, software program 602 (e.g., user-implemented software program) utilizes one or more application programming interfaces (APIs) 610 to perform various computational operations, such as memory reservation, matrix multiplication, arithmetic operations, or any computational operation performed by a parallel processing unit (PPU) (e.g., a graphics processing unit (GPU)), as further described herein. In at least one embodiment, one or more APIs 610 provide a set of callable functions 612, referred to herein as APIs, API functions, and / or functions, which individually perform one or more computational operations, such as computational operations associated with parallel computing.

[0080] In at least one embodiment, one or more software programs 602 interact with or otherwise communicate with one or more APIs 610 to perform one or more computational operations using one or more PPUs (e.g., GPUs). In at least one embodiment, the one or more computational operations using one or more PPUs include at least one set or more groups of computational operations that will be accelerated, at least partially, by the one or more PPUs. In at least one embodiment, one or more software programs 602 interact with one or more APIs 610 to facilitate parallel computing using remote or local interfaces.

[0081] In at least one embodiment, the interface is software instructions that, if executed, provide access to one or more functions 612 provided by one or more APIs 610. In at least one embodiment, when a software developer compiles one or more software programs 602 in conjunction with one or more libraries 606 that contain one or more APIs 610 or otherwise provide access to one or more APIs 610, the software program 602 uses the native interface. In at least one embodiment, one or more software programs 602 are statically compiled in conjunction with a pre-compiled library 606 containing instructions for executing one or more APIs 610 or uncompiled source code. In at least one embodiment, one or more software programs 602 are dynamically compiled, and the one or more software programs are linked to one or more pre-compiled libraries 606 that contain one or more APIs 610 using a linker.

[0082] In at least one embodiment, when a software developer performs an operation that utilizes or otherwise communicates with a library 606 containing one or more APIs 610 via a network or other remote communication medium, the software program 602 uses a remote interface. In at least one embodiment, the library 606 containing one or more APIs 610 is executed by a remote computing service (e.g., a computing resource service provider). In another embodiment, the library 606 containing one or more APIs 610 is executed by any other computing host that provides the one or more APIs 610 to the software program 602.

[0083] In at least one embodiment, a processor executing or using one or more software programs 602 calls, uses, executes, or otherwise implements one or more APIs 610 to allocate and manage memory to be used by the software program 602. In at least one embodiment, one or more software programs 602 utilize one or more APIs 610 to allocate and manage memory to be used by one or more portions of the software program 602 for acceleration using one or more PPUs (e.g., GPUs) or any other accelerators or processors further described herein. These software programs 602 may be executed by one or more processors at least in part based on latency of the interconnect coupled to the one or more processors using functions 612 (in one embodiment) provided by one or more APIs 610.

[0084] In at least one embodiment, API 610 is an API for facilitating parallel computing. In at least one embodiment, API 610 is any other API further described herein. In at least one embodiment, API 610 is provided by a driver and / or runtime 604. In at least one embodiment, API 610 is provided by a CUDA user-mode driver. In at least one embodiment, API 610 is provided by a CUDA runtime. In at least one embodiment, driver 604 is a data value and software instructions that, if executed, perform one or more functions 612 of API 610 or otherwise facilitate the operation of one or more functions 612 of API 610 during loading and execution of one or more portions of software program 602. In at least one embodiment, runtime 604 is a data value and software instructions that, if executed, perform one or more functions 612 of API 610 or otherwise facilitate the operation of one or more functions 612 of API 610 during execution of software program 602. In at least one embodiment, one or more software programs 602 utilize one or more APIs 610 implemented by a driver and / or runtime 604 or otherwise provided to perform combined arithmetic operations by the one or more software programs 602 during execution by one or more PPUs (e.g., GPUs).

[0085] In at least one embodiment, one or more software programs 602 utilize one or more APIs 610 provided by the driver and / or runtime 604 to perform combinatorial arithmetic operations on one or more PPUs (e.g., GPUs). In at least one embodiment, one or more APIs 610 provide combinatorial arithmetic operations via the driver and / or runtime 604, as described above. In at least one embodiment, one or more software programs 602 utilize one or more APIs 610 provided by the driver and / or runtime 604 to allocate or otherwise reserve one or more memory blocks 614 for one or more PPUs (e.g., GPUs). In at least one embodiment, one or more software programs 602 utilize one or more APIs 610 provided by the driver and / or runtime 604 to allocate or otherwise reserve memory blocks. In at least one embodiment, one or more APIs 610 are used to perform combinatorial arithmetic operations, such as combining... Figures 1 to 4 Any one of the above.

[0086] To improve the usability of software program 602 and / or optimize one or more portions of software program 602 to enable acceleration by one or more PPUs (e.g., GPUs), in one embodiment, one or more APIs 610 provide one or more API functions 612 to execute a system that can be used or utilized by one or more computing devices, as described above, and in conjunction with... Figures 1 to 4 Further description. In at least one embodiment, exemplary block diagram 600 depicts a processor including one or more circuits for executing one or more software programs to combine two or more application programming interfaces (APIs) into one API. In at least one embodiment, exemplary block diagram 600 depicts a system including one or more processors for executing one or more software programs to combine two or more application programming interfaces (APIs) into one API.

[0087] In at least one embodiment, combined Figure 6 The described components, methods, and / or systems are in Figures 1 to 5 The non-exclusivity of any one of them is further demonstrated.

[0088] Data Center

[0089] Figure 7 An example data center 700 according to at least one embodiment is shown. In at least one embodiment, the data center 700 includes, but is not limited to, a data center infrastructure layer 710, a framework layer 720, a software layer 730, and an application layer 740.

[0090] In at least one embodiment, such as Figure 7 As shown, the data center infrastructure layer 710 may include a resource coordinator 712, grouped computing resources 714, and node computing resources (“nodes CR”) 716(1)-716(N), where “N” represents any complete positive integer. In at least one embodiment, nodes CR 716(1)-716(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (“FPGAs”), data processing units (DPUs) in network devices, graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid-state drives or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more nodes CR 716(1)-716(N) may be servers having one or more of the aforementioned computing resources.

[0091] In at least one embodiment, the grouped computing resources 714 may include individual groups (not shown) of node CRs housed in one or more racks, or a plurality of racks (also not shown) housed in data centers in various geographical locations. The individual groups of node CRs within the grouped computing resources 714 may include computing, networking, memory, or storage resources that can be configured or allocated to support groups of one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, the one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0092] In at least one embodiment, resource coordinator 712 may configure or otherwise control one or more nodes CR716(1)-716(N) and / or grouped computing resources 714. In at least one embodiment, resource coordinator 712 may include a Software Design Infrastructure (“SDI”) management entity for data center 700. In at least one embodiment, resource coordinator 712 may include hardware, software, or some combination thereof.

[0093] In at least one embodiment, such as Figure 7 As shown, the framework layer 720 includes, but is not limited to, a job scheduler 732, a configuration manager 734, a resource manager 736, and a distributed file system 738. In at least one embodiment, the framework layer 720 may include a framework of software 752 supporting the software layer 730 and / or one or more applications 742 of the application layer 740. In at least one embodiment, the software 752 or application 742 may respectively include web-based service software or applications, such as services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 720 may be, but is not limited to, a free and open-source software web application framework, such as Apache Spark, which can utilize the distributed file system 738 for large-scale data processing (e.g., "big data"). TM(Hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 732 may include a Spark driver to facilitate the scheduling of workloads supported by various layers of the data center 700. In at least one embodiment, the configuration manager 734 may be able to configure different layers, such as the software layer 730 and the framework layer 720, which includes Spark and a distributed file system 738 for supporting large-scale data processing. In at least one embodiment, the resource manager 736 is able to manage cluster or group computing resources mapped to or allocated to support the distributed file system 738 and the job scheduler 732. In at least one embodiment, the cluster or group computing resources may include grouped computing resources 714 on the data center infrastructure layer 710. In at least one embodiment, the resource manager 736 may coordinate with the resource coordinator 712 to manage these mapped or allocated computing resources.

[0094] In at least one embodiment, the software 752 included in the software layer 730 may include software used by at least a portion of nodes CR716(1)-716(N), grouped computing resources 714, and / or the distributed file system 738 of the framework layer 720. One or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0095] In at least one embodiment, one or more applications 742 included in the application layer 740 may include one or more types of applications used by at least a portion of nodes CR716(1)-716(N), grouped computing resources 714, and / or the distributed file system 738 of the framework layer 720. One or more types of applications may include, but are not limited to, CUDA applications.

[0096] In at least one embodiment, any of the configuration manager 734, resource manager 736, and resource coordinator 712 can implement any number and type of self-modification actions based on any amount and type of data acquired in any technically feasible manner. In at least one embodiment, self-modification actions can mitigate potentially poor configuration decisions by data center operators of data center 700 and can prevent underutilization and / or poor performance of the data center.

[0097] In at least one embodiment, at least one component shown or described in the above figures is used to achieve the combination. Figures 1 to 6 One or more of the described technologies and / or functions are used to select the design frequency of the processing unit.

[0098] Computer-based systems

[0099] The following figures present, but are not limited to, exemplary computer-based systems that can be used to implement at least one embodiment.

[0100] Figure 8 A processing system 800 according to at least one embodiment is illustrated. In at least one embodiment, the system 800 includes one or more processors 802 and one or more graphics processors 808, and may be a single-processor desktop system, a multiprocessor workstation system, or a server system having a large number of processors 802 or processor cores 807. In at least one embodiment, the processing system 800 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices. In at least one embodiment, the processor core 807 is referred to as a computing unit or arithmetic unit.

[0101] In at least one embodiment, the processing system 800 may include or be integrated into a server-based gaming platform, including a game console, mobile game console, handheld game console, or online game console, which are game and media consoles. In at least one embodiment, the processing system 800 is a mobile phone, smartphone, tablet computing device, or mobile internet device. In at least one embodiment, the processing system 800 may also include components coupled to or integrated into a wearable device, such as a smartwatch, smart glasses, augmented reality, or virtual reality device. In at least one embodiment, the processing system 800 is a television or set-top box device having one or more processors 802 and a graphical interface generated by one or more graphics processors 808.

[0102] In at least one embodiment, one or more processors 802 each include one or more processor cores 807 to process instructions that, when executed, perform operations against the system and user software. In at least one embodiment, each of the one or more processor cores 807 is configured to process a particular instruction set 809. In at least one embodiment, the instruction set 809 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computation via Very Long Instruction Word (VLIW). In at least one embodiment, the plurality of processor cores 807 may each process a different instruction set 809, which may include instructions that facilitate emulation of other instruction sets. In at least one embodiment, the processor cores 807 may also include other processing devices, such as digital signal processors (“DSPs”).

[0103] In at least one embodiment, processor 802 includes cache memory 804. In at least one embodiment, processor 802 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory is shared among various components of processor 802. In at least one embodiment, processor 802 also uses an external cache (e.g., a Level 3 (L3) cache or a last-level cache (LLC)) (not shown), which can be shared among processor cores 807 using known cache coherence techniques. In at least one embodiment, processor 802 further includes a register file 806, which may include different types of registers (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 806 may include general-purpose registers or other registers.

[0104] In at least one embodiment, one or more processors 802 are coupled to one or more interface buses 810 to transmit communication signals, such as address, data, or control signals, between the processor 802 and other components in the system 800. In at least one embodiment, the interface bus 810 may be a processor bus, such as a version of the Direct Media Interface (DMI) bus. In at least one embodiment, the interface bus 810 is not limited to the DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, the processor 802 includes an integrated memory controller 816 and a platform controller hub 830. In at least one embodiment, the memory controller 816 facilitates communication between storage devices and other components of the processing system 800, while the platform controller hub (PCH) 830 provides connectivity to input / output (I / O) devices via a local I / O bus. In at least one embodiment, one or more peripheral component interconnect buses include PCIe Gen 5, which provides an interface for the processor.

[0105] In at least one embodiment, memory device 820 may be a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, a phase-change memory device, or a device with suitable performance for use as processor memory. In at least one embodiment, memory device 820 may be used as system memory of processing system 800 to store data 822 and instructions 821 for use when one or more processors 802 execute applications or processes. In at least one embodiment, memory controller 816 is also coupled to an optional external graphics processor 812, which may communicate with one or more graphics processors 808 of processor 802 to perform graph and media operations. In at least one embodiment, display device 811 may be connected to processor 802. In at least one embodiment, display device 811 may include one or more internal display devices, such as those in mobile electronic devices or portable computer devices, or external display devices connected via a display interface (e.g., DisplayPort). In at least one embodiment, display device 811 may include a head-mounted display (HMD), such as a stereoscopic display device for virtual reality (VR) or augmented reality (AR) applications.

[0106] In at least one embodiment, the platform controller hub 830 enables peripheral devices to connect to the memory device 820 and the processor 802 via a high-speed I / O bus. In at least one embodiment, the I / O peripheral devices include, but are not limited to, an audio controller 846, a network controller 834, a firmware interface 828, a wireless transceiver 826, a touch sensor 825, and a data storage device 824 (e.g., a hard disk drive, flash memory, etc.). In at least one embodiment, the data storage device 824 may be connected via a memory interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 825 may include a touchscreen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 826 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or LTE transceiver. In at least one embodiment, the firmware interface 828 enables communication with the system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, the network controller 834 may enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to an interface bus 810. In at least one embodiment, the audio controller 846 is a multi-channel high-definition audio controller. In at least one embodiment, the processing system 800 includes an optional legacy I / O controller 840 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the processing system 800. In at least one embodiment, the platform controller hub 830 may also be connected to one or more Universal Serial Bus (USB) controllers 842 that connect input devices, such as a keyboard and mouse combination 843, a camera 844, or other USB input devices.

[0107] In at least one embodiment, instances of the memory controller 816 and platform controller hub 830 may be integrated into a discrete external graphics processor, such as external graphics processor 812. In at least one embodiment, the platform controller hub 830 and / or the memory controller 816 may be external to one or more processors 802. For example, in at least one embodiment, the processing system 800 may include an external memory controller 816 and a platform controller hub 830, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset communicating with the processor 802.

[0108] In at least one embodiment, at least one component shown or described in the above figures is used to achieve the combination. Figures 1 to 6 One or more of the described technologies and / or functions are used to select the design frequency of the processing unit.

[0109] Figure 9 A computer system 900 according to at least one embodiment is illustrated. In at least one embodiment, the computer system 900 may be a system having interconnected devices and components, a System-on-a-Chip (SoC), or some combination thereof. In at least one embodiment, the computer system 900 is formed by a processor 902, which may include execution units for executing instructions. In at least one embodiment, the computer system 900 may include, but is not limited to, components such as the processor 902, which employs execution units including logic to execute algorithms for processing data. In at least one embodiment, the computer system 900 may include a processor, such as one available from Intel Corporation of Santa Clara, California. Processor family, Xeon TM , XScale TM and / or StrongARM TM , Core TM or Nervana TM A microprocessor may be used, although other systems (including PCs, engineering workstations, set-top boxes, etc.) with other microprocessors may also be used. In at least one embodiment, computer system 900 may execute a version of the Windows operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0110] In at least one embodiment, the computer system 900 can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip (SoC), a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system capable of executing one or more instructions according to at least one embodiment.

[0111] In at least one embodiment, the computer system 900 may include, but is not limited to, a processor 902, which may include, but is not limited to, one or more execution units 908 configured to execute a Computational Unified Device Architecture (“CUDA”). (Developed by NVIDIA Corporation, Santa Clara, California) In at least one embodiment, the CUDA program is at least a part of a software application written in the CUDA programming language. In at least one embodiment, the computer system 900 is a single-processor desktop or server system. In at least one embodiment, the computer system 900 may be a multiprocessor system. In at least one embodiment, the processor 902 may include, but is not limited to, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing instruction set combinations, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 902 may be coupled to a processor bus 910, which allows data signals to be transmitted between the processor 902 and other components in the computer system 900.

[0112] In at least one embodiment, processor 902 may include, but is not limited to, a Level 1 (“L1”) internal cache memory (“cache”) 904. In at least one embodiment, processor 902 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 902. In at least one embodiment, processor 902 may include a combination of internal and external caches. In at least one embodiment, register file 906 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0113] In at least one embodiment, an execution unit 908, including but not limited to logic for performing integer and floating-point operations, is also located within the processor 902. The processor 902 may also include a microcode (“ucode”) read-only memory (“ROM”) for storing microcode of certain macro instructions. In at least one embodiment, the execution unit 908 may include logic for processing a packaged instruction set 909. In at least one embodiment, by including the packaged instruction set 909 in the instruction set of the general-purpose processor 902, along with the associated circuitry for executing the instructions, packaged data in the general-purpose processor 902 can be used to perform operations used by many multimedia applications. In at least one embodiment, many multimedia applications can be executed more quickly and efficiently by using the full width of the processor’s data bus to perform operations on the packaged data, which may eliminate the need to transfer smaller data units on the processor’s data bus to perform one or more operations on a data element at a time.

[0114] In at least one embodiment, the execution unit 908 may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, the computer system 900 may include, but is not limited to, the memory 920. In at least one embodiment, the memory 920 may be implemented as a DRAM device, an SRAM device, a flash memory device, or other storage device. The memory 920 may store instructions 919 and / or data 921 represented by data signals that can be executed by the processor 902.

[0115] In at least one embodiment, the system logic chip may be coupled to the processor bus 910 and the memory 920. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 916, and the processor 902 may communicate with the MCH 916 via the processor bus 910. In at least one embodiment, the MCH 916 may provide a high-bandwidth memory path 918 to the memory 920 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 916 may initiate data signals between the processor 902, the memory 920, and other components in the computer system 900, and bridge data signals between the processor bus 910, the memory 920, and the system I / O 922. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 916 may be coupled to the memory 920 via the high-bandwidth memory path 918, and the graphics / video card 912 may be coupled to the MCH 916 via an Accelerated Graphics Port (“AGP”) interconnect 914.

[0116] In at least one embodiment, computer system 900 may use system I / O 922 as a proprietary hub interface bus to couple MCH 916 to I / O controller hub (“ICH”) 930. In at least one embodiment, ICH 930 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to memory 920, chipset, and processor 902. Examples may include, but are not limited to, an audio controller 929, a firmware hub (“Flash BIOS”) 928, a wireless transceiver 926, data storage 924, a conventional I / O controller 923 including user input 925 and a keyboard interface, a serial expansion port 927 (e.g., USB), and a network controller 934. Data storage 924 may include a hard disk drive, floppy disk drive, CD-ROM device, flash memory device, or other mass storage device.

[0117] In at least one embodiment, Figure 9 A system comprising interconnected hardware devices or "chips" is shown. In at least one embodiment, Figure 9 An exemplary SoC can be shown. In at least one embodiment, Figure 9 The devices shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 900 are interconnected using compute fast link (“CXL”) interconnects.

[0118] In at least one embodiment, at least one component shown or described in the above figures is used to achieve the combination. Figures 1 to 6 One or more of the described technologies and / or functions are used to select the design frequency of the processing unit.

[0119] Figure 10 A system 1000 according to at least one embodiment is illustrated. In at least one embodiment, the system 1000 is an electronic device utilizing a processor 1010. In at least one embodiment, the system 1000 may be, for example, but not limited to, a laptop computer, a tower server, a rack server, a blade server, an edge device communicatively coupled to one or more local or cloud service providers, a laptop computer, a desktop computer, a tablet computer, a mobile device, a telephone, an embedded computer, or any other suitable electronic device.

[0120] In at least one embodiment, system 1000 may include, but is not limited to, processor 1010 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, processor 1010 is coupled using a bus or interface, such as I... 2C-bus, System Management Bus (“SMBus”), Low Pin Count (LPC) bus, Serial Peripheral Interface (“SPI”), High Definition Audio (“HDA”) bus, Serial Advanced Technology Accessory (“SATA”) bus, USB (versions 1, 2, and 3) or Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, Figure 10 A system is illustrated, comprising interconnected hardware devices or "chips". In at least one embodiment, Figure 10 An exemplary SoC can be shown. In at least one embodiment, Figure 10 The device shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof.

[0121] In at least one embodiment, Figure 10 One or more components are interconnected using Computational Fast Link (CXL) interconnects.

[0122] In at least one embodiment, Figure 10 This may include a display 1024, a touchscreen 1025, a touchpad 1030, a near-field communication unit (“NFC”) 1045, a sensor hub 1040, a thermal sensor 1046, a fast chipset (“EC”) 1035, a trusted platform module (“TPM”) 1038, a BIOS / firmware / flash memory (“BIOS, FW Flash”) 1022, a DSP 1060, a solid-state drive (“SSD”) or hard disk drive (“HDD”) 1020, a wireless local area network unit (“WLAN”) 1050, a Bluetooth unit 1052, a wireless wide area network unit (“WWAN”) 1056, a global positioning system (GPS) 1055, a camera (“USB 3.0 camera”) 1054 (e.g., a USB 3.0 camera), or a low-power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1015 implemented in, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0123] In at least one embodiment, other components may be communicatively coupled to processor 1010 via the components discussed above. In at least one embodiment, accelerometer 1041, ambient light sensor (“ALS”) 1042, compass 1043, and gyroscope 1044 may be communicatively coupled to sensor hub 1040. In at least one embodiment, thermal sensor 1039, fan 1037, keyboard 1036, and touchpad 1030 may be communicatively coupled to EC 1035. In at least one embodiment, speaker 1063, earphone 1064, and microphone (“mic”) 1065 may be communicatively coupled to audio unit (“audio codec and Class D amplifier”) 1062, which in turn may be communicatively coupled to DSP 1060. In at least one embodiment, audio unit 1062 may include, for example, but not limited to, audio encoder / decoder (“codec”) and Class D amplifier. In at least one embodiment, SIM card (“SIM”) 1057 may be communicatively coupled to WWAN unit 1056. In at least one embodiment, components such as WLAN unit 1050, Bluetooth unit 1052, and WWAN unit 1056 can be implemented as next-generation form factor (NGFF).

[0124] In at least one embodiment, at least one component shown or described in the above figures is used to achieve the combination. Figures 1 to 6 One or more of the described technologies and / or functions are used to select the design frequency of the processing unit.

[0125] Figure 11 An exemplary integrated circuit 1100 according to at least one embodiment is illustrated. In at least one embodiment, the exemplary integrated circuit 1100 is a SoC (System-on-a-Chip) that can be fabricated using one or more IP cores. In at least one embodiment, the integrated circuit 1100 includes one or more application processors 1105 (e.g., CPU, DPU), at least one graphics processor 1110, and may additionally include an image processor 1115 and / or a video processor 1120, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 1100 includes peripheral or bus logic, which includes a USB controller 1125, a UART controller 1130, an SPI / SDIO controller 1135, and an I... 2 S / I 2C controller 1140. In at least one embodiment, integrated circuit 1100 may include display device 1145 coupled to one or more of high-definition multimedia interface (“HDMI”) controller 1150 and mobile industrial processor interface (“MIPI”) display interface 1155. In at least one embodiment, storage may be provided by flash memory subsystem 1160, including flash memory and flash memory controller. In at least one embodiment, a memory interface may be provided via memory controller 1165 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include embedded security engine 1170.

[0126] In at least one embodiment, at least one component shown or described in the above figures is used to achieve the combination. Figures 1 to 6 One or more of the described technologies and / or functions are used to select the design frequency of the processing unit.

[0127] Figure 12 A computing system 1200 according to at least one embodiment is illustrated. In at least one embodiment, the computing system 1200 includes a processing subsystem 1201 having one or more processors 1202 and a system memory 1204 communicating via an interconnect path that may include a memory hub 1205. In at least one embodiment, the memory hub 1205 may be a separate component within a chipset assembly or may be integrated within one or more processors 1202. In at least one embodiment, the memory hub 1205 is coupled to an I / O subsystem 1211 via a communication link 1206. In at least one embodiment, the I / O subsystem 1211 includes an I / O hub 1207 that enables the computing system 1200 to receive input from one or more input devices 1208. In at least one embodiment, the I / O hub 1207 may enable a display controller, which is included in one or more processors 1202, for providing output to one or more display devices 1210A. In at least one embodiment, one or more display devices 1210A coupled to the I / O hub 1207 may include local, internal, or embedded display devices.

[0128] In at least one embodiment, the processing subsystem 1201 includes one or more parallel processors 1212 coupled to the memory hub 1205 via a bus or other communication link 1213. In at least one embodiment, the communication link 1213 may be one of many standards-based communication link technologies or protocols, such as, but not limited to, PCIe, or may be a vendor-specific communication interface or communication architecture. In at least one embodiment, the one or more parallel processors 1212 form a compute-intensive parallel or vector processing system that may include a large number of processing cores and / or processing clusters, such as multi-core integrated (MIC) processors or computing units. In at least one embodiment, the one or more parallel processors 1212 form a graphics processing subsystem capable of outputting pixels to one or more display devices 1210A coupled via an I / O hub 1207. In at least one embodiment, the one or more parallel processors 1212 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 1210B.

[0129] In at least one embodiment, system storage unit 1214 may be connected to I / O hub 1207 to provide a storage mechanism for computing system 1200. In at least one embodiment, I / O switch 1216 may be used to provide an interface mechanism to enable connectivity between I / O hub 1207 and other components, such as network adapter 1218 and / or wireless network adapter 1219 that may be integrated into the platform, and various other devices that may be added via one or more additional devices 1220. In at least one embodiment, network adapter 1218 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1219 may include one or more Wi-Fi, Bluetooth, NFC, or other network devices comprising one or more radios.

[0130] In at least one embodiment, the computing system 1200 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., and may also be connected to the I / O hub 1207. In at least one embodiment, for Figure 12 The communication paths between the various components can be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect) based protocols (e.g., PCIe), or other bus or point-to-point communication interfaces and / or protocols (e.g., NVLink high-speed interconnect or interconnect protocols).

[0131] In at least one embodiment, one or more parallel processors 1212 include circuitry optimized for graphics and video processing (including, for example, video output circuitry) and constitute a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 1212 include circuitry optimized for general-purpose processing. In at least one embodiment, components of the computing system 1200 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1212, memory hub 1205, processor 1202, and I / O hub 1207 may be integrated into a system-on-a-chip (SoC) integrated circuit. In at least one embodiment, components of the computing system 1200 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computing system 1200 may be integrated into a multi-chip module (MCM) that can interconnect with other MCMs to a modular computing system. In at least one embodiment, the I / O subsystem 1211 and display device 1210B are omitted from the computing system 1200. In at least one embodiment, one or more parallel processors 1212 include one or more tensor memory accelerator (TMA) units that can transfer data blocks between global memory and shared memory. In at least one embodiment, one or more processors use or access one or more TMAs to perform bidirectional copy operations, such as from global memory to shared memory and vice versa.

[0132] In at least one embodiment, at least one component shown or described in the above figures is used to achieve the combination. Figures 1 to 6 One or more of the described technologies and / or functions are used to select the design frequency of the processing unit.

[0133] Processing system

[0134] The following figures illustrate, but are not limited to, exemplary processing systems that can be used to implement at least one embodiment.

[0135] Figure 13An accelerated processing unit (“APU”) 1300 according to at least one embodiment is illustrated. In at least one embodiment, the APU 1300 was developed by AMD Inc. of Santa Clara, California. In at least one embodiment, the APU 1300 can be configured to execute applications, such as CUDA programs. In at least one embodiment, the APU 1300 includes, but is not limited to, a core complex 1310, a graphics complex 1340, an architecture 1360, an I / O interface 1370, a memory controller 1380, a display controller 1392, and a multimedia engine 1394. In at least one embodiment, the APU 1300 can be, but is not limited to, any combination of any number of core complexes 1310, any number of graphics complexes 1350, any number of display controllers 1392, and any number of multimedia engines 1394. For illustrative purposes, multiple instances of similar objects are indicated herein by reference numerals, wherein the reference numerals identify the object, and the numbers in parentheses identify the desired instances.

[0136] In at least one embodiment, the core complex 1310 is a CPU, the graphics complex 1340 is a GPU, and the APU 1300 is a processing unit that integrates, but is not limited to, the core complex 1310 and the graphics complex 1340 onto a single chip. In at least one embodiment, some tasks may be assigned to the core complex 1310, while other tasks may be assigned to the graphics complex 1340. In at least one embodiment, the core complex 1310 is configured to execute main control software associated with the APU 1300, such as an operating system. In at least one embodiment, the core complex 1310 is the main processor of the APU 1300, which controls and coordinates the operation of other processors. In at least one embodiment, the core complex 1310 issues commands to control the operation of the graphics complex 1340. In at least one embodiment, the core complex 1310 may be configured to execute host executable code derived from CUDA source code, and the graphics complex 1340 may be configured to execute device executable code derived from CUDA source code.

[0137] In at least one embodiment, the core complex 1310 includes, but is not limited to, cores 1320(1)-1320(4) and L3 cache 1330. In at least one embodiment, the core complex 1310 may include, but is not limited to, any number of cores 1320 in any combination and any number and type of cache. In at least one embodiment, the cores 1320 are configured to execute instructions of a specific instruction set architecture (“ISA”). In at least one embodiment, each core 1320 is a CPU core. In at least one embodiment, the core 1320 is referred to as a compute unit or arithmetic unit.

[0138] In at least one embodiment, each core 1320 includes, but is not limited to, a fetch / decode unit 1322, an integer execution engine 1324, a floating-point execution engine 1326, and an L2 cache 1328. In at least one embodiment, the fetch / decode unit 1322 fetches instructions, decodes these instructions, generates micro-operations, and dispatches individual micro-instructions to the integer execution engine 1324 and the floating-point execution engine 1326. In at least one embodiment, the fetch / decode unit 1322 may simultaneously dispatch one micro-instruction to the integer execution engine 1324 and another micro-instruction to the floating-point execution engine 1326. In at least one embodiment, the integer execution engine 1324 performs operations not limited to integer and memory operations. In at least one embodiment, the floating-point engine 1326 performs operations not limited to floating-point and vector operations. In at least one embodiment, the fetch-decode unit 1322 dispatches micro-instructions to a single execution engine, which replaces both the integer execution engine 1324 and the floating-point execution engine 1326.

[0139] In at least one embodiment, each core 1320(i) can access an L2 cache 1328(i) included in core 1320(i), where i is an integer representing a specific instance of core 1320. In at least one embodiment, each core 1320 included in core complex 1310(j) is connected to other cores 1320 included in core complex 1310(j) via an L3 cache 1330(j) included in core complex 1310(j), where j is an integer representing a specific instance of core complex 1310. In at least one embodiment, a core 1320 included in core complex 1310(j) can access all L3 caches 1330(j) included in core complex 1310(j), where j is an integer representing a specific instance of core complex 1310. In at least one embodiment, the L3 cache 1330 may include, but is not limited to, any number of slices.

[0140] In at least one embodiment, the graphics complex 1340 may be configured to perform computational operations in a highly parallel manner. In at least one embodiment, the graphics complex 1340 is configured to perform graphics pipeline operations, such as drawing commands, pixel operations, geometric calculations, and other operations associated with rendering an image to a display. In at least one embodiment, the graphics complex 1340 is configured to perform graphics-independent operations. In at least one embodiment, the graphics complex 1340 is configured to perform both graphics-related and graphics-independent operations.

[0141] In at least one embodiment, the graphics complex 1340 includes, but is not limited to, any number of computing units 1350 and an L2 cache 1342. In at least one embodiment, the computing units 1350 share the L2 cache 1342. In at least one embodiment, the L2 cache 1342 is partitioned. In at least one embodiment, the graphics complex 1340 includes, but is not limited to, any number of computing units 1350 and any number (including zero) and type of cache. In at least one embodiment, the graphics complex 1340 includes, but is not limited to, any number of dedicated graphics hardware.

[0142] In at least one embodiment, each computing unit 1350 includes, but is not limited to, any number of SIMD units 1352 and shared memory 1354. In at least one embodiment, each SIMD unit 1352 implements a SIMD architecture and is configured to execute operations in parallel. In at least one embodiment, each computing unit 1350 may execute any number of thread blocks, but each thread block executes on a single computing unit 1350. In at least one embodiment, a thread block includes, but is not limited to, any number of execution threads. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit 1352 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in the warp belongs to a single thread block and is configured to process different datasets based on a single instruction set. In at least one embodiment, prediction can be used to disable one or more threads in a warp. In at least one embodiment, a channel is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block can be synchronized together and communicate via shared memory 1354. In at least one embodiment, each computing unit 1350 includes one or more thread block clusters, wherein the thread block clusters can implement locality programming control at a larger granularity than a single thread block of a single streaming multiprocessor (SM). In at least one embodiment, the thread block cluster (also referred to as a “cluster”) enables multiple thread blocks running concurrently across a streaming multiprocessor to synchronously and cooperatively acquire, exchange, or otherwise use data.

[0143] In at least one embodiment, architecture 1360 is a system interconnect that facilitates data and control transfers across core complex 1310, graphics complex 1340, I / O interface 1370, memory controller 1380, display controller 1392, and multimedia engine 1394. In at least one embodiment, in addition to or replacing architecture 1360, APU 1300 may also include, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of components that may be directly or indirectly linked, either internally or externally to APU 1300. In at least one embodiment, I / O interface 1370 represents any number and type of I / O interface (e.g., PCI, PCI-Extended (“PCI-X”), PCIe, Gigabit Ethernet (“GBE”), USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1370. In at least one embodiment, the peripheral device coupled to the I / O interface 1370 may include, but is not limited to, a keyboard, mouse, printer, scanner, joystick or other types of game controllers, media recording devices, external storage devices, network interface cards, etc.

[0144] In at least one embodiment, the display controller AMD92 displays images on one or more display devices (e.g., liquid crystal display (LCD) devices). In at least one embodiment, the multimedia engine 1394 includes, but is not limited to, any number and type of multimedia-related circuitry, such as video decoders, video encoders, image signal processors, etc. In at least one embodiment, the memory controller 1380 facilitates data transfer between the APU 1300 and the unified system memory 1390. In at least one embodiment, the core complex 1310 and the graphics complex 1340 share the unified system memory 1390.

[0145] In at least one embodiment, the APU 1300 implements a memory subsystem, which includes, but is not limited to, any number and type of memory controllers 1380 and memory devices (e.g., shared memory 1354) that may be dedicated to a single component or shared among multiple components. In at least one embodiment, the APU 1300 implements a cache subsystem, which includes, but is not limited to, one or more cache memories (e.g., L2 cache 1428, L3 cache 1330, and L2 cache 1342), each cache memory may be private or shared among any number of components (e.g., core 1320, core complex 1310, SIMD unit 1352, compute unit 1350, and graphics complex 1340).

[0146] In at least one embodiment, at least one component shown or described in the above figures is used to achieve the combination. Figures 1 to 6 One or more of the described technologies and / or functions are used to select the design frequency of the processing unit.

[0147] Figure 14 A CPU 1400 according to at least one embodiment is illustrated. In at least one embodiment, the CPU 1400 was developed by AMD Inc. of Santa Clara, California. In at least one embodiment, the CPU 1400 can be configured to execute an application. In at least one embodiment, the CPU 1400 is configured to execute host control software, such as an operating system. In at least one embodiment, the CPU 1400 issues commands to control the operation of an external GPU (not shown). In at least one embodiment, the CPU 1400 can be configured to execute host executable code derived from CUDA source code, and the external GPU can be configured to execute device executable code derived from such CUDA source code. In at least one embodiment, the CPU 1400 includes, but is not limited to, any number of core complexes 1410, architectures 1460, I / O interfaces 1470, and memory controllers 1480.

[0148] In at least one embodiment, the core complex 1410 includes, but is not limited to, cores 1420(1)-1420(4) and L3 cache 1430. In at least one embodiment, the core complex 1410 may include, but is not limited to, any combination of any number of cores 1420 and any number and type of cache. In at least one embodiment, the cores 1420 are configured to execute instructions of a specific ISA. In at least one embodiment, each core 1420 is a CPU core.

[0149] In at least one embodiment, each core 1420 includes, but is not limited to, a fetch / decode unit 1422, an integer execution engine 1424, a floating-point execution engine 1426, and an L2 cache 1428. In at least one embodiment, the fetch / decode unit 1422 fetches instructions, decodes these instructions, generates micro-operations, and dispatches individual micro-instructions to the integer execution engine 1424 and the floating-point execution engine 1426. In at least one embodiment, the fetch / decode unit 1422 may simultaneously dispatch one micro-instruction to the integer execution engine 1424 and another micro-instruction to the floating-point execution engine 1426. In at least one embodiment, the integer execution engine 1424 performs operations not limited to integer and memory operations. In at least one embodiment, the floating-point engine 1426 performs operations not limited to floating-point and vector operations. In at least one embodiment, the fetch-decode unit 1422 dispatches micro-instructions to a single execution engine, which replaces both the integer execution engine 1424 and the floating-point execution engine 1426.

[0150] In at least one embodiment, each core 1420(i) can access an L2 cache 1428(i) included in core 1420(i), where i is a number representing a specific instance of core 1420. In at least one embodiment, each core 1420 included in core complex 1410(j) is connected to other cores 1420 included in core complex 1410(j) via an L3 cache 1430(j) included in core complex 1410(j), where j is an integer representing a specific instance of core complex 1410. In at least one embodiment, a core 1420 included in core complex 1410(j) can access all L3 caches 1430(j) included in core complex 1410(j), where j is an integer representing a specific instance of core complex 1410. In at least one embodiment, the L3 cache 1430 may include, but is not limited to, any number of slices.

[0151] In at least one embodiment, structure 1460 is a system interconnect that facilitates data and control transfers across core complexes 1410(1)-1410(N) (where N is a positive integer), I / O interface 1470, and memory controller 1480. In at least one embodiment, in addition to or instead of structure 1460, CPU 1400 may also include, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of components that may be directly or indirectly linked, either inside or outside CPU 1400. In at least one embodiment, I / O interface 1470 represents any number and type of I / O interfaces (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1470. In at least one embodiment, peripheral devices coupled to I / O interface 1470 may include, but are not limited to, displays, keyboards, mice, printers, scanners, joysticks or other types of game controllers, media recording devices, external storage devices, network interface cards, etc.

[0152] In at least one embodiment, memory controller 1480 facilitates data transfer between CPU 1400 and system memory 1490. In at least one embodiment, core complex 1410 and graphics complex 1440 share system memory 1490. In at least one embodiment, CPU 1400 implements a memory subsystem, which includes, but is not limited to, any number and type of memory controllers 1480 and memory devices that may be dedicated to a component or shared among multiple components. In at least one embodiment, CPU 1400 implements a cache subsystem, which includes, but is not limited to, one or more cache memories (e.g., L2 cache 1428 and L3 cache 1430), each cache memory may be component-private or shared among any number of components (e.g., core 1420 and core complex 1410).

[0153] In at least one embodiment, at least one component shown or described in the above figures is used to achieve the combination. Figures 1 to 6 One or more of the described technologies and / or functions are used to select the design frequency of the processing unit.

[0154] Figure 15 An exemplary accelerator integration slice 1590 according to at least one embodiment is illustrated. As used herein, a "slice" includes a designated portion of the processing resources of an accelerator integrated circuit. In at least one embodiment, the accelerator integrated circuit provides cache management, memory access, environment management, and interrupt management services for multiple graphics processing engines among multiple graphics acceleration modules. Each graphics processing engine may comprise a separate GPU. Optionally, the graphics processing engine may include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, a graphics acceleration module may be a GPU having multiple graphics processing engines. In at least one embodiment, the graphics processing engines may be individual GPUs integrated on a general-purpose package, line card, or chip.

[0155] In one embodiment, process element 1583 is stored in the application's effective address space 1582 within system memory 1514 in response to a GPU call 1581 from an application 1580 executing on processor 1507. Process element 1583 contains the processing state of the corresponding application 1580. A job descriptor (“WD”) 1584 contained in process element 1583 may be a single job requested by the application or may contain pointers to job queues. In at least one embodiment, WD 1584 is a pointer to a job request queue in the application's effective address space 1582.

[0156] The graphics acceleration module 1546 and / or the various graphics processing engines may be shared by all or some processes in the system. In at least one embodiment, infrastructure may be included for establishing a processing state and sending the WD 1584 to the graphics acceleration module 1546 to begin operation in a virtualized environment.

[0157] In at least one embodiment, a dedicated process programming model is used for implementation. In this model, a single process owns the graphics acceleration module 1546 or an individual graphics processing engine. Since the graphics acceleration module 1546 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and the operating system initializes the accelerator integrated circuit for the owned partition when the graphics acceleration module 1546 is allocated.

[0158] During operation, the WD fetch unit 1591 in the accelerator integrated slice 1590 fetches the next WD 1584, which includes instructions for the work to be performed by one or more graphics processing engines of the graphics acceleration module 1546. Data from the WD 1584 can be stored in register 1545 and used by the memory management unit (“MMU”) 1539, interrupt management circuitry 1547, and / or environment management circuitry 1548, as illustrated. For example, one embodiment of the MMU 1539 includes segment / page roaming circuitry for accessing segment / page tables 1586 within the OS virtual address space 1585. The interrupt management circuitry 1547 can handle interrupt events (INT) 1592 received from the graphics acceleration module 1546. When performing graph operations, the effective address 1593 generated by the graphics processing engine is translated into an actual address by the MMU 1539.

[0159] In one embodiment, the same register set 1545 is copied for each graphics processing engine and / or graphics acceleration module 1546 and can be initialized by the hypervisor or operating system. Each of these copied registers can be included in the accelerator integration slice 1590. Table 1 shows exemplary registers that can be initialized by the hypervisor.

[0160] Table 1 – Registers for Supervisor Initialization

[0161] 1 Slice Control Register 2 Real Address (RA) plan processing area pointer 3 Permission mask overwrite register 4 Interrupt vector table input offset 5 Interrupt vector table entry restrictions 6 Status Register 7 Logical partition ID 8 Real Address (RA) Manager Accelerator Utilization Record Pointer 9 Storage description register

[0162] Table 2 shows exemplary registers that can be initialized by the operating system.

[0163] Table 2 – Operating System Initialization Registers

[0164]

[0165]

[0166] In one embodiment, each WD 1584 is specific to a particular graphics acceleration module 1546 and / or a particular graphics processing engine. It contains all the information required for the graphics processing engine to perform its work or to do its job, or it may be a pointer to a memory location where the application has established a command queue for the work to be done.

[0167] In at least one embodiment, at least one component shown or described in the above figures is used to achieve the combination. Figures 1 to 6 One or more of the described technologies and / or functions are used to select the design frequency of the processing unit.

[0168] Figures 16A-16B An exemplary graphics processor according to at least one embodiment herein is illustrated. In at least one embodiment, any exemplary graphics processor may be manufactured using one or more IP cores. In addition to the illustrations, other logic and circuitry may be included in at least one embodiment, including additional graphics processor / cores, peripheral interface controllers, or general-purpose processor cores. In at least one embodiment, the exemplary graphics processor is used within a System-on-a-Chip (SoC).

[0169] Figure 16A An exemplary graphics processor 1610 of a SoC integrated circuit according to at least one embodiment is shown, which can be manufactured using one or more IP cores. Figure 16B An additional exemplary graphics processor 1640 of a SoC integrated circuit according to at least one embodiment is shown, which can be manufactured using one or more IP cores. In at least one embodiment, Figure 16A The graphics processor 1610 is a low-power graphics processor core. In at least one embodiment, Figure 16B The graphics processor 1640 is a higher-performance graphics processor core. In at least one embodiment, each graphics processor 1610, 1640 may be... Figure 11 A variant of the 1110 graphics processor.

[0170] In at least one embodiment, the graphics processor 1610 includes a vertex processor 1605 and one or more fragment processors 1615A-1615N (e.g., 1615A, 1615B, 1615C, 1615D to 1615N-1 and 1615N). In at least one embodiment, the graphics processor 1610 can execute different shader programs via separate logic, such that the vertex processor 1605 is optimized to perform operations for the vertex shader program, while one or more fragment processors 1615A-1615N perform fragment (e.g., pixel) shading operations for fragments or pixels or shader programs. In at least one embodiment, the vertex processor 1605 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. In at least one embodiment, the fragment processors 1615A-1615N use the primitive and vertex data generated by the vertex processor 1605 to generate framebuffers for display on a display device. In at least one embodiment, the fragment processors 1615A-1615N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs provided in the Direct 3D API.

[0171] In at least one embodiment, the graphics processor 1610 additionally includes one or more MMUs 1620A-1620B, caches 1625A-1625B, and circuit interconnects 1630A-1630B. In at least one embodiment, one or more MMUs 1620A-1620B provide a virtual-to-physical address mapping for the graphics processor 1610, including for vertex processors 1605 and / or fragment processors 1615A-1615N, which can reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more caches 1625A-1625B. In at least one embodiment, one or more MMUs 1620A-1620B can be synchronized with other MMUs within the system, including with... Figure 11 One or more application processors 1105, image processors 1115, and / or video processors 1120 are associated with one or more MMUs, enabling each processor 1105-1120 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1630A-1630B enable the graphics processor 1610 to connect to other IP cores within the SoC via the SoC's internal bus or via a direct connection.

[0172] In at least one embodiment, the graphics processor 1640 includes Figure 16AThe graphics processor 1610 includes one or more MMUs 1620A-1620B, caches 1625A-1625B, and circuit interconnects 1630A-1630B. In at least one embodiment, the graphics processor 1640 includes one or more shader cores 1655A-1655N (e.g., 1655A, 1655B, 1655C, 1655D, 1655E, 1655F, to 1655N-1 and 1655N) that provide a unified shader core architecture, wherein a single core or type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores may vary. In at least one embodiment, the graphics processor 1640 includes an inter-core task manager 1645 that acts as a thread dispatcher to assign execution threads to one or more shader cores 1655A-1655N and a tile unit 1658 to accelerate tile-based rendering operations, wherein rendering operations of a scene are subdivided in image space, for example, to take advantage of local spatial consistency within the scene or to optimize the use of internal caches.

[0173] In at least one embodiment, at least one component shown or described in the above figures is used to achieve the combination. Figures 1 to 6 One or more of the described technologies and / or functions are used to select the design frequency of the processing unit.

[0174] Figure 17A A graphics core 1700 according to at least one embodiment is shown. In at least one embodiment, the graphics core 1700 may include... Figure 11 The graphics processor 1110 is located within it. In at least one embodiment, the graphics core 1700 may be... Figure 16BThe graphics core 1700 uses a unified shader core 1655A-1655N. In at least one embodiment, the graphics core 1700 includes a shared instruction cache 1702, texture units 1718, and cache / shared memory 1720, which are common to execution resources within the graphics core 1700. In at least one embodiment, the graphics core 1700 may include multiple slices 1701A-1701N or partitions of each core, and the graphics processor may include multiple instances of the graphics core 1700. Slices 1701A-1701N may include supporting logic, including local instruction caches 1704A-1704N, thread schedulers 1706A-1706N, thread dispatchers 1708A-1708N, and a set of registers 1710A-1710N. In at least one embodiment, slices 1701A-1701N may include a set of additional functional units (“AFUs”) 1712A-1712N, floating-point units (“FPUs”) 1714A-1714N, integer arithmetic logic units (“ALUs”) 1716A-1716N, address calculation units (“ACUs”) 1713A-1713N, double-precision floating-point units (“DPFPUs”) 1715A-1715N, and matrix processing units (“MPUs”) 1717A-1717N. In at least one embodiment, graphics core 1700 is referred to as a computing unit or arithmetic unit.

[0175] In one embodiment, the FPU 1714A-1714N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 1715A-1715N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 1716A-1716N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 1717A-1717N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 1717A-1717N can perform various matrix operations to accelerate CUDA programs, including enabling support for accelerated General Matrix-to-Matrix Multiplication (GEMM). In at least one embodiment, the AFU 1712A-1712N can perform additional logical operations not supported by floating-point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.).

[0176] Figure 17BA general-purpose graphics processing unit (GPGPU) 1730 is illustrated in at least one embodiment. In at least one embodiment, the GPGPU 1730 is highly parallel and suitable for deployment on a multi-chip module. In at least one embodiment, the GPGPU 1730 can be configured to enable highly parallel computational operations to be performed by a GPU array. In at least one embodiment, the GPGPU 1730 can be directly linked to other instances of the GPGPU 1730 to create a multi-GPU cluster to improve execution time for CUDA programs. In at least one embodiment, the GPGPU 1730 includes a host interface 1732 for connection to a host processor. In at least one embodiment, the host interface 1732 is a PCIe interface. In at least one embodiment, the host interface 1732 can be a vendor-specific communication interface or communication structure. In at least one embodiment, the GPGPU 1730 receives commands from the host processor and uses a global scheduler 1734 to assign execution threads associated with those commands to a set of computational clusters 1736A-1736H. In at least one embodiment, computing clusters 1736A-1736H share cache memory 1738. In at least one embodiment, cache memory 1738 can be used as an advanced cache of cache memory within computing clusters 1736A-1736H.

[0177] In at least one embodiment, the GPGPU 1730 includes memory 1744A-1744B coupled to the computing cluster 1736A-1736H via a set of memory controllers 1742A-1742B. In at least one embodiment, memory 1744A-1744B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (“SGRAM”), including graphics double data rate (“GDDR”) memory.

[0178] In at least one embodiment, computing clusters 1736A-1736H each include a set of graphics cores, such as Figure 17A The graphics core 1700 may include various types of integer and floating-point logic units, capable of performing computational operations at various precisions, including computations suitable for CUDA programs. For example, in at least one embodiment, at least a subset of the floating-point units in each computing cluster 1736A-1736H may be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of the floating-point units may be configured to perform 64-bit floating-point operations.

[0179] In at least one embodiment, multiple instances of GPGPU 1730 can be configured to operate as a compute cluster. Computation clusters 1736A-1736H can implement any technically feasible communication technology for synchronization and data exchange. In at least one embodiment, the multiple instances of GPGPU 1730 communicate via host interface 1732. In at least one embodiment, GPGPU 1730 includes an I / O hub 1739 that couples GPGPU 1730 to GPU link 1740, enabling direct connection to other instances of GPGPU 1730. In at least one embodiment, GPU link 1740 is coupled to a dedicated GPU-to-GPU bridge, enabling communication and synchronization among the multiple instances of GPGPU 1730. In at least one embodiment, GPU link 1740 is coupled to a high-speed interconnect for sending and receiving data to and from other GPGPUs or parallel processors. In at least one embodiment, the multiple instances of GPGPU 1730 reside in a separate data processing system and communicate via a network device accessible via host interface 1732. In at least one embodiment, the GPU link 1740 may be configured to connect to a host processor, supplementing or replacing the host interface 1732. In at least one embodiment, the GPGPU 1730 may be configured to execute CUDA programs.

[0180] In at least one embodiment, at least one component shown or described in the above figures is used to achieve the combination. Figures 1 to 6 One or more of the described technologies and / or functions are used to select the design frequency of the processing unit.

[0181] Figure 18A A parallel processor 1800 according to at least one embodiment is illustrated. In at least one embodiment, various components of the parallel processor 1800 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application-specific integrated circuit (“ASIC”), or an FPGA.

[0182] In at least one embodiment, the parallel processor 1800 includes a parallel processing unit 1802. In at least one embodiment, the parallel processing unit 1802 includes an I / O unit 1804 that enables communication with other devices, including other instances of the parallel processing unit 1802. In at least one embodiment, the I / O unit 1804 can be directly connected to other devices. In at least one embodiment, the I / O unit 1804 is connected to other devices using a hub or switch interface (e.g., a memory hub 1805). In at least one embodiment, the connection between the memory hub 1805 and the I / O unit 1804 forms a communication link. In at least one embodiment, the I / O unit 1804 is connected to a host interface 1806 and a memory crossbar switch 1816, wherein the host interface 1806 receives commands for performing processing operations, and the memory crossbar switch 1816 receives commands for performing memory operations. In at least one embodiment, when the host interface 1806 receives a command buffer via the I / O unit 1804, the host interface 1806 can direct work operations to execute those commands to the front end 1808. In at least one embodiment, front-end 1808 is coupled to scheduler 1810, which is configured to assign commands or other work items to processing array 1812. In at least one embodiment, scheduler 1810 ensures that processing array 1812 is correctly configured and in an active state before assigning tasks to it. In at least one embodiment, scheduler 1810 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 1810 is configured to perform complex scheduling and work assignment operations at both coarse and fine granular levels, enabling rapid preemption and context switching of threads executing on processing array 1812. In at least one embodiment, host software can demonstrate workloads scheduled on processing array 1812 via one of a plurality of graphics processing doorbells. In at least one embodiment, the workloads can then be automatically assigned on processing array 1812 by scheduler 1810 logic within the microcontroller including scheduler 1810.

[0183] In at least one embodiment, the processing array 1812 may include up to "N" processing clusters (e.g., clusters 1814A, 1814B to 1814N). In at least one embodiment, each cluster 1814A-1814N of the processing array 1812 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 1810 may use various scheduling and / or work allocation algorithms to allocate work to the clusters 1814A-1814N of the processing array 1812, which may vary depending on the workload generated by each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 1810, or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing array 1812. In at least one embodiment, different clusters 1814A-1814N of the processing array 1812 may be assigned to process different types of programs or to perform different types of computations.

[0184] In at least one embodiment, the processing array 1812 may be configured to perform various types of parallel processing operations. In at least one embodiment, the processing array 1812 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing array 1812 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations, including physical operations, and performing data transformations.

[0185] In at least one embodiment, the processing array 1812 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing array 1812 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing array 1812 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 1802 may transfer data from system memory via I / O unit 1804 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 1822) and then written back to system memory.

[0186] In at least one embodiment, when the parallel processing unit 1802 is used to perform graph processing, the scheduler 1810 may be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations among the multiple clusters 1814A-1814N of the processing array 1812. In at least one embodiment, portions of the processing array 1812 may be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 1814A-1814N may be stored in a buffer to allow intermediate data to be transferred between the clusters 1814A-1814N for further processing.

[0187] In at least one embodiment, the processing array 1812 may receive processing tasks to be executed via a scheduler 1810, which receives commands defining the processing tasks from a front end 1808. In at least one embodiment, the processing task may include an index of data to be processed, such as surface (patch) data, raw data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is processed (e.g., what program to execute). In at least one embodiment, the scheduler 1810 may be configured to acquire an index corresponding to a task, or may receive an index from the front end 1808. In at least one embodiment, the front end 1808 may be configured to ensure that the processing array 1812 is configured to be active before initiating a workload specified by an incoming command buffer (e.g., a batch buffer, push buffer, etc.).

[0188] In at least one embodiment, each of one or more instances of the parallel processing unit 1802 may be coupled to the parallel processor memory 1822. In at least one embodiment, the parallel processor memory 1822 may be accessed via a memory crossbar switch 1816, which may receive memory requests from the processing array 1812 and the I / O unit 1804. In at least one embodiment, the memory crossbar switch 1816 may be accessed via a memory interface 1818. In at least one embodiment, the memory interface 1818 may include a plurality of partition units (e.g., partition units 1820A, 1820B to 1820N), each of which may be coupled to a portion (e.g., a memory cell) of the parallel processor memory 1822. In at least one embodiment, the plurality of partition units 1820A-1820N are configured to be equal to the number of memory units, such that the first partition unit 1820A has a corresponding first memory unit 1824A, the second partition unit 1820B has a corresponding memory unit 1824B, and the Nth partition unit 1820N has a corresponding Nth memory unit 1824N. In at least one embodiment, the number of partition units 1820A-1820N may not be equal to the number of memory devices.

[0189] In at least one embodiment, memory cells 1824A-1824N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory cells 1824A-1824N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps may be stored across memory cells 1824A-1824N, allowing partitioning cells 1820A-1820N to write portions of each rendering target in parallel, to efficiently utilize the available bandwidth of the parallel processor memory 1822. In at least one embodiment, local instances of the parallel processor memory 1822 may be excluded to facilitate a unified memory design that combines system memory with local cache memory.

[0190] In at least one embodiment, any of the clusters 1814A-1814N of the processing array 1812 can process data to be written to any memory cell 1824A-1824N within the parallel processor memory 1822. In at least one embodiment, the memory crossbar switch 1816 can be configured to transfer the output of each cluster 1814A-1814N to any partition cell 1820A-1820N or another cluster 1814A-1814N, and the clusters 1814A-1814N can perform further processing operations on the output. In at least one embodiment, each cluster 1814A-1814N can communicate with the memory interface 1818 via the memory crossbar switch 1816 to read from or write to various external storage devices. In at least one embodiment, the memory crossbar switch 1816 has a connection to a memory interface 1818 for communication with I / O unit 1804, and a connection to a local instance of parallel processor memory 1822, thereby enabling processing units within different processing clusters 1814A-1814N to communicate with system memory or other memory not local to parallel processing unit 1802. In at least one embodiment, the memory crossbar switch 1816 may use virtual channels to separate traffic flows between clusters 1814A-1814N and partition units 1820A-1820N.

[0191] In at least one embodiment, multiple instances of the parallel processing unit 1802 may be provided on a single insert card, or multiple insert cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 1802 may be configured to interoperate, even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 1802 may include higher-precision floating-point units relative to other instances. In at least one embodiment, a system combining one or more instances of the parallel processing unit 1802 or the parallel processor 1800 may be implemented in various configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0192] Figure 18B A processing cluster 1894 according to at least one embodiment is illustrated. In at least one embodiment, the processing cluster 1894 is included within a parallel processing unit. In at least one embodiment, the processing cluster 1894 is... Figure 18AAn instance of one of the processing clusters 1814A-1814N. In at least one embodiment, the processing cluster 1894 can be configured to execute a number of threads in parallel, wherein the term "thread" refers to an instance of a specific program executing on a particular set of input data. In at least one embodiment, a Single Instruction Multiple Data (SIMD) instruction issuing technique is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, a Single Instruction Multiple Threading (SIMT) technique is used to support the parallel execution of a large number of generally synchronous threads, which uses a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster 1894.

[0193] In at least one embodiment, the operation of the processing cluster 1894 can be controlled by a pipeline manager 1832 that assigns processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 1832... Figure 18A The scheduler 1810 receives instructions and manages the execution of these instructions via the graphics multiprocessor 1834 and / or texture unit 1836. In at least one embodiment, the graphics multiprocessor 1834 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, the processing cluster 1894 may include various types of SIMT parallel processors with different architectures. In at least one embodiment, the processing cluster 1894 may include one or more instances of the graphics multiprocessor 1834. In at least one embodiment, the graphics multiprocessor 1834 can process data, and the data cross switch 1840 can be used to distribute the processed data to one of a number of possible destinations, including other shader units. In at least one embodiment, the pipeline manager 1832 can facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data cross switch 1840.

[0194] In at least one embodiment, each graphics multiprocessor 1834 within the processing cluster 1894 may include the same set of functional execution logic (e.g., arithmetic logic units, load-memory units (LSUs), etc.). In at least one embodiment, the functional execution logic may be configured in a pipelined manner, wherein new instructions may be issued before previous instructions complete. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shift operations, and computation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be used to perform different operations, and any combination of functional units may exist.

[0195] In at least one embodiment, instructions sent to the processing cluster 1894 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, the thread group executes programs on different input data. In at least one embodiment, each thread within the thread group may be assigned to a different processing engine within the graphics multiprocessor 1834. In at least one embodiment, the thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 1834. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during a loop that is processing the thread group. In at least one embodiment, the thread group may also include more threads than the number of processing engines within the graphics multiprocessor 1834. In at least one embodiment, when the thread group includes more threads than the number of processing engines within the graphics multiprocessor 1834, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 1834.

[0196] In at least one embodiment, the graphics multiprocessor 1834 includes an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 1834 may forgo the internal cache and use a cache memory within the processing cluster 1894 (e.g., L1 cache 1848). In at least one embodiment, each graphics multiprocessor 1834 may also access partition units (e.g., Figure 18A The L2 cache is located within partition units 1820A-1820N, which are shared among all processing clusters 1894 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 1834 can also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory outside of the parallel processing unit 1802 can be used as global memory. In at least one embodiment, the processing cluster 1894 includes multiple instances of the graphics multiprocessor 1834, which can share common instructions and data that can be stored in the L1 cache 1848.

[0197] In at least one embodiment, each processing cluster 1894 may include an MMU 1845 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 1845 may reside in Figure 18AThe memory interface 1818 is located within the MMU 1845. In at least one embodiment, the MMU 1845 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles (more information about tiles is discussed) and optionally to cache line indices. In at least one embodiment, the MMU 1845 may include an address translation back buffer (TLB) or a cache that may reside within the graphics multiprocessor 1834, the L1 cache 1848, or the processing cluster 1894. In at least one embodiment, physical addresses are processed to allocate surface data access locality for efficient request interleaving between partition units. In at least one embodiment, cache line indices may be used to determine whether a request for a cache line is a hit or a miss.

[0198] In at least one embodiment, the processing cluster 1894 may be configured such that each graphics multiprocessor 1834 is coupled to a texture unit 1836 to perform texture mapping operations, which may involve determining texture sample locations, reading texture data, and filtering texture data. In at least one embodiment, texture data is read as needed from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 1834, and texture data is also retrieved from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 1834 outputs a processed task to a data crossbar switch 1840 to provide the processed task to another processing cluster 1894 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via a memory crossbar switch 1816. In at least one embodiment, a pre-raster operation unit (“preROP”) 1842 is configured to receive data from the graphics multiprocessor 1834 and direct the data to a ROP unit, which may be associated with a partitioning unit (e.g., [missing information]). Figure 18A The PreROP1842 unit is located together with the partition units 1820A-1820N. In at least one embodiment, the PreROP1842 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0199] Figure 18C A graphics multiprocessor 1896 according to at least one embodiment is illustrated. In at least one embodiment, the graphics multiprocessor 1896 is... Figure 18BThe graphics multiprocessor 1834 is described. In at least one embodiment, the graphics multiprocessor 1896 is coupled to the pipeline manager 1832 of the processing cluster 1894. In at least one embodiment, the graphics multiprocessor 1896 has an execution pipeline including, but not limited to, an instruction cache 1852, an instruction unit 1854, an address mapping unit 1856, a register file 1858, one or more GPGPU cores 1862, and one or more LSUs 1866. The GPGPU cores 1862 and LSUs 1866 are coupled to cache memory 1872 and shared memory 1870 via memory and cache interconnect 1868.

[0200] In at least one embodiment, instruction cache 1852 receives a stream of instructions to be executed from pipeline manager 1832. In at least one embodiment, instructions are cached in instruction cache 1852 and dispatched to instruction unit 1854 for execution. In one embodiment, instruction unit 1854 may dispatch instructions as thread groups (e.g., thread bundles), assigning each thread of the thread group to a different execution unit within GPGPU core 1862. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit 1856 may be used to translate addresses in the unified address space into different memory addresses that can be accessed by LSU 1866.

[0201] In at least one embodiment, register file 1858 provides a set of registers for the functional units of graphics multiprocessor 1896. In at least one embodiment, register file 1858 provides temporary storage for operands of data paths connected to functional units of graphics multiprocessor 1896 (e.g., GPGPU core 1862, LSU 1866). In at least one embodiment, register file 1858 is partitioned among each functional unit, such that a dedicated portion of register file 1858 is allocated to each functional unit. In at least one embodiment, register file 1858 is partitioned among different thread groups being executed by graphics multiprocessor 1896.

[0202] In at least one embodiment, each of the GPGPU cores 1862 may include an FPU and / or an ALU for executing instructions of the graph multiprocessor 1896. The GPGPU cores 1862 may be architecturally similar or may differ in architecture. In at least one embodiment, a first portion of the GPGPU core 1862 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core 1862 includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 1896 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 1862 may also include fixed-function or special-function logic.

[0203] In at least one embodiment, the GPGPU core 1862 includes SIMD logic capable of executing a single instruction on multiple sets of data. In at least one embodiment, the GPGPU core 1862 can physically execute SIMD4, SIMD8, and SIMD9 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a Single Program Multiple Data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed using a single SIMD instruction. For example, in at least one embodiment, eight SIMD threads performing the same or similar operations can be executed in parallel using a single SIMD8 logic unit.

[0204] In at least one embodiment, the memory and cache interconnect 1868 is an interconnect network connecting each functional unit of the graphics multiprocessor 1896 to the register file 1858 and the shared memory 1870. In at least one embodiment, the memory and cache interconnect 1868 is a cross-switch interconnect that allows the LSU 1866 to perform load and store operations between the shared memory 1870 and the register file 1858. In at least one embodiment, the register file 1858 can operate at the same frequency as the GPGPU core 1862, resulting in very low latency for data transfer between the GPGPU core 1862 and the register file 1858. In at least one embodiment, the shared memory 1870 can be used to enable communication between threads executing on functional units within the graphics multiprocessor 1896. In at least one embodiment, the cache memory 1872 can be used, for example, as a data cache to cache texture data communicated between functional units and texture units 1836. In at least one embodiment, the shared memory 1870 can also be used as a program-managed cache. In at least one embodiment, in addition to the data automatically cached in cache memory 1872, the thread executing on GPGPU core 1862 can also programmatically store data in shared memory.

[0205] In at least one embodiment, a parallel processor or GPGPU, as described herein, is communicatively coupled to the host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., high-speed interconnects such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). In at least one embodiment, regardless of how the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in the WD. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0206] In at least one embodiment, at least one component shown or described in the above figures is used to achieve the combination. Figures 1 to 6 One or more of the described technologies and / or functions are used to select the design frequency of the processing unit.

[0207] Figure 19A graphics processor 1900 according to at least one embodiment is illustrated. In at least one embodiment, the graphics processor 1900 includes a ring interconnect 1902, a pipeline front end 1904, a media engine 1937, and graphics cores 1980A-1980N. In at least one embodiment, the ring interconnect 1902 couples the graphics processor 1900 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, the graphics processor 1900 is one of many processors integrated within a multi-core processing system.

[0208] In at least one embodiment, the graphics processor 1900 receives multiple batches of commands via a ring interconnect 1902. In at least one embodiment, the input commands are interpreted by a command stream converter 1903 in a pipeline front-end 1904. In at least one embodiment, the graphics processor 1900 includes scalable execution logic to perform 3D geometry processing and media processing via graphics cores 1980A-1980N. In at least one embodiment, for 3D geometry processing commands, the command stream converter 1903 provides commands to the geometry pipeline 1936. In at least one embodiment, for at least some media processing commands, the command stream converter 1903 provides commands to a video front-end 1934, which is coupled to a media engine 1937. In at least one embodiment, the media engine 1937 includes a video quality engine (VQE) 1930 for video and image post-processing, and a multi-format encoding / decoding (MFX) engine 1933 for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 1936 and the media engine 1937 each generate an execution thread for thread execution resources provided by at least one graphics core 1980A.

[0209] In at least one embodiment, the graphics processor 1900 includes scalable thread execution resources characterized by modular graphics cores 1980A-1980N (sometimes referred to as core slices), each modular core having multiple sub-cores 1950A-550N, 1960A-1960N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 1900 may have any number of graphics cores 1980A to 1980N. In at least one embodiment, the graphics processor 1900 includes a graphics core 1980A having at least a first sub-core 1950A and a second sub-core 1960A. In at least one embodiment, the graphics processor 1900 is a low-power processor having a single sub-core (e.g., 1950A). In at least one embodiment, the graphics processor 1900 includes multiple graphics cores 1980A-1980N, each graphics core including a set of first sub-cores 1950A-1950N and a set of second sub-cores 1960A-1960N. In at least one embodiment, each of the first sub-cores 1950A-1950N includes at least a first set of execution units (EUs) 1952A-1952N and media / texture samplers 1954A-1954N. In at least one embodiment, each of the second sub-cores 1960A-1960N includes at least a second set of execution units 1962A-1962N and samplers 1964A-1964N. In at least one embodiment, each sub-core 1950A-1950N and 1960A-1960N shares a set of shared resources 1970A-1970N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic.

[0210] In at least one embodiment, at least one component shown or described in the above figures is used to achieve the combination. Figures 1 to 6 One or more of the described technologies and / or functions are used to select the design frequency of the processing unit.

[0211] Figure 20A processor 2000 according to at least one embodiment is illustrated. In at least one embodiment, the processor 2000 may include, but is not limited to, logic circuitry for executing instructions. In at least one embodiment, the processor 2000 can execute instructions, including x86 instructions, ARM instructions, special-purpose instructions for ASICs, etc. In at least one embodiment, the processor 2010 may include registers for storing packaged data, such as the 64-bit wide MMX™ registers in an Intel microprocessor enabled by MMX technology in Santa Clara, California. In at least one embodiment, the MMX registers available in integer and floating-point forms can operate with packaged data elements accompanied by SIMD and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, a 128-bit wide XMM register associated with SSE2, SSE3, SSE4, AVX, or later (generally referred to as “SSEx”) technologies can hold such packaged data operands. In at least one embodiment, the processor 2010 can execute instructions to accelerate CUAD programs.

[0212] In at least one embodiment, processor 2000 includes an ordered front end (“front end”) 2001 to fetch instructions to be executed and prepare instructions for later use in the processor pipeline. In at least one embodiment, front end 2001 may include several units. In at least one embodiment, instruction prefetcher 2026 fetches instructions from memory and provides the instructions to instruction decoder 2028, which in turn decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2028 decodes the received instructions into one or more operations, so-called “micro-instructions” or “micro-operations” (also referred to as “micro-operations” or “micro-instructions”), for execution. In at least one embodiment, instruction decoder 2028 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform the operations. In at least one embodiment, trace cache 2030 may assemble the decoded micro-instructions into a program-ordered sequence or trace in micro-instruction queue 2034 for execution. In at least one embodiment, when trace cache 2030 encounters complex instructions, microcode ROM 2032 provides the micro-instructions required to complete the operation.

[0213] In at least one embodiment, some instructions may be converted into a single micro-operation, while others require several micro-operations to complete the entire operation. In at least one embodiment, if more than four micro-instructions are required to complete an instruction, the instruction decoder 2028 may access the microcode ROM 2032 to execute the instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-instructions for processing at the instruction decoder 2028. In at least one embodiment, if multiple micro-instructions are required to complete an operation, the instructions may be stored in the microcode ROM 2032. In at least one embodiment, the trace cache 2030 references an entry point programmable logic array (“PLA”) to determine the correct micro-instruction pointer for reading a microcode sequence from the microcode ROM 2032 to complete one or more instructions, according to at least one embodiment. In at least one embodiment, after the microcode ROM 2032 has completed the micro-operation ordering of the instructions, the machine front end 2001 may resume fetching micro-operations from the trace cache 2030.

[0214] In at least one embodiment, the out-of-order execution engine (“out-of-order engine”) 2003 can prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions descend the pipeline and are scheduled for execution. The out-of-order execution engine 2003 includes, but is not limited to, an allocator / register renamer 2040, a memory microinstruction queue 2042, an integer / floating-point microinstruction queue 2044, a memory scheduler 2046, a fast scheduler 2002, a slow / general-purpose floating-point scheduler (“slow / general-purpose FP scheduler”) 2004, and a simple floating-point scheduler (“simple FP scheduler”) 2006. In at least one embodiment, the fast scheduler 2002, the slow / general-purpose floating-point scheduler 2004, and the simple floating-point scheduler 2006 are also collectively referred to as “microinstruction schedulers 2002, 2004, 2006”. The allocator / register renamer 2040 allocates the machine buffers and resources required for the sequential execution of each microinstruction. In at least one embodiment, the allocator / register renamer 2040 renames logical registers to entries in a register file. In at least one embodiment, the allocator / register renamer 2040 also assigns an entry for each microinstruction in one of two microinstruction queues, memory microinstruction queue 2042 for memory operations and integer / floating-point microinstruction queue 2044 for non-memory operations, preceding the memory scheduler 2046 and microinstruction schedulers 2002, 2004, and 2006. In at least one embodiment, the microinstruction schedulers 2002, 2004, and 2006 determine when they are ready to execute a microinstruction based on the readiness of their dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. In at least one embodiment, the fast scheduler 2002 of at least one embodiment can schedule on each half of the master clock cycle, while the slow / general-purpose floating-point scheduler 2004 and the simple floating-point scheduler 2006 can schedule once per master processor clock cycle. In at least one embodiment, microinstruction schedulers 2002, 2004, and 2006 arbitrate the scheduling port to schedule microinstructions for execution.

[0215] In at least one embodiment, execution block 2011 includes, but is not limited to, integer register file / tribute network 2008, floating-point register file / tribute network (“FP register file / tribute network”) 2010, address generation unit (“AGU”) 2012 and 2014, fast arithmetic logic unit (“fast ALU”) 2016 and 2018, slow ALU 2020, floating-point ALU (“FP”) 2022, and floating-point movement unit (“FP movement”) 2024. In at least one embodiment, integer register file / tribute network 2008 and floating-point register file / bypass network 2010 are also referred to herein as “register file 2008, 2010”. In at least one embodiment, AGUS2012 and 2014, fast ALU 2016 and 2018, slow ALU 2020, floating-point ALU 2022, and floating-point movement unit 2024 are also referred to herein as "execution units 2012, 2014, 2016, 2018, 2020, 2022, and 2024". In at least one embodiment, the execution block may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0216] In at least one embodiment, register files 2008 and 2010 may be arranged between microinstruction schedulers 2002, 2004, and 2006 and execution units 2012, 2014, 2016, 2018, 2020, 2022, and 2024. In at least one embodiment, integer register file / tribute network 2008 performs integer operations. In at least one embodiment, floating-point register file / tribute network 2010 performs floating-point operations. In at least one embodiment, each of register files 2008 and 2010 may include, but is not limited to, a tribute network that can bypass or forward recently completed results not yet written to the register file to a new dependent object. In at least one embodiment, register files 2008 and 2010 can communicate data with each other. In at least one embodiment, integer register file / tribute network 2008 may include, but is not limited to, two separate register files, one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, the floating-point register file / tribute network 2010 may include, but is not limited to, 128-bit wide entries, since floating-point instructions typically have operands with a width of 64 to 128 bits.

[0217] In at least one embodiment, execution units 2012, 2014, 2016, 2018, 2020, 2022, and 2024 can execute instructions. In at least one embodiment, register files 2008 and 2010 store integer and floating-point data operation values ​​that the microinstructions need to execute. In at least one embodiment, processor 2000 may include, but is not limited to, any number of execution units 2012, 2014, 2016, 2018, 2020, 2022, and 2024, and combinations thereof. In at least one embodiment, floating-point ALU 2022 and floating-point movement unit 2024 can perform floating-point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2022 may include, but is not limited to, a 64-bit multiplication-64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to the fast ALU 2016, 2018. In at least one embodiment, the fast ALU 2016, 2018 can perform fast operations with an effective delay of half a clock cycle. In at least one embodiment, most complex integer operations are routed to the slow ALU 2020, because the slow ALU 2020 can include, but is not limited to, integer execution hardware for long-latency type operations, such as multipliers, shifters, flag logic, and branching. In at least one embodiment, memory load / store operations can be performed by the ALU 2012, 2014. In at least one embodiment, the fast ALU 2016, fast ALU 2018, and slow ALU 2020 can perform integer operations on 64-bit data operands. In at least one embodiment, the fast ALU 2016, fast ALU 2018, and slow ALU 2020 can be implemented to support various data bit sizes including 16, 32, 128, 256, etc. In at least one embodiment, the floating-point ALU 2022 and the floating-point movement unit 2024 can be implemented to support a range of operands with various bit widths. In at least one embodiment, the floating-point ALU 2022 and the floating-point movement unit 2024 can operate on 128-bit wide packaged data operands in conjunction with SIMD and multimedia instructions.

[0218] In at least one embodiment, microinstruction schedulers 2002, 2004, and 2006 schedule dependent operations before the parent load completes execution. In at least one embodiment, since microinstructions can be speculatively scheduled and executed within processor 2000, processor 2000 may also include logic for handling memory misses. In at least one embodiment, if a data load miss occurs in the data cache, there may be a dependent operation running in the pipeline that temporarily deprives the scheduler of the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and may allow independent operations to be completed. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences used for text string comparison operations.

[0219] In at least one embodiment, the term "register" may refer to an onboard processor storage location that can be used as part of an instruction that identifies operands. In at least one embodiment, a register may be one that can be used externally to the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented using a variety of different techniques via circuitry within the processor, such as dedicated physical registers, dynamically allocated physical registers renamed using register renaming, a combination of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, an integer register stores 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for encapsulating data.

[0220] In at least one embodiment, at least one component shown or described in the above figures is used to achieve the combination. Figures 1 to 6 One or more of the described technologies and / or functions are used to select the design frequency of the processing unit.

[0221] Figure 21A processor 2100 according to at least one embodiment is illustrated. In at least one embodiment, the processor 2100 includes, but is not limited to, one or more processor cores (cores) 2102A-2102N, an integrated memory controller 2114, and an integrated graphics processor 2108. In at least one embodiment, the processor 2100 may include additional cores up to and including additional processor cores 2102N, indicated by dashed boxes. In at least one embodiment, each processor core 2102A-2102N includes one or more internal cache units 2104A-2104N. In at least one embodiment, each processor core may also access one or more units 2106 of a shared cache. In at least one embodiment, one or more processor cores 2102A-2102N are referred to as one or more computing units or arithmetic units.

[0222] In at least one embodiment, internal cache units 2104A-2104N and shared cache unit 2106 represent a cache memory hierarchy within processor 2100. In at least one embodiment, cache memory units 2104A-2104N may include at least one level of instruction and data within each processor core, and one or more levels of cache in a shared intermediate cache, such as L2, L3, L4, or other levels of cache, wherein the highest level of cache is classified as LLC before external memory. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 2106 and 2104A-2104N.

[0223] In at least one embodiment, the processor 2100 may further include a set of one or more bus controller units 2116 and a system agent core 2110. In at least one embodiment, the one or more bus controller units 2116 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, the system agent core 2110 provides management functions for various processor components. In at least one embodiment, the system agent core 2110 includes one or more integrated memory controllers 2114 to manage access to various external memory devices (not shown).

[0224] In at least one embodiment, one or more processor cores 2102A-2102N include support for multi-threaded concurrent processing. In at least one embodiment, system agent core 2110 includes components for coordinating and operating processor cores 2102A-2102N during multi-threaded processing. In at least one embodiment, system agent core 2110 may additionally include a power control unit (PCU) including logic and components for regulating one or more power states of processor cores 2102A-2102N and graphics processor 2108.

[0225] In at least one embodiment, processor 2100 further includes graphics processor 2108 to perform graphics processing operations. In at least one embodiment, graphics processor 2108 is coupled to a shared cache unit 2106 and a system proxy core 2110 including one or more integrated memory controllers 2114. In at least one embodiment, system proxy core 2110 further includes a display controller 2111 for driving graphics processor outputs to one or more coupled displays. In at least one embodiment, display controller 2111 may also be a separate module coupled to graphics processor 2108 via at least one interconnect, or it may be integrated within graphics processor 2108.

[0226] In at least one embodiment, ring-based interconnect unit 2112 is used to couple internal components of processor 2100. In at least one embodiment, alternative interconnect units, such as point-to-point interconnects, switched interconnects, or other technologies, may be used. In at least one embodiment, graphics processor 2108 is coupled to ring interconnect 2112 via I / O link 2113.

[0227] In at least one embodiment, I / O link 2113 represents at least one of a variety of I / O interconnects, including packaged I / O interconnects that facilitate communication between various processor components and high-performance embedded memory module 2118 (e.g., eDRAM module). In at least one embodiment, each of processor cores 2102A-2102N and graphics processor 2108 uses embedded memory module 2118 as a shared LLC.

[0228] In at least one embodiment, processor cores 2102A-2102N are homogeneous cores executing a common instruction set architecture. In at least one embodiment, processor cores 2102A-2102N are heterogeneous in terms of the instruction set architecture (ISA), with one or more processor cores 2102A-2102N executing a common instruction set, while one or more other processor cores 2102A-2102N execute a common instruction set or a subset of a different instruction set. In at least one embodiment, processor cores 2102A-2102N are heterogeneous in terms of microarchitecture, with one or more cores having relatively high power consumption coupled to one or more power cores having lower power consumption. In at least one embodiment, processor 2100 can be implemented on one or more chips or implemented as a SoC integrated circuit.

[0229] In at least one embodiment, at least one component shown or described in the above figures is used to achieve the combination. Figures 1 to 6 One or more of the described technologies and / or functions are used to select the design frequency of the processing unit.

[0230] Figure 22 A graphics processing unit (GPU) core 2200 according to at least one embodiment described is illustrated. In at least one embodiment, the GPU core 2200 is included within a GPU core array. In at least one embodiment, the GPU core 2200 (sometimes referred to as a core slice) may be one or more GPU cores within a modular GPU. In at least one embodiment, the GPU core 2200 is an example of a GPU core slice, and the GPU described herein may include multiple GPU core slices based on target power and performance envelopes. In at least one embodiment, each GPU core 2200 may include a fixed-function block 2230, also referred to as a sub-slice, coupled to a plurality of sub-cores 2201A-2201F, which includes modular blocks of general-purpose and fixed-function logic.

[0231] In at least one embodiment, the fixed-function block 2230 includes a geometry / fixed-function pipeline 2236, which, for example, may be shared by all sub-cores of the graphics processor 2200 in a lower-performance and / or lower-power graphics processor implementation. In at least one embodiment, the geometry / fixed-function pipeline 2236 includes a 3D fixed-function pipeline, a video front-end unit, a thread generator and a thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0232] In at least one embodiment, fixed function block 2230 further includes a graphics SoC interface 2237, a graphics microcontroller 2238, and a media pipeline 2239. The graphics SoC interface 2237 provides an interface between the graphics core 2200 and other processor cores in the SoC integrated circuit system. In at least one embodiment, the graphics microcontroller 2238 is a programmable subprocessor configurable to manage various functions of the graphics processor 2200, including thread dispatch, scheduling, and preemption. In at least one embodiment, the media pipeline 2239 includes logic that facilitates decoding, encoding, preprocessing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, the media pipeline 2239 implements media operations via requests for computation or sampling logic within subcores 2201-2201F.

[0233] In at least one embodiment, the SoC interface 2237 enables the graphics core 2200 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as shared LLC memory, system RAM, and / or embedded on-chip or packaged DRAM. In at least one embodiment, the SoC interface 2237 also enables communication with fixed-function devices within the SoC (e.g., a camera imaging pipeline) and enables the use and / or implementation of global memory atoms that can be shared between the graphics core 2200 and the CPU within the SoC. In at least one embodiment, the SoC interface 2237 also implements power management control for the graphics core 2200 and enables interfacing between the clock domain of the graphics core 2200 and other clock domains within the SoC. In at least one embodiment, the SoC interface 2237 enables the reception of command buffers from a command stream converter and a global thread dispatcher, configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, when a media operation is to be performed, commands and instructions can be dispatched to media pipeline 2239, or when a graph processing operation is to be performed, they can be assigned to geometry and fixed function pipelines (e.g., geometry and fixed function pipeline 2236, geometry and fixed function pipeline 2214).

[0234] In at least one embodiment, the graphics microcontroller 2238 can be configured to perform various scheduling and management tasks on the graphics core 2200. In at least one embodiment, the graphics microcontroller 2238 can perform graph and / or computation workload scheduling on various graphics parallel engines within the execution unit (EU) arrays 2202A-2202F, 2204A-2204F in subcores 2201A-2201F. In at least one embodiment, host software executing on the CPU core of the SoC including the graphics core 2200 can submit a workload of one of a plurality of graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, the scheduling operation includes determining which workload should be run next, submitting the workload to a command stream converter, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is completed. In at least one embodiment, the graphics microcontroller 2238 may also facilitate a low-power or idle state of the graphics core 2200, thereby providing the graphics core 2200 with the ability to save and restore registers across low-power state transitions within the graphics core 2200, independent of the operating system and / or the graphics driver software on the system.

[0235] In at least one embodiment, the graphics core 2200 may have more or fewer subcores than the illustrated subcores 2201A-2201F, up to N modular subcores. For each group of N subcores, in at least one embodiment, the graphics core 2200 may further include shared functional logic 2210, shared and / or cache memory 2212, geometry / fixed-function pipeline 2214, and additional fixed-function logic 2216 to accelerate various graphics and computational processing operations. In at least one embodiment, the shared functional logic 2210 may include logic units (e.g., samplers, mathematical and / or inter-thread communication logic) that can be shared by each of the N subcores within the graphics core 2200. The shared and / or cache memory 2212 may be an LLC of the N subcores 2201A-2201F within the graphics core 2200, and may also be used as shared memory accessible by multiple subcores. In at least one embodiment, a geometry / fixed function pipeline 2214 may be included to replace the geometry / fixed function pipeline 2236 within the fixed function block 2230, and may include the same or similar logic units.

[0236] In at least one embodiment, the graphics core 2200 includes additional fixed-function logic 2216, which may include various fixed-function acceleration logics for use by the graphics core 2200. In at least one embodiment, the additional fixed-function logic 2216 includes additional geometry pipelines for use in position-only shading. In position-only shading, there are at least two geometry pipelines, and in the full geometry pipeline and culling pipeline within the geometry / fixed-function pipelines 2216, 2236, it is an additional geometry pipeline that can be included in the additional fixed-function logic 2216. In at least one embodiment, the culling pipeline is a trimmed version of the full geometry pipeline. In at least one embodiment, the full pipeline and the culling pipeline can execute different instances of the application, each with a separate environment. In at least one embodiment, position-only shading can hide long culling runs of discarded triangles, thereby allowing shading to be completed earlier in some cases. For example, in at least one embodiment, the culling pipeline logic in the additional fixed-function logic 2216 can execute the position shader in parallel with the main application and typically generates critical results faster than the full pipeline because the culling pipeline acquires and occludes the positional attributes of vertices without performing rasterization and rendering pixels to the framebuffer. In at least one embodiment, the culling pipeline can use the generated critical results to compute visibility information for all triangles, regardless of whether those triangles were culled. In at least one embodiment, the full pipeline (which may be referred to as the replay pipeline in this case) can consume visibility information to skip culled triangles and only occlude the visible triangles that are ultimately passed to the rasterization stage.

[0237] In at least one embodiment, the additional fixed-function logic 2216 may also include general target processing acceleration logic, such as fixed-function matrix multiplication logic, for implementing a decelerated CUAD program.

[0238] In at least one embodiment, each graphics subcore 2201A-2201F includes a set of row resources that can be used to perform graph, media, and computation operations in response to requests from the graphics pipeline, media pipeline, or shader program. In at least one embodiment, the graphics subcore 2201A-2201F includes multiple EU arrays 2202A-2202F, 2204A-2204F, thread dispatch and inter-thread communication (TD / IC) logic 2203A-2203F, 3D (e.g., texture) samplers 2205A-2205F, media samplers 2206A-2206F, shader processors 2207A-2207F, and shared local memory (SLM) 2208A-2208F. Each of the EU arrays 2202A-2202F and 2204A-2204F contains multiple execution units, which are GUGPUs capable of servicing graphics, media, or computational operations, performing floating-point and integer / fixed-point logic operations, including graphics, media, or computational shader programs. In at least one embodiment, the TD / IC logic 2203A-2203F performs local thread dispatch and thread control operations for the execution units within the subcore and facilitates communication between threads executing on the execution units of the subcore. In at least one embodiment, the 3D samplers 2205A-2205F can read data associated with other 3D graphics textures into memory. In at least one embodiment, the 3D samplers can read texture data differently based on the sampling state and texture format configured and associated with a given texture. In at least one embodiment, the media samplers 2206A-2206F can perform similar read operations based on the type and format associated with the media data. In at least one embodiment, each graphics subcore 2201A-2201F may alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each subcore 2201A-2201F may utilize shared local memory 2208A-2208F within each subcore, enabling threads executing within a thread group to use a common pool of on-chip memory for execution.

[0239] In at least one embodiment, at least one component shown or described in the above figures is used to achieve the combination. Figures 1 to 6 One or more of the described technologies and / or functions are used to select the design frequency of the processing unit.

[0240] Figure 23A parallel processing unit (“PPU”) 2300 according to at least one embodiment is illustrated. In at least one embodiment, the PPU 2300 is configured with machine-readable code that, if executed by the PPU 2300, causes the PPU 2300 to perform some or all of the processes and techniques described herein. In at least one embodiment, the PPU 2300 is a multi-threaded processor implemented on one or more integrated circuit devices and utilizes multi-threading as a latency-hiding technique designed to process computer-readable instructions (also known as machine-readable instructions or simple instructions) that are executed in parallel on multiple threads. In at least one embodiment, a thread refers to an execution thread and is an instance of a set of instructions configured to be executed by the PPU 2300. In at least one embodiment, the PPU 2300 is a graphics processing unit (“GPU”) configured to implement a graphics rendering pipeline for processing three-dimensional (“3D”) graphics data to generate two-dimensional (“2D”) image data for display on a display device, such as an LCD device. In at least one embodiment, the PPU 2300 is used to perform computations, such as linear algebra operations and machine learning operations. Figure 23 An example parallel processor is shown for illustrative purposes only and should be interpreted as a non-limiting example of a processor architecture implemented in at least one embodiment.

[0241] In at least one embodiment, one or more PPUs 2300 are configured to accelerate high-performance computing (“HPC”), data center, and machine learning applications. In at least one embodiment, one or more PPUs 2300 are configured to accelerate CUDA programs. In at least one embodiment, the PPU 2300 includes, but is not limited to, I / O unit 2306, front-end unit 2310, scheduler unit 2312, job allocation unit 2314, hub 2316, crossbar switch (“Xbar”) 2320, one or more general-purpose processing clusters (“GPC”) 2318, and one or more partitioning units (“memory partitioning units”) 2322. In at least one embodiment, the PPU 2300 is connected to a host processor or other PPU 2300 via one or more high-speed GPU interconnects (“GPU interconnects”) 2308. In at least one embodiment, the PPU 2300 is connected to a host processor or other peripheral devices via a system bus or interconnect 2302. In one embodiment, the PPU 2300 is connected to a local memory including one or more memory devices (“memory”) 2304. In at least one embodiment, the memory device 2304 includes, but is not limited to, one or more dynamic random access memory (“DRAM”) devices. In at least one embodiment, the one or more DRAM devices are configured and / or configurable as a high bandwidth memory (“HBM”) subsystem, and multiple DRAM dies are stacked within each device.

[0242] In at least one embodiment, the high-speed GPU interconnect 2308 may refer to a wire-based multi-channel communication link used by the system for scaling, and includes one or more PPUs 2300s (“CPUs”) coupled with one or more CPUs, supporting cache coherency between the PPUs 2300s and the CPUs, as well as CPU master control. In at least one embodiment, the high-speed GPU interconnect 2308 transmits data and / or commands to other units of the PPU 2300, such as one or more copy engines, video encoders, video decoders, power management units, and / or other components, via a hub 2316. Figure 23 Other components that may not be explicitly shown.

[0243] In at least one embodiment, the I / O unit 2306 is configured to access the host processor via the system bus 2302. Figure 23(Not shown) Sending and receiving communications (e.g., commands, data). In at least one embodiment, I / O unit 2306 communicates directly with the host processor via system bus 2302 or via one or more intermediate devices (e.g., memory bridges). In at least one embodiment, I / O unit 2306 may communicate with one or more other processors (e.g., one or more PPUs 2300) via system bus 2302. In at least one embodiment, I / O unit 2306 implements a PCIe interface for communication via the PCIe bus. In at least one embodiment, I / O unit 2306 implements an interface for communication with external devices.

[0244] In at least one embodiment, I / O unit 2306 decodes packets received via system bus 2302. In at least one embodiment, at least some packets represent commands configured to cause PPU 2300 to perform various operations. In at least one embodiment, I / O unit 2306 sends the decoded commands to various other units of PPU 2300 as specified by the commands. In at least one embodiment, the commands are sent to front-end unit 2310 and / or to hub 2316 or other units of PPU 2300, such as one or more copy engines, video encoders, video decoders, power management units, etc. Figure 23 (Not explicitly shown). In at least one embodiment, I / O unit 2306 is configured to route communication between various logical units of PPU 2300.

[0245] In at least one embodiment, a program executed by the host processor encodes a command stream in a buffer that provides a workload to the PPU 2300 for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffer is a region in memory accessible (e.g., read / write) by both the host processor and the PPU 2300—the host interface unit can be configured to access a buffer in system memory connected to the system bus 2302 via memory requests transmitted through the system bus 2302 via the I / O unit 2306. In at least one embodiment, the host processor writes a command stream to the buffer and then sends a pointer indicating the start of the command stream to the PPU 2300, causing the front-end unit 2310 to receive pointers to one or more command streams and manage one or more command streams, read commands from the command streams, and forward the commands to the respective units of the PPU 2300.

[0246] In at least one embodiment, front-end unit 2310 is coupled to scheduler unit 2312, which configures various GPCs 2318 to process tasks defined by one or more command streams. In at least one embodiment, scheduler unit 2312 is configured to track status information related to the various tasks managed by scheduler unit 2312, wherein the status information may indicate which GPC 2318 a task is assigned to, whether the task is active or inactive, the priority associated with the task, etc. In at least one embodiment, scheduler unit 2312 manages multiple tasks executed on one or more GPCs 2318.

[0247] In at least one embodiment, scheduler unit 2312 is coupled to job allocation unit 2314, which is configured to dispatch tasks for execution on GPC 2318. In at least one embodiment, job allocation unit 2314 tracks multiple scheduled tasks received from scheduler unit 2312 and manages a pool of pending tasks and an active task pool for each GPC 2318. In at least one embodiment, the pool of pending tasks includes multiple time slots (e.g., 32 time slots) containing tasks assigned to a particular GPC 2318 for processing; the active task pool may include multiple time slots (e.g., 4 time slots) for tasks actively processed by GPC 2318, such that as one of the GPCs 2318 completes its execution, that task is evicted from the active task pool of the GPC 2318, and one of other tasks is selected from the pool of pending tasks and scheduled for execution on the GPC 2318. In at least one embodiment, if an active task is idle on GPC 2318, for example while waiting for data dependency resolution, the active task is evicted from GPC 2318 and returned to the task pool, while another task in the task pool is selected and scheduled to be executed on GPC 2318.

[0248] In at least one embodiment, the work allocation unit 2314 communicates with one or more GPCs 2318 via XBar 2320. In at least one embodiment, XBar 2320 is an interconnect network that couples a plurality of units of PPU 2300 to other units of PPU 2300, and can be configured to couple the work allocation unit 2314 to a specific GPC 2318. In at least one embodiment, other units of one or more PPUs 2300 can also be connected to XBar 2320 via hub 2316.

[0249] In at least one embodiment, tasks are managed by scheduler unit 2312 and assigned to one of GPCs 2318 by job allocation unit 2314. GPCs 2318 are configured to process tasks and produce results. In at least one embodiment, results may be consumed by other tasks in GPCs 2318, routed to different GPCs 2318 via XBar 2320, or stored in memory 2304. In at least one embodiment, results may be written to memory 2304 via partitioning unit 2322, which implements a memory interface for writing data to or reading data from memory 2304. In at least one embodiment, results may be transferred to another PPU 2300 or CPU via high-speed GPU interconnect 2308. In at least one embodiment, PPU 2300 includes, but is not limited to, U partitioning units 2322, which is equal to the number of separate and distinct memory devices 2304 coupled to PPU 2300.

[0250] In at least one embodiment, the host processor executes a driver core that implements an application programming interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU 2300. In one embodiment, multiple computing applications are executed concurrently by the PPU 2300, and the PPU 2300 provides isolation, Quality of Service (“QoS”), and independent address spaces for the multiple computing applications. In at least one embodiment, an application generates instructions (e.g., in the form of API calls) that cause the driver core to generate one or more tasks for execution by the PPU 2300, and the driver core outputs the tasks to one or more streams processed by the PPU 2300. In at least one embodiment, each task includes one or more associated thread groups, which may be referred to as a warp. In at least one embodiment, a warp includes multiple associated threads (e.g., 32 threads) that can be executed in parallel. In at least one embodiment, a cooperating thread may refer to multiple threads, including instructions for performing tasks and exchanging data via shared memory.

[0251] In at least one embodiment, at least one component shown or described in the above figures is used to achieve the combination. Figures 1 to 6 One or more of the described technologies and / or functions are used to select the design frequency of the processing unit.

[0252] Figure 24 A GPC 2400 according to at least one embodiment is shown. In at least one embodiment, the GPC 2400 is Figure 23The GPC 2318. In at least one embodiment, each GPC 2400 includes, but is not limited to, a plurality of hardware units for processing tasks, and each GPC 2400 includes, but is not limited to, a pipeline manager 2402, a pre-raster operation unit (“PROP”) 2404, a raster engine 2408, a work assignment crossbar switch (“WDX”) 2416, a memory management unit (“MMU”) 2418, one or more data processing clusters (“DPC”) 2406, and any suitable combination of components.

[0253] In at least one embodiment, the operation of GPC 2400 is controlled by pipeline manager 2402. In at least one embodiment, pipeline manager 2402 manages the configuration of one or more DPCs 2406 to handle tasks assigned to GPC 2400. In at least one embodiment, pipeline manager 2402 configures at least one of one or more DPCs 2406 to implement at least a portion of the graphics rendering pipeline. In at least one embodiment, DPC 2406 is configured to execute vertex shader programs on programmable streaming multiprocessor (“SM”) 2414. In at least one embodiment, pipeline manager 2402 is configured to route packets received from the work allocation unit to appropriate logic units within GPC 2400, and in at least one embodiment, some packets may be routed to fixed-function hardware units in PROP 2404 and / or raster engine 2408, while other packets may be routed to DPC 2406 for processing by raw engine 2412 or SM 2414. In at least one embodiment, pipeline manager 2402 configures at least one of DPCs 2406 to implement a neural network model and / or computation pipeline. In at least one embodiment, pipeline manager 2402 configures at least one of DPCs 2406 to execute at least a portion of a CUDA program.

[0254] In at least one embodiment, the PROP unit 2404 is configured to route data generated by the raster engine 2408 and DPC 2406 to the raster operation (“ROP”) unit in the partition unit, for example, in conjunction with the above. Figure 23Memory partitioning unit 2322, etc., are described in more detail. In at least one embodiment, PROP unit 2404 is configured to perform optimizations for color blending, organize pixel data, perform address translation, etc. In at least one embodiment, raster engine 2408 includes, but is not limited to, multiple fixed-function hardware units configured to perform various raster operations, and in at least one embodiment, raster engine 2408 includes, but is not limited to, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile aggregation engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives the transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices; the plane equations are transmitted to the coarse raster engine to generate coverage information of basic primitives (e.g., x, y coverage masks of tiles); the output of the coarse raster engine is transmitted to the culling engine, in which fragments associated with primitives that fail the z-test are culled, and transmitted to the clipping engine, in which fragments located outside the view frustum are clipped. In at least one embodiment, the cropped and culled fragments are passed to a fine raster engine to generate properties of pixel fragments based on a planar equation generated by the settings engine. In at least one embodiment, the output of the raster engine 2408 includes fragments that will be processed by any suitable entity (e.g., by a fragment shader implemented within the DPC 2406).

[0255] In at least one embodiment, each DPC 2406 included in the GPC 2400 includes, but is not limited to, an M-pipeline controller (“MPC”) 2410; a primitive engine 2412; one or more SMs 2414; and any suitable combination thereof. In at least one embodiment, the MPC 2410 controls the operation of the DPC 2406, routing packets received from the pipeline manager 2402 to the appropriate units within the DPC 2406. In at least one embodiment, packets associated with vertices are routed to the primitive engine 2412, which is configured to retrieve vertex attributes associated with vertices from memory; conversely, packets associated with shader programs may be sent to the SM 2414.

[0256] In at least one embodiment, the SM 2414 includes, but is not limited to, a programmable streaming processor configured to process tasks represented by multiple threads. In at least one embodiment, the SM 2414 is multithreaded and configured to execute multiple threads (e.g., 32 threads) from a specific thread group concurrently, and implements a Single Instruction, Multiple Data (“SIMD”) architecture, wherein each thread in a group of threads (e.g., a thread bundle) is configured to process a different dataset based on the same instruction set. In at least one embodiment, all threads in the thread group execute the same instructions. In at least one embodiment, the SM 2414 implements a Single Instruction, Multiple Thread (“SIMT”) architecture, wherein each thread in a group of threads is configured to process a different dataset based on the same instruction set, but wherein individual threads in the thread group are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each thread bundle, thereby achieving concurrency between the thread bundle and serial execution within the thread bundle when threads in the thread bundle diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread, thereby ensuring equal concurrency among all threads within and between thread bundles. In at least one embodiment, an execution state is maintained for each individual thread, and threads executing the same instructions can be converged and executed in parallel to improve efficiency. The following is in conjunction with... Figure 25 At least one embodiment of SM 2414 is described in more detail.

[0257] In at least one embodiment, the MMU 2418 is integrated with the GPC 2400 and memory partitioning unit (e.g., Figure 23 The MMU 2418 provides an interface between the partition units 2322 and provides virtual address to physical address translation, memory protection, and memory request arbitration. In at least one embodiment, the MMU 2418 provides one or more translation back buffers (“TLBs”) for performing virtual address to physical address translation in memory.

[0258] In at least one embodiment, at least one component shown or described in the above figures is used to achieve the combination. Figures 1 to 6 One or more of the described technologies and / or functions are used to select the design frequency of the processing unit.

[0259] Figure 25 A streaming multiprocessor (“SM”) 2500 according to at least one embodiment is illustrated. In at least one embodiment, the SM 2500 is Figure 24The SM 2414. In at least one embodiment, the SM 2500 includes, but is not limited to, instruction cache 2502; one or more scheduler units 2504; register file 2508; one or more processing cores (“cores”) 2510; one or more special function units (“SFUs”) 2512; one or more load / store units (“LSUs”) 2514; interconnect network 2516; shared memory / Level 1 (“L1”) cache 2518; and any suitable combination thereof. In at least one embodiment, the work allocation unit schedules tasks to execute on a general-purpose processing cluster (“GPC”) of parallel processing units (“PPUs”), and each task is assigned to a specific data processing cluster (“DPC”) within the GPC, and if the task is associated with a shader program, the task is assigned to one of the SMs 2500. In at least one embodiment, the scheduler unit 2504 receives tasks from the work allocation unit and manages instruction scheduling for one or more thread blocks assigned to the SM 2500. In at least one embodiment, scheduler unit 2504 schedules thread blocks to execute as thread bundles of parallel threads, wherein each thread block is assigned at least one thread bundle. In at least one embodiment, each thread bundle executes a thread. In at least one embodiment, scheduler unit 2504 manages multiple different thread blocks, assigns thread bundles to different thread blocks, and then dispatches instructions from multiple different cooperative groups to various functional units (e.g., processing core 2510, SFU 2512, and LSU 2514) in each clock cycle. In at least one embodiment, SM 2500 includes one or more thread block clusters, wherein thread block clusters can implement programmable control of locality at a granularity greater than that of a single thread block in a single streaming multiprocessor (SM). In at least one embodiment, thread block clusters (also referred to as “clusters”) enable multiple thread blocks running concurrently across streaming multiprocessors to synchronously and cooperatively acquire, exchange, or otherwise use data.

[0260] In at least one embodiment, a "cooperative group" can refer to a programming model used to organize groups of communicating threads, allowing developers to express the granularity at which threads are communicating, thereby enabling richer and more efficient parallel decompositions. In at least one embodiment, the cooperative startup API supports synchronization between thread blocks to execute parallel algorithms. In at least one embodiment, the API of a conventional programming model provides a single, simple construct for synchronizing cooperative threads: a barrier across all threads in a thread block (e.g., the `syncthreads()` function). However, in at least one embodiment, programmers can define thread groups at a granularity smaller than that of thread blocks and synchronize within the defined groups to achieve higher performance, design flexibility, and software reuse in the form of a set of group-wide functional interfaces. In at least one embodiment, cooperative groups enable programmers to explicitly define thread groups at the sub-block and multi-block granularity and perform set operations, such as synchronizing threads within the cooperative group. In at least one embodiment, the sub-block granularity is as small as that of a single thread. In at least one embodiment, the programming model supports clean composition across software boundaries, allowing library and utility functions to be safely synchronized in their local environment without having to make assumptions about convergence. In at least one embodiment, the cooperative group primitives enable new patterns of cooperative parallelism, including but not limited to producer-consumer parallelism, opportunistic parallelism, and global synchronization across the entire thread block mesh.

[0261] In at least one embodiment, dispatch unit 2506 is configured to send instructions to one or more functional units, and scheduler unit 2504 includes, but is not limited to, two dispatch units 2506 that enable two different instructions from the same thread bundle to be dispatched in each clock cycle. In at least one embodiment, each scheduler unit 2504 includes a single dispatch unit 2506 or additional dispatch units 2506.

[0262] In at least one embodiment, each SM 2500 includes, but is not limited to, a register file 2508 that provides a set of registers for functional units of the SM 2500. In at least one embodiment, the register file 2508 is partitioned between each functional unit, thereby allocating a dedicated portion of the register file 2508 for each functional unit. In at least one embodiment, the register file 2508 is partitioned between different thread bundles executed by the SM 2500, and the register file 2508 provides temporary storage for operands connected to data paths of functional units. In at least one embodiment, each SM 2500 includes, but is not limited to, a plurality of L processing cores 2510. In at least one embodiment, the SM 2500 includes, but is not limited to, a large number (e.g., 128 or more) of different processing cores 2510. In at least one embodiment, each processing core 2510 includes, but is not limited to, a fully pipelined, single-precision, double-precision, and / or mixed-precision processing unit, which includes, but is not limited to, a floating-point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, the floating-point arithmetic logic unit implements the IEEE 754-2008 standard for floating-point arithmetic. In at least one embodiment, the processing core 2510 includes, but is not limited to, 64 single-precision (32-bit) floating-point cores, 64 integer cores, 32 double-precision (64-bit) floating-point cores and 8 tensor cores.

[0263] In at least one embodiment, the tensor core is configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in the processing core 2510. In at least one embodiment, the tensor core is configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inference. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs matrix multiplication and accumulation operations D = A×B + C, where A, B, C, and D are 4×4 matrices.

[0264] In at least one embodiment, matrix multiplication inputs A and B are 16-bit floating-point matrices, and accumulation matrices C and D are either 16-bit or 32-bit floating-point matrices. In at least one embodiment, the Tensor Core performs 32-bit floating-point accumulation on the 16-bit floating-point input data. In at least one embodiment, the 16-bit floating-point multiplication uses 64 operations to obtain a full-precision product, which is then accumulated with other intermediate multiplications using 32-bit floating-point addition to perform a 4x4x4 matrix multiplication. In at least one embodiment, the Tensor Core is used to perform matrix operations on larger two-dimensional or higher-dimensional matrices composed of these smaller components. In at least one embodiment, an API (such as the CUDA-C++ API) exposes specialized matrix loading, matrix multiplication and accumulation, and matrix storage operations to efficiently utilize the Tensor Core from CUDA-C++ programs. In at least one embodiment, at the CUDA level, the thread bundle level interface assumes a 16×16 matrix spanning all 32 thread bundle threads.

[0265] In at least one embodiment, each SM 2500 includes, but is not limited to, M SFUs 2512 that perform special functions (e.g., attribute evaluation, inverse square root, etc.). In at least one embodiment, the SFUs 2512 include, but are not limited to, tree traversal units configured to traverse hierarchical tree data structures. In at least one embodiment, the SFUs 2512 include, but are not limited to, texture units configured to perform texture map filtering operations. In at least one embodiment, the texture unit is configured to load texture maps (e.g., a 2D array of texture pixels) from memory and sample the texture maps to produce sampled texture values ​​for use by a shader program executed by the SM 2500. In at least one embodiment, the texture maps are stored in shared memory / L1 cache 2518. In at least one embodiment, the texture unit uses mip-maps (e.g., texture maps with different levels of detail) to implement texture operations (such as filtering operations). In at least one embodiment, each SM 2500 includes, but is not limited to, two texture units.

[0266] In at least one embodiment, each SM 2500 includes, but is not limited to, N LSUs 2514 that implement load and store operations between the shared memory / L1 cache 2518 and the register file 2508. In at least one embodiment, each SM 2500 includes, but is not limited to, an interconnect network 2516 that connects each functional unit to the register file 2508, and the LSUs 2514 that connect the register file 2508 and the shared memory / L1 cache 2518. In at least one embodiment, the interconnect network 2516 is a crossbar switch that can be configured to connect any functional unit to any register in the register file 2508 and to connect the LSUs 2514 to memory locations in the register file 2508 and the shared memory / L1 cache 2518.

[0267] In at least one embodiment, the shared memory / L1 cache 2518 is an array of on-chip memory that, in at least one embodiment, allows data storage and communication between the SM 2500 and the primitive engine, as well as between threads within the SM 2500. In at least one embodiment, the shared memory / L1 cache 2518 includes, but is not limited to, a storage capacity of 128KB and is located on the path from the SM 2500 to the partition unit. In at least one embodiment, the shared memory / L1 cache 2518 is used for cache reads and writes. In at least one embodiment, one or more of the shared memory / L1 cache 2518, the L2 cache, and memory are backup storage.

[0268] In at least one embodiment, combining data caching and shared memory functionality into a single memory block provides improved performance for both types of memory access. In at least one embodiment, the capacity is used by programs that do not use shared memory or is used as a cache; for example, if shared memory is configured to use half its capacity, texture and load / store operations can use the remaining capacity. According to at least one embodiment, integration within the shared memory / L1 cache 2518 enables the shared memory / L1 cache 2518 to be used as a high-throughput pipeline for streaming data, while providing high-bandwidth and low-latency access to frequently reused data. In at least one embodiment, a simpler configuration can be used compared to graphics processing when configured for general-purpose parallel computing. In at least one embodiment, a simpler programming model is created by bypassing fixed-function GPUs. In at least one embodiment, in a general-purpose parallel computing configuration, the work allocation unit directly allocates and distributes blocks of threads to the DPC. In at least one embodiment, threads within a block execute the same program, using unique thread IDs in computation to ensure each thread produces unique results, using SM 2500 to execute programs and perform computations, using shared memory / L1 cache 2518 for communication between programs, and using LSU 2514 to read and write global memory via shared memory / L1 cache 2518 and memory partitioning units. In at least one embodiment, when configured for general-purpose parallel computing, SM 2500 writes commands to scheduler unit 2504 that can be used to start new work on DPC. In at least one embodiment, SM 2500 includes one or more distributed shared memories (or distributed shared memories) that support direct SM-to-SM operations, such as loading, storing, and executing atomic operations across multiple SM shared memory blocks.

[0269] In at least one embodiment, the SM 2500 includes one or more asynchronous execution functions, each including a Tensor Memory Accelerator (TMA) unit capable of transferring data blocks between global memory and shared memory. In at least one embodiment, one or more processors use or access one or more TMAs to perform bidirectional copy operations, such as from global memory to shared memory and vice versa. In at least one embodiment, the SM 2500 includes one or more TMAs for asynchronous copying between thread blocks in a cluster. In at least one embodiment, the SM 2500 includes one or more asynchronous transaction barriers to perform atomic data movements and synchronization. In at least one embodiment, the SM 2500 includes a Tensor Core Transformer Engine, comprising software and one or more cores to accelerate transformer model training and inference. In at least one embodiment, transformers (one or more processor cores) executing one or more Tensor Core Transformer Engines manage and dynamically select FP8 and 16-bit computations by re-scaling and re-converting between FP8 and 16-bit in each layer of one or more neural networks.

[0270] In at least one embodiment, the PPU is included in or coupled to a desktop computer, laptop computer, tablet computer, server, supercomputer, smartphone (e.g., wireless, handheld device), PDA, digital camera, vehicle, head-mounted display, handheld electronic device, etc. In at least one embodiment, the PPU is implemented on a single semiconductor substrate. In at least one embodiment, the PPU is included in a system-on-a-chip (“SoC”) along with one or more other devices (e.g., additional PPUs, memory, RISC CPU, MMU, digital-to-analog converter (“DAC”), etc.).

[0271] In at least one embodiment, the PPU may be included on a graphics card that includes one or more storage devices. The graphics card may be configured to connect to a PCIe slot on a desktop computer motherboard. In at least one embodiment, the PPU may be an integrated GPU (“iGPU”) included in the motherboard's chipset.

[0272] In at least one embodiment, at least one component shown or described in the above figures is used to achieve the combination. Figures 1 to 6 One or more of the described technologies and / or functions are used to select the design frequency of the processing unit.

[0273] Software architecture for general-purpose computing

[0274] The following figures illustrate, but are not limited to, exemplary software constructions for implementing at least one embodiment.

[0275] Figure 26A software stack of a programming platform according to at least one embodiment is illustrated. In at least one embodiment, the programming platform is a platform for accelerating computational tasks by utilizing hardware on a computing system. In at least one embodiment, software developers can access the programming platform through libraries, compiler instructions, and / or extensions to programming languages. In at least one embodiment, the programming platform may be, but is not limited to, CUDA, Radeon Open Computing Platform (“ROCm”), OpenCL (OpenCL developed by Khronosgroup). TM ), SYCL or Intel One API.

[0276] In at least one embodiment, the software stack 2600 of the programming platform provides an execution environment for the application 2601. In at least one embodiment, the application 2601 may include any computer software capable of being launched on the software stack 2600. In at least one embodiment, the application 2601 may include, but is not limited to, artificial intelligence (“AI”) / machine learning (“ML”) applications, high-performance computing (“HPC”) applications, virtual desktop infrastructure (“VDI”) or data center workloads.

[0277] In at least one embodiment, application 2601 and software stack 2600 run on hardware 2607. In at least one embodiment, hardware 2607 may include one or more GPUs, CPUs, FPGAs, AI engines, and / or other types of computing devices supporting a programming platform. In at least one embodiment, such as using CUDA, software stack 2600 may be vendor-specific and compatible only with devices from a specific vendor. In at least one embodiment, such as using OpenCL, software stack 2600 may be used with devices from different vendors. In at least one embodiment, hardware 2607 includes a host connected to one or more devices that can be accessed via application programming interface (API) calls to perform computational tasks. In at least one embodiment, compared to the host within hardware 2607, which may include, but is not limited to, a CPU (but may also include computing devices) and its memory, devices within hardware 2607 may include, but are not limited to, GPUs, FPGAs, AI engines, or other computing devices (but may also include CPUs) and their memory.

[0278] In at least one embodiment, the software stack 2600 of the programming platform includes, but is not limited to, multiple libraries 2603, a runtime 2605, and a device kernel driver 2606. In at least one embodiment, each library 2603 may include data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, library 2603 may include, but is not limited to, pre-written code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and / or message templates. In at least one embodiment, library 2603 includes functions optimized for execution on one or more types of devices. In at least one embodiment, library 2603 may include, but is not limited to, functions for performing mathematical, deep learning, and / or other types of operations on the device. In at least one embodiment, library 2603 is associated with a corresponding API 2602, which may include one or more APIs that expose functions implemented in library 2603. In at least one embodiment, a processor (e.g., CPU, GPU) executes, calls, or otherwise uses one or more APIs to prioritize kernels. For example, a first kernel (e.g., a parent kernel) can boot a second kernel (e.g., a child kernel), and the processor can use the second kernel to boot an additional kernel (e.g., a grandchild kernel) independent of the first kernel. In at least one embodiment, the processor executes an API or calls an API from memory to support dynamic stream priorities (e.g., updating priorities when performing operations using streams). For example, when the processor executes the API, it allows a programmer to copy a stream priority from one stream to one or more other streams.

[0279] In at least one embodiment, the software stack 2600 includes an API to support dynamic stream prioritization (e.g., updating priority when performing an operation using the stream), which allows a programmer to set the priority of the stream at any time after the stream is created. In at least one embodiment, the software stack 2600 includes an API to support dynamic stream prioritization (e.g., updating priority when performing an operation using the stream), which allows a programmer to obtain the current priority of the stream, where priority is one of several attributes of the stream. In at least one embodiment, the software stack 2600 includes an API to support dynamic stream prioritization (e.g., updating priority when performing an operation using the stream), which allows a programmer to obtain the current priority of the stream as a single attribute. In at least one embodiment, the software stack 2600 includes an API to support dynamic stream prioritization (e.g., updating priority when the stream is used to perform an operation), which allows a programmer to launch a kernel to perform an operation on the stream at a set priority, which may be different from the stream priority. In at least one embodiment, the software stack 2600 includes an API to indicate whether an object (e.g., a thread synchronization object, such as a barrier) tracks whether all data movement operations of a set of threads running on the GPU have a specified state after a specified time period, wherein the specified state may be a state indicating that data has been moved and is ready for use, and is specified using an expected parity value as input to the API.

[0280] In at least one embodiment, the software stack 2600 includes one or more APIs for updating the kernel. In at least one embodiment, the processor executes APIs or calls APIs from memory to update existing APIs to support a context-independent kernel. This allows programmers to add kernel nodes to a graph without a graphics context so that the graphics context can be dynamically associated with the kernel at runtime. In at least one embodiment, the software stack 2600 includes one or more APIs to allow programmers to obtain kernel identifiers and graphics contexts as separate parameters from kernel nodes, enabling parameter retrieval from both the kernel and the context-independent kernel. In at least one embodiment, the software stack 2600 includes one or more APIs to use parallel processors (e.g., one or more graphics processing units) to initiate task graphs (e.g., task graphs) and execute one or more task graphs (e.g., including one or more programs).

[0281] In at least one embodiment, the software stack 2600 includes one or more APIs to associate one or more instructions with one or more memory sorting operations (e.g., fence or membar operations). In at least one embodiment, instructions are associated with one or more domains, such that memory sorting operations are executed in association with one or more specific domains without interfering with instructions in other domains. APIs indicate that a thread has arrived at (e.g., at a thread synchronization barrier) or has completed a work phase associated with an asynchronous data movement operation on the GPU. In at least one embodiment, the software stack 2600 includes one or more features to allow a programmer to manually indicate an expected transaction count when a thread completes a work phase; this transaction count is used to update an object that tracks whether all data movement operations for a set of threads have been completed.

[0282] In at least one embodiment, application 2601 is written as source code, which is compiled into executable code, as follows: Figures 31-33 This will be discussed in more detail. In at least one embodiment, the executable code of application 2601 may run at least partially on an execution environment provided by software stack 2600. In at least one embodiment, during the execution of application 2601, code that needs to run on the device (compared to the host) may be obtained. In this case, in at least one embodiment, runtime 2605 may be invoked to load and start the necessary code on the device. In at least one embodiment, runtime 2605 may include any technically feasible runtime system capable of supporting the execution of application 2601.

[0283] In at least one embodiment, runtime 2605 is implemented as one or more runtime libraries associated with a corresponding API (which is shown as API 2604). In at least one embodiment, one or more such runtime libraries may include, but are not limited to, functions for memory management, execution control, device management, error handling and / or synchronization, etc. In at least one embodiment, memory management functions may include, but are not limited to, functions for allocating, dealing with, and copying device memory, and for transferring data between host memory and device memory. In at least one embodiment, execution control functions may include, but are not limited to, functions for launching functions on the device (sometimes referred to as "kernels" when the function is a global function that can be called from the host), and functions for setting attribute values ​​in buffers maintained by the runtime library for a given function to be executed on the device.

[0284] In at least one embodiment, the runtime library and the corresponding API 2604 can be implemented in any technically feasible manner. In at least one embodiment, one (or any number of) APIs may expose a low-level set of functions for fine-grained control of the device, while another (or any number of) APIs may expose such a higher-level set of functions. In at least one embodiment, a high-level runtime API can be built on top of the low-level APIs. In at least one embodiment, one or more runtime APIs may be language-specific APIs layered on top of language-independent runtime APIs.

[0285] In at least one embodiment, one or more processors disclosed in the "processing system" may execute, access, or otherwise use the software stack 2600. For example, the APU 1300, CPU 1400, 16A-16B exemplary graphics processors, general-purpose graphics processing unit ("GPGPU") 1730, parallel processor 1800, processing cluster 1894, graphics multiprocessor 1834, graphics multiprocessor 1896, graphics processor 1900, processor 2000, processor 2100, parallel processing unit ("PPU") 2300, GPC 2400, and / or streaming multiprocessor ("SM") 2500 may execute, use, invoke, or otherwise implement (e.g., by accessing memory) one or more APIs contained in the software stack 2600.

[0286] In at least one embodiment, device kernel driver 2606 is configured to facilitate communication with the underlying device. In at least one embodiment, device kernel driver 2606 may provide APIs such as API 2604 and / or low-level functions upon which other software depends. In at least one embodiment, device kernel driver 2606 may be configured to compile intermediate representation (“IR”) code into binary code at runtime. In at least one embodiment, for CUDA, device kernel driver 2606 may compile non-hardware-specific parallel thread execution (“PTX”) IR code into binary code for a specific target device (cached compiled binary code), which is sometimes referred to as “final” code. In at least one embodiment, doing so allows the final code to run on the target device, which may not exist when the source code was initially compiled into PTX code. Alternatively, in at least one embodiment, the device source code may be compiled into binary code offline, without requiring device kernel driver 2606 to compile the IR code at runtime.

[0287] In at least one embodiment, at least one component shown or described in the above figures is used to achieve the combination. Figures 1 to 6 One or more of the described technologies and / or functions are used to select the design frequency of the processing unit.

[0288] Figure 27 The illustration shows an embodiment according to at least one of the embodiments. Figure 26 The software stack 2600 is a CUDA implementation. In at least one embodiment, the CUDA software stack 2700 on which an application 2701 can be launched includes a CUDA library 2703, a CUDA runtime 2705, a CUDA driver 2707, and a device kernel driver 2708. In at least one embodiment, the CUDA software stack 2700 executes on hardware 2709, which may include a CUDA-enabled GPU developed by NVIDIA Corporation of Santa Clara, California.

[0289] In at least one embodiment, application 2701, CUDA runtime 2705, and device kernel driver 2708 can respectively perform functions similar to those of application 2601, runtime 2605, and device kernel driver 2606, in combination with the above. Figure 26 The CUDA driver 2707 is described in at least one embodiment. In at least one embodiment, the CUDA driver API 2707 includes a library (libcuda.so) implementing the CUDA driver API 2706. In at least one embodiment, similar to the CUDA runtime API 2704 implemented by the CUDA runtime library (cudart), the CUDA driver API 2706 may expose, but is not limited to, functions for memory management, execution control, device management, error handling, synchronization, and / or graphics interoperability. In at least one embodiment, the CUDA driver API 2706 differs from the CUDA runtime API 2704 in that the CUDA runtime API 2704 simplifies device code management by providing implicit initialization, context (similar to processes) management, and module (similar to dynamically loaded libraries) management. In contrast to the high-level CUDA runtime API 2704, in at least one embodiment, the CUDA driver API 2706 is a low-level API that provides finer-grained control over the device, particularly regarding context and module loading. In at least one embodiment, the CUDA driver API 2706 may expose functions for context management that are not exposed by the CUDA runtime API 2704. In at least one embodiment, the CUDA driver API 2706 is also language-independent and supports, in addition to the CUDA runtime API 2704, OpenCL, for example. Furthermore, in at least one embodiment, development libraries, including the CUDA runtime 2705, can be considered separate from the driver components, including the user-mode CUDA driver 2707 and the kernel-mode device driver 2708 (sometimes also referred to as the "display" driver).

[0290] In at least one embodiment, CUDA library 2703 may include, but is not limited to, mathematical libraries, deep learning libraries, parallel algorithm libraries, and / or signal / image / video processing libraries, which parallel computing applications (e.g., application 2701) may utilize. In at least one embodiment, CUDA library 2703 may include mathematical libraries, such as the cuBLAS library, which is an implementation of basic linear algebra subroutines (“BLAS”) for performing linear algebra operations; the cuFFT library for computing the Fast Fourier Transform (“FFT”); and the cuRAND library for generating random numbers, etc. In at least one embodiment, CUDA library 2703 may include deep learning libraries, such as the cuDNN library for primitives of deep neural networks and the TensorRT platform for high-performance deep learning inference, etc.

[0291] In at least one embodiment, at least one component shown or described in the above figures is used to achieve the combination. Figures 1 to 6 One or more of the described technologies and / or functions are used to select the design frequency of the processing unit.

[0292] Figure 28 The illustration shows an embodiment according to at least one of the embodiments. Figure 26 The software stack 2600 is a ROCm implementation. In at least one embodiment, the ROCm software stack 2800 on which the application 2801 can be launched includes a language runtime 2803, a system runtime 2805, a thunk 2807, and a ROCm kernel driver 2808. In at least one embodiment, the ROCm software stack 2800 executes on hardware 2809, which may include a ROCm-enabled GPU developed by AMD Inc. of Santa Clara, California.

[0293] In at least one embodiment, application 2801 can perform the above-described combination. Figure 26 The discussed application 2601 has similar functionality. Additionally, in at least one embodiment, the language runtime 2803 and system runtime 2805 can perform functions combined with the above. Figure 26The runtime 2605 discussed has similar functionality. In at least one embodiment, the language runtime 2803 and the system runtime 2805 differ in that the system runtime 2805 is a language-independent runtime that implements the ROCr System Runtime API 2804 and utilizes the Heterogeneous System Architecture (“HSA”) runtime API. In at least one embodiment, the HSA runtime API is a thin-user mode API that exposes interfaces for accessing and interacting with AMD GPUs, including functions for memory management, kernel execution control dispatched by the architecture, error handling, system and agent information, and runtime initialization and shutdown, etc. In at least one embodiment, compared to the system runtime 2805, the language runtime 2803 is an implementation of a language-specific runtime API 2802 layered on top of the ROCr System Runtime API 2804. In at least one embodiment, the language runtime API may include, but is not limited to, the Portable Heterogeneous Computing Interface (“HIP”) language runtime API, the Heterogeneous Computing Compiler (“HCC”) language runtime API, or the OpenCL API, etc. In particular, the HIP language is an extension of the C++ programming language, a functionally similar version with CUDA mechanisms, and in at least one embodiment, the HIP language runtime API includes elements combined with the above. Figure 27 The functions discussed are similar to those in CUDA runtime API 2704, such as those used for memory management, execution control, device management, error handling, and synchronization.

[0294] In at least one embodiment, the thunk (ROCt) 2807 is an interface 2806 that can be used to interact with the underlying ROCm driver 2808. In at least one embodiment, the ROCm driver 2808 is a ROCk driver, which is a combination of an AMD GPU driver and an HSA core driver (amdkfd). In at least one embodiment, the AMD GPU driver is a device core driver for GPUs developed by AMD, which performs the above-described combination. Figure 26 The device kernel driver 2606 discussed has similar functionality. In at least one embodiment, the HSA kernel driver is a driver that allows different types of processors to share system resources more efficiently via hardware features.

[0295] In at least one embodiment, various libraries (not shown) may be included in the ROCm software stack 2800 above the language runtime 2803, and provide integration with the above. Figure 27 The discussed CUDA library 2703 has similar functionality. In at least one embodiment, various libraries may include, but are not limited to, mathematical, deep learning, and / or other libraries, such as the hipBLAS library which implements functions similar to CUDA cuBLAS, the rocFFT library which is similar to CUDA cuFFT for computing FFT, etc.

[0296] In at least one embodiment, at least one component shown or described in the above figures is used to achieve the combination. Figures 1 to 6 One or more of the described technologies and / or functions are used to select the design frequency of the processing unit.

[0297] Figure 29 The illustration shows an embodiment according to at least one of the embodiments. Figure 26 The software stack 2600 is an OpenCL implementation. In at least one embodiment, the OpenCL software stack 2900 on which the application 2901 can be launched includes an OpenCL framework 2910, an OpenCL runtime 2906, and a driver 2907. In at least one embodiment, the OpenCL software stack 2900 executes on non-vendor-specific hardware 2709. In at least one embodiment, because devices developed by different vendors support OpenCL, specific OpenCL drivers may be required for interoperability with hardware from such vendors.

[0298] In at least one embodiment, the application 2901, the OpenCL runtime 2906, the device kernel driver 2907, and the hardware 2908 can respectively execute the above-described combination. Figure 26 The application 2601, runtime 2605, device kernel driver 2606, and hardware 2607 discussed have similar functionality. In at least one embodiment, application 2901 also includes an OpenCL kernel 2902 with code that will execute on the device.

[0299] In at least one embodiment, OpenCL defines a "platform" that allows a host to control devices connected to that host. In at least one embodiment, the OpenCL framework provides a platform-level API and a runtime API, shown as Platform API 2903 and Runtime API 2905. In at least one embodiment, Runtime API 2905 uses a context to manage the execution of the kernel on the device. In at least one embodiment, each identified device can be associated with a respective context, which Runtime API 2905 can use to manage the device's command queue, program objects and kernel objects, shared memory objects, etc. In at least one embodiment, Platform API 2903 discloses functions that allow the device context to select and initialize devices, submit work to devices via command queues, and enable data transfers to and from devices, etc. Additionally, in at least one embodiment, the OpenCL framework provides various built-in functions (not shown), including mathematical functions, relational functions, and image processing functions, etc.

[0300] In at least one embodiment, compiler 2904 is also included in the OpenCL framework 2910. In at least one embodiment, the source code can be compiled offline before executing the application or online during application execution. Unlike CUDA and ROCm, the OpenCL application in at least one embodiment can be compiled online by compiler 2904, which is included to represent any number of compilers that can be used to compile source code and / or IR code (e.g., Standard Portable Intermediate Representation (“SPIR-V”) code) into binary code. Alternatively, in at least one embodiment, the OpenCL application can be compiled offline before executing such an application.

[0301] In at least one embodiment, at least one component shown or described in the above figures is used to achieve the combination. Figures 1 to 6 One or more of the described technologies and / or functions are used to select the design frequency of the processing unit.

[0302] Figure 30 Software supported by a programming platform according to at least one embodiment is illustrated. In at least one embodiment, the programming platform 3004 is configured to support various programming models 3003, middleware and / or libraries 3002, and frameworks 3001 that an application 3000 may depend on. In at least one embodiment, the application 3000 may be an AI / ML application implemented using, for example, a deep learning framework (e.g., MXNet, PyTorch, or TensorFlow), which may depend on libraries such as cuDNN, the NVIDIA Collective Communications Library (“NCCL”), and / or the NVIDIA Developer Data Loading Library (“DALI”) CUDA library to provide accelerated computation on the underlying hardware.

[0303] In at least one embodiment, the programming platform 3004 can be a combination of the above-described components. Figure 27 , Figure 28 and Figure 29 One of the described CUDA, ROCm, or OpenCL platforms. In at least one embodiment, the programming platform 3004 supports multiple programming models 3003, which are abstractions of the underlying computing system that allow for the expression of algorithms and data structures. In at least one embodiment, the programming model 3003 may expose features of the underlying hardware to improve performance. In at least one embodiment, the programming model 3003 may include, but is not limited to, CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism (“C++AMP”), Open Multiprocessing (“OpenMP”), Open Accelerator (“OpenACC”), and / or Vulcan Compute.

[0304] In at least one embodiment, the library and / or middleware 3002 provides an abstract implementation of the programming model 3004. In at least one embodiment, such a library includes data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, in addition to those available from the programming platform 3004, such middleware also includes software that provides services to applications. In at least one embodiment, the library and / or middleware 3002 may include, but is not limited to, cuBLAS, cuFFT, cuRAND, and other CUDA libraries, or rocBLAS, rocFFT, rocRAND, and other ROCm libraries. Additionally, in at least one embodiment, the library and / or middleware 3002 may include NCCL and ROCm communication collection library (“RCCL”) libraries, which provide communication routines for GPUs, the MIOpen library for deep learning acceleration, and / or intrinsic libraries for linear algebra, matrix and vector operations, geometric transformations, numerical solvers, and related algorithms.

[0305] In at least one embodiment, the application framework 3001 depends on libraries and / or middleware 3002. In at least one embodiment, each application framework 3001 is a software framework for implementing a standard structure of application software. Returning to the AI / ML example discussed above, in at least one embodiment, AI / ML applications can be implemented using frameworks such as Caffe, Caffe2, TensorFlow, Keras, PyTorch, or the MxNet deep learning framework.

[0306] In at least one embodiment, at least one component shown or described in the above figures is used to achieve the combination. Figures 1 to 6 One or more of the described technologies and / or functions are used to select the design frequency of the processing unit.

[0307] Figure 31 Compilation code according to at least one embodiment is shown to be used in Figure 26-29 The program is executed on one of the programming platforms. In at least one embodiment, compiler 3101 receives source code 3100, which includes both host code and device code. In at least one embodiment, compiler 3101 is configured to translate source code 3100 into host executable code 3102 for execution on a host and device executable code 3103 for execution on a device. In at least one embodiment, source code 3100 may be compiled offline before executing the application or compiled online during application execution. In at least one embodiment, compiler 3101 includes or may access one or more libraries to identify a series of API calls to execute a single fused API, wherein the single fused API is a combination API of two or more APIs.

[0308] In at least one embodiment, source code 3100 may include code in any programming language supported by compiler 3101, such as C++, C, Fortran, etc. In at least one embodiment, source code 3100 may be included in a single-source file, which has a mixture of host code and device code, and indicates the location of the device code therein. In at least one embodiment, the single-source file may be a .cu file including CUDA code or a .hip.cpp file including HIP code. Alternatively, in at least one embodiment, source code 3100 may include multiple source code files instead of a single source file, in which the host code and device code are separate.

[0309] In at least one embodiment, compiler 3101 is configured to compile source code 3100 into host executable code 3102 for execution on a host and device executable code 3103 for execution on a device. In at least one embodiment, compiler 3101 performs operations including resolving source code 3100 into an abstract system tree (AST), performing optimizations, and generating executable code. In at least one embodiment where source code 3100 comprises a single source file, compiler 3101 may separate device code and host code within this single source file, compile the device code and host code into device executable code 3103 and host executable code 3102 respectively, and link the device executable code 3103 and host executable code 3102 together in a single file, as described below. Figure 32 To be discussed in more detail.

[0310] In at least one embodiment, the host executable code 3102 and the device executable code 3103 can be in any suitable format, such as binary code and / or IR code. In the case of CUDA, in at least one embodiment, the host executable code 3102 may include native object code, while the device executable code 3103 may include code in a PTX intermediate representation. In at least one embodiment, in the case of ROCm, both the host executable code 3102 and the device executable code 3103 can include target binary code.

[0311] In at least one embodiment, at least one component shown or described in the above figures is used to achieve the combination. Figures 1 to 6 One or more of the described technologies and / or functions are used to select the design frequency of the processing unit.

[0312] Figure 32 It is compiled code according to at least one embodiment to be used in Figure 26-29A more detailed illustration is provided on one of the programming platforms. In at least one embodiment, compiler 3201 is configured to receive source code 3200, compile source code 3200, and output executable file 3210. In at least one embodiment, source code 3200 is a single source file, such as a .cu file, a .hip.cpp file, or a file of other formats, which includes both host code and device code. In at least one embodiment, compiler 3201 may be, but is not limited to, an NVIDIA CUDA compiler (“NVCC”) for compiling CUDA code in .cu files, or an HCC compiler for compiling HIP code in .hip.cpp files.

[0313] In at least one embodiment, compiler 3201 includes compiler front-end 3202, host compiler 3205, device compiler 3206, and linker 3209. In at least one embodiment, compiler front-end 3202 is configured to separate device code 3204 from host code 3203 in source code 3200. In at least one embodiment, device code 3204 is compiled by device compiler 3206 into device executable code 3208, which, as described, may include binary code or IR code. In at least one embodiment, host code 3203 is compiled separately by host compiler 3205 into host executable code 3207. In at least one embodiment, for NVCC, host compiler 3205 may be, but is not limited to, a general-purpose C / C++ compiler that outputs native object code, while device compiler 3206 may be, but is not limited to, a low-level virtual machine (“LLVM”) based compiler that forks the LLVM compiler infrastructure and outputs PTX code or binary code. In at least one embodiment, for HCC, both the host compiler 3205 and the device compiler 3206 can be, but are not limited to, LLVM-based compilers that output target binary code.

[0314] In at least one embodiment, after compiling source code 3200 into host executable code 3207 and device executable code 3208, linker 3209 links the host and device executable codes 3207 and 3208 together in executable file 3210. In at least one embodiment, the native object code of the host and PTX or the binary code of the device can be linked together in an executable and linkable format (“ELF”) file, which is a container format for storing object code.

[0315] In at least one embodiment, at least one component shown or described in the above figures is used to achieve the combination. Figures 1 to 6 One or more of the described technologies and / or functions are used to select the design frequency of the processing unit.

[0316] Figure 33 The illustration shows the transformation of source code prior to compilation, according to at least one embodiment. In at least one embodiment, source code 3300 is passed via a transformation tool 3301, which transforms source code 3300 into transformed source code 3302. In at least one embodiment, a compiler 3303 is used to compile the transformed source code 3302 into host executable code 3304 and device executable code 3305, a process similar to that of compiler 3101 compiling source code 3100 into host executable code 3102 and device executable code 3103, as described above. Figure 31 The subject of discussion.

[0317] In at least one embodiment, the transformation performed by the transformation tool 3301 is used to port source code 3300 to perform in an environment different from where it was originally intended to run. In at least one embodiment, the transformation tool 3301 may include, but is not limited to, a HIP converter for “hipify” CUDA code for a CUDA platform into HIP code that can be compiled and executed on the ROCm platform. In at least one embodiment, the transformation of source code 3300 may include: parsing source code 3300 and converting calls to APIs provided by one programming model (e.g., CUDA) into corresponding calls to APIs provided by another programming model (e.g., HIP), as combined below. Figure 34A and Figure 35 This will be discussed in more detail. Returning to the example of porting CUDA code, in at least one embodiment, calls to the CUDA runtime API, CUDA driver API, and / or CUDA libraries can be translated into corresponding HIP API calls. In at least one embodiment, the automatic translation performed by the translation tool 3301 may sometimes be incomplete, requiring additional manual intervention to fully port the source code 3300.

[0318] In at least one embodiment, at least one component shown or described in the above figures is used to achieve the combination. Figures 1 to 6 One or more of the described technologies and / or functions are used to select the design frequency of the processing unit.

[0319] Configure GPUs for general-purpose computing

[0320] The following figures illustrate, but are not limited to, exemplary architectures for compiling and executing computational source code according to at least one embodiment.

[0321] Figure 34AA system 3400 is shown, configured to compile and execute CUDA source code 3410 using different types of processing units according to at least one embodiment. In at least one embodiment, system 3400 includes, but is not limited to, CUDA source code 3410, CUDA compiler 3450, host executable code 3470(1), host executable code 3470(2), CUDA device executable code 3484, CPU 3490, CUDA-enabled GPU 3494, GPU 3492, CUDA to HIP conversion tool 3420, HIP source code 3430, HIP compiler driver 3440, HCC 3460, and HCC device executable code 3482.

[0322] In at least one embodiment, CUDA source code 3410 is a collection of human-readable code in the CUDA programming language. In at least one embodiment, CUDA code is human-readable code in the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension of the C++ programming language, including but not limited to defining device code and mechanisms for distinguishing between device code and host code. In at least one embodiment, device code is source code that can be executed in parallel on a device after compilation. In at least one embodiment, the device may be a processor optimized for parallel instruction processing, such as a CUDA-enabled GPU 3490, GPU 3492, or another GPGPU. In at least one embodiment, host code is source code that can be executed on a host machine after compilation. In at least one embodiment, the host machine is a processor optimized for sequential instruction processing, such as CPU 3490.

[0323] In at least one embodiment, CUDA source code 3410 includes, but is not limited to, any number (including zero) of global functions 3412, any number (including zero) of device functions 3414, any number (including zero) of host functions 3416, and any number (including zero) of host / device functions 3418. In at least one embodiment, the global functions 3412, device functions 3414, host functions 3416, and host / device functions 3418 can be mixed in CUDA source code 3410. In at least one embodiment, each global function 3412 is executable on a device and is callable from a host. Therefore, in at least one embodiment, one or more of the global functions 3412 can serve as entry points for a device. In at least one embodiment, each global function 3412 is a kernel. In at least one embodiment, and in a technique called dynamic parallelism, one or more global functions 3412 define a kernel that is executable on a device and is callable from such a device. In at least one embodiment, the kernel is executed in parallel N times (where N is any positive integer) by N different threads on the device during execution.

[0324] In at least one embodiment, each device function 3414 executes on a device and can only be called from such a device. In at least one embodiment, each host function 3416 executes on a host and can only be called from such a host. In at least one embodiment, each host / device function 3416 defines both a host version of a function that is executable on a host and can only be called from such a host, and a device version of a function that is executable on a device and can only be called from such a device.

[0325] In at least one embodiment, CUDA source code 3410 may also include, but is not limited to, any number of calls to any number of functions defined by CUDA runtime API 3402. In at least one embodiment, CUDA runtime API 3402 may include, but is not limited to, any number of functions executed on the host for allocating and dealing device memory, transferring data between host memory and device memory, managing a system with multiple devices, etc. In at least one embodiment, CUDA source code 3410 may also include, but is not limited to, any number of calls to any number of functions specified in any number of other CUDA APIs. In at least one embodiment, a CUDA API may be any API designed to be used by CUDA code. In at least one embodiment, a CUDA API includes, but is not limited to, CUDA runtime API 3402, CUDA driver APIs, APIs for any number of CUDA libraries, etc. In at least one embodiment, and relative to CUDA runtime API 3402, the CUDA driver API is a lower-level API but can provide finer-grained control over devices. In at least one embodiment, examples of CUDA libraries include, but are not limited to, cuBLAS, cuFFT, cURAND, cuDNN, etc.

[0326] In at least one embodiment, CUDA compiler 3450 compiles input CUDA code (e.g., CUDA source code 3410) to generate host executable code 3470(1) and CUDA device executable code 3484. In at least one embodiment, CUDA compiler 3450 is an NVCC. In at least one embodiment, host executable code 3470(1) is a compiled version of host code included in input source code executable on CPU 3490. In at least one embodiment, CPU 3490 can be any processor optimized for sequential instruction processing.

[0327] In at least one embodiment, CUDA device executable code 3484 is a compiled version of device code included in input source code executable on a CUDA-enabled GPU 3494. In at least one embodiment, CUDA device executable code 3484 includes, but is not limited to, binary code. In at least one embodiment, CUDA device executable code 3484 includes, but is not limited to, IR code, such as PTX code, which is further compiled at runtime by a device driver into binary code for a specific target device (e.g., a CUDA-enabled GPU 3494). In at least one embodiment, the CUDA-enabled GPU 3494 can be any processor optimized for parallel instruction processing and supporting CUDA. In at least one embodiment, the CUDA-enabled GPU 3494 was developed by NVIDIA Corporation of Santa Clara, California.

[0328] In at least one embodiment, the CUDA-to-HIP conversion tool 3420 is configured to convert CUDA source code 3410 into functionally similar HIP source code 3430. In at least one embodiment, the HIP source code 3430 is a collection of human-readable code in a HIP programming language. In at least one embodiment, the HIP code is human-readable code in a HIP programming language. In at least one embodiment, the HIP programming language is an extension of the C++ programming language, including but not limited to a functionally similar version of the CUDA mechanism, used to define device code and distinguish between device code and host code. In at least one embodiment, the HIP programming language may include a subset of the functionality of the CUDA programming language. In at least one embodiment, for example, the HIP programming language includes, but is not limited to, a mechanism for defining global functions 3412; however, such a HIP programming language may lack support for dynamic parallelism, therefore, the global functions 3412 defined in the HIP code can only be called from the host.

[0329] In at least one embodiment, the HIP source code 3430 includes, but is not limited to, any number (including zero) of global functions 3412, any number (including zero) of device functions 3414, any number (including zero) of host functions 3416, and any number (including zero) of host / device functions 3418. In at least one embodiment, the HIP source code 3430 may also include any number of calls to any number of functions specified in the HIP runtime API 3432. In one embodiment, the HIP runtime API 3432 includes, but is not limited to, functionally similar versions of a subset of functions included in the CUDA runtime API 3402. In at least one embodiment, the HIP source code 3430 may also include any number of calls to any number of functions specified in any number of other HIP APIs. In at least one embodiment, the HIP API may be any API designed for use by HIP code and / or ROCm. In at least one embodiment, the HIP API includes, but is not limited to, the HIP runtime API 3432, the HIP driver API, APIs for any number of HIP libraries, APIs for any number of ROCm libraries, etc.

[0330] In at least one embodiment, the CUDA-to-HIP conversion tool 3420 converts each kernel call in the CUDA code from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the CUDA code into any number of other functionally similar HIP calls. In at least one embodiment, a CUDA call is a call to a function specified in the CUDA API, and a HIP call is a call to a function specified in the HIP API. In at least one embodiment, the CUDA-to-HIP conversion tool 3420 converts any number of calls to functions specified in the CUDA runtime API 3402 into any number of calls to functions specified in the HIP runtime API 3432.

[0331] In at least one embodiment, the CUDA to HIP conversion tool 3420 is a tool called hipify-perl that performs a text-based conversion process. In at least one embodiment, the CUDA to HIP conversion tool 3420 is a tool called hipify-clang that, compared to hipify-perl, performs a more complex and robust conversion process involving parsing the CUDA code using clang (a compiler front-end) and then converting the resulting symbols. In at least one embodiment, in addition to the modifications performed by the CUDA to HIP conversion tool 3420, correctly converting the CUDA code into HIP code may require further modifications (e.g., manual editing).

[0332] In at least one embodiment, the HIP compiler driver 3440 is the front end that determines the target device 3446 and then configures a compiler compatible with the target device 3446 to compile the HIP source code 3430. In at least one embodiment, the target device 3446 is a processor optimized for parallel instruction processing. In at least one embodiment, the HIP compiler driver 3440 can determine the target device 3446 in any technically feasible manner.

[0333] In at least one embodiment, if the target device 3446 is CUDA compatible (e.g., a CUDA-enabled GPU 3494), the HIP compiler driver 3440 generates HIP / NVCC compilation commands 3442. In at least one embodiment and in conjunction with... Figure 34B In more detail, the HIP / NVCC compilation command 3442 configures the CUDA compiler 3450 to compile the HIP source code 3430 using, but not limited to, a HIP-to-CUDA translation header and a CUDA runtime library. In at least one embodiment and in response to the HIP / NVCC compilation command 3442, the CUDA compiler 3450 generates host executable code 3470(1) and CUDA device executable code 3484.

[0334] In at least one embodiment, if the target device 3446 is incompatible with CUDA, the HIP compiler driver 3440 generates HIP / HCC compilation commands 3444. In at least one embodiment and as in conjunction with... Figure 34C In more detail, HIP / HCC compilation command 3444 configures HCC 3460 to compile HIP source code 3430 using the HCC header and HIP / HCC runtime library. In at least one embodiment and in response to HIP / HCC compilation command 3444, HCC 3460 generates host executable code 3470(2) and HCC device executable code 3482. In at least one embodiment, HCC device executable code 3482 is a compiled version of device code executable on GPU 3492 contained in HIP source code 3430. In at least one embodiment, GPU 3492 may be any processor optimized for parallel instruction processing, CUDA incompatible, and HCC compatible. In at least one embodiment, GPU 3492 was developed by AMD Inc. of Santa Clara, California. In at least one embodiment, GPU 3492 is a GPU 3492 without CUDA enabled.

[0335] For illustrative purposes only, Figure 34AThe document describes three different processes that, in at least one embodiment, can be implemented to compile CUDA source code 3410 for execution on CPU 3490 and various devices. In at least one embodiment, a direct CUDA process compiles CUDA source code 3410 for execution on CPU 3490 and a CUDA-enabled GPU 3494 without converting CUDA source code 3410 to HIP source code 3430. In at least one embodiment, an indirect CUDA process converts CUDA source code 3410 to HIP source code 3430 and then compiles the HIP source code 3430 for execution on CPU 3490 and a CUDA-enabled GPU 3494. In at least one embodiment, a CUDA / HCC process converts CUDA source code 3410 to HIP source code 3430 and then compiles the HIP source code 3430 for execution on CPU 3490 and GPU 3492.

[0336] The direct CUDA flow, which can be implemented in at least one embodiment, can be depicted by dashed lines and a series of bubble comments A1-A3. In at least one embodiment, and as indicated by bubble comment A1, CUDA compiler 3450 receives CUDA source code 3410 and CUDA compilation command 3448 that configures CUDA compiler 3450 to compile CUDA source code 3410. In at least one embodiment, the CUDA source code 3410 used in the direct CUDA flow is written in a CUDA programming language based on a programming language other than C++ (e.g., C, Fortran, Python, Java, etc.). In at least one embodiment, and in response to CUDA compilation command 3448, CUDA compiler 3450 generates host executable code 3470(1) and CUDA device executable code 3484 (indicated by bubble comment A2). In at least one embodiment, and as indicated by bubble comment A3, host executable code 3470(1) and CUDA device executable code 3484 can be executed on CPU 3490 and CUDA-enabled GPU 3494, respectively. In at least one embodiment, the CUDA device executable code 3484 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3484 includes, but is not limited to, PTX code, and is further compiled at runtime into binary code for a specific target device.

[0337] The indirect CUDA process, which can be implemented in at least one embodiment, can be described by dashed lines and a series of bubble comments B1-B6. In at least one embodiment, and as shown in bubble comment B1, the CUDA-to-HIP conversion tool 3420 receives CUDA source code 3410. In at least one embodiment, and as shown in bubble comment B2, the CUDA-to-HIP conversion tool 3420 converts the CUDA source code 3410 into HIP source code 3430. In at least one embodiment, and as shown in bubble comment B3, the HIP compiler driver 3440 receives the HIP source code 3430 and determines whether the target device 3446 has CUDA enabled.

[0338] In at least one embodiment and as shown in bubble note B4, the HIP compiler driver 3440 generates HIP / NVCC compilation commands 3442 and sends both the HIP / NVCC compilation commands 3442 and the HIP source code 3430 to the CUDA compiler 3450. In at least one embodiment and as shown in combination Figure 34B In more detail, HIP / NVCC compilation command 3442 configures CUDA compiler 3450 to compile HIP source code 3430 using, but not limited to, a HIP-to-CUDA translation header and a CUDA runtime library. In at least one embodiment and in response to HIP / NVCC compilation command 3442, CUDA compiler 3450 generates host executable code 3470(1) and CUDA device executable code 3484 (indicated by bubble comment B5). In at least one embodiment and as shown by bubble comment B6, host executable code 3470(1) and CUDA device executable code 3484 can be executed on CPU 3490 and CUDA-enabled GPU 3494, respectively. In at least one embodiment, CUDA device executable code 3484 includes, but is not limited to, binary code. In at least one embodiment, CUDA device executable code 3484 includes, but is not limited to, PTX code, and is further compiled at runtime into binary code for a specific target device.

[0339] The CUDA / HCC process, which can be implemented in at least one embodiment, can be described by solid lines and a series of bubble comments C1-C6. In at least one embodiment, and as shown in bubble comment C1, the CUDA to HIP conversion tool 3420 receives CUDA source code 3410. In at least one embodiment, and as shown in bubble comment C2, the CUDA to HIP conversion tool 3420 converts the CUDA source code 3410 into HIP source code 3430. In at least one embodiment, and as shown in bubble comment C3, the HIP compiler driver 3440 receives the HIP source code 3430 and determines that the target device 3446 does not have CUDA enabled.

[0340] In at least one embodiment, the HIP compiler driver 3440 generates HIP / HCC compilation commands 3444, and sends both the HIP / HCC compilation commands 3444 and the HIP source code 3430 to the HCC 3460 (indicated by bubble comment C4). In at least one embodiment and as in combination Figure 34C In more detail, HIP / HCC compilation command 3444 configures HCC 3460 to compile HIP source code 3430 using, but not limited to, the HCC header and HIP / HCC runtime library. In at least one embodiment and in response to HIP / HCC compilation command 3444, HCC 3460 generates host executable code 3470(2) and HCC device executable code 3482 (indicated by bubble comment C5). In at least one embodiment and as shown by bubble comment C6, host executable code 3470(2) and HCC device executable code 3482 can be executed on CPU 3490 and GPU 3492, respectively.

[0341] In at least one embodiment, after converting CUDA source code 3410 to HIP source code 3430, the HIP compiler driver 3440 can then be used to generate executable code for a CUDA-enabled GPU 3494 or GPU 3492 without re-executing CUDA to the HIP conversion tool 3420. In at least one embodiment, the CUDA to HIP conversion tool 3420 converts CUDA source code 3410 to HIP source code 3430 and then stores it in memory. In at least one embodiment, the HIP compiler driver 3440 then configures HCC 3460 to generate host executable code 3470(2) and HCC device executable code 3482 based on the HIP source code 3430. In at least one embodiment, the HIP compiler driver 3440 then configures CUDA compiler 3450 to generate host executable code 3470(1) and CUDA device executable code 3484 based on the stored HIP source code 3430.

[0342] Figure 34B The diagram illustrates a configuration, according to at least one embodiment, to compile and execute using a CPU 3490 and a CUDA-enabled GPU 3494. Figure 34A The system 3404 includes, but is not limited to, CUDA source code 3410, CUDA to HIP conversion tool 3420, HIP source code 3430, HIP compiler driver 3440, CUDA compiler 3450, host executable code 3470(1), CUDA device executable code 3484, CPU 3490 and CUDA-enabled GPU 3494.

[0343] In at least one embodiment and as previously mentioned herein Figure 34A As described, the CUDA source code 3410 includes, but is not limited to, any number (including zero) of global functions 3412, any number (including zero) of device functions 3414, any number (including zero) of host functions 3416, and any number (including zero) of host / device functions 3418. In at least one embodiment, the CUDA source code 3410 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs.

[0344] In at least one embodiment, the CUDA to HIP conversion tool 3420 converts CUDA source code 3410 into HIP source code 3430. In at least one embodiment, the CUDA to HIP conversion tool 3420 converts each kernel call in the CUDA source code 3410 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the CUDA source code 3410 into any number of other functionally similar HIP calls.

[0345] In at least one embodiment, the HIP compiler driver 3440 determines that the target device 3446 is CUDA enabled and generates a HIP / NVCC compilation command 3442. In at least one embodiment, the HIP compiler driver 3440 then configures the CUDA compiler 3450 via the HIP / NVCC compilation command 3442 to compile the HIP source code 3430. In at least one embodiment, as part of configuring the CUDA compiler 3450, the HIP compiler driver 3440 provides access to a HIP-to-CUDA translation header 3452. In at least one embodiment, the HIP-to-CUDA translation header 3452 translates an arbitrary number of mechanisms (e.g., functions) specified in an arbitrary number of HIP APIs into an arbitrary number of mechanisms specified in an arbitrary number of CUDA APIs. In at least one embodiment, the CUDA compiler 3450 uses the HIP-to-CUDA translation header 3452 in conjunction with a CUDA runtime library 3454 corresponding to the CUDA runtime API 3402 to generate host executable code 3470(1) and CUDA device executable code 3484. In at least one embodiment, host executable code 3470(1) and CUDA device executable code 3484 can then be executed on CPU 3490 and CUDA-enabled GPU 3494, respectively. In at least one embodiment, CUDA device executable code 3484 includes, but is not limited to, binary code. In at least one embodiment, CUDA device executable code 3484 includes, but is not limited to, PTX code, and is further compiled at runtime into binary code for a specific target device.

[0346] Figure 34C A system 3406 according to at least one embodiment is shown, the system 3406 being configured to compile and execute using a CPU 3490 and a GPU 3492 with CUDA disabled. Figure 34A The CUDA source code 3410. In at least one embodiment, the system 3406 includes, but is not limited to, the CUDA source code 3410, the CUDA to HIP conversion tool 3420, the HIP source code 3430, the HIP compiler driver 3440, the HCC 3460, the host executable code 3470(2), the HCC device executable code 3482, the CPU 3490, and the GPU 3492.

[0347] In at least one embodiment, and as previously mentioned herein Figure 34AAs described, the CUDA source code 3410 includes, but is not limited to, any number (including zero) of global functions 3412, any number (including zero) of device functions 3414, any number (including zero) of host functions 3416, and any number (including zero) of host / device functions 3418. In at least one embodiment, the CUDA source code 3410 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs.

[0348] In at least one embodiment, the CUDA to HIP conversion tool 3420 converts CUDA source code 3410 into HIP source code 3430. In at least one embodiment, the CUDA to HIP conversion tool 3420 converts each kernel call in the CUDA source code 3410 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the source code 3410 into any number of other functionally similar HIP calls.

[0349] In at least one embodiment, the HIP compiler driver 3440 then determines that the target device 3446 is not CUDA enabled and generates a HIP / HCC compilation command 3444. In at least one embodiment, the HIP compiler driver 3440 then configures the HCC 3460 to execute the HIP / HCC compilation command 3444, thereby compiling the HIP source code 3430. In at least one embodiment, the HIP / HCC compilation command 3444 configures the HCC 3460 to use, but not limited to, the HIP / HCC runtime library 3458 and the HCC header 3456 to generate host executable code 3470(2) and HCC device executable code 3482. In at least one embodiment, the HIP / HCC runtime library 3458 corresponds to the HIP runtime API 3432. In at least one embodiment, the HCC header 3456 includes, but is not limited to, any number and type of interoperability mechanisms for HIP and HCC. In at least one embodiment, host executable code 3470(2) and HCC device executable code 3482 can be executed on CPU 3490 and GPU 3492, respectively.

[0350] In at least one embodiment, at least one component shown or described in the above figures is used to achieve the combination. Figures 1 to 6 One or more of the described technologies and / or functions are used to select the design frequency of the processing unit.

[0351] Figure 35 The diagram illustrates a method according to at least one embodiment. Figure 34CAn exemplary kernel is converted by the CUDA to HIP conversion tool 3420. In at least one embodiment, the CUDA source code 3410 divides the overall problem that a given kernel is designed to solve into relatively coarse subproblems that can be solved independently using thread blocks. In at least one embodiment, each thread block includes, but is not limited to, any number of threads. In at least one embodiment, each subproblem is divided into relatively small pieces that can be solved in parallel by the threads within the thread block. In at least one embodiment, threads within a thread block can cooperate by sharing data through shared memory and by coordinating memory accesses through synchronized execution.

[0352] In at least one embodiment, CUDA source code 3410 organizes thread blocks associated with a given kernel into a one-dimensional, two-dimensional, or three-dimensional grid of thread blocks. In at least one embodiment, each thread block includes, but is not limited to, any number of threads, and the grid includes, but is not limited to, any number of thread blocks.

[0353] In at least one embodiment, the kernel is a function in the device code defined using the "__global__" declaration specifier. In at least one embodiment, CUDA kernel startup syntax 3510 is used to specify the size of the mesh for executing the kernel for a given kernel call and the associated flow. In at least one embodiment, CUDA kernel startup syntax 3510 is specified as "KernelName <<<GridSize,BlockSize,SharedMemorySize,Stream> >>(KernelArguments);". In at least one embodiment, the execution configuration syntax is a "<<<...>>>" construct, which is inserted between the kernel name ("KernelName") and the bracketed list of kernel parameters ("KernelArguments"). In at least one embodiment, the CUDA kernel boot syntax 3510 includes, but is not limited to, the CUDA boot function syntax instead of the execution configuration syntax.

[0354] In at least one embodiment, "GridSize" is of type dim3 and specifies the size and dimensions of the grid. In at least one embodiment, type dim3 is a CUDA-defined structure, which includes, but is not limited to, unsigned integers x, y, and z. In at least one embodiment, if z is not specified, z defaults to 1. In at least one embodiment, if y is not specified, y defaults to 1. In at least one embodiment, the number of thread blocks in the grid is equal to the product of GridSize.x, GridSize.y, and GridSize.z. In at least one embodiment, "BlockSize" is of type dim3 and specifies the size and dimensions of each thread block. In at least one embodiment, the number of threads per thread block is equal to the product of BlockSize.x, BlockSize.y, and BlockSize.z. In at least one embodiment, each thread executing the kernel has a unique thread ID, which can be accessed within the kernel via a built-in variable (e.g., "threadIdx").

[0355] In at least one embodiment, regarding CUDA kernel startup syntax 3510, "SharedMemorySize" is an optional parameter that specifies the number of bytes dynamically allocated for each thread block in shared memory for a given kernel call, excluding statically allocated memory. In at least one embodiment and regarding CUDA kernel startup syntax 3510, SharedMemorySize defaults to zero. In at least one embodiment and regarding CUDA kernel startup syntax 3510, "stream" is an optional parameter that specifies an associated stream and defaults to zero to specify a default stream. In at least one embodiment, a stream is a sequence of commands executed sequentially (which may be issued by different host threads). In at least one embodiment, different streams may execute commands out of order or simultaneously relative to each other.

[0356] In at least one embodiment, CUDA source code 3410 includes, but is not limited to, kernel definitions and a main function for the exemplary kernel "MatAdd". In at least one embodiment, the main function is host code executed on the host and includes, but is not limited to, kernel calls that cause the kernel MatAdd to execute on the device. In at least one embodiment, as shown, the kernel MatAdd adds two matrices A and B of size NxN, where N is a positive integer, and stores the result in matrix C. In at least one embodiment, the main function defines the threadsPerBlock variable as 16x16 and the numBlocks variable as N / 16xN / 16. In at least one embodiment, the main function then specifies the kernel call "MatAdd<<<numBlocks,threadsPerBlock> >>(A, B, C);”. In at least one embodiment, and in accordance with CUDA kernel startup syntax 3510, a grid of thread blocks of size N / 16 × N / 16 is used to execute the kernel MatAdd, where each thread block is 16 × 16. In at least one embodiment, each thread block includes 256 threads, creating a grid with enough blocks to allow one thread per matrix element, and each thread in the grid executes the kernel MatAdd to perform a pairwise addition.

[0357] In at least one embodiment, while converting CUDA source code 3410 into HIP source code 3430, the CUDA-to-HIP conversion tool 3420 converts each kernel call in the CUDA source code 3410 from CUDA kernel startup syntax 3510 into HIP kernel startup syntax 3520, and converts any number of other CUDA calls in the source code 3410 into any number of other functionally similar HIP calls. In at least one embodiment, the HIP kernel startup syntax 3520 is specified as “hipLaunchKernelGGL(KernelName,GridSize,BlockSize,SharedMemorySize,Stream,KernelArguments);”. In at least one embodiment, each of KernelName, GridSize, BlockSize, ShareMemorySize, Stream, and KernelArguments has the same meaning in the HIP kernel startup syntax 3520 as it does in the CUDA kernel startup syntax 3510 (as previously described herein). In at least one embodiment, the parameters SharedMemorySize and Stream are required in HIP kernel startup syntax 3520, but optional in CUDA kernel startup syntax 3510.

[0358] In at least one embodiment, in addition to the kernel call that causes the kernel MatAdd to execute on the device, Figure 35 The part of HIP source code 3430 described in the text is related to Figure 35 The kernel MatAdd is identical to a portion of the CUDA source code 3410 depicted in the HIP source code 3430. In at least one embodiment, the kernel MatAdd is defined in the HIP source code 3430, having the same "__global__" declaration specifier as the kernel MatAdd defined in the CUDA source code 3410. In at least one embodiment, the kernel call in the HIP source code 3430 is "hipLaunchKernelGGL(MatAdd, numBlocks, threadsPerBlock, 0, 0, A, B, C);", while the corresponding kernel call in the CUDA source code 3410 is "MatAdd <<<numBlocks,threadsPerBlock> >>(A, B, C);”.

[0359] In at least one embodiment, at least one component shown or described in the above figures is used to achieve the combination. Figures 1 to 6 One or more of the described technologies and / or functions are used to select the design frequency of the processing unit.

[0360] Figure 36 A more detailed description is provided according to at least one embodiment. Figure 34C The GPU 3492 is a CUDA-unenabled GPU. In at least one embodiment, the GPU 3492 was developed by AMD Inc. of Santa Clara City. In at least one embodiment, the GPU 3492 can be configured to perform computational operations in a highly parallel manner. In at least one embodiment, the GPU 3492 is configured to perform graphics pipeline operations, such as drawing commands, pixel operations, geometric calculations, and other operations associated with rendering images to a display. In at least one embodiment, the GPU 3492 is configured to perform graphics-independent operations. In at least one embodiment, the GPU 3492 is configured to perform both graphics-related and graphics-independent operations. In at least one embodiment, the GPU 3492 can be configured to execute device code included in HIP source code 3430.

[0361] In at least one embodiment, the GPU 3492 includes, but is not limited to, any number of programmable processing units 3620, an command processor 3610, an L2 cache 3622, a memory controller 3670, a DMA engine 3680(1), a system memory controller 3682, a DMA engine 3680(2), and a GPU controller 3684. In at least one embodiment, each programmable processing unit 3620 includes, but is not limited to, a workload manager 3630 and any number of compute units 3640. In at least one embodiment, the command processor 3610 reads commands from one or more command queues (not shown) and distributes the commands to the workload manager 3630. In at least one embodiment, for each programmable processing unit 3620, the associated workload manager 3630 distributes work to the compute units 3640 included in the programmable processing unit 3620. In at least one embodiment, each compute unit 3640 can execute any number of thread blocks, but each thread block executes on a single compute unit 3640. In at least one embodiment, the workgroup is a thread block.

[0362] In at least one embodiment, each computing unit 3640 includes, but is not limited to, any number of SIMD units 3650 and shared memory 3660. In at least one embodiment, each SIMD unit 3650 implements a SIMD architecture and is configured to perform operations in parallel. In at least one embodiment, each SIMD unit 3650 includes, but is not limited to, a vector ALU 3652 and a vector register file 3654. In at least one embodiment, each SIMD unit 3650 executes a different thread bundle. In at least one embodiment, a thread bundle is a group of threads (e.g., 16 threads), wherein each thread in the thread bundle belongs to a single thread block and is configured to process different datasets based on a single instruction set. In at least one embodiment, prediction can be used to disable one or more threads in the thread bundle. In at least one embodiment, a channel is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a thread bundle. In at least one embodiment, different wavefronts in a thread block can be synchronized together and communicate via shared memory 3660. In at least one embodiment, computing unit 3640 includes one or more distributed shared memories (or distributed shared memory) that allow direct streaming multiprocessor (SM) to streaming multiprocessor (SM) to perform atomic operations related to loading, storing, and executing across multiple SM shared memory blocks. Computing unit 3640 includes one or more clustered distributed shared memories (DSMEMs), which are memory blocks within a cluster that can directly access each other's shared memory.

[0363] In at least one embodiment, the programmable processing unit 3620 is referred to as a "shading engine". In at least one embodiment, in addition to the computing unit 3640, each programmable processing unit 3620 also includes, but is not limited to, any number of dedicated graphics hardware. In at least one embodiment, each programmable processing unit 3620 includes, but is not limited to, any number (including zero) of geometry processors, any number (including zero) of rasterizers, any number (including zero) of rendering backends, a workload manager 3630, and any number of computing units 3640.

[0364] In at least one embodiment, compute units 3640 share an L2 cache 3622. In at least one embodiment, the L2 cache 3622 is partitioned. In at least one embodiment, all compute units 3640 in the GPU 3492 have access to the GPU memory 3690. In at least one embodiment, a memory controller 3670 and a system memory controller 3682 facilitate data transfer between the GPU 3492 and the host, and a DMA engine 3680(1) enables asynchronous memory transfers between the GPU 3492 and the host. In at least one embodiment, a memory controller 3670 and a GPU controller 3684 facilitate data transfers between the GPU 3492 and other GPUs 3492, and a DMA engine 3680(2) enables asynchronous memory transfers between the GPU 3492 and other GPUs 3492.

[0365] In at least one embodiment, GPU 3492 includes, but is not limited to, any number and type of system interconnects that facilitate data and control transfers between any number and type of directly or indirectly linked components, either internally or externally to GPU 3492. In at least one embodiment, GPU 3492 includes, but is not limited to, any number and type of I / O interfaces (e.g., PCIe) coupled to any number and type of peripheral devices. In at least one embodiment, GPU 3492 may include, but is not limited to, any number (including zero) of display engines and any number (including zero) of multimedia engines. In at least one embodiment, GPU 3492 implements a memory subsystem that includes, but is not limited to, any number and type of memory controllers (e.g., memory controller 3670 and system memory controller 3682) and memory devices dedicated to a component or shared among multiple components (e.g., shared memory 3660). In at least one embodiment, GPU 3492 implements a cache subsystem that includes, but is not limited to, one or more cache memories (e.g., L2 cache 3622), each cache memory being either private or shared among any number of components (e.g., SIMD unit 3650, compute unit 3640, and programmable processing unit 3620).

[0366] In at least one embodiment, at least one component shown or described in the above figures is used to achieve the combination. Figures 1 to 6 One or more of the described technologies and / or functions are used to select the design frequency of the processing unit.

[0367] Figure 37 This illustrates how threads of an exemplary CUDA mesh 3720, according to at least one embodiment, are mapped to... Figure 36 Different computational units 3640. In at least one embodiment, and for illustrative purposes only, the grid 3720 has a GridSize of BX multiplied by BY multiplied by 1 and a BlockSize of TX multiplied by TY multiplied by 1. Therefore, in at least one embodiment, the grid 3720 includes, but is not limited to, (BX*BY) thread blocks 3730, and each thread block 3730 includes, but is not limited to, (TX*TY) threads 3740. Threads 3740 in Figure 37 It is depicted as a curved arrow.

[0368] In at least one embodiment, grid 3720 is mapped to programmable processing unit 3620(1), which includes, but is not limited to, computing units 3640(1)-3640(C). In at least one embodiment, and as shown, (BJ*BY) thread block 3730 is mapped to computing unit 3640(1), and the remaining thread blocks 3730 are mapped to computing unit 3640(2). In at least one embodiment, each thread block 3730 may include, but is not limited to, any number of thread bundles, and each thread bundle is mapped to... Figure 36 Different SIMD units 3650.

[0369] In at least one embodiment, the thread bundles in a given thread block 3730 can be synchronized together and communicate via shared memory 3660 included in the associated computing unit 3640. For example, and in at least one embodiment, the thread bundles in thread block 3730 (BJ, 1) can be synchronized together and communicate via shared memory 3660 (1). For example, and in at least one embodiment, the thread bundles in thread block 3730 (BJ+1, 1) can be synchronized together and communicate via shared memory 3660 (2).

[0370] In at least one embodiment, at least one component shown or described in the above figures is used to achieve the combination. Figures 1 to 6 One or more of the described technologies and / or functions are used to select the design frequency of the processing unit.

[0371] Figure 38 This document illustrates how to migrate existing CUDA code to data-parallel C++ code according to at least one embodiment. Data-parallel C++ (DPC++) can refer to an open, standards-based alternative to a single-architecture proprietary language that allows developers to reuse code across hardware targets (CPUs and accelerators, such as GPUs and FPGAs) and also perform custom tweaks for specific accelerators. DPC++ uses similar and / or the same C and C++ constructs as ISOC++, which developers may be familiar with. DPC++ incorporates the Khronos Group's standard SYCL to support data parallelism and heterogeneous programming. SYCL stands for Cross-Platform Abstraction Layer, which builds upon the underlying concepts, portability, and efficiency of OpenCL, enabling code for heterogeneous processors to be written in a "single-source" style using standard C++. SYCL enables single-source development, where C++ template functions can contain both host code and device code to build complex algorithms accelerated using OpenCL, and then reuse them throughout the source code for different types of data.

[0372] In at least one embodiment, a DPC++ compiler is used to compile DPC++ source code that can be deployed across various hardware targets. In at least one embodiment, the DPC++ compiler is used to generate DPC++ applications that can be deployed across various hardware targets, and DPC++ compatibility tools are used to migrate CUDA applications to multi-platform programs in DPC++. In at least one embodiment, the DPC++ basic toolkit includes: a DPC++ compiler for deploying applications across various hardware targets; DPC++ libraries for improving productivity and performance on CPUs, GPUs, and FPGAs; DPC++ compatibility tools for migrating CUDA applications to multi-platform applications; and any suitable combination thereof.

[0373] In at least one embodiment, the DPC++ programming model simplifies one or more aspects related to programming CPUs and accelerators by using modern C++ features to express parallelism with a programming language called Data Parallel C++. The DPC++ programming language can be used for code reuse against hosts (e.g., CPUs) and accelerators (e.g., GPUs or FPGAs) using a single-source language, and clearly communicates execution and memory dependencies. Mappings within the DPC++ code can be used to translate applications to run on the hardware or set of hardware devices that best accelerate workloads. Even on platforms without available accelerators, the host can be used to simplify the development and debugging of device code.

[0374] In at least one embodiment, CUDA source code 3800 is provided as input to the DPC++ compatibility tool 3802 to generate human-readable DPC++ 3804. In at least one embodiment, the human-readable DPC++ 3804 includes inline comments generated by the DPC++ compatibility tool 3802, which guide developers on how and / or where to modify the DPC++ code to complete coding and tuning to the desired performance 3806, thereby generating DPC++ source code 3808.

[0375] In at least one embodiment, CUDA source code 3800 is or includes a collection of human-readable source code in the CUDA programming language. In at least one embodiment, CUDA source code 3800 is human-readable source code using the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension of the C++ programming language, which includes, but is not limited to, mechanisms for defining device code and distinguishing between device code and host code. In at least one embodiment, device code is source code that, after compilation, can be executed on a device (e.g., a GPU or FPGA) and may include one or more parallelizable workflows that can be executed on one or more processor cores of the device. In at least one embodiment, the device may be a processor optimized for parallel instruction processing, such as a CUDA-enabled GPU, GPU, or another GPGPU. In at least one embodiment, host code is source code that, after compilation, can be executed on a host machine. In at least one embodiment, some or all of the host code and device code can be executed in parallel across CPU and GPU / FPGA. In at least one embodiment, the host is a processor optimized for sequential instruction processing, such as a CPU. Figure 38 The CUDA source code 3800 described is consistent with what is discussed elsewhere in this document.

[0376] In at least one embodiment, DPC++ compatibility tool 3802 refers to an executable tool, program, application, or any other suitable type of tool for facilitating the migration of CUDA source code 3800 to DPC++ source code 3808. In at least one embodiment, DPC++ compatibility tool 3802 is a command-line based code migration tool that can be used as part of the DPC++ toolkit for porting existing CUDA sources to DPC++. In at least one embodiment, DPC++ compatibility tool 3802 converts some or all of the source code of a CUDA application from CUDA to DPC++ and generates a result file, at least partially written in DPC++, referred to as human-readable DPC++ 3804. In at least one embodiment, human-readable DPC++ 3804 includes comments generated by DPC++ compatibility tool 3802 to indicate where user intervention may be required. In at least one embodiment, user intervention is necessary when CUDA source code 3800 calls a CUDA API that does not have a DPC++ API; other examples requiring user intervention will be discussed in more detail later.

[0377] In at least one embodiment, the workflow for migrating CUDA source code 3800 (e.g., an application or a portion thereof) includes creating one or more build database files; migrating CUDA to DPC++ using a DPC++ compatibility tool 3802; completing the migration and verifying its correctness to generate DPC++ source code 3808; and compiling the DPC++ source code 3808 using a DPC++ compiler to generate a DPC++ application. In at least one embodiment, the compatibility tool provides a utility that intercepts commands used during Makefile execution and stores them in the build database files. In at least one embodiment, the files are stored in JSON format. In at least one embodiment, intercepted build commands translate Makefile commands into DPC compatibility commands.

[0378] In at least one embodiment, intercept-build is a utility script that intercepts the build process to capture build options, macro definitions, and include paths, and writes this data to a build database file. In at least one embodiment, the build database file is a JSON file. In at least one embodiment, the DPC++ compatibility tool 3802 parses the build database and applies options when migrating input sources. In at least one embodiment, the use of intercept-build is optional but strongly recommended for Make or CMake-based environments. In at least one embodiment, the migration database includes commands, directories, and files: commands may include necessary build flags; directories may include paths to header files; and files may include paths to CUDA files.

[0379] In at least one embodiment, the DPC++ compatibility tool 3802 migrates CUDA code (e.g., applications) written in CUDA to DPC++ by generating DPC++ as much as possible. In at least one embodiment, the DPC++ compatibility tool 3802 is available as part of a toolkit. In at least one embodiment, the DPC++ toolkit includes an intercept-build tool. In at least one embodiment, the intercept-build tool creates a build database that captures build commands to migrate CUDA files. In at least one embodiment, the DPC++ compatibility tool 3802 uses the build database generated by the intercept-build tool to migrate CUDA code to DPC++. In at least one embodiment, non-CUDA C++ code and files are migrated as is. In at least one embodiment, the DPC++ compatibility tool 3802 generates human-readable DPC++ 3804, which may be DPC++ code, such as that generated by the DPC++ compatibility tool 3802, that cannot be compiled by the DPC++ compiler and requires additional pipelines to verify incorrectly migrated code portions, and may involve manual intervention, such as intervention by a developer. In at least one embodiment, the DPC++ compatibility tool 3802 provides hints or tools embedded in the code to help developers manually migrate additional code that cannot be migrated automatically. In at least one embodiment, the migration is a one-time activity for a source file, project, or application.

[0380] In at least one embodiment, the DPC++ compatibility tool 3802 is capable of successfully migrating all portions of CUDA code to DPC++, and can simply include optional steps for manually verifying and tuning the performance of the generated DPC++ source code. In at least one embodiment, the DPC++ compatibility tool 3802 directly generates DPC++ source code 3808 that is compiled by the DPC++ compiler, without requiring or utilizing manual intervention to modify the DPC++ code generated by the DPC++ compatibility tool 3802. In at least one embodiment, the DPC++ compatibility tool generates compilable DPC++ code that developers can selectively tune based on performance, readability, maintainability, and various other considerations, or any combination thereof.

[0381] In at least one embodiment, one or more CUDA source files are migrated to DPC++ source files, at least in part, using the DPC++ compatibility tool 3802. In at least one embodiment, the CUDA source code includes one or more header files, which may include CUDA header files. In at least one embodiment, the CUDA source files include text that can be printed.<cuda.h> header files and<stdio.h> Header file. In at least one embodiment, a portion of the vector addition kernel CUDA source file may be written as or related to:

[0382]

[0383]

[0384] In at least one embodiment, and in conjunction with the CUDA source files presented above, the DPC++ compatibility tool 3802 parses the CUDA source code and replaces the header files with appropriate DPC++ and SYCL header files. In at least one embodiment, the DPC++ header files include helper declarations. In CUDA, there is a concept of thread IDs; correspondingly, in DPC++ or SYCL, there is a local identifier for each element.

[0385] In at least one embodiment, and in relation to the CUDA source file presented above, there are two vectors A and B, which are initialized and the result of vector addition is placed into vector C as part of VectorAddKernel(). In at least one embodiment, as part of migrating CUDA code to DPC++ code, the DPC++ compatibility tool 3802 converts the CUDA thread ID used to index worker elements to the SYCL standard addressing of the worker elements via the local ID. In at least one embodiment, the DPC++ code generated by the DPC++ compatibility tool 3802 can be optimized—for example, by reducing the dimension of nd_item, thereby increasing memory and / or processor utilization.

[0386] In at least one embodiment, and in conjunction with the CUDA source files presented above, memory allocation is migrated. In at least one embodiment, relying on SYCL concepts such as platform, device, context, and queue, cudaMalloc() is migrated to a unified shared memory SYCL call malloc_device() to which the device and context are passed. In at least one embodiment, the SYCL platform may have multiple devices (e.g., host and GPU devices); a device may have multiple queues to which jobs can be submitted; each device may have a context; and a context may have multiple devices and manage shared memory objects.

[0387] In at least one embodiment, and in conjunction with the CUDA source files presented above, the `main()` function invokes or calls `VectorAddKernel()` to add two vectors A and B and store the result in vector C. In at least one embodiment, the CUDA code calling `VectorAddKernel()` is replaced by DPC++ code to submit the kernel to the command queue for execution. In at least one embodiment, the command group handler `cgh` passes the data submitted to the queue, synchronization, and computation, and `parallel_for` is called for multiple global elements and multiple work items in the workgroup that call `VectorAddKernel()`.

[0388] In at least one embodiment, and in conjunction with the CUDA source files presented above, CUDA calls to copy device memory and then free memory for vectors A, B, and C are migrated to corresponding DPC++ calls. In at least one embodiment, C++ code (e.g., standard ISOC++ code for printing vectors of floating-point variables) is migrated as is without modification by the DPC++ compatibility tool 3802. In at least one embodiment, the DPC++ compatibility tool 3802 modifies the CUDA API used for memory setup and / or host calls to execute the kernel on an accelerated device. In at least one embodiment, and in conjunction with the CUDA source files presented above, the corresponding human-readable DPC++ 3804 (e.g., compilable) is written as or related to:

[0389]

[0390]

[0391] In at least one embodiment, human-readable DPC++ 3804 refers to the output generated by the DPC++ compatibility tool 3802 and can be optimized in one or another. In at least one embodiment, the human-readable DPC++ 3804 generated by the DPC++ compatibility tool 3802 can be manually edited by developers after migration to make it more maintainable, performant, or for other considerations. In at least one embodiment, the DPC++ code generated by the DPC++ compatibility tool 3802 (e.g., publicly available DPC++) can be optimized by removing duplicate calls to get_current_device() and / or get_default_context() for each malloc_device() call. In at least one embodiment, the DPC++ code generated above uses a 3D nd_range, which can be refactored to use only a single dimension, thereby reducing memory usage. In at least one embodiment, developers can manually edit the DPC++ code generated by the DPC++ compatibility tool 3802 to replace the use of unified shared memory with accessors. In at least one embodiment, the DPC++ compatibility tool 3802 has the option to change how it migrates CUDA code to DPC++ code. In at least one embodiment, the DPC++ compatibility tool 3802 is verbose because it uses a generic template to migrate CUDA code to DPC++ code, which is suitable for a wide range of situations.

[0392] In at least one embodiment, the CUDA to DPC++ migration workflow includes the following steps: preparing the migration using an intercept-build script; performing the migration of the CUDA project to DPC++ using the DPC++ compatibility tool 3802; manually reviewing and editing the source files of the migration to ensure their integrity and correctness; and compiling the final DPC++ code to generate the DPC++ application. In at least one embodiment, manual review of the DPC++ source code may be required in one or more scenarios, including but not limited to: the migrated API not returning error codes (CUDA code can return error codes that can subsequently be used by the application, but SYCL uses exceptions to report errors, therefore error codes are not used to expose errors); DPC++ does not support CUDA compute capability-related logic; statements cannot be deleted. In at least one embodiment, scenarios requiring manual intervention in the DPC++ code may include, but are not limited to: replacing error code logic with (*,0) code or commenting it out; equivalent DPC++ APIs being unavailable; CUDA compute capability-related logic; hardware-related APIs (clock()); APIs lacking unsupported features; performing time measurement logic; handling built-in vector type conflicts; migrating the cuBLAS API; and more.

[0393] In at least one embodiment, one or more techniques described herein utilize an API programming model. In at least one embodiment, the oneAPI programming model refers to a programming model for interacting with different computing accelerator architectures. In at least one embodiment, oneAPI refers to an application programming interface (API) designed to interact with various computing accelerator architectures. In at least one embodiment, the oneAPI programming model utilizes the DPC++ programming language. In at least one embodiment, the DPC++ programming language refers to a high-level language used for data-parallel programming productivity. In at least one embodiment, the DPC++ programming language is at least partially based on the C and / or C++ programming languages. In at least one embodiment, the oneAPI programming model is one such programming model as those developed by Intel Corporation of Santa Clara, California.

[0394] In at least one embodiment, oneAPI and / or the oneAPI programming model are used to interact with various accelerators, GPUs, processors, and / or their variants and architectures. In at least one embodiment, oneAPI includes a set of libraries that implement various functions. In at least one embodiment, oneAPI includes at least the oneAPIDPC++ library, the oneAPI math kernel library, the oneAPI data analysis library, the oneAPI deep neural network library, the oneAPI collection communication library, the oneAPI thread building block library, the oneAPI video processing library, and / or their variants.

[0395] In at least one embodiment, the oneAPIDPC++ library (also known as oneDPL) is a library that implements algorithms and functions to accelerate DPC++ kernel programming. In at least one embodiment, oneDPL implements one or more Standard Template Library (STL) functions. In at least one embodiment, oneDPL implements one or more parallel STL functions. In at least one embodiment, oneDPL provides a set of library classes and functions, such as parallel algorithms, iterators, function object classes, range-based APIs, and / or their variants. In at least one embodiment, oneDPL implements one or more classes and / or functions from the C++ Standard Library. In at least one embodiment, oneDPL implements one or more random number generator functions.

[0396] In at least one embodiment, the oneAPI math kernel library (also known as oneMKL) is a library that implements various optimized and parallelized routines for the various mathematical functions and / or operations. In at least one embodiment, oneMKL implements one or more Basic Linear Algebra Subroutines (BLAS) and / or Linear Algebra Encapsulations (LAPACK) dense linear algebra routines. In at least one embodiment, oneMKL implements one or more sparse BLAS linear algebra routines. In at least one embodiment, oneMKL implements one or more random number generators (RNGs). In at least one embodiment, oneMKL implements one or more vector mathematics (VM) routines for performing mathematical operations on vectors. In at least one embodiment, oneMKL implements one or more Fast Fourier Transform (FFT) functions.

[0397] In at least one embodiment, the oneAPI data analytics library (also known as oneDAL) is a library that implements various data analytics applications and distributed computing. In at least one embodiment, oneDAL implements various algorithms for preprocessing, transformation, analysis, modeling, verification, and decision-making for data analysis in batch, online, and distributed processing modes. In at least one embodiment, oneDAL implements various C++ and / or Java APIs and various connectors to one or more data sources. In at least one embodiment, oneDAL implements the DPC++ API extension to the traditional C++ interface and enables GPUs to be used for various algorithms.

[0398] In at least one embodiment, the oneAPI deep neural network library (also referred to as oneDNN) is a library that implements various deep learning functions. In at least one embodiment, oneDNN implements various neural networks, machine learning and deep learning functions, algorithms and / or variations thereof.

[0399] In at least one embodiment, the oneAPI collection communication library (also known as oneCCL) is a library for implementing various applications of deep learning and machine learning workloads. In at least one embodiment, oneCCL is built on top of lower-level communication middleware such as Message Passing Interface (MPI) and libfabrics. In at least one embodiment, oneCCL enables a set of deep learning-specific optimizations, such as prioritization, persistent operations, out-of-order execution, and / or variations thereof. In at least one embodiment, oneCCL implements various CPU and GPU functionalities.

[0400] In at least one embodiment, the oneAPI thread building block library (also referred to as oneTBB) is a library that implements various parallelization processes for various applications. In at least one embodiment, oneTBB is used for task-based shared parallel programming on a host machine. In at least one embodiment, oneTBB implements a general-purpose parallel algorithm. In at least one embodiment, oneTBB implements a concurrent container. In at least one embodiment, oneTBB implements a scalable memory allocator. In at least one embodiment, oneTBB implements a work-stealing task scheduler. In at least one embodiment, oneTBB implements low-level synchronization primitives. In at least one embodiment, oneTBB is compiler-independent and can be used on various processors, such as GPU...

Claims

1. A processor, comprising: One or more circuits are used to dynamically adjust the operating frequency of one or more integrated circuits, at least in part, based on the maximum throughput of one or more integrated circuits measured dynamically.

2. The processor of claim 1, wherein the one or more circuits are used for: Two or more processing units are acquired through fine-tuning; Two or more frequencies are calculated, at least in part, based on comparisons between the two or more frequencies obtained through fine-tuning; and The change in the design frequency of the processing unit is calculated based at least in part on a comparison between the two or more frequencies.

3. The processor of claim 1, wherein the one or more circuits are configured to compare two or more sets of data collected during the execution of two or more applications, the two or more applications including a reference application corresponding to a reference frequency and a user application corresponding to a user frequency.

4. The processor of claim 1, wherein the dynamically measured maximum throughput indicates a change in the design frequency of the processing unit.

5. The processor of claim 1, wherein the one or more circuits are configured to use one or more critical path monitors to acquire data indicating the maximum throughput of dynamic measurements.

6. The processor of claim 1, wherein the measurement is performed in one or more critical paths.

7. The processor of claim 1, wherein the one or more circuits are configured to select different frequencies of the processing unit for different applications.

8. A system comprising: One or more processors, said one or more processors being used to dynamically adjust the operating frequency of said one or more integrated circuits based at least in part on the maximum throughput of said one or more integrated circuits as measured dynamically.

9. The system of claim 8, wherein the one or more processors are configured to: Two or more processing units are acquired through fine-tuning; Two or more frequencies are calculated, at least in part, based on comparisons between the two or more frequencies obtained through fine-tuning; and The change in the design frequency of the processing unit is calculated based at least in part on a comparison between the two or more frequencies.

10. The system of claim 8, wherein the one or more processors compare two or more sets of data collected during the execution of two or more applications, the two or more applications including a reference application corresponding to a reference frequency and a user application corresponding to a user frequency.

11. The system of claim 8, wherein the dynamically measured maximum throughput indicates a change in the design frequency of the processing unit.

12. The system of claim 8, wherein the one or more processors are configured to use one or more critical path monitors to acquire data indicating the maximum throughput of dynamic measurements.

13. The system of claim 8, wherein the measurement is performed in one or more critical paths.

14. The system of claim 8, wherein the one or more processors are configured to select different frequencies of the processing units for different applications.

15. A method comprising: The operating frequency of the one or more integrated circuits is dynamically adjusted, at least in part, based on the maximum throughput of the one or more integrated circuits measured dynamically.

16. The method of claim 15, further comprising: Two or more processing units are acquired through fine-tuning; Two or more frequencies are calculated, at least in part, based on comparisons between the two or more frequencies through fine-tuning. as well as The change in the design frequency of the processing unit is calculated based at least in part on a comparison between the two or more frequencies.

17. The method of claim 15, further comprising: Compare two or more sets of data collected during the execution of two or more applications, including a reference application corresponding to a reference frequency and a user application corresponding to a user frequency.

18. The method of claim 15, wherein the dynamically measured maximum throughput indicates a change in the design frequency of the processing unit.

19. The method of claim 15, further comprising: Use one or more critical path monitors to obtain data indicating the maximum throughput for dynamic measurements.

20. The method of claim 15, further comprising: Different frequencies of processing units are selected for different applications.

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