Leveling method and system for processing PCB (Printed Circuit Board) in integrated circuit

Abstract

The invention discloses a leveling method and system for PCB processing in an integrated circuit, and relates to the related field of printed circuit boards, the method comprises the following steps: collecting surface data of a to-be-processed PCB, obtaining a morphology data set, and establishing a three-dimensional morphology model of the to-be-processed PCB based on the morphology data set; performing three-dimensional deviation identification on the to-be-processed PCB through the three-dimensional shape model, and extracting a three-dimensional deviation area; mapping to an integrated circuit for leveling analysis according to the three-dimensional deviation area, setting a leveling priority mapping graph, and performing dynamic leveling planning based on the leveling priority mapping graph to generate a leveling path; the leveling path is executed for leveling monitoring, flatness verification is carried out according to multi-source monitoring data, leveling quality parameters are obtained and backtracked to the leveling path for iterative updating, and self-adaptive leveling is carried out on the PCB to be processed. The technical problem that existing PCB machining leveling is insufficient in adaptability and precision is solved, and the technical effect of high-precision self-adaptive leveling is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of printed circuit, in particular to a flattening method and system for PCB processing in integrated circuits. BACKGROUND

[0002] In the field of integrated circuit manufacturing, the flatness of the PCB plays a crucial role in circuit performance, component mounting reliability and overall product quality. Even slight deviations in flatness can cause signal interference, poor component contact and other serious problems, thereby affecting the normal operation and service life of the integrated circuit. Currently, mechanical flattening or hot air flattening methods are mainly used for appearance correction of PCBs before processing. However, these methods lack accurate identification and dynamic planning capabilities for three-dimensional surface topography, resulting in poor adaptability, insufficient precision and easy secondary deformation during flattening.

[0003] At present, in the related art, the flattening for PCB processing in integrated circuits has the technical problems of insufficient adaptability and precision. SUMMARY

[0004] The present application provides a flattening method and system for PCB processing in integrated circuits, which collects surface data of the PCB to be processed to form a topography data set, establishes a three-dimensional topography model based on the topography data set, identifies three-dimensional deviations using the three-dimensional topography model, finds out three-dimensional deviation areas such as warping and unevenness, maps the three-dimensional deviation areas to the integrated circuit for flattening analysis, sets a flattening priority mapping diagram, dynamically plans the flattening based on the flattening priority mapping diagram, generates a flattening path, monitors the flattening when executing the flattening path, verifies the flatness based on multi-source monitoring data, and iteratively updates the flattening quality parameters obtained from the flattening path. The technical means of adaptive flattening of the PCB to be processed is achieved, the technical problems of insufficient adaptability and precision of the existing flattening for PCB processing in integrated circuits are solved, and the technical effect of high-precision adaptive flattening is achieved.

[0005] The present application provides a flattening method for PCB processing in integrated circuits, comprising: collecting surface data of the PCB to be processed to obtain a topography data set, establishing a three-dimensional topography model of the PCB to be processed based on the topography data set; identifying three-dimensional deviations of the PCB to be processed through the three-dimensional topography model, extracting three-dimensional deviation areas, which include warping areas and uneven areas; mapping the three-dimensional deviation areas to the integrated circuit for flattening analysis, setting a flattening priority mapping diagram, dynamically planning the flattening based on the flattening priority mapping diagram, and generating a flattening path; monitoring the flattening by executing the flattening path, verifying the flatness based on multi-source monitoring data, obtaining flattening quality parameters, and iteratively updating the flattening path for adaptive flattening of the PCB to be processed.

[0006] In a possible implementation, the three-dimensional deviation identification is performed on the PCB to be processed by using the three-dimensional topographic model, and a three-dimensional deviation region is extracted. The following processing is performed: a plurality of feature points in a four-corner region of the PCB to be processed are selected as reference points, fitting is performed according to the reference points, and reference plane data is set; a vertical distance between a first grid node of the three-dimensional topographic model and the reference plane data is fitted, and a plurality of node deviation values are obtained; the node deviation values of the plurality of nodes are stored in association with coordinate positions of the reference plane data, and a deviation distribution map is generated; and the deviation distribution map is subjected to region identification, and the three-dimensional deviation region is extracted.

[0007] In a possible implementation, the deviation distribution map is subjected to region identification, and the three-dimensional deviation region is extracted. The following processing is performed: a positive and negative deviation threshold is set, a potential deviation point set is generated by determining and identifying based on the deviation distribution map in combination with the positive and negative deviation threshold; region growing analysis is performed based on the potential deviation point set, and adjacent potential deviation points in a spatial position are aggregated to construct a deviation continuous region; curvature calculation is performed on the deviation continuous region, and a warping region is determined according to region curvature; local roughness calculation is performed on the deviation continuous region, and an uneven region is determined according to region roughness; and the warping region and the uneven region are integrated to construct the three-dimensional deviation region.

[0008] In a possible implementation, flattening analysis is performed according to mapping of the three-dimensional deviation region to an integrated circuit, a flattening priority mapping map is set, dynamic flattening planning is performed based on the flattening priority mapping map, a flattening path is generated, and the following processing is performed: an integrated circuit layout map is called to identify key elements, and key circuit element coordinates are obtained; contour identification is performed on the three-dimensional deviation region, and region outer contour coordinates are extracted; the key circuit element coordinates and the region outer contour coordinates are subjected to spatial mapping to construct a region-circuit connection network map; circuit function influence analysis is performed according to the region-circuit connection network map, and a circuit function influence coefficient is obtained; region deviation influence analysis is performed according to the region-circuit connection network map, and a region deviation influence coefficient is obtained; flattening weight analysis is performed based on the circuit function influence coefficient and the region deviation influence coefficient, and a flattening priority is constructed; and the flattening priority is traced back to the three-dimensional deviation region for mapping and labeling according to the flattening priority, and the flattening priority mapping map is constructed.

[0009] In a possible implementation, the key circuit element coordinates are spatially mapped with the region outer contour coordinates to construct a region-circuit connection graph, and the following processing is performed: adjacent sorting is performed based on the region outer contour coordinates, a boundary point coordinate sequence is generated for geometric analysis, and geometric feature parameters are extracted; topography reading is performed on the region outer contour coordinates according to the boundary point coordinate sequence, and topographic feature parameters are generated; spatial region division is performed by traversing the three-dimensional topography model, and a plurality of spatial grid coding units are generated; the key circuit element coordinates are matched with the plurality of spatial grid codes, and the key circuit element coordinates are mapped to the plurality of spatial grid coding units according to the matching result to generate element spatial coding positions; spatial position mapping analysis is performed on the element spatial coding positions and the region outer contour coordinates according to the geometric feature parameters and the topographic feature parameters, and the region-circuit connection graph is constructed.

[0010] In a possible implementation, dynamic flattening planning is performed based on the flattening priority mapping graph to generate a flattening path, and the following processing is performed: the performance constraints and flattening process constraints of a flattening device are called, and a flattening path optimization target is established; a path starting point is determined by performing maximum value search on the flattening priority mapping graph according to the flattening priority; a region access order is determined by performing nearest neighbor search on the flattening priority mapping graph according to the path starting point; a to-be-flattened trajectory is generated by performing flattening planning on the flattening priority mapping graph based on the region access order; and the flattening path is constructed by performing real-time correction according to the to-be-flattened trajectory in a flattening moving direction.

[0011] In a possible implementation, flattening monitoring is performed on the flattening path, flatness verification is performed according to multi-source monitoring data, flattening quality parameters are obtained, and the following processing is performed: the flattening path is controlled to move the flattening head according to the planning path to perform flattening monitoring on the to-be-processed PCB, and multi-source monitoring data is obtained; a plurality of surface topography data are obtained by performing interval collection based on the multi-source monitoring data; real-time flatness is calculated according to the plurality of surface topography data, and a real-time flatness index is set; flatness verification is performed on the multi-source monitoring data according to the real-time flatness index, and a flattening verification evaluation result is generated; surface flatness errors and local curling degrees are generated by performing flattening calculation according to the flattening verification evaluation result; first flattening quality parameters are obtained by performing surface roughness quality analysis based on the surface flatness errors; and second flattening quality parameters are obtained by performing flattening residual stress distribution quality analysis based on the local curling degrees.

[0012] In a possible implementation, leveling calculations are performed based on the leveling verification and evaluation results to generate surface flatness error and local warping. The following processes are then performed: Multiple surface leveling points that have passed verification are extracted from the leveling verification and evaluation results; local deformation is identified by traversing the leveling verification and evaluation results, and multiple local deformation regions are extracted; the vertical distance between the multiple surface leveling points and the reference plane data is calculated to generate deviation data; the range of the deviation data is calculated as the overall plane error value, and local plane partitioning is performed according to the overall plane error value to generate surface flatness error; curvature is calculated based on the multiple local deformation regions to obtain curvature change characteristics, and the multiple local deformation regions are aggregated according to the curvature change characteristics to generate continuous deformation regions; deformation calculations are performed according to the continuous deformation regions to determine the warping angle and warping height; and the local warping is determined by comprehensive identification based on the warping angle and the warping height.

[0013] In a possible implementation, the leveling quality parameters are obtained and iteratively updated by tracing back to the leveling path. Adaptive leveling is then performed on the PCB board to be processed, and the following processes are executed: Multi-level quality tolerance thresholds are set; the leveling quality parameters are compared and analyzed with the multi-level quality tolerance thresholds to generate a leveling quality defect distribution map; the leveling path is associated and mapped according to the traversal order determined by the leveling quality defect distribution map to determine the leveling path parameters to be optimized, the leveling path parameters to be optimized including the path optimization target; the leveling path is updated according to the path optimization target to generate an optimized leveling path; a virtual environment is constructed to perform feasibility simulation verification of the optimized leveling path; the optimized leveling path is iteratively corrected based on the verification results, and a leveling strategy is formulated for adaptive leveling of the PCB board to be processed.

[0014] This application also provides a leveling system for PCB board processing in integrated circuits, comprising: a three-dimensional topography model building module, used to collect surface data of the PCB board to be processed, obtain a topography dataset, and build a three-dimensional topography model of the PCB board to be processed based on the topography dataset; a three-dimensional deviation identification module, used to identify three-dimensional deviations of the PCB board to be processed through the three-dimensional topography model, extract three-dimensional deviation regions, the three-dimensional deviation regions including warped regions and uneven regions; a dynamic leveling planning module, used to perform leveling analysis by mapping the three-dimensional deviation regions to integrated circuits, set a leveling priority mapping map, perform dynamic leveling planning based on the leveling priority mapping map, and generate a leveling path; and an adaptive leveling module, used to perform leveling monitoring by executing the leveling path, verify flatness based on multi-source monitoring data, obtain leveling quality parameters, backtrack to the leveling path for iterative updates, and perform adaptive leveling for the processing of the PCB board to be processed.

[0015] The proposed leveling method and system for PCB board processing in integrated circuits involves several steps. First, surface data of the PCB board to be processed is collected to obtain a topography dataset. A three-dimensional topography model of the PCB board is then established based on this dataset. Next, the 3D topography model is used to identify 3D deviations in the PCB board, extracting deviation regions, including warped and uneven areas. These deviation regions are then mapped onto the integrated circuit for leveling analysis. A leveling priority mapping is established, and dynamic leveling planning is performed based on this mapping to generate a leveling path. Finally, the leveling path is executed for leveling monitoring. Flatness is verified based on multi-source monitoring data, and leveling quality parameters are obtained and iteratively updated back to the leveling path, enabling adaptive leveling of the PCB board. This achieves high-precision adaptive leveling. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings of the embodiments of the present invention will be briefly described below. Flowcharts are used in this application to illustrate the operations performed by the system according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed precisely in sequence. Instead, various steps can be processed in reverse order or simultaneously as needed. Furthermore, other operations can be added to these processes, or one or more steps can be removed from these processes.

[0017] Figure 1 This is a schematic flowchart of a leveling method for PCB board processing in integrated circuits, provided in an embodiment of this application.

[0018] Figure 2 This is a schematic diagram of a leveling system for PCB board processing in integrated circuits, provided in an embodiment of this application.

[0019] Figure labeling: 3D topography model building module 10, 3D deviation recognition module 20, dynamic leveling planning module 30, adaptive leveling module 40. Detailed Implementation

[0020] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, specific embodiments of this application are given below.

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description of this application will be provided in conjunction with the accompanying drawings. The described embodiments should not be considered as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] In the following description, references to "some embodiments" describe a subset of all possible embodiments. However, it is understood that "some embodiments" can be the same or different subsets of all possible embodiments and can be combined with each other without conflict. The terms "first" and "second" are used merely to distinguish similar objects and do not represent a specific ordering of objects. The terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or server that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or modules not explicitly listed or inherent to these processes, methods, products, or devices. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only.

[0023] This application provides a leveling method for PCB board processing in integrated circuits, such as... Figure 1 As shown, the method includes: Step S100: Collect surface data of the PCB board to be processed to obtain a morphology dataset, and establish a three-dimensional morphology model of the PCB board to be processed based on the morphology dataset.

[0024] Specifically, a 3D scanner or laser rangefinder is used to non-contactly scan the surface of the PCB board to be processed, acquiring 3D coordinate data of various points on the surface. For example, the 3D scanner emits a laser beam and receives the reflected signal; by calculating the round-trip time of the signal, the distance between various points on the surface is determined, thereby acquiring 3D coordinate data. This data constitutes a topography dataset, containing topographic information such as the height and unevenness of the PCB board surface. Computer-aided design software or 3D modeling software is used to import the acquired topography dataset, and through data processing, a 3D topography model of the PCB board to be processed is generated.

[0025] Step S200: The three-dimensional topography model is used to identify three-dimensional deviations of the PCB board to be processed, and the three-dimensional deviation areas are extracted. The three-dimensional deviation areas include warped areas and uneven areas.

[0026] Specifically, image processing technology is used to analyze the 3D topographic model and identify areas that deviate from the ideal flat surface. These deviations manifest as differences in height, changes in curvature, etc. Based on the identification results, areas where the deviation exceeds a preset threshold are extracted as 3D deviation areas. These areas include warped areas and uneven areas, such as areas on the PCB board surface where edges or parts are warped due to stress, temperature, or other factors, and areas on the PCB board surface with uneven phenomena such as protrusions and depressions.

[0027] In one possible implementation, the three-dimensional topography model is used to identify three-dimensional deviations in the PCB board to be processed, and the three-dimensional deviation areas are extracted. Step S200 further includes step S210, which selects multiple feature points in the four corner areas of the PCB board to be processed as reference points, and fits the reference points to set reference plane data. Specifically, in the four corner areas of the PCB board to be processed, multiple representative feature points are selected using image recognition technology or by a pre-set marker point positioning method. These feature points have obvious geometric features, such as corner points, edge intersections, etc. For example, at the four corners of the PCB board, two obvious intersections of the edges of each corner are selected as feature points, for a total of 8 feature points selected at the four corners.

[0028] Mathematical fitting algorithms, such as the least squares method, are used to fit multiple selected feature points. The least squares method finds the best function match for the data by minimizing the sum of squared errors, i.e., finding a plane that best approximates these feature points. Through calculation, the equation parameters of this fitted plane are determined, thereby setting the reference plane data. This data includes information such as the position and normal vector of the reference plane, representing the theoretically flat plane that the PCB board should be on, and is used for comparison with the actual surface of the PCB board.

[0029] Step S220: Fit the vertical distances between the first mesh node of the 3D topography model and the reference plane data to obtain the deviation values ​​of multiple nodes. Specifically, the 3D topography model of the PCB board to be processed is meshed to form multiple small mesh units, and the vertex of each mesh unit is a mesh node. A programming algorithm is used to traverse these mesh nodes, for example, using a double loop structure to visit each mesh node sequentially in row and column order. For each mesh node, the vertical distance from the node to the reference plane is calculated based on its 3D coordinates and the equation of the reference plane data. This can be calculated using vector operations or the distance formula from a point to a plane. The calculated vertical distance is used as the deviation value of the mesh node, which reflects the degree of deviation of the point relative to the reference plane.

[0030] Step S230: Associate and store the deviation values ​​of multiple nodes with the coordinate positions of the reference plane data to generate a deviation distribution map. Specifically, establish a data structure, such as an array or dictionary, to associate and store the deviation value of each grid node with its coordinate position in the reference plane coordinate system, so that the deviation value of the corresponding node can be quickly retrieved based on the coordinate position. Using a graphics library or visualization tool, display the distribution of deviation on the PCB board surface graphically based on the associated stored data. Different colors or grayscale can be used to represent different deviation value ranges; for example, green can be used to represent areas with small deviations, and red can be used to represent areas with large deviations, thereby generating a deviation distribution map.

[0031] Step S240 involves performing region identification on the deviation distribution map to extract the three-dimensional deviation regions. Specifically, image segmentation algorithms, such as threshold-based segmentation, region growing algorithms, or edge detection algorithms, are used to process the deviation distribution map. Taking threshold-based segmentation as an example, a deviation threshold is set, and regions with deviation values ​​greater than this threshold are identified as a single region. This threshold can be determined based on the PCB board's processing accuracy requirements and actual production experience. Based on the region identification results, the identified regions are located and marked in the three-dimensional shape model, and the corresponding three-dimensional deviation regions are extracted. These regions are the areas that need to be leveled.

[0032] In one possible implementation, the deviation distribution map is used for region identification to extract the three-dimensional deviation regions. Step S240 further includes step S241, setting positive and negative deviation thresholds, and identifying potential deviation points based on the deviation distribution map and the positive and negative deviation thresholds to generate a set of potential deviation points. Specifically, based on the PCB board's processing accuracy requirements and actual production experience, a positive deviation threshold and a negative deviation threshold are set. The positive deviation threshold is used to identify abnormal areas on the PCB board surface that are higher than the reference plane, and the negative deviation threshold is used to identify abnormal areas on the surface that are lower than the reference plane. Each point in the deviation distribution map is traversed, and its deviation value is compared with the set positive and negative deviation thresholds. If the deviation value is greater than the positive deviation threshold or less than the negative deviation threshold, the point is marked as a potential deviation point, and its coordinates and deviation value are recorded. All data marked as potential deviation points are stored in a data structure, such as an array or linked list, to form a set of potential deviation points.

[0033] Step S242: Based on the set of potential deviation points, perform region growing analysis, extract spatially adjacent potential deviation points, aggregate them, and construct a deviation-continuous region. Specifically, select a region growing algorithm, such as a neighborhood-based seed point region growing algorithm. This algorithm starts from a seed point and gradually merges points adjacent to the seed point that meet certain conditions into the current region. A point is randomly selected from the set of potential deviation points as the seed point. For each neighboring point of the seed point, check if that neighboring point is also in the set of potential deviation points. If it is, merge that neighboring point into the current region and use it as a new seed point to continue region growing. Repeat the above process until no new neighboring points can be merged into the current region, at which point a deviation-continuous region is constructed. Then, select a seed point again from the remaining potential deviation points and repeat the above steps to construct other deviation-continuous regions.

[0034] Step S243: Traverse the deviated continuous regions to calculate curvature, and determine the warped regions based on the region curvature. Specifically, for each deviated continuous region, a curvature calculation algorithm, such as a method based on differential geometry, is used to calculate the curvature of each point in that region. Curvature reflects the degree of bending of the surface at that point. For a discrete set of three-dimensional points, a difference approximation method can be used to calculate the curvature. A curvature threshold is set; if the curvature of most points in a deviated continuous region is greater than this threshold, the region is determined to be a warped region. A warped region manifests as a large local bending of the PCB board surface.

[0035] Step S244: Traverse the deviated continuous regions to perform local roughness calculations, and determine the uneven regions based on the regional roughness. Specifically, for each deviated continuous region, a local roughness calculation algorithm is used, such as the arithmetic mean deviation Ra calculation method in surface roughness evaluation parameters. A local region of a certain size is selected within the deviated continuous region, and the average of the absolute values ​​of the distances from all points within this region to the reference plane is calculated as the roughness value of this local region. A roughness threshold is set; if the roughness value of a deviated continuous region is greater than this threshold, the region is determined to be an uneven region. Uneven regions manifest as local roughness and unevenness on the PCB board surface.

[0036] Step S245: Integrate the warped region with the uneven region to construct the three-dimensional deviation region. Specifically, merge the warped region and the flat region to form a complete three-dimensional deviation region. Set operations, such as union, can be used to merge all points in the two regions into a new region. The integrated region is then located and marked in the three-dimensional topography model to construct the three-dimensional deviation region. This region contains all areas on the PCB board surface that require leveling.

[0037] Step S300: Map the three-dimensional deviation region to the integrated circuit for leveling analysis, set a leveling priority mapping map, perform dynamic leveling planning based on the leveling priority mapping map, and generate a leveling path.

[0038] Specifically, the location information of the identified 3D deviation regions in the 3D topography model is mapped onto the actual integrated circuit layout to determine which regions have the greatest impact on the performance and reliability of the integrated circuit. Based on the mapping results and the design requirements of the integrated circuit, a leveling priority mapping map is established. This map determines the leveling order and priority of each 3D deviation region. Using a path planning algorithm, a leveling path is generated based on the leveling priority mapping map.

[0039] In one possible implementation, the three-dimensional deviation region is mapped to the integrated circuit for leveling analysis. A leveling priority mapping map is set, and dynamic leveling planning is performed based on the leveling priority mapping map to generate a leveling path. Step S300 further includes step S310, retrieving the integrated circuit layout diagram for key component identification and obtaining the coordinates of key circuit components. Specifically, the integrated circuit layout diagram is retrieved from the PCB design file or a relevant database. This layout diagram records the position, size, and other information of each component in the integrated circuit on the PCB board. Based on the functional and performance requirements of the integrated circuit, rules for determining key components are formulated. For example, for high-speed signal transmission circuits, high-speed signal pins, high-frequency filter capacitors, etc., are considered key components; for power supply circuits, power chips, large-capacity capacitors, etc., are key components. Image recognition or data parsing technology is used to identify key components in the integrated circuit layout diagram according to the determined key component rules. Then, by parsing the coordinate information in the layout diagram, the center coordinates or other representative coordinate points of each key component are obtained and recorded in a data structure, such as an array or dictionary.

[0040] Step S320: Traverse the 3D off-center region for contour marking and extract the coordinates of the outer contour. Specifically, read relevant information from the 3D off-center region data and select a contour marking algorithm, such as an edge detection-based algorithm or a region growing-based contour extraction algorithm. Use the selected algorithm to mark the contours of the 3D off-center region, and then extract the coordinates of the outer contour. Store the extracted outer contour coordinates in a data structure, such as a linked list or array.

[0041] Step S330: Spatially map the coordinates of the key circuit components to the coordinates of the outer contour of the region to construct a region-circuit network diagram. Specifically, coordinate transformation and spatial relationship judgment methods are used to map the coordinates of the key circuit components and the outer contour coordinates of the region to the same three-dimensional spatial coordinate system. Homogeneous coordinate transformation and other methods can be used for coordinate transformation to ensure the consistency of the two coordinate systems. Determine the spatial relationship between the key circuit components and the three-dimensional deviation region, such as whether the component is located in the deviation region and its distance from the deviation region. Construct an association relationship matrix or graph structure based on these relationships. Use graph structures from graph theory to represent the association relationship between the region and the circuit components. Treat the three-dimensional deviation region and the key circuit components as nodes in the graph, and add edges according to their association relationships to construct a region-circuit network diagram.

[0042] Step S340: Perform circuit function impact analysis based on the region-circuit correlation network diagram to obtain the circuit function impact coefficient. Specifically, establish a circuit function model based on the integrated circuit design document and functional description. This model can be a circuit simulation model or a rule-based functional model, used to describe the functional relationships and signal transmission paths between various components in the circuit. Analyze the impact of the three-dimensional deviation region on the function of key circuit components. For example, for components on the signal transmission path, if the deviation region causes a change in component position or performance degradation, it will affect the signal transmission quality; for components in the power supply circuit, the deviation region will affect the stability and voltage accuracy of the power supply. Calculate the circuit function impact coefficient based on the results of the impact analysis. This coefficient can be a numerical value ranging from 0 to 1, representing the degree of influence of the deviation region on the circuit function, where 0 indicates no impact and 1 indicates a severe impact.

[0043] Step S350: Perform a region deviation impact analysis based on the region-circuit correlation network diagram to obtain the region deviation impact coefficient. Specifically, determine the indicators for evaluating the degree of deviation of the three-dimensional deviation region, such as deviation height, deviation area, and deviation curvature. These indicators can reflect the geometric characteristics of the deviation region and its impact on the overall flatness of the PCB board. Link the deviation degree evaluation indicators with the impact on PCB board performance. For example, a larger deviation height will cause gaps in the PCB board during assembly, affecting mechanical stability; a larger deviation area will affect signal transmission and heat dissipation performance. Calculate the region deviation impact coefficient based on the impact analysis and the geometric characteristics of the three-dimensional deviation region. This coefficient is also a numerical value, ranging from 0 to 1, representing the degree of influence of the deviation region on the PCB board performance.

[0044] Step S360: Based on the circuit function influence coefficient and the regional deviation influence coefficient, perform a leveling weight analysis to construct a leveling priority. Specifically, according to the importance of the circuit function and the severity of the regional deviation, assign weights to the circuit function influence coefficient and the regional deviation influence coefficient using methods such as the analytic hierarchy process (AHP) or expert scoring. For example, if the circuit function is crucial to the performance of the entire system, the weight of the circuit function influence coefficient can be set higher. Based on the assigned weights, calculate the leveling weight for each three-dimensional deviation region. The leveling weight can be calculated using a weighted summation method, i.e., leveling weight = circuit function influence coefficient × circuit function weight + regional deviation influence coefficient × regional deviation weight. Based on the magnitude of the leveling weight, sort the three-dimensional deviation regions to determine the leveling priority. Regions with larger leveling weights have higher leveling priority.

[0045] Step S370: Map and label the 3D deviation region according to the leveling priority to construct the leveling priority mapping map. Specifically, labels are made on the model or image of the 3D deviation region according to the leveling priority. Different colors, symbols, or labels can be used to represent different leveling priorities. For example, red represents high priority, yellow represents medium priority, and green represents low priority. The labeled 3D deviation region models or images are then integrated to construct the leveling priority mapping map.

[0046] In one possible implementation, the coordinates of the key circuit components are spatially mapped to the coordinates of the outer contour of the region to construct a region-circuit association network. Step S330 further includes step S331, which involves sorting adjacent points based on the outer contour coordinates of the region to generate a sequence of boundary point coordinates for geometric analysis and extraction of geometric feature parameters. Specifically, a distance-based adjacent sorting algorithm is used. For the set of outer contour coordinate points of the three-dimensional offset region, the distance between each point and other points is calculated, and the adjacent points of each point are determined in ascending order of distance. For example, for point P... i Find the distance from P i The nearest n points are taken as its neighbors, and then these neighbors are sorted according to certain rules, such as clockwise or counterclockwise, to generate a sequence of boundary point coordinates.

[0047] Geometric analysis is performed on the generated boundary point coordinate sequence to extract geometric feature parameters, including contour curvature, contour length, and contour area. Contour curvature can be obtained by calculating the curvature of the curve formed by three adjacent points in the boundary point coordinate sequence; contour length can be calculated by summing the distances between adjacent points; and contour area can be calculated using the polygon area calculation formula.

[0048] Step S332: The outer contour coordinates of the region are read according to the boundary point coordinate sequence to generate shape feature parameters. Specifically, based on the boundary point coordinate sequence, the outer contour coordinates of the region are interpolated or fitted to more accurately describe the shape of the outer contour. Linear interpolation, cubic spline interpolation, and other methods can be used to interpolate the coordinates between boundary points to obtain a denser set of coordinate points, thus more accurately reflecting the shape of the outer contour. Shape analysis is performed on the interpolated or fitted set of coordinate points to generate shape feature parameters, including surface roughness and surface undulation. For surface roughness, the standard deviation of the height difference between adjacent points in the coordinate point set can be calculated; for surface undulation, the height difference between the highest and lowest points in the coordinate point set can be calculated.

[0049] Step S333: Traverse the 3D topography model to divide it into spatial regions, generating multiple spatial mesh coding units. Specifically, a uniform mesh division method is used to divide the 3D topography model into spatial regions. First, the size of the mesh is determined. Then, based on the mesh size and the extent of the 3D topography model, the number of meshes is calculated, and a unique code is assigned to each mesh. Based on the calculated number of meshes and the coding rules, multiple spatial mesh coding units are generated. Each spatial mesh coding unit corresponds to a specific spatial region in the 3D topography model.

[0050] Step S334 involves matching the coordinates of the key circuit element with the multiple spatial grid codes, and mapping the coordinates of the key circuit element to multiple spatial grid code units based on the matching results to generate the spatial code position of the element. Specifically, for each key circuit element coordinate, the spatial grid code unit to which it belongs is determined based on its coordinate value. The specific method is to divide the value of the key circuit element coordinate by the size of the grid in the corresponding direction, and then round down to obtain the grid number of the coordinate in the three directions, thereby determining its spatial grid code unit. The key circuit element coordinates are mapped to the matched spatial grid code units, and the position information of the element in the spatial grid code unit is recorded to generate the spatial code position of the element. The spatial code position of the element can be represented as a data structure containing the element coordinates and the grid code to which it belongs.

[0051] Step S335: Perform spatial position mapping analysis on the spatial coding position of the component and the outer contour coordinates of the region according to the geometric feature parameters and the morphological feature parameters to construct the region-circuit association network diagram. Specifically, analyze the spatial position relationship between the spatial coding position of the component and the outer contour coordinates of the region by combining the geometric feature parameters and the morphological feature parameters. For example, calculate the distance between the component coordinates and the outer contour coordinates of the region, and combine parameters such as contour curvature and surface roughness to determine whether the component is located in the deviation region or has a close spatial relationship with the deviation region. Use graph structure in graph theory to represent the relationship between the region and the circuit component. Treat the three-dimensional deviation region and the key circuit component as nodes in the graph. Add edges between the nodes according to the results of the spatial position mapping analysis. The weight of the edge can be determined according to the tightness of the spatial position relationship, thereby constructing the region-circuit association network diagram.

[0052] In one possible implementation, dynamic leveling planning is performed based on the leveling priority mapping map to generate a leveling path. Step S300 further includes step S380, retrieving the performance constraints and process constraints of the leveling equipment to establish a leveling path optimization objective. Specifically, the performance parameters of the leveling equipment, including maximum moving speed, maximum acceleration, and maximum leveling pressure, are obtained from the equipment's database or configuration file. These parameters reflect the physical limitations of the equipment; for example, the maximum moving speed determines the maximum distance the equipment can move per unit time, and the maximum acceleration limits the rate of speed change during startup and shutdown. Relevant specifications and standards for the leveling process are consulted to obtain process constraints, such as the leveling temperature range, leveling time interval, and leveling cycle limit. These conditions are set to ensure leveling quality; for example, the leveling temperature range ensures that the material is leveled at a suitable temperature, avoiding changes in material properties due to excessively high or low temperatures.

[0053] The optimization objectives for the leveling path are established, with minimizing the total leveling time as the primary objective and minimizing the length of the leveling head's movement path as a secondary objective. A shorter movement path reduces equipment energy consumption and mechanical wear, while also improving leveling efficiency. The requirement for leveling quality uniformity is used as a constraint to ensure consistent leveling results across different areas, avoiding localized over- or under-leveling. Simultaneously, constraints on equipment energy consumption and mechanical wear are added, avoiding frequent acceleration and deceleration during path planning to further reduce energy consumption and mechanical wear.

[0054] Step S390: Traverse the leveling priority map according to the leveling priority to perform a maximum search and determine the starting point of the path. Specifically, a depth-first search or breadth-first search algorithm is used to traverse the leveling priority map. Depth-first search starts from the starting node and searches as deep as possible along a path until a leaf node is reached or a specific condition is met; breadth-first search starts from the starting node and searches adjacent nodes layer by layer. During the traversal, the leveling priority value of each node is compared, and the node with the highest priority is recorded as the starting point of the path. A variable can be used to store the currently found maximum priority value, and this variable is continuously updated during the traversal.

[0055] Step S3100: Perform a nearest neighbor search on the leveling priority mapping map according to the path starting point to determine the region access order. Specifically, starting from the path starting point, calculate the distance between the starting point and other surrounding nodes using Euclidean distance or other distance metrics. Select the node closest to the starting point as the next access node, and then repeat the above process with that node as the new starting point until all nodes have been accessed. Record the nearest neighbor nodes selected each time in the access order to form the region access order. This order can be stored using a list or array.

[0056] Step S3110: Based on the area access order, traverse the leveling priority mapping map to perform leveling planning and generate a leveling trajectory. Specifically, according to the area access order, determine the dwell time and leveling parameters of the leveling head in each area, such as leveling pressure and leveling time. These parameters are set according to the leveling process constraints and equipment performance constraints. Combine the movement path and dwell time of the leveling head in each area to form the leveling trajectory. Coordinate points can be used to represent the position of the leveling head, and time parameters can be used to represent the dwell time.

[0057] Step S3120: The leveling path is constructed by real-time correction of the leveling trajectory according to the leveling movement direction. Specifically, during the leveling process, sensors are used to monitor the position and movement direction of the leveling head in real time. If a deviation is found between the actual movement direction of the leveling head and the direction set in the leveling trajectory, the movement direction of the leveling head is adjusted by the control device to return it to the correct trajectory. The leveling head movement path after real-time correction is recorded to construct the final leveling path. A series of continuous coordinate points can be used to represent the leveling path.

[0058] Step S400: Execute the leveling path to monitor leveling, verify flatness based on multi-source monitoring data, obtain leveling quality parameters, backtrack to the leveling path for iterative updates, and perform adaptive leveling for the PCB board to be processed.

[0059] Specifically, the leveling equipment processes the PCB board according to the generated leveling path, leveling three-dimensional deviation areas through mechanical pressure, heat treatment, and other methods. During the leveling process, sensors monitor the movement status and processing effect of the leveling equipment in real time, acquiring multi-source monitoring data. Based on the multi-source monitoring data, the flatness of the leveled PCB board surface is verified, and the leveling quality is evaluated to determine whether it meets the preset standards. The flatness verification results are fed back, and the leveling path is iteratively updated based on the leveling quality parameters to optimize the leveling process and achieve adaptive leveling.

[0060] In one possible implementation, the leveling path is executed for leveling monitoring, and flatness verification is performed based on multi-source monitoring data to obtain leveling quality parameters. Step S400 further includes step S410, where the leveling head is controlled to move along the planned path to the PCB board to be processed for leveling monitoring, and multi-source monitoring data is obtained. Specifically, the pre-planned leveling path is input into the equipment through the control system of the leveling equipment. The control system controls the movement of the leveling head according to the path information, including parameters such as movement direction, speed, and acceleration, to ensure that the leveling head moves on the PCB board to be processed along the planned path. During the movement of the leveling head, a multi-source monitoring system composed of multiple sensors is used to monitor the leveling process in real time. For example, a laser displacement sensor is used to measure the distance between the PCB board surface and the leveling head to obtain surface height information; a pressure sensor is used to monitor the pressure applied by the leveling head to the PCB board to ensure that the pressure is within a suitable range; a vision sensor can also be used to capture images of the PCB board surface for morphology analysis. These sensors work simultaneously, transmitting the collected data to the data processing unit to form multi-source monitoring data.

[0061] Step S420: Based on the multi-source monitoring data, perform interval acquisition to obtain multiple surface morphology data. Specifically, set the acquisition interval. For example, data can be acquired at certain distances or time intervals based on the moving speed of the leveling head and the size of the PCB board. During acquisition, extract surface morphology-related information from the multi-source monitoring data, such as distance data measured by the laser displacement sensor and image data captured by the vision sensor. Process and analyze the acquired distance data and image data to generate data that can describe the surface morphology of the PCB board. For distance data, noise interference can be removed through data filtering and fitting to obtain the surface height profile; for image data, image processing algorithms, such as edge detection and feature extraction, can be used to obtain the geometric features and texture information of the surface. Combine the processed distance data and image data to form multiple surface morphology data.

[0062] Step S430: Perform real-time flatness calculation based on the multiple surface topography data and set a real-time flatness index. Specifically, process the multiple surface topography data to calculate the flatness of the PCB board surface. Methods that can be used include least squares plane fitting and calculating surface roughness parameters. For example, when using least squares plane fitting, fit multiple points from the surface topography data onto a plane, calculate the distance from each point to the plane, and then evaluate the surface flatness based on the statistical characteristics of these distances, such as the standard deviation.

[0063] Based on the requirements of the leveling process and the quality standards of the PCB board, real-time flatness indicators are set. These indicators may include the maximum permissible deviation of flatness, the upper limit of surface roughness, etc. The calculated flatness value is compared with the set indicators to determine whether the flatness of the current surface meets the requirements.

[0064] Step S440: Verify the flatness of the multi-source monitoring data according to the real-time flatness index, and generate a flatness verification evaluation result. Specifically, compare and analyze the flatness value calculated in real time with the set real-time flatness index. If the flatness value is within the allowable range of the index, the flatness verification of the current area is considered to have passed; if the flatness value exceeds the index range, the verification is considered to have failed, and the location and degree of the deviation are recorded. Based on the flatness verification result, a flatness verification evaluation report is generated, including the number of areas that passed verification, the location and deviation of areas that failed verification, and the overall flatness evaluation conclusion.

[0065] Step S450: Based on the leveling verification and evaluation results, leveling calculations are performed to generate surface flatness error and local warping. Specifically, leveling calculations are performed based on the out-of-tolerance locations and degrees recorded in the leveling verification and evaluation results. For the calculation of surface flatness error, three-dimensional coordinate measurement and fitting methods can be used to determine the deviation between the actual surface and the ideal plane; for the calculation of local warping, the location and degree of warping can be determined by analyzing local height changes and slope information in the surface morphology data. The calculated results are then organized and statistically analyzed to generate specific values ​​for surface flatness error and local warping.

[0066] Step S460: Surface roughness quality analysis is performed based on the surface flatness error to obtain the first leveling quality parameter. Specifically, the surface roughness quality is analyzed according to the magnitude and distribution of the surface flatness error, combined with relevant quality standards and specifications. Methods that can be used include calculating surface roughness parameters, such as arithmetic mean roughness, maximum profile height, etc., and comparing them with standard values. Simultaneously, the impact of surface flatness error on the electrical and mechanical properties of the PCB board can be analyzed to comprehensively evaluate the surface roughness quality. Based on the results of the surface roughness quality analysis, the first leveling quality parameter is determined. This parameter can be a comprehensive score or a classification index, such as qualified, unqualified, excellent, etc., used to reflect the quality of the surface roughness.

[0067] Step S470: Based on the local warpage, perform a quality analysis of the residual stress distribution during leveling to obtain a second leveling quality parameter. Specifically, the local warpage is related to the residual stress generated during the leveling process. By establishing a mathematical model between the local warpage and the residual stress, and using methods such as finite element analysis, the distribution of residual stress during the leveling process is simulated. Based on the simulation results, the impact of residual stress on the PCB board performance is analyzed, such as whether it will lead to board deformation, cracking, or other problems, thereby evaluating the quality of the residual stress distribution during leveling. Based on the results of the quality analysis of the residual stress distribution during leveling, the second leveling quality parameter is determined. This parameter reflects the rationality of the residual stress distribution and its degree of influence on the PCB board quality; it can also be a comprehensive scoring or classification index.

[0068] In one possible implementation, leveling calculations are performed based on the leveling verification evaluation results to generate surface flatness error and local warping. Step S450 further includes step S451, which involves traversing the leveling verification evaluation results to extract multiple verified surface leveling points from the PCB board to be processed. Specifically, the leveling verification evaluation results are scanned row by row, column by column, or according to a preset data structure order. The evaluation results contain information such as the verification status and position coordinates of each measurement point. The verification status of each point is checked, and when a verified point is found, its relevant information is recorded; these points are the surface leveling points. The coordinate information of the extracted surface leveling points is stored in a data structure, such as an array, list, or database table.

[0069] Step S452: Traverse the leveling verification evaluation results to identify local deformations and extract multiple local deformation regions. Specifically, image processing or geometric analysis-based methods are used to identify local deformation regions. For example, edge detection algorithms can be used to detect edge changes in PCB board surface topography images; areas with large edge abrupt changes indicate local deformation. Alternatively, local difference calculations can be performed on the height data of measurement points; when the difference value exceeds a set threshold, the region is considered to have local deformation. Once the location of the local deformation is identified, the boundary of the local deformation region is determined based on the distribution of the deformation points. Clustering algorithms can be used to cluster adjacent deformation points together, forming multiple local deformation regions, and the boundary coordinates or the set of points contained in each region are recorded.

[0070] Step S453: Calculate the vertical distance between the plurality of surface leveling points and the reference plane data to generate deviation data. Specifically, for each surface leveling point, calculate its vertical distance to the reference plane using the point-to-plane distance formula. Store the calculated vertical distances between each surface leveling point and the reference plane to form a deviation dataset.

[0071] Step S454: Calculate the range of the deviation data as the overall planar error value. Then, perform local planar partitioning calculations based on the overall planar error value to generate the surface flatness error. Specifically, the range of the deviation dataset refers to the difference between the maximum and minimum values ​​in the dataset. By calculating the range, the overall deviation range of the surface leveling points relative to the reference plane can be determined. Different partitioning thresholds are set based on the overall planar error value to divide the PCB board surface into multiple local planar regions. For example, the range can be divided into three intervals, each corresponding to a different flatness level region. For each local planar region, calculate the average or standard deviation of the deviation of the surface leveling points within that region as the surface flatness error index for that region. By combining the flatness error indices of each local planar region, a description of the flatness error of the entire PCB board surface is generated, which can be a comprehensive score or a regional error report.

[0072] Step S455: Based on the multiple local deformation regions, curvature calculation is performed to obtain curvature change characteristics. The multiple local deformation regions are then aggregated according to these curvature change characteristics to generate a continuous deformation region. Specifically, for each point within a local deformation region, curvature is calculated using curvature calculation formulas from differential geometry. For example, for a point on a two-dimensional surface, the degree of curvature of the surface can be described by calculating the normal curvature or principal curvature at that point. In practical applications, approximate calculation methods can be used, such as locally fitting points within the deformation region and then calculating the curvature based on the parameters of the fitted surface. The distribution of curvature within each local deformation region is analyzed, and curvature change characteristics are extracted, such as the maximum, minimum, and average curvature values, and the rate of change of curvature. These characteristics reflect the degree of curvature and the trend of change in the local deformation region. Based on the similarity of curvature change characteristics, a clustering algorithm is used to aggregate adjacent local deformation regions together. A similarity threshold is set; when the similarity of the curvature change characteristics of two local deformation regions exceeds this threshold, they are merged into a single continuous deformation region.

[0073] Step S456: Perform deformation calculations according to the continuous deformation regions to determine the warp angle and warp height. Specifically, for each continuous deformation region, establish a deformation calculation model. If the deformation region is small and the deformation degree is not significant, it can be approximated as a simple geometric deformation, such as the deformation of a triangle or quadrilateral, and the warp angle and warp height can be calculated using geometric relationships. If the deformation region is large or the deformation is complex, precise calculations can be performed using methods such as finite element analysis. For deformation regions with approximate geometric shapes, the warp angle is determined by measuring the change in the included angle of the relevant sides before and after deformation. For example, for a triangular deformation region, the change in the included angle of two sides before and after deformation is the warp angle. Determine the highest and lowest points within the deformation region and calculate the vertical distance between them as the warp height. In finite element analysis, the warp height can be calculated by extracting the displacement information of the nodes after deformation, finding the maximum and minimum displacements.

[0074] Step S457: Based on the curl angle and the warp height, a comprehensive identification is performed to determine the local curl degree. Specifically, a weighted average or other comprehensive evaluation method is used, combining the curl angle and the warp height to determine the local curl degree. Different weighting coefficients can be set for the curl angle and the warp height according to actual application needs. For example, if the curl angle is more sensitive, a larger weight can be assigned to the curl angle; if the warp height is more important, a larger weight can be assigned to the warp height. Based on the calculated results, the local curl degree is determined according to a preset curl degree level standard. The level standard can be divided into different levels such as mild curl, moderate curl, and severe curl.

[0075] In one possible implementation, the obtained leveling quality parameters are iteratively updated by tracing back to the leveling path, and adaptive leveling is performed on the PCB board to be processed. Step S400 further includes step S480, setting multi-level quality tolerance thresholds, comparing and analyzing the leveling quality parameters with the multi-level quality tolerance thresholds, and generating a leveling quality defect distribution map. Specifically, in the leveling quality evaluation system, multiple different levels of quality tolerance thresholds are pre-set based on factors such as the application scenario, performance requirements, and industry standards of the PCB board. For example, for PCB boards in high-precision electronic devices, quality tolerance thresholds of different strictness levels are set, such as Level 1, Level 2, and Level 3. Level 1 threshold is the most stringent, representing an extremely high leveling quality standard, suitable for core circuit boards with extremely high requirements for signal transmission stability and component mounting accuracy; Level 2 threshold is relatively more lenient, used for PCB boards with general performance requirements; Level 3 threshold is the most basic quality requirement, meeting the needs of some simple circuit boards with low leveling quality requirements.

[0076] The leveling quality parameters are compared and analyzed with the aforementioned multi-level quality tolerance thresholds to determine the leveling quality level and the difference between it and each threshold level. Based on the comparison analysis results, a leveling quality defect distribution map is generated. This map is presented graphically, such as using a two-dimensional or three-dimensional coordinate graph, with different colors or markers representing different levels of quality defect areas.

[0077] Step S490: Based on the leveling quality defect distribution map, determine the traversal order of the leveling path and perform an association mapping on the leveling path to determine the parameters of the leveling path to be optimized. The parameters of the leveling path to be optimized include the path optimization objective. Specifically, based on the generated leveling quality defect distribution map, determine the traversal order of the leveling path according to certain logical rules. For example, prioritize processing the areas with the most severe quality defects to ensure the leveling quality of key parts; or traverse in order from edge to center, from simple areas to complex areas. Associate the determined traversal order with the original leveling path, assigning new processing priority and order information to each point or line segment on the leveling path. Based on the association mapping, analyze and determine the parameters of the leveling path to be optimized, including the path optimization objective, such as adjusting the curvature of the path to better adapt to the shape of the quality defect area, optimizing the spacing of the path to ensure the uniformity of leveling, or changing the direction of the path to improve leveling efficiency, etc.

[0078] Step S4100: Update the leveling path according to the path optimization objective to generate an optimized leveling path. Specifically, based on the leveling path parameters and optimization objective determined in step S490, perform a substantial update operation on the original leveling path, including rerunning the path planning algorithm, using new parameter inputs, and generating a completely new leveling path through computer-aided design software or a specialized path planning tool. After the update operation, the optimized leveling path is finally obtained.

[0079] Step S4110 involves constructing a virtual environment to simulate and verify the feasibility of the leveling optimization path. Based on the verification results, the leveling optimization path is iteratively corrected, and a leveling strategy is formulated for adaptive leveling of the PCB board to be processed. Specifically, computer simulation technology is used to construct a virtual environment similar to the actual processing environment. In this virtual environment, the generated leveling optimization path is imported into the corresponding simulation model to simulate the entire process of the leveling equipment leveling the PCB board to be processed according to the path. Through simulation, various phenomena during the leveling process can be observed, such as the distribution of leveling force, material deformation, and leveling time consumption, thereby evaluating the feasibility of the leveling optimization path in practical applications. If problems are found in the leveling optimization path during the simulation verification process, such as excessive leveling force in certain areas causing damage to the PCB board, or excessive leveling time affecting production efficiency, the leveling optimization path is iteratively corrected based on these verification results. Iterative correction is a continuous optimization and improvement process. By adjusting the path parameters multiple times and re-performing simulation verification, problems in the path are gradually eliminated, making the leveling optimization path more perfect. After multiple iterations and corrections, the final leveling optimization path was determined, and a leveling strategy was formulated based on this. During actual processing, the leveling equipment adaptively leveled the PCB board to be processed according to the formulated leveling strategy, dynamically adjusting the leveling parameters based on the real-time quality feedback of the PCB board to ensure a high-quality leveling effect.

[0080] This application embodiment uses surface data of the PCB board to be processed to form a topography dataset, and establishes a three-dimensional topography model based on it. The three-dimensional topography model is used to identify three-dimensional deviations, such as warping and unevenness, and the three-dimensional deviation areas are mapped to the integrated circuit for leveling analysis. A leveling priority mapping map is set, and dynamic leveling planning is performed to generate a leveling path. Leveling monitoring is performed when the leveling path is executed, and the flatness is verified based on multi-source monitoring data. The obtained leveling quality parameters are traced back to the leveling path for iterative updates, realizing an adaptive leveling technology for the PCB board to be processed. This solves the technical problems of insufficient adaptability and accuracy of existing leveling methods used for PCB board processing in integrated circuits, and achieves the technical effect of high-precision adaptive leveling.

[0081] In the above text, refer to Figure 1A leveling method for PCB board processing in integrated circuits according to embodiments of the present invention is described in detail. Next, reference will be made to... Figure 2 A leveling system for PCB board fabrication in integrated circuits is described according to an embodiment of the present invention.

[0082] The leveling system for PCB board processing in integrated circuits according to embodiments of the present invention addresses the technical problems of insufficient adaptability and precision in existing leveling methods for PCB board processing in integrated circuits, achieving a high-precision adaptive leveling effect. The leveling system for PCB board processing in integrated circuits includes: a three-dimensional topography model establishment module 10, a three-dimensional deviation recognition module 20, a dynamic leveling planning module 30, and an adaptive leveling module 40.

[0083] The three-dimensional topography model building module 10 is used to collect surface data of the PCB board to be processed, obtain a topography dataset, and build a three-dimensional topography model of the PCB board to be processed based on the topography dataset; the three-dimensional deviation recognition module 20 is used to perform three-dimensional deviation recognition on the PCB board to be processed through the three-dimensional topography model, extract the three-dimensional deviation region, which includes warped region and uneven region; the dynamic leveling planning module 30 is used to perform leveling analysis according to the mapping of the three-dimensional deviation region to the integrated circuit, set a leveling priority mapping map, perform dynamic leveling planning based on the leveling priority mapping map, and generate a leveling path; the adaptive leveling module 40 is used to execute the leveling path to perform leveling monitoring, perform flatness verification based on multi-source monitoring data, obtain leveling quality parameters and backtrack to the leveling path for iterative updates, and perform adaptive leveling for the processing of the PCB board to be processed.

[0084] The detailed description of the specific configuration of the three-dimensional deviation recognition module 20 is explained as follows: As mentioned above, the three-dimensional deviation recognition module 20 performs three-dimensional deviation recognition on the PCB board to be processed through the three-dimensional topography model and extracts the three-dimensional deviation region. The three-dimensional deviation recognition module 20 may further include: a reference plane data setting unit for selecting multiple feature points in the four corner regions of the PCB board to be processed as reference points, fitting the reference points, and setting reference plane data; a deviation degree value acquisition unit for fitting the vertical distance between the first grid node of the three-dimensional topography model and the reference plane data to obtain the deviation degree values ​​of multiple nodes; a deviation degree distribution map generation unit for associating and storing the deviation degree values ​​of multiple nodes with the coordinate positions of the reference plane data to generate a deviation degree distribution map; and a region recognition unit for performing region recognition on the deviation degree distribution map to extract the three-dimensional deviation region.

[0085] The deviation distribution map is used for region identification to extract the three-dimensional deviation region. The region identification unit may further include: a judgment identification subunit for setting positive and negative deviation thresholds, and making judgment identifications based on the deviation distribution map and the positive and negative deviation thresholds to generate a set of potential deviation points; a region growth analysis subunit for performing region growth analysis based on the set of potential deviation points, extracting spatially adjacent potential deviation points for aggregation, and constructing a continuous deviation region; a curvature calculation subunit for traversing the continuous deviation region to perform curvature calculation, and determining a warped region based on the region curvature; a local roughness calculation subunit for traversing the continuous deviation region to perform local roughness calculation, and determining an uneven region based on the region roughness; and a region integration subunit for integrating the warped region and the uneven region to construct the three-dimensional deviation region.

[0086] The specific configuration of the dynamic leveling planning module 30 is described in detail below: As mentioned above, leveling analysis is performed by mapping the three-dimensional deviation area to the integrated circuit, a leveling priority mapping map is set, and dynamic leveling planning is performed based on the leveling priority mapping map to generate a leveling path. The dynamic leveling planning module 30 may further include: a key component identification unit for retrieving the integrated circuit layout diagram to identify key components and obtain the coordinates of key circuit components; a contour identification unit for traversing the three-dimensional deviation area to identify contours and extract the outer contour coordinates of the area; and a spatial mapping unit for mapping the coordinates of the key circuit components to the outer contour of the area. The system performs spatial mapping using contour coordinates to construct a region-circuit correlation network diagram. A circuit function impact analysis unit performs circuit function impact analysis based on the region-circuit correlation network diagram to obtain circuit function impact coefficients. A region deviation impact analysis unit performs region deviation impact analysis based on the region-circuit correlation network diagram to obtain region deviation impact coefficients. A leveling weight analysis unit performs leveling weight analysis based on the circuit function impact coefficients and the region deviation impact coefficients to construct leveling priorities. A mapping and annotation unit backtracks to the three-dimensional deviation regions according to the leveling priorities to perform mapping and annotation, constructing the leveling priority mapping diagram.

[0087] Specifically, the key circuit element coordinates are spatially mapped to the region's outer contour coordinates to construct a region-circuit association network. The spatial mapping unit may further include: an adjacent sorting subunit for sorting adjacent components based on the region's outer contour coordinates, generating a boundary point coordinate sequence for geometric analysis, and extracting geometric feature parameters; a shape reading subunit for reading the shape of the region's outer contour coordinates according to the boundary point coordinate sequence, and generating shape feature parameters; a spatial region division subunit for traversing the three-dimensional shape model to divide the space into regions, generating multiple spatial grid coding units; a component spatial coding position generation subunit for matching the key circuit element coordinates with the multiple spatial grid codes, mapping the key circuit element coordinates to the multiple spatial grid coding units according to the matching results, and generating the component spatial coding position; and a spatial position mapping analysis subunit for performing spatial position mapping analysis on the component spatial coding position and the region's outer contour coordinates according to the geometric feature parameters and the shape feature parameters, and constructing the region-circuit association network.

[0088] The dynamic leveling planning module 30, which generates a leveling path based on the leveling priority mapping map, may further include: a constraint retrieval unit for retrieving performance constraints of the leveling equipment and leveling process constraints to establish a leveling path optimization objective; a maximum value search unit for traversing the leveling priority mapping map according to the leveling priority to perform a maximum value search and determine the path starting point; a nearest neighbor search unit for performing a nearest neighbor search on the leveling priority mapping map according to the path starting point to determine the region access order; a leveling planning unit for traversing the leveling priority mapping map according to the region access order to perform leveling planning and generate a trajectory to be leveled; and a real-time correction unit for performing real-time correction according to the leveling movement direction based on the trajectory to be leveled to construct the leveling path.

[0089] The adaptive leveling module 40 is described in detail below: As mentioned above, it executes the leveling path to monitor leveling, verifies flatness based on multi-source monitoring data, and obtains leveling quality parameters. The adaptive leveling module 40 may further include: a leveling monitoring unit for controlling the leveling head to move along the planned path to monitor the leveling of the PCB board to be processed and obtain multi-source monitoring data; an interval acquisition unit for performing interval acquisition based on the multi-source monitoring data to obtain multiple surface morphology data; and a real-time flatness calculation unit for calculating the flatness based on the multiple surface morphology data. The system performs real-time flatness calculations and sets real-time flatness indices. A flatness verification unit verifies the flatness of multi-source monitoring data according to the real-time flatness indices, generating a flatness verification evaluation result. A flatness calculation unit performs flatness calculations based on the flatness verification evaluation result, generating surface flatness error and local warping. A surface roughness quality analysis unit performs surface roughness quality analysis based on the surface flatness error, obtaining a first flatness quality parameter. A flatness residual stress distribution quality analysis unit performs flatness residual stress distribution quality analysis based on the local warping, obtaining a second flatness quality parameter.

[0090] The process includes: performing leveling calculations based on the leveling verification and evaluation results to generate surface flatness error and local warping. The leveling calculation unit may further include: a surface leveling point extraction subunit for traversing the leveling verification and evaluation results to extract multiple verified surface leveling points on the PCB board to be processed; a local deformation identification subunit for traversing the leveling verification and evaluation results to identify local deformations and extract multiple local deformation regions; a vertical distance calculation subunit for calculating the vertical distance between the multiple surface leveling points and the reference plane data to generate deviation data; a local plane partitioning calculation subunit for calculating the range of the deviation data as the overall plane error value, performing local plane partitioning calculations according to the overall plane error value to generate surface flatness error; a curvature calculation subunit for performing curvature calculations based on the multiple local deformation regions to obtain curvature change characteristics, aggregating the multiple local deformation regions according to the curvature change characteristics to generate a continuous deformation region; a deformation calculation subunit for performing deformation calculations according to the continuous deformation region to determine the warping angle and warping height; and a comprehensive identification subunit for performing comprehensive identification based on the warping angle and warping height to determine the local warping.

[0091] The adaptive leveling module 40 further includes: a comparison and analysis unit for setting multi-level quality tolerance thresholds, comparing and analyzing the leveling quality parameters with the multi-level quality tolerance thresholds to generate a leveling quality defect distribution map; an association mapping unit for determining the traversal order of the leveling path according to the leveling quality defect distribution map to determine the leveling path parameters to be optimized, wherein the leveling path parameters to be optimized include the path optimization target; a leveling path update unit for updating the leveling path according to the path optimization target to generate an optimized leveling path; and a feasibility simulation verification unit for constructing a virtual environment to perform feasibility simulation verification of the optimized leveling path, iteratively correcting the optimized leveling path based on the verification results, and formulating a leveling strategy for adaptive leveling of the PCB board to be processed.

[0092] The leveling system for PCB board processing in integrated circuits provided in this embodiment of the invention can execute the leveling method for PCB board processing in integrated circuits provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the method.

[0093] Although this application makes various references to certain modules in the system according to the embodiments of this application, any number of different modules can be used and run on user terminals and / or servers. The various units and modules included are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be achieved; in addition, the specific names of each functional unit are only for easy distinction between each other and are not used to limit the scope of protection of this invention.

[0094] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application. In some cases, the actions or steps described in this application can be performed in a different order than that shown in the embodiments and still achieve the desired results. Furthermore, the processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

Claims

1. A leveling method for PCB board processing in integrated circuits, characterized in that, The method includes: Collect surface data of the PCB board to be processed to obtain a morphology dataset, and establish a three-dimensional morphology model of the PCB board to be processed based on the morphology dataset; The three-dimensional topography model is used to identify three-dimensional deviations in the PCB board to be processed, and the three-dimensional deviation areas are extracted. The three-dimensional deviation areas include warped areas and uneven areas. The three-dimensional deviation region is mapped to the integrated circuit for leveling analysis. A leveling priority mapping map is set, and dynamic leveling planning is performed based on the leveling priority mapping map to generate a leveling path. The leveling path is executed to monitor leveling, and the flatness is verified based on multi-source monitoring data. The obtained leveling quality parameters are traced back to the leveling path for iterative updates, and adaptive leveling is performed on the PCB board to be processed.

2. The leveling method for PCB board processing in integrated circuits as described in claim 1, characterized in that, The method involves using the three-dimensional topography model to identify three-dimensional deviations in the PCB board to be processed and extracting the three-dimensional deviation regions. Multiple feature points in the four corner areas of the PCB board to be processed are selected as reference points. Fitting is performed based on the reference points to set the reference plane data. The vertical distance between the first mesh node of the three-dimensional topography model and the reference plane data is fitted to obtain the deviation values ​​of multiple nodes; The deviation values ​​of multiple nodes are associated with and stored with the coordinate positions of the reference plane data to generate a deviation distribution map; The deviation distribution map is used for region identification to extract the three-dimensional deviation region.

3. The leveling method for PCB board processing in integrated circuits as described in claim 2, characterized in that, The method involves performing region identification on the deviation distribution map and extracting the three-dimensional deviation region, including: Set positive and negative deviation thresholds, and use the deviation distribution map in conjunction with the positive and negative deviation thresholds to make judgments and generate a set of potential deviation points; Based on the set of potential deviation points, a region growing analysis is performed to extract spatially adjacent potential deviation points and aggregate them to construct a continuous deviation region. The curvature is calculated by traversing the deviated continuous regions, and the warped regions are determined based on the curvature of the regions. The local roughness is calculated by traversing the deviated continuous region, and the uneven region is determined based on the region roughness. The warped region and the uneven region are integrated to construct the three-dimensional deviation region.

4. The leveling method for PCB board processing in integrated circuits as described in claim 1, characterized in that, The method involves mapping the three-dimensional deviation region to the integrated circuit for leveling analysis, setting a leveling priority mapping map, performing dynamic leveling planning based on the leveling priority mapping map, and generating a leveling path. Retrieve the integrated circuit layout diagram to identify key components and obtain the coordinates of key circuit components; Traverse the 3D off-center region to identify the contour and extract the coordinates of the outer contour of the region; The coordinates of the key circuit components are spatially mapped to the coordinates of the outer contour of the region to construct a region-circuit relationship network diagram. Based on the aforementioned region-circuit correlation network diagram, a circuit function impact analysis is performed to obtain the circuit function impact coefficient; Based on the region-circuit correlation network diagram, a region deviation impact analysis is performed to obtain the region deviation impact coefficient; Based on the circuit function influence coefficient and the area deviation influence coefficient, a leveling weight analysis is performed to construct a leveling priority. According to the leveling priority, backtrack to the three-dimensional deviation area for mapping and annotation, and construct the leveling priority mapping map.

5. The leveling method for PCB board processing in integrated circuits as described in claim 4, characterized in that, The method involves spatially mapping the coordinates of the key circuit components to the coordinates of the outer contour of the region to construct a region-circuit network diagram, including: Based on the coordinates of the outer contour of the region, adjacent points are sorted to generate a sequence of boundary point coordinates for geometric analysis, and geometric feature parameters are extracted. The shape of the outer contour coordinates of the region is read according to the boundary point coordinate sequence, and shape feature parameters are generated. The three-dimensional topography model is traversed to divide the spatial region and generate multiple spatial mesh coding units; The coordinates of the key circuit components are matched with the multiple spatial grid codes, and the coordinates of the key circuit components are mapped to multiple spatial grid code units according to the matching results to generate the spatial code position of the components. Based on the geometric feature parameters and the morphological feature parameters, a spatial position mapping analysis is performed on the spatial coding position of the component and the outer contour coordinate of the region to construct the region-circuit association network diagram.

6. The leveling method for PCB board processing in integrated circuits as described in claim 4, characterized in that, Dynamic leveling planning is performed based on the leveling priority mapping map to generate leveling paths. The method includes: Retrieve the performance constraints of the leveling equipment and the leveling process constraints, and establish the leveling path optimization objective; According to the leveling priority, the leveling priority mapping map is traversed to perform a maximum search to determine the starting point of the path; A nearest neighbor search is performed on the leveling priority mapping map according to the starting point of the path to determine the region access order; Based on the region access order, the leveling priority mapping map is traversed to perform leveling planning and generate a trajectory to be leveled. The leveling path is constructed by real-time correction of the trajectory to be leveled according to the leveling movement direction.

7. The leveling method for PCB board processing in integrated circuits as described in claim 2, characterized in that, The leveling path is executed to monitor leveling, and the flatness is verified based on multi-source monitoring data to obtain leveling quality parameters. The method includes: The leveling path control is executed to move the leveling head along the planned path to monitor the leveling of the PCB board to be processed and obtain multi-source monitoring data. Multiple surface morphology data are obtained by collecting data at intervals based on the multi-source monitoring data. Real-time flatness calculation is performed based on the multiple surface morphology data, and real-time flatness index is set; The flatness of the multi-source monitoring data is verified according to the real-time flatness index, and a flatness verification evaluation result is generated. Based on the leveling verification and evaluation results, leveling calculations are performed to generate surface flatness error and local warping. Surface roughness quality analysis is performed based on the surface flatness error to obtain the first leveling quality parameter; Based on the local warping, a quality analysis of the residual stress distribution during leveling is performed to obtain the second leveling quality parameter.

8. The leveling method for PCB board processing in integrated circuits as described in claim 7, characterized in that, Based on the leveling verification and evaluation results, leveling calculations are performed to generate surface flatness error and local warping. The method includes: Extract multiple surface leveling points that have passed verification from the PCB board to be processed by traversing the leveling verification and evaluation results; The local deformation is identified by iterating through the leveling verification and evaluation results, and multiple local deformation areas are extracted. Calculate the vertical distance between the plurality of surface leveling points and the reference plane data to generate deviation data; The range of the deviation data is calculated as the overall plane error value. Local plane partitioning is then calculated according to the overall plane error value to generate the surface flatness error. Curvature calculation is performed based on the multiple local deformation regions to obtain curvature change characteristics. The multiple local deformation regions are then aggregated according to the curvature change characteristics to generate a continuous deformation region. Deformation calculations are performed based on the continuous deformation region to determine the curling angle and warping height. The local curl degree is determined by comprehensively identifying the curl angle and the curl height.

9. The leveling method for PCB board processing in integrated circuits as described in claim 1, characterized in that, The method involves obtaining leveling quality parameters, iterating back along the leveling path, and performing adaptive leveling for the PCB board to be processed. The method includes: A multi-level quality tolerance threshold is set, and the leveling quality parameters are compared and analyzed with the multi-level quality tolerance threshold to generate a leveling quality defect distribution map. Based on the leveling quality defect distribution map, the traversal order of the leveling path is determined, and the leveling path is associated and mapped to determine the leveling path parameters to be optimized. The leveling path parameters to be optimized include the path optimization target. The leveling path is updated according to the path optimization objective to generate an optimized leveling path; A virtual environment is constructed to conduct feasibility simulation verification of the leveling optimization path. Based on the verification results, the leveling optimization path is iteratively corrected, and a leveling strategy is formulated to adaptively level the PCB board to be processed.

10. A leveling system for PCB board processing in integrated circuits, characterized in that, The system is used to implement the leveling method for PCB board processing in integrated circuits as described in any one of claims 1-9, the system comprising: The three-dimensional topography model building module is used to collect surface data of the PCB board to be processed, obtain a topography dataset, and build a three-dimensional topography model of the PCB board to be processed based on the topography dataset. The three-dimensional deviation recognition module is used to perform three-dimensional deviation recognition on the PCB board to be processed through the three-dimensional topography model, and extract the three-dimensional deviation area, which includes warped area and uneven area; The dynamic leveling planning module is used to perform leveling analysis by mapping the three-dimensional deviation area to the integrated circuit, set a leveling priority mapping map, perform dynamic leveling planning based on the leveling priority mapping map, and generate a leveling path. The adaptive leveling module is used to perform leveling monitoring on the leveling path, verify flatness based on multi-source monitoring data, obtain leveling quality parameters, backtrack to the leveling path for iterative updates, and perform adaptive leveling on the PCB board to be processed.

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