MPSoC multi-interface large-capacity data recording device based on Beidou positioning time service

Abstract

The invention discloses an MPSoC multi-interface large-capacity data recording device based on Beidou positioning time service, and relates to the technical field of data recording, the MPSoC multi-interface large-capacity data recording device comprises a data base plate, a core plate, a storage module and a Beidou module, and each module is connected with the data base plate through a connector; the Beidou module communicates with the core board through two serial ports and one GPIO, and communicates with a satellite antenna through a radio frequency cable; a plurality of monitoring serial ports are preset on the data base plate and used for being connected with monitored equipment, and a plurality of network ports are preset on the data base plate and used for being connected with an upper computer and monitoring network port equipment. When the device works, space-time information is obtained through the Beidou module, a hardware-level timestamp is generated in combination with a high-resolution counter in the core board, multi-source data summarization labeling is achieved, the labeled data are reported to an upper computer in real time and written into the storage module through the high-speed storage interface, and the data are stored in the storage module. The problems of multi-protocol concurrence bottleneck, time jitter ultramicro-second and insufficient storage bandwidth in the prior art are solved.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of data recording, and in particular to an MPSoC multi-interface large-capacity data recording device based on Beidou positioning and timing. BACKGROUND

[0002] With the rapid development of industrial internet and intelligent devices, various field devices have higher requirements for accurate recording of high-speed, multi-source and long-term data. For example, in scenarios such as rail transit, seismic exploration, oil and gas logging and military testing, it is often necessary to continuously collect multi-channel signals in harsh environments and assign a unified time reference to each piece of data.

[0003] The prior art still has the following common deficiencies: 1) MCU or single-core SoC is mostly used as the main control, and such a controller is difficult to simultaneously bear multi-protocol concurrent collection due to limited bus bandwidth, and is prone to data packet loss and serial bottlenecks; 2) the network NTP or external timing module is mostly relied on, and due to the lack of hardware-level timestamp cooperation, the sampling data is still mainly marked with time in the user state by the operating system, and the jitter is difficult to compress to below microseconds; in addition, the positioning information is usually recorded in a low-frequency manner, and real-time spatial annotation of high-speed sampling data cannot be realized, which brings errors to the subsequent data alignment and event positioning; 3) the existing products still use eMMC, SD card or small-capacity SATA SSD, and the continuous writing bandwidth and service life are limited, and in the field scene without network backhaul, TB-level long-time lossless recording cannot be supported. SUMMARY

[0004] Therefore, the application provides an MPSoC multi-interface large-capacity data recording device based on Beidou positioning and timing to solve the deficiencies in the prior art.

[0005] The first aspect of the application provides an MPSoC multi-interface large-capacity data recording device based on Beidou positioning and timing, which comprises a data backplane, a core board, a storage module and a Beidou module. The core board, the storage module and the Beidou module are connected with the data backplane through connectors; the Beidou module is connected with the core board through two serial ports and one GPIO, and is connected with a Beidou antenna through a radio frequency cable; the core board is connected with the storage module through a high-speed storage interface; the data backplane is provided with a plurality of monitoring serial ports for connecting with monitored devices, and a plurality of network ports for connecting with upper computers and monitoring network port devices.

[0006] In a possible implementation manner of the first aspect, a power module is integrated on the data backplane, and the power module cooperates with a plurality of synchronous step-down voltage stabilizers to provide power for the core board, the Beidou module and the storage module.

[0007] In a possible implementation manner of the first aspect, the data backplane is further pre-arranged with high-speed differential lines and multi-layer signal channels.

[0008] In a possible implementation manner of the first aspect, the core board is an MPSoC core board, and the storage module is a solid state disk.

[0009] In a possible implementation manner of the first aspect, the MPSoC core board integrates a heterogeneous processor and programmable logic, and runs a Linux operating system.

[0010] In a possible implementation manner of the first aspect, the MPSoC core board further integrates a high-resolution counter, which counts at a clock frequency of 100 MHz.

[0011] In a possible implementation manner of the first aspect, the solid state disk is a standard M.2 NVMe solid state disk.

[0012] In a possible implementation manner of the first aspect, data recording of the monitored device by the device includes: powering on and initializing; after the Beidou module receives satellite signals, continuously sending satellite messages to the MPSoC core board through two serial ports, and sending a configurable PPS pulse to the MPSoC core board through a GPIO; the MPSoC core board receives and parses the satellite messages to obtain time information and location information; and the MPSoC core board empties the high-resolution counter after receiving the configurable PPS pulse each time; network connection is established between the network port and the host computer to establish a data reporting channel and an instruction receiving channel; the plurality of monitoring serial ports each receive data of the monitored device and parse the data, and simultaneously cache the parsed data to the memory of the MPSoC core board; the MPSoC core board triggers multi-source data aggregation according to the frequency of the configurable PPS pulse, and integrates the cached data of the plurality of monitoring serial ports into a multi-source data frame; the time information is obtained and combined with the current count value of the high-resolution counter to generate a hardware-level timestamp, and the hardware-level timestamp is bound to the location information to uniformly label the multi-source data frame; the labeled multi-source data frame is sent to the host computer through the network port for display and monitoring, and is temporarily stored in the cache of the MPSoC core board, and after accumulation to a preset number, is written in batches to the solid state disk through the high-speed storage interface; The MPSoC core board reports the device running state to the upper computer in real time through a network port, and sends an alarm message to the upper computer if an abnormality is detected; The MPSoC core board listens to the instructions issued by the upper computer in real time and executes the instructions, and after listening to a stop instruction, saves all cached data to the solid state disk and then exits safely.

[0013] In a possible implementation of the first aspect, the data backplane is further provided with a compatible card slot, and the compatible card slot is used to install a new storage module.

[0014] In a possible implementation of the first aspect, the number of monitoring serial ports is 6, and the number of network ports is 2.

[0015] Beneficial effects of the present application are as follows: the present application discloses an MPSoC multi-interface large-capacity data recording device based on Beidou positioning and timing, which comprises a data backplane, a core board, a storage module and a Beidou module, and each module is connected with the data backplane through a connector; the Beidou module communicates with the core board through two serial ports and one GPIO, and communicates with a satellite antenna through a radio frequency cable; the data backplane is provided with a plurality of monitoring serial ports for connecting monitored devices, and a plurality of network ports for connecting an upper computer and monitoring network port devices; when the device works, the Beidou module is used to obtain space-time information, a hardware-level time stamp is generated by combining a high-resolution counter in the core board, multi-source data is collected and labeled, the labeled data is reported to the upper computer in real time and written into the storage module through a high-speed storage interface, and the pain points of the prior art, such as multi-protocol concurrent bottleneck, time jitter less than microseconds and insufficient storage bandwidth, are solved. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0017] Figure 1 It is a schematic diagram of an MPSoC multi-interface large-capacity data recording device based on Beidou positioning and timing provided by the present application. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0019] In this application, relational terms such as first and second and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0020] Embodiment In the scenarios of rail transportation, seismic exploration, oil and gas well logging, and military testing, higher requirements are put forward for accurate recording of high-speed, multi-source, and long-time data. These scenarios often need to continuously collect multi-channel signals in harsh environments and assign a unified time reference to each piece of data to meet the needs of later data alignment, event positioning, and analysis. However, the current mainstream data recording technical solutions have obvious shortcomings in adapting to such needs and have failed to effectively address the core demands of concurrent collection of multi-source data, time and space synchronization accuracy, and long-time storage capacity.

[0021] Therefore, the application provides an MPSoC multi-interface large-capacity data recording device based on Beidou positioning and timing, as shown in Figure 1 which comprises a data backplane, a core board, a storage module, and a Beidou module. The core board, the storage module, and the Beidou module are all connected with the data backplane through connectors. The Beidou module is connected with the core board through two serial ports and one GPIO and is connected with a Beidou antenna through a radio frequency cable. The core board is connected with the storage module through a high-speed storage interface. The data backplane is provided with a plurality of monitoring serial ports for connecting with monitored devices and a plurality of network ports for connecting with upper computers and monitoring network port devices.

[0022] The embodiment provides an MPSoC multi-interface large-capacity data recording device based on Beidou positioning and timing, which comprises a data backplane, a core board, a storage module, and a Beidou module. The core board, the storage module, and the Beidou module are all connected with the data backplane through connectors. The Beidou module is connected with the core board through two serial ports and one GPIO and is connected with a Beidou antenna through a radio frequency cable to receive satellite signals. The core board is connected with the storage module through a high-speed storage interface. The data backplane is further provided with a plurality of monitoring serial ports and a plurality of network ports. Next, all the modules of the data recording device are described in detail, specifically as follows: Core board: MPSoC core board is adopted, which integrates heterogeneous processors (processing system PS) and programmable logic (PL), and runs Linux operating system; 8-way UART controller is implemented on the PL side, which is used for high-speed serial communication with peripherals, and 2-way gigabit Ethernet controller is provided on the PS side to access network data sources; in addition, a high-resolution counter is integrated, which counts at a clock of 100Mhz; Beidou module: satellite messages are transmitted to the core board through two serial ports, and a configurable PPS pulse of 1Hz-10Hz is output to the core board through a GPIO, which enters the hardware timestamp logic of the core board. The hardware timestamp logic drives the high-resolution counter based on the configurable PPS pulse, and labels the data frames arriving at all serial ports and network ports with hardware time, achieving nanosecond-level synchronization; Data board: integrated with a power module, supporting 28V DC power supply, providing 12V, 5.5V and 3.3V sub-power to MPSoC core board, Beidou module and storage module through multiple synchronous voltage stabilizers; the bottom layer is also pre-laid with high-speed differential lines and multi-layer signal channels, including PCIe lines, eight serial ports, two gigabit Ethernet and a number of spare EMIO pins, which are all connected with the core board through an inter-board connector, and then uniformly led out on the surface of the data board for easy plug-and-play of peripherals; Storage module: standard M.2 NVMe solid state disk is adopted, which is directly mounted to the PCIe controller of the MPsoc core board through the PCIe high-speed channel laid on the data board, realizing a continuous writing capacity of more than 500MB / s; the data board also has a compatible card slot compatible with 2280 / 2240 size, supporting users to replace larger capacity or higher performance solid state disks as needed, so as to flexibly extend the offline collection time.

[0023] Further, the data recording device further comprises a case, which is provided with a special heat dissipation channel for dissipating heat of the data recording device.

[0024] Specifically, the data recording device in the embodiment is used for data recording, and the steps are as follows: Power-on and initialization operation: automatically load the locally pre-stored parameter configuration, including serial port parameters (such as baud rate, data bits), data segmentation parameters (such as the number of threshold values for cache start writing), etc.; open 8-way RS422 port, start serial port information monitoring thread, and ensure real-time capture of monitored device data; check the integrity of the solid state disk data directory, and if the directory is damaged, automatically rebuild it to avoid storage abnormalities; Positioning and timing: After receiving satellite signals through the satellite antenna, the Beidou module continuously sends satellite messages to the MPSoC core board through two serial ports. The core board analyzes the satellite messages to obtain current time information (millisecond-level time) and position information (latitude and longitude position). The Beidou module sends a configurable PPS pulse (hardware interrupt signal) to the MPSoC core board through a GPIO. After receiving the configurable PPS pulse, the MPSoC core board clears the high-resolution counter once. The core board has a built-in 100Mhz clock-driven high-resolution counter (1 clock cycle = 10 nanoseconds, count +1 per cycle). Each time an interrupt is received, it is immediately cleared and re-counted. Finally, the nanosecond-level reference time is calculated by "Beidou millisecond time + counter value x 10 nanoseconds"; Network establishment: Through two network ports, network connection is established with the upper computer and network port monitoring equipment, and data reporting channel (transmitting collected multi-source data) and instruction receiving channel (receiving control instructions from the upper computer) are built. After successful connection, the core board sends a device ready signal to the upper computer to confirm that the channel is normal. Data collection and labeling: Six serial ports each receive data from the monitored device and perform analysis, temporarily storing it in the MPSoC core board's memory. Based on the configurable PPS pulse frequency of the Beidou module (supporting 1Hz~10Hz configurable), the core board triggers multi-source data aggregation, integrating the buffered data from the six serial ports into one multi-source data frame. The aggregated multi-source data frame is labeled with time (nanosecond-level accurate time determined by the positioning and timing step) and position (latitude and longitude). The aggregated and labeled multi-source data frame is uploaded to the upper computer for display and monitoring through the network port, and is temporarily stored in the core board for buffering. When the buffer reaches the preset number, the data is written in bulk to the solid state drive through the high-speed NVMe interface. The solid state drive uses a rolling storage mechanism, automatically deleting the oldest historical data when the remaining space is insufficient, ensuring continuous writing of new data without interrupting the collection process. Monitoring and alarm: The core board reports the device's running status to the upper computer in real time through the network port. When an anomaly is detected, an alarm message is sent to the upper computer. Control instruction issuance: The core board listens to and executes instructions from the upper computer in real time through the network port. Stop and shutdown: When a stop instruction from the upper computer is detected, the collection and reporting of new data are immediately stopped, and all buffered data is written to the solid state drive to avoid data loss. Finally, the system exits safely.

[0025] The embodiment utilizes the configurable PPS pulse output by the Beidou module to construct a unified hardware time reference, combines the hardware time logic of the MPSoC core board, generates hardware-level time stamps for the collected data of 8 serial ports and 2 network ports, finally compresses the time error of data of different interfaces to the nanosecond level, and completely solves the problems of inconsistency of multi-source data and complexity of post-alignment in the traditional scheme; while time stamping the data, the real-time latitude and longitude information of the Beidou module is also encapsulated into the same data frame, so that each data record carries dual identification of occurrence time + occurrence location, further ensuring the natural alignment of multi-source data.

[0026] The PPS pulse in the embodiment is configurable, and the PPS pulse frequency of 1Hz~10Hz can be selected according to the scene requirements, so as to balance between synchronization accuracy and device power consumption; the EMIO pin and the standby PCIe channel are reserved on the data board, and additional serial ports, industrial buses or GbE high-speed network ports can be expanded through the plug-in board in the later stage, without the need to change the existing hardware logic and software architecture, thereby reducing the upgrade cost; the collected data is sequentially written into the NVMe solid state disk through the MPSoC core board, and the writing speed can reach 250~350MB / s at most; the DC-DC and heat conduction channel are integrated on the data floor, so as to ensure that the long-time full-speed writing does not reduce the frequency under high-temperature working conditions.

[0027] The two serial ports and one GPIO between the Beidou module and the core board in the embodiment are designed, and the spatiotemporal precision labeling is realized through the cooperative mode of data transmission and synchronous triggering; after receiving the satellite signal, the Beidou module continuously transmits the satellite message to the core board through the two serial ports, the core board analyzes the satellite message to obtain the millisecond-level time and latitude and longitude position, and provides the basic spatiotemporal information for data labeling; after receiving the configurable PPS pulse, the Beidou module sends a hardware interrupt signal to the core board through the GPIO, triggers the 100Mhz counter of the core board to clear and re-count, and improves the time accuracy from the millisecond level of the Beidou message to the nanosecond level; the cooperative logic is that when the core board collects 6 serial port data, the accurate time stamp is generated by combining the Beidou millisecond time and the counter nanosecond value, and the latitude and longitude information is associated, so that each multi-source data frame is labeled with time + position dual label, and finally the spatiotemporal precise labeling of data is realized.

[0028] The hardware of the embodiment relies on the 100MHz clock driven high-resolution counter (1 clock cycle = 10 nanoseconds, +1 per cycle) built in the MPSoC core board to achieve nanosecond-level timing, and the logic is triggered by the configurable PPS pulse of the Beidou module. The GPIO sends a hardware interrupt to the core board every time the Beidou module sends a configurable PPS pulse. After receiving the interrupt signal, the core board immediately clears the counter and starts counting again. Finally, the nanosecond-level time is calculated by "Beidou millisecond time + counter value x 10 nanoseconds". The traditional millisecond-level timing cannot meet the time differentiation requirements of high-speed multi-source data, which may cause multiple sets of data in the same millisecond to be time-stamped repeatedly. However, nanosecond-level timing can finely differentiate all data within the same PPS cycle, ensuring that each piece of data has a unique timestamp, and completely solving the problem of time overlap and difficulty in later alignment in existing multi-source data recording technology.

[0029] In some embodiments, a power module is integrated on the data backplane, which cooperates with the multi-channel synchronous step-down voltage regulator to provide power for the core board, the Beidou module, and the storage module.

[0030] In some embodiments, high-speed differential lines and multi-layer signal channels are also pre-arranged on the data backplane.

[0031] In some embodiments, the core board uses an MPSoC core board, and the storage module uses a solid-state drive.

[0032] In some embodiments, the MPSoC core board integrates heterogeneous processors and programmable logic, and runs a Linux operating system.

[0033] In some embodiments, a high-resolution counter is also integrated on the MPSoC core board, which counts at a clock speed of 100MHz.

[0034] In some embodiments, the solid-state drive is a standard M.2 NVMe solid-state drive.

[0035] In some embodiments, the device is used for data recording of monitored equipment, including: Power-on and initialization operations are performed; When the Beidou module receives satellite signals, it continuously sends satellite messages to the MPSoC core board through two serial ports, and sends a configurable PPS pulse to the MPSoC core board through a GPIO; The MPSoC core board receives and parses the satellite messages to obtain time and location information. The MPSoC core board clears the high-resolution counter every time it receives the configurable PPS pulse; The network port is used to establish a network connection with the host computer, establish a data reporting channel and an instruction receiving channel; The plurality of monitoring serial ports each receive data of the monitored device and analyze the data, and simultaneously cache the analyzed data to the memory of the MPSoC core board; The MPSoC core board triggers multi-source data aggregation according to the frequency of the configurable PPS pulse, and integrates the cached data of the plurality of monitoring serial ports into a multi-source data frame; The time information is acquired and combined with the current counting value of the high-resolution counter to generate a hardware-level timestamp, and the hardware-level timestamp is bound with the position information to uniformly label the multi-source data frame; The labeled multi-source data frame is sent to the host computer through the network port for display monitoring, and is temporarily stored in the cache of the MPSoC core board, and after accumulation to a preset number, is written in batches to the solid state disk through the high-speed storage interface; The MPSoC core board reports the device running state to the host computer in real time through the network port, and sends an alarm message to the host computer if an abnormality is detected; The MPSoC core board listens to the instructions issued by the host computer in real time through the network port and executes the instructions, and after listening to a stop instruction, saves all cached data to the solid state disk and then safely exits.

[0036] In some embodiments, the data backplane is further provided with a compatible card slot for installing a new storage module.

[0037] In some embodiments, the number of monitoring serial ports is 6, and the number of network ports is 2.

[0038] Those skilled in the art will further appreciate that the units and algorithm steps of each example described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or combinations of both. To clearly illustrate the interchangeability of hardware and software, various aspects of examples have been described generally in terms of their functionality without loss of generality. Whether such functionality is implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. Skilled persons can implement the described functionality in varying ways for each particular application, but such implementation should not be construed as a departure from the scope of the present application.

[0039] Although the preferred embodiments of the present application have been described, those skilled in the art who have the basic inventive concept can make further changes and modifications to the embodiments. Therefore, the appended claims are intended to include the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0040] Obviously, many modifications and variations of the present application are possible in light of the above teachings. It is, therefore, to be understood that within the scope of the appended claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. A multi-interface mass data recording device based on Beidou positioning and timing of MPSoC, characterized in that, The data backboard, the core board, the storage module and the Beidou module are included. The core board, the storage module and the Beidou module are connected with the data backboard through connectors; the Beidou module is connected with the core board through two serial ports and a GPIO, and is connected with a Beidou antenna through a radio frequency cable; the core board is connected with the storage module through a high-speed storage interface; the data backboard is provided with a plurality of monitoring serial ports for connecting with monitored devices, and a plurality of network ports for connecting with a host computer and a monitoring network port device.

2. The MPSoC multi-interface mass data recording device based on Beidou positioning and timing according to claim 1, characterized in that, The data backboard is integrated with a power module, which cooperates with a plurality of synchronous voltage stabilizers to provide power for the core board, the Beidou module and the storage module. 3.The MPSoC multi-interface mass data recording device based on Beidou positioning and timing of claim 1, wherein, The data backboard is also pre-arranged with high-speed differential lines and multi-layer signal channels.

4. The MPSoC multi-interface mass data recording device based on Beidou positioning and timing according to claim 1, characterized in that, The core board adopts an MPSoC core board, and the storage module adopts a solid state disk.

5. The MPSoC multi-interface mass data recording device based on Beidou positioning and timing according to claim 4, characterized in that, The MPSoC core board is integrated with a heterogeneous processor and programmable logic, and runs a Linux operating system.

6. The MPSoC multi-interface mass data recording device based on Beidou positioning and timing according to claim 4, characterized in that, The MPSoC core board is also integrated with a high-resolution counter, which counts at a clock of 100 MHz.

7. The MPSoC multi-interface mass data recording device based on Beidou positioning and timing according to claim 4, characterized in that, The solid state disk is a standard M.2 NVMe solid state disk.

8. The MPSoC multi-interface mass data recording device based on Beidou positioning and timing according to claim 6, characterized in that, Data recording of the monitored devices by the device includes: powering on and initializing; after the Beidou module receives satellite signals, continuously sending satellite messages to the MPSoC core board through two serial ports, and sending a configurable PPS pulse to the MPSoC core board through a GPIO; the MPSoC core board receives and parses the satellite messages to obtain time information and position information; the MPSoC core board empties the high-resolution counter after receiving the configurable PPS pulse each time; network connection is established between the network port and the host computer to establish a data reporting channel and an instruction receiving channel; a plurality of monitoring serial ports each receive data of a monitored device and parse the data, and simultaneously cache the parsed data to the memory of the MPSoC core board; the MPSoC core board triggers multi-source data aggregation according to the frequency of the configurable PPS pulse, and integrates the cached data of the plurality of monitoring serial ports into a multi-source data frame; the time information is obtained and combined with the current count value of the high-resolution counter to generate a hardware-level timestamp, which is bound with the position information to uniformly label the multi-source data frame; the labeled multi-source data frame is sent to the host computer through the network port for display and monitoring, and is temporarily stored in the cache of the MPSoC core board, and after accumulating to a preset number, is written in batches to the solid state disk through the high-speed storage interface; the MPSoC core board reports the device running status to the host computer in real time through the network port, and sends an alarm message to the host computer if an abnormality is detected; the MPSoC core board listens to the instructions issued by the host computer in real time through the network port and executes the instructions, and after listening to a stop instruction, saves all cached data to the solid state disk and then safely exits.

9. The MPSoC multi-interface mass data recording device based on Beidou positioning and timing according to claim 1, characterized in that, The data backboard is further provided with a compatible card slot, which is used for installing a new storage module.

10. The MPSoC multi-interface mass data recording device based on Beidou positioning and timing according to claim 1, characterized in that, The number of monitoring serial ports is 6, and the number of network ports is 2.

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