Neural signal acquisition chip integrated with electrical stimulation function and method
By integrating signal acquisition and stimulation modules onto a CMOS chip and combining them with artifact elimination technology, the problem of independent existence of the signal acquisition unit and stimulator was solved, realizing a high-precision, low-power bidirectional brain-computer interface and improving the accuracy of signal acquisition and the real-time performance of control.
Patent Information
- Application Number
- CN202511052546.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-29
- Publication Date
- 2025-11-11
AI Technical Summary
In existing technologies, the signal acquisition unit and the stimulator are two independent unidirectional brain-computer interfaces, which have problems such as inaccurate measurement, large size, high power consumption, and inability to achieve real-time closed-loop control.
The signal acquisition unit and stimulator are integrated on a single CMOS chip, including a signal acquisition module, a signal processing module, a stimulation control module, a stimulation module, and an artifact elimination module, to achieve real-time closed-loop control and eliminate artifacts generated by electrical stimulation through an adaptive filter.
It achieves a high-precision, low-power bidirectional brain-computer interface, reducing surgical trauma, improving the accuracy of signal acquisition and the real-time performance of control, and reducing noise interference.
Smart Images
Figure CN120918665A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of brain-computer interfaces, and more particularly to a neural signal acquisition chip and method with integrated electrical stimulation function. Background Technology
[0002] Brain-computer interfaces (BCIs) are technologies that enable direct information exchange between the brain and external devices (such as computers, prosthetics, and robots) without relying on conventional neuromuscular pathways. Traditional BCIs unidirectionally acquire partial brain information and are mainly used to record and analyze neural activity, thereby enabling the brain to control external devices or monitor neural activity. In recent years, electrical stimulation technology has shown promising prospects in functional recovery and assisted control. Correspondingly, another type of BCI unidirectionally inputs electrical stimulation signals to the brain. Electrical stimulation technology can also be implemented using both invasive and non-invasive BCIs.
[0003] One current approach involves using a non-invasive brain-computer interface (BCI) to continuously collect neural signals (EEG) from the patient. These signals are then continuously monitored, and when specific signal characteristics are identified, invasive electrical stimulation is applied to the BCI to achieve the desired effect. However, this approach requires the patient to wear a head-mounted neural signal acquisition device, causing inconvenience. Furthermore, the neural signals acquired by non-invasive devices are significantly affected by environmental factors, resulting in high levels of noise and inaccurate identification of specific features.
[0004] However, if an invasive brain-computer interface (BCI) is implanted to collect neural signals (EEG), and another invasive BCI is implanted simultaneously to electrically stimulate the brain, craniotomy is required to implant the two BCI devices into specific areas of the cerebral cortex or deep within the brain. The surgical trauma and risks involved cannot be ignored.
[0005] To simultaneously meet the three requirements of accurate signal acquisition, bidirectional communication with the brain, and minimal surgical trauma, it is necessary to integrate the signal acquisition unit and stimulator onto a single chip for invasive or semi-invasive implantation into the brain. This approach offers three advantages over implanting the signal acquisition unit and stimulator separately: First, a closed-loop control module can be integrated onto the same chip, enabling real-time closed-loop control of the stimulator based on the acquired neural signals. Second, it reduces the number of surgical incisions, requiring implantation at only one target location. Third, by minimizing the number of interconnects between the signal acquisition unit and stimulator, it reduces area and power consumption, and also mitigates the noise issues introduced by multi-chip solutions.
[0006] However, integrating the signal acquisition unit and stimulator into a single chip presents two challenges. First, integrating the signal acquisition unit and stimulator into a single chip introduces artifacts to the acquired neural signals with each electrical stimulation, affecting the final output neural signal. Second, current technologies rely on off-chip high-voltage power supplies or large-capacity charge pumps, requiring low-frequency switching and large capacitors, resulting in excessively large chip sizes and thus causing greater tissue damage.
[0007] The above information is presented as background information only to aid in understanding this disclosure. No confirmation or other representation is made regarding whether any of the above constitutes an application of prior art to this disclosure. Summary of the Invention
[0008] The embodiments disclosed herein address the problems of inaccurate measurement, large size, high power consumption, and inability to achieve real-time closed-loop control inherent in existing technologies where the signal acquisition unit and stimulator are treated as two independent unidirectional brain-computer interfaces. A bidirectional brain-computer interface chip is provided that not only integrates signal acquisition and electrical stimulation functions but also achieves real-time closed-loop control and eliminates signal artifacts generated by electrical stimulation. Furthermore, a miniaturization scheme for the electrical stimulator is provided.
[0009] The first aspect of this disclosure provides a neural signal acquisition chip with integrated electrical stimulation function, including a signal acquisition module, a signal processing module, a stimulation control module, a stimulation module, and an artifact elimination module integrated on a single CMOS chip; the signal acquisition module is connected to the signal processing module and configured to acquire raw neural signals and transmit them to the signal processing module; the signal processing module is connected to the signal acquisition module, the stimulation control module, the artifact elimination module, and a signal output terminal respectively, and is configured to receive the raw neural signals, process them to obtain actual neural signals, and output them to the stimulation control module and the signal output terminal; the stimulation control module is connected to the signal processing module, the stimulation module, and the artifact elimination module. The system is configured to output a stimulation command to the stimulation module and stimulation parameters to the artifact elimination module when specific information is extracted from the actual neural signal. The stimulation module is connected to an electrical input terminal, the stimulation control module, and an electrical output terminal, and is configured to receive a low-voltage electrical signal from the electrical input terminal and output a high-voltage electrical stimulation signal to the electrical output terminal according to the stimulation command. The artifact elimination module is connected to the stimulation control module and the signal processing module, and is configured to obtain an artifact cancellation signal based on the stimulation parameters and output it to the signal processing module. The signal processing module is further configured to cancel artifacts in the original neural signal based on the artifact cancellation signal and output the actual neural signal after artifact cancellation.
[0010] For example, in at least one embodiment, the integrated communication module on the monolithic CMOS chip, the communication module being connected to the signal processing module and the stimulation control module, is configured to output the actual neural signals and the stimulation parameters to the outside of the chip, and to receive update information of the stimulation control model; the update information is obtained by an artificial intelligence algorithm based on dynamic optimization of the actual neural signals and the stimulation parameters.
[0011] For example, in at least one embodiment, the signal acquisition module includes multiple signal input terminals, a multi-channel encoder, and a capacitor-to-analog converter; the signal processing module includes a front-end amplifier, an analog-to-digital converter, and a recorder.
[0012] For example, in at least one embodiment, the stimulation module includes two cross-coupled NMOS pairs, two LC oscillation networks, two high-voltage adapters, and one current controller; the cross-coupled NMOS pairs are connected to the electrical input terminal, receive low-voltage electrical signals from the electrical input terminal, and generate negative impedance to compensate for the resistive losses of the LC oscillation network; the LC oscillation network is connected to the cross-coupled NMOS pairs and generates a high self-resonant frequency oscillation signal; the LC oscillation network is sequentially connected to the high-voltage adapters and the current controller.
[0013] For example, in at least one embodiment, the artifact cancellation module includes: an adaptive filter and a random access memory; the adaptive filter has a preset response model and outputs the artifact cancellation signal based on the stimulus parameters and filter coefficients; the random access memory stores the filter coefficients.
[0014] For example, in at least one embodiment, the adaptive filter includes an adaptive digital feedback loop. After an electrical stimulation signal is emitted, the adaptive filter obtains an artifact prediction value based on filter coefficients stored in a random access memory, calculates an artifact prediction error based on the artifact prediction value and the original neural signal, updates the filter coefficients based on the artifact prediction error, and obtains the artifact cancellation signal based on the updated filter coefficients. The random access memory stores the updated filter coefficients and replaces the filter coefficients before the update.
[0015] The first aspect of this disclosure provides a method for acquiring neural signals with integrated electrical stimulation function, including the following steps performed on a monolithic CMOS chip:
[0016] Continuously collect raw neural signals, process the raw neural signals, and obtain actual neural signals;
[0017] The actual neural signals are continuously extracted, and when specific information is extracted, stimulation instructions and stimulation parameters are output.
[0018] According to the stimulation command, a low-voltage electrical signal is received at the electrical input terminal, and a high-voltage electrical stimulation signal is output to the electrical output terminal.
[0019] Based on the stimulation parameters, an artifact cancellation signal is obtained;
[0020] Based on the artifact cancellation signal, artifacts generated by the electrical stimulation signal in the original neural signal are canceled, and the actual neural signal after the artifacts are eliminated is continuously acquired.
[0021] For example, in at least one embodiment, the method further includes outputting the actual neural signal and the stimulation parameters to the outside of the chip, and receiving update information of the stimulation control model; updating the control model of the electrical stimulation signal based on the update information; the update information is obtained by an artificial intelligence algorithm based on the actual neural signal and the stimulation parameters through dynamic optimization.
[0022] For example, in at least one embodiment, the artifact cancellation signal is obtained in an adaptive filter preset response model based on the stimulus parameters and filter coefficients; wherein the filter coefficients are stored in random access memory.
[0023] For example, in at least one embodiment, obtaining an artifact cancellation signal based on stimulation parameters of the electrical stimulation signal includes: receiving the stimulation parameters, returning an artifact prediction value, calculating an artifact prediction error based on the artifact prediction value and the original neural signal; updating the filter coefficients based on the artifact prediction error, obtaining the artifact cancellation signal based on the updated filter coefficients; storing the updated filter coefficients in the random access memory, and replacing the filter coefficients before the update. Attached Figure Description
[0024] Figure 1 This is a schematic diagram of a neural signal acquisition chip with integrated electrical stimulation function.
[0025] Figure 2 This is a schematic diagram of the signal acquisition module and the signal processing module.
[0026] Figure 3 This is a schematic diagram of the stimulation module.
[0027] Figure 4 This is a schematic diagram of the artifact removal module.
[0028] Figure 5 This is a flowchart of a neural signal acquisition method integrating electrical stimulation function.
[0029] Figure 6 This is a flowchart of the artifact removal method. Detailed Implementation
[0030] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.
[0031] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes. In this disclosure, “multiple” means two or more.
[0032] According to embodiments of this disclosure, Figure 1 A neural signal acquisition chip with integrated electrical stimulation function is disclosed, comprising a signal acquisition module 1, a signal processing module 2, a stimulation control module 3, a stimulation module 4, and an artifact elimination module 5 integrated on a single CMOS chip. All these functional modules adopt a structure suitable for CMOS technology, integrating them onto a single chip. This avoids noise caused by multi-chip interconnection in multi-chip solutions and effectively reduces the overall layout area. This neural signal acquisition chip with integrated electrical stimulation function is surgically placed above the site of acquisition and stimulation in the human body, directly contacting nerve tissue or meninges. The site of acquisition and stimulation can be a part of the brain or spinal cord. Direct contact with nerve tissue is an invasive implantation, offering advantages of high precision, high resolution, and high signal-to-noise ratio; direct contact with meninges is a semi-invasive implantation, balancing signal accuracy and operational safety.
[0033] Signal acquisition module 1 is connected to signal processing module 2 and configured to acquire raw neural signals and transmit them to signal processing module 2. Existing research has demonstrated that neural signals with specific characteristics are generated in different scenarios. Continuously acquiring these specific characteristic signals can lay the foundation for subsequent electrical stimulation demand identification and closed-loop control.
[0034] Signal processing module 2 is connected to signal acquisition module 1, stimulation control module 3, artifact cancellation module 5, and signal output terminal, respectively. It is configured to acquire raw neural signals, process them to obtain actual neural signals, and output these signals to stimulation control module 3 and the signal output terminal. Signal processing module 3 continuously receives neural signals acquired by signal acquisition module 1, filters, amplifies, and converts them to digital signals to obtain actual neural signals, and then outputs these signals to stimulation control module 3 to control the initiation of electrical stimulation; it also outputs signals to an external artificial intelligence system to help stimulation control module 3 update its control model. Signal processing module 3 records artifact cancellation signals and transmits the digital signals used for artifact cancellation to signal acquisition module 1 for artifact cancellation.
[0035] The stimulation control module 3 is connected to the signal processing module 2, the stimulation module 4, and the artifact elimination module 5. It is configured to output a stimulation command to the stimulation module 4 and stimulation parameters to the artifact elimination module 5 when specific information is extracted from the actual neural signal. The stimulation control module 3 continuously identifies the actual neural signal. When a specific feature appears in the actual neural signal, it sends a control command to the stimulation module 4 to initiate electrical stimulation. For example, using a computational method, the high-amplitude peak value required for stimulation is separated and marked as a specific feature. When the specific feature is identified and the corresponding conditions are met, an electrical stimulation signal is emitted to a specific location, effectively achieving the purpose of electrical stimulation. However, many tissues in the human body are conductive. After the electrical stimulation begins, the high-voltage electrical signal generated by the stimulation is conducted in the human tissue, reaching the area around the measurement site of the signal acquisition module 1, thus forming artifacts and affecting the accuracy of subsequent signal acquisition. Therefore, the stimulation control module 3 outputs stimulation parameters to the artifact elimination module 5 simultaneously with the control command, so that the artifact elimination module 5 can eliminate artifacts and maintain the accuracy of the actual neural signal.
[0036] Stimulation module 4 is connected to the electrical input terminal, stimulation control module 3, and electrical output terminal. It is configured to receive a low-voltage electrical signal from the electrical input terminal and, according to stimulation commands, output a high-voltage electrical stimulation signal to the electrical output terminal. The input low-voltage electrical signal is generated by the brain-computer interface power supply, which can be between 1 and 3 volts. After processing by stimulation module 4, a high-voltage electrical stimulation signal with a voltage of ±10-±15V is obtained. Stimulation module 4 can be a charge pump including an LC oscillation network, dynamically activating only the required voltage according to load current demands, thereby optimizing energy efficiency.
[0037] The artifact cancellation module 5 is connected to the stimulation control module 3 and the signal processing module 2. It is configured to obtain an artifact cancellation signal based on stimulation parameters and output it to the signal processing module 2. The signal processing module 2 is also configured to cancel artifacts in the original neural signal based on the artifact cancellation signal. The artifacts eliminated by the artifact cancellation module 5 are those generated by the electrical stimulation signal. If the signal acquisition module 1 and the signal processing module 2 are placed on a separate chip, and the stimulation control module 3 and the stimulation module 4 are placed on another separate chip, with their positions and distances appropriately controlled, the artifacts generated by electrical stimulation can be ignored. However, in the single-chip solution of this disclosure, the electrical stimulation signal is emitted from the chip where the signal acquisition module 1 is located, and the artifacts are very obvious and must be eliminated. The artifact cancellation module 5 obtains the predicted artifact value based on the stimulation parameters and returns it to the signal processing module 2 via a digital signal, thus achieving the cancellation of artifacts in the actual neural signal.
[0038] Preferably, the monolithic CMOS chip integrates a communication module 6, which is connected to the signal processing module 2 and the stimulation control module 3. The communication module 6 is configured to output actual neural signals and stimulation parameters to the outside of the chip and receive updated information from the stimulation control model. The updated information is obtained by an artificial intelligence algorithm based on dynamic optimization of the actual neural signals and stimulation parameters. Currently, electrical stimulation such as deep brain stimulation, vagus nerve stimulation, trigeminal nerve stimulation, and spinal cord stimulation has been proven to have good auxiliary effects on disabled individuals. In the embodiments of this disclosure, closed-loop control of electrical stimulation is implemented within the monolithic CMOS chip; that is, after detecting specific characteristic signals in real time, the chip generates control signals and produces electrical stimulation signals. This design ensures the timeliness and accuracy of control. However, the specific neural characteristics generated for the same control target differ for different users. Therefore, it is necessary to continuously use the actual neural signals collected by the chip, stimulation parameters, and computer-generated historical context as vectors, and optimize and update the stimulation control model based on the effect of electrical stimulation using an artificial intelligence algorithm. For example, the TD3 algorithm can be used. As the user's usage time increases, the stimulation control model is continuously updated, and after several months, a control accuracy rate of over 95% can be gradually achieved.
[0039] Preferred, such as Figure 2 As shown, the signal acquisition module 1 includes multiple signal input terminals 11, a multi-channel encoder 12, and a capacitor-to-analog converter 13. The multi-channel encoder 12 is a time-division multiplexing encoding front-end, and the number of sampling channels can be flexibly selected without limitation. Preferably, 16 channels, 32 channels, etc., can be selected. The capacitor-to-analog converter 13 receives digital signals from the signal processing module 2 and converts them into analog signals to cancel out artifacts generated by the electrical stimulation signals. In the case of multiple channels, a single computing unit is used, and updates are performed by spiral scanning according to the "channel-timestamp" sequence.
[0040] Preferred, such as Figure 2 As shown, the signal processing module 2 includes a front-end amplifier 21, an analog-to-digital converter 22, and a recorder 23. The input of the front-end amplifier 21 includes a digital integral feedback loop, which eliminates low-frequency components and matches the dynamic range to the spectral characteristics of the neural signal. The analog-to-digital converter 22 converts the analog signal into a digital signal. The recorder 23 records the original neural signal and the artifact cancellation signal. Based on the artifact cancellation signal, it sends a digital signal to the capacitor-to-analog converter 13 to cancel the artifacts generated by the electrical stimulation signal at the front end, acquire the actual neural signal, and output the actual neural signal.
[0041] Preferably, the stimulation control module 3 includes an adaptive controller 31 and a memory 32. The adaptive controller 31 has a built-in control model trained with artificial intelligence, continuously monitors the actual neural signals, and outputs control commands when specific characteristics of the actual neural signals appear. The memory 32 stores the actual neural signals and control command parameters, transmits the control command parameters to the artifact elimination module 5 and the communication module 6, and transmits them to an external device through the communication module 6. The external device uses an artificial intelligence algorithm to continuously update the control model. The communication module 6 receives the control model update information from the external device and updates the control model accordingly.
[0042] Preferred, such as Figure 3 As shown, the stimulation module 4 includes a pair of H-bridge stimulators 41, a current controller 42, and a switching circuit 43. Each H-bridge stimulator 41 includes an LC oscillation network 411, a cross-coupled NMOS pair 412, and a high-voltage adapter 413. The cross-coupled NMOS pair 412 is connected to the electrical input terminal, receives the low-voltage electrical signal from the electrical input terminal, and generates a negative impedance to compensate for the resistive loss of the LC oscillation network 411. The LC oscillation network 411 is connected to the cross-coupled NMOS pair 412 to generate a high self-resonant frequency oscillation signal, with the following resonant frequencies:
[0043] Where f is the resonant frequency, C Total It is the total capacitance, C PAR It is the total parasitic capacitance, C SW It's a switch
[0044]
[0045] Interstage coupling capacitor, C gs It is the cross-coupled NMOS gate-source capacitance, C gd It is the cross-coupled NMOS gate-drain capacitor. C PAR The resonant frequency f is directly determined by the manufacturing process and should be minimized to improve efficiency. SW It is the main source of loss at high frequencies, affecting the negative impedance requirement. C gs Participating in the formation of total capacitance C TotalTogether with the inductance Ls, they determine the resonant point. C gd Introducing phase shift at high frequencies requires size optimization to balance negative impedance and power consumption.
[0046] The high-voltage adapter 413 is connected to the LC oscillation network 411, receiving a high self-resonant frequency oscillation signal and outputting a high-voltage electrical stimulation signal. When the stimulation module 4 is operating, the H-bridge stimulator on one side is powered, while the current is absorbed and regulated through the H-bridge stimulator on the other side of the load. During the return phase, the H-bridge stimulator on the opposite side is activated, and the current is absorbed through the previously activated H-bridge stimulator on one side. The current controller 42 is responsible for controlling the output current. The switching circuit 43 consists of diodes and a distributed current buffer, which can overcome the low voltage tolerance problem of a single CMOS device. The stimulation module 4 is designed as an improved cross-coupled switched-capacitor circuit, integrated in a triple-well deep submicron CMOS process, operating at a high self-resonant frequency. It utilizes an integrated differential inductor and cascaded flying capacitors to form an LC resonant circuit to create an oscillator. High-frequency operation significantly reduces the required capacitor size, maximizing chip area savings. The cross-coupled NMOS device generates negative impedance to compensate for the resistive losses of the LC circuit, maintaining oscillation without a phase-locked loop.
[0047] Preferably, multiple stimulation modules 4 are connected in parallel, and the artifact cancellation module 5 obtains multiple independent artifact cancellation signals based on the stimulation parameters of each stimulation module 4. Depending on the stimulation location requirements, multiple stimulation modules 4 are connected in parallel on the same CMOS chip, which can effectively improve the stimulation effect and reduce power consumption.
[0048] Preferred, such as Figure 4 As shown, the artifact canceller 5 includes an adaptive filter 51 and a random access memory 52. The adaptive filter 51 has a preset response model and outputs an artifact cancellation signal based on stimulation parameters and filter coefficients; the random access memory 52 stores the filter coefficients. Simultaneously with the issuance of an electrical stimulation command, stimulation parameters are input to the adaptive filter 51, indicating the need for artifact processing. At the same time, the original neural signal is also input to the adaptive filter 51. The adaptive filter 51 reads the filter coefficients from the random access memory 52, and the random access memory 52 returns the artifact prediction value to the adaptive filter 51. The adaptive filter 51 runs a preset program to calculate the artifact prediction error based on the original neural signal and the artifact prediction value. The adaptive filter 51 updates the filter coefficients based on the artifact prediction error, calculates and outputs the artifact cancellation signal based on the updated filter coefficients, and stores the new filter coefficients in the random access memory 52, overwriting the original filter coefficients. After multiple error calculations and replacements, the error of the filter coefficients gradually decreases, and the accuracy of artifact cancellation gradually improves.
[0049] Preferably, the adaptive filter 51 includes an adaptive digital feedback loop that multiplexes the digital signal processed by the acquisition signal processing module 2 to eliminate stimulus-induced artifacts. After the electrical stimulation signal is emitted, the adaptive filter 51 obtains the artifact prediction value based on the filter coefficients stored in the random access memory 52, and calculates the artifact prediction error based on the artifact prediction value and the original neural signal. The adaptive filter 51 updates the filter coefficients based on the artifact prediction error, and obtains the artifact cancellation signal based on the updated filter coefficients. The random access memory 52 stores the updated filter coefficients and replaces the filter coefficients before the update.
[0050] Preferably, the adaptive filter 51 is a 32-tap least mean square (LMS) adaptive filter, which establishes a time-domain artifact impulse response model for each stimulus-acquisition channel pair. To reduce hardware complexity and power consumption, the system implements a simplified LMS filter architecture based on impulse excitation: the input is a discrete delta function of the corresponding stimulus impulse, and the hardware is updated by successively activating individual taps and time-division multiplexing LMS, eliminating the need for multipliers and tap delay lines.
[0051] Preferably, the random access memory 52 is a static random access memory (SRAM), and the filter coefficients characterizing the sampled artifact waveform are stored in the on-chip SRAM, organized by acquisition channel, stimulation channel, and tap number index. Multiple independent cancellation back-ends process the artifact cancellation of multiple stimulation modules 4 in parallel, with each back-end time-division multiplexing multiple acquisition channels. The analog-to-digital converter 22 sums the cancellation output before the signal input, achieving cancellation based on the linear superposition assumption of overlapping artifacts.
[0052] The second aspect of this disclosure provides a method for acquiring neural signals with integrated electrical stimulation function, such as... Figure 5 As shown, the following steps are performed on a single CMOS chip:
[0053] S1 continuously acquires raw neural signals, processes the raw neural signals, and obtains actual neural signals.
[0054] S2 continuously extracts information from actual neural signals, and when specific information is extracted, it outputs stimulation instructions and stimulation parameters.
[0055] S3 receives a low-voltage electrical signal from the electrical input terminal according to the stimulation command, and outputs a high-voltage electrical stimulation signal to the electrical output terminal.
[0056] S4 obtains the artifact cancellation signal based on the stimulus parameters and outputs it to the signal processing module.
[0057] S5 is based on artifact cancellation signals to cancel artifacts generated by electrical stimulation signals in the original neural signals, and continuously obtains the actual neural signals after artifact cancellation.
[0058] Understandably, the above steps are performed dynamically. In the absence of daily stimulation needs, only S1 and S2 are executed. S2 only issues a control command when specific information is extracted from the signal waveform output by S2. S4 and S5 are executed only after S3 issues the electrical stimulation signal. After obtaining the actual neural signal in S5, the signal returns to step S2. At this point, step S2 extracts the signal based on the actual neural signal after artifact removal in the preceding step S5.
[0059] Preferred options also include:
[0060] S6 outputs actual neural signals and stimulation parameters to the outside of the chip and receives updated information from the stimulation control model.
[0061] S7 uses a control model that updates electrical stimulation signals based on updated information, which is obtained by an artificial intelligence algorithm through dynamic optimization based on actual neural signals and stimulation parameters.
[0062] Understandably, the above steps are performed dynamically. Steps S6 and S7 are not executed when there is no daily need for stimulation. Steps S6 and S7 are only executed after an electrical stimulation signal is emitted in step S3. After obtaining the updated control model in step S7, it returns to step S2, where step S2 performs control based on the previously updated control model.
[0063] Preferred, such as Figure 4 As shown, it also includes: S41 obtaining the artifact cancellation signal in the preset response model of the adaptive filter based on the stimulus parameters and filter coefficients; wherein the filter coefficients are stored in random access memory.
[0064] Preferred, such as Figure 4 and Figure 6 As shown, the artifact cancellation signal obtained from the stimulation parameters based on the electrical stimulation signal in S41 includes:
[0065] After receiving the stimulus parameters, S411 returns the artifact prediction value and calculates the artifact prediction error based on the artifact prediction value and the original neural signal.
[0066] S412 updates the filter coefficients based on the artifact prediction error, and obtains the artifact cancellation signal based on the updated filter coefficients;
[0067] S413 stores the updated filter coefficients in random access memory and replaces the previous filter coefficients.
[0068] It is understood that in the chip product of the first aspect of the present disclosure, all methods included in the preferred embodiments can be used as preferred embodiments of the methods in the second aspect of the present disclosure.
[0069] The following points also need to be explained:
[0070] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.
[0071] (2) For clarity, the thickness of devices, layers, or regions is enlarged or reduced in the drawings used to describe embodiments of the present disclosure, i.e., these drawings are not drawn to scale. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element or there may be intermediate elements.
[0072] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.
[0073] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure shall be determined by the scope of the claims.
Claims
1. A neural signal acquisition chip with integrated electrical stimulation function, comprising a signal acquisition module, a signal processing module, a stimulation control module, a stimulation module, and an artifact elimination module integrated on a single CMOS chip; The signal acquisition module is connected to the signal processing module and is configured to acquire raw neural signals and transmit them to the signal processing module. The signal processing module is connected to the signal acquisition module, the stimulation control module, the artifact elimination module and the signal output terminal respectively, and is configured to receive the original neural signal, process it to obtain the actual neural signal, and output it to the stimulation control module and the signal output terminal. The stimulation control module is connected to the signal processing module, the stimulation module and the artifact elimination module, and is configured to output stimulation instructions to the stimulation module and stimulation parameters to the artifact elimination module when specific information is extracted from the actual neural signal. The stimulation module is connected to the electrical input terminal, the stimulation control module, and the electrical output terminal, and is configured to receive a low-voltage electrical signal from the electrical input terminal and output a high-voltage electrical stimulation signal to the electrical output terminal according to the stimulation command. The artifact cancellation module is connected to the stimulus control module and the signal processing module, and is configured to obtain an artifact cancellation signal based on the stimulus parameters and output it to the signal processing module. The signal processing module is further configured to cancel artifacts in the original neural signal based on the artifact cancellation signal, and output the actual neural signal after canceling the artifacts.
2. The neural signal acquisition chip with integrated electrical stimulation function according to claim 1, characterized in that, The integrated communication module on the monolithic CMOS chip is connected to the signal processing module and the stimulation control module, and is configured to output the actual neural signals and stimulation parameters to the outside of the chip, and receive update information from the stimulation control model. The updated information is obtained by an artificial intelligence algorithm based on the actual neural signals and the stimulation parameters through dynamic optimization.
3. The neural signal acquisition chip with integrated electrical stimulation function according to claim 1, characterized in that, The signal acquisition module includes multiple signal input terminals, a multi-channel encoder, and a capacitor-to-digital converter. The signal processing module includes a front-end amplifier, an analog-to-digital converter, and a recorder.
4. The neural signal acquisition chip with integrated electrical stimulation function according to claim 1, characterized in that, The stimulation module includes two cross-coupled NMOS pairs, two LC oscillation networks, two high-voltage adapters, and one current controller. The cross-coupled NMOS pair is connected to the electrical input terminal, receives the low-voltage electrical signal from the electrical input terminal, and generates a negative impedance to compensate for the resistive loss of the LC oscillation network. The LC oscillation network is connected to the cross-coupled NMOS pair to generate a high self-resonant frequency oscillation signal; The LC oscillation network is connected in sequence to the high-voltage adapter and the current controller.
5. The neural signal acquisition chip with integrated electrical stimulation function according to claim 1, characterized in that, The artifact elimination module includes: an adaptive filter and a random access memory; The adaptive filter has a preset response model and outputs the artifact cancellation signal based on the stimulus parameters and filter coefficients. The random access memory stores the filter coefficients.
6. The neural signal acquisition chip with integrated electrical stimulation function according to claim 5, characterized in that, The adaptive filter includes an adaptive digital feedback loop. After an electrical stimulation signal is emitted, the adaptive filter obtains the artifact prediction value based on the filter coefficients stored in the random access memory, and calculates the artifact prediction error based on the artifact prediction value and the original neural signal. The adaptive filter updates the filter coefficients based on the artifact prediction error, and obtains the artifact cancellation signal based on the updated filter coefficients; The random access memory stores the updated filter coefficients and replaces the original filter coefficients.
7. A method for acquiring neural signals with integrated electrical stimulation function, comprising the following steps performed on a single CMOS chip: Continuously collect raw neural signals, process the raw neural signals, and obtain actual neural signals; The actual neural signals are continuously extracted, and when specific information is extracted, stimulation instructions and stimulation parameters are output. According to the stimulation command, a low-voltage electrical signal is received at the electrical input terminal, and a high-voltage electrical stimulation signal is output to the electrical output terminal. Based on the stimulation parameters, an artifact cancellation signal is obtained; Based on the artifact cancellation signal, artifacts generated by the electrical stimulation signal in the original neural signal are canceled, and the actual neural signal after the artifacts are eliminated is continuously acquired.
8. The neural signal acquisition method with integrated electrical stimulation function according to claim 7, characterized in that, It also includes outputting the actual neural signal and the stimulation parameters to the outside of the chip, and receiving update information of the stimulation control model; updating the control model of the electrical stimulation signal based on the update information; the update information is obtained by dynamic optimization of the actual neural signal and the stimulation parameters by an artificial intelligence algorithm.
9. The neural signal acquisition method with integrated electrical stimulation function according to claim 7, characterized in that, Based on the stimulus parameters and filter coefficients, the artifact cancellation signal is obtained in the preset response model of the adaptive filter; wherein... The filter coefficients are stored in a random access memory.
10. The neural signal acquisition method with integrated electrical stimulation function according to claim 9, characterized in that, Obtaining the artifact cancellation signal based on the stimulation parameters of the electrical stimulation signal includes: After receiving the stimulation parameters, the artifact prediction value is returned, and the artifact prediction error is calculated based on the artifact prediction value and the original neural signal. The filter coefficients are updated based on the artifact prediction error, and the artifact cancellation signal is obtained based on the updated filter coefficients. The updated filter coefficients are stored in the random access memory, replacing the original filter coefficients.