Driving circuit and display panel

Abstract

The application discloses a driving circuit and a display panel. The driving circuit comprises a plurality of driving cables, a driving unit and a delay circuit. The driving unit comprises an output signal end for outputting a driving signal. The delay circuit comprises a first input end, a first output end and a second output end. The output signal end is connected with the first input end. The first output end is used for outputting a first clock signal. The second output end is used for outputting a second clock signal later than the first clock signal. In two adjacent driving cables, one driving cable is connected with the first output end, and the other driving cable is connected with the second output end. The driving circuit provided by the application adds the delay circuit between the driving unit and the driving cable, so that the driving unit can control two rows of pixels through the delay circuit, thereby reducing the number of the driving units and the line area of the driving units in the display panel, and the frame width of the display panel is reduced.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a driving circuit and a display panel. Background Technology

[0002] Gate-on-Array (GOA) is a display technology that integrates the gate driver chip onto the glass. Its core principle is to directly integrate the shift register function of the gate driver chip onto the display panel, thereby reducing the need for external gate driver chips. Specifically, GOA technology controls the turning off of the previous row and on of the next row by moving the output of the gate driver chip row by row; each GOA controls only one row of pixels. However, since each GOA can only control one row of pixels, achieving high-resolution displays requires adding more GOAs, which increases the area occupied by the GOAs and consequently increases the width of the display panel bezel. Summary of the Invention

[0003] This application provides a driving circuit and a display panel that can reduce the width of the display panel bezel.

[0004] In a first aspect, this application provides a driving circuit, comprising:

[0005] Multiple drive cables, each used to connect multiple transistors;

[0006] The drive unit includes an output signal terminal, which is used to output a drive signal.

[0007] The delay circuit includes a first input terminal, a first output terminal, a second output terminal, an inverter, a first buffer, a first NAND gate, and a second NAND gate; the first input terminal, the first output terminal, and the second output terminal are electrically connected; the inverter is connected between the first input terminal and the first NAND gate, the first buffer is connected between the first input terminal and the second NAND gate, the output terminal of the first NAND gate is connected to the input terminal of the second NAND gate, and the output terminal of the second NAND gate is connected to the input terminal of the first NAND gate;

[0008] The output signal terminal is connected to the first input terminal, and the first output terminal is connected between the first buffer and the second NAND gate. The first output terminal is used to output the first clock signal. The second output terminal is connected to the side of the first NAND gate away from the inverter. The second output terminal is used to output a second clock signal that is later than the first clock signal.

[0009] In two adjacent drive cables, one drive cable is connected to the first output terminal, and the other drive cable is connected to the second output terminal.

[0010] In some feasible implementations, both the first and second clock signals are positive clock signals, and the transistors on each drive cable are N-type field-effect transistors.

[0011] In some feasible implementations, a second buffer is connected between the second output and the first NAND gate.

[0012] In some feasible implementations, the delay circuit also includes a third output and a fourth output. The third output is connected between the inverter and the first NAND gate, and the fourth output is connected to the side of the second NAND gate away from the first buffer.

[0013] In some feasible implementations, a third buffer is connected between the fourth output and the second NAND gate.

[0014] In some feasible implementations, the driving unit also includes a gate-off signal terminal, the transistors on each driving cable are N-type field-effect transistors, the third output terminal is connected to the gate-off signal terminal, and the fourth output terminal is connected to the gate-off signal terminal.

[0015] In some feasible implementations, the transistors on each drive cable are N-type field-effect transistors, with the third output terminal grounded and the fourth output terminal grounded.

[0016] In some feasible implementations, the delay circuit also includes a third output terminal and a fourth output terminal, each connected to a drive cable. The drive cables connected to the first output terminal, the second output terminal, the third output terminal, and the fourth output terminal are all different.

[0017] In some feasible implementations, the transistors include P-type field-effect transistors and N-type field-effect transistors. In two adjacent drive cables, the transistor on one drive cable is a P-type field-effect transistor and the transistor on the other drive cable is an N-type field-effect transistor. The transistor on the drive cable connecting the first output terminal and the second output terminal is an N-type field-effect transistor, and the transistor on the drive cable connecting the third output terminal and the fourth output terminal is a P-type field-effect transistor.

[0018] Secondly, this application provides a display panel including the driving circuit described in the first aspect.

[0019] The driving circuit provided in this application adds a delay circuit between the driving unit and the driving cable. This allows the driving signal output from the driving unit to enter the delay circuit via the first input terminal, and then be output from the first and second output terminals of the delay circuit, becoming a first clock signal and a second clock signal later than the first clock signal. Each of the first and second output terminals is connected to a driving cable, and both the first and second clock signals can respectively control the transistors on one driving cable, enabling the driving unit to control two rows of pixels through the delay circuit. Compared to a display panel driving the same number of pixels in a row, this application requires fewer driving units and has a smaller footprint, thus reducing the bezel width and power consumption of the display panel. Compared to a display panel with the same number of driving units, the driving unit in this application can drive more rows of pixels, thereby improving the resolution of the display panel and making the displayed image clearer. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the background art, the accompanying drawings used in the embodiments of this application or the background art will be described below.

[0021] Figure 1 A schematic diagram of the driving circuit provided in this application;

[0022] Figure 2 Wiring diagram of the drive unit and delay circuit provided in this application;

[0023] Figure 3 This is a schematic diagram of the driving unit involved in this application;

[0024] Figure 4 This is a schematic diagram showing the connection of the multiple drive units involved in this application;

[0025] Figure 5 This is an internal circuit diagram of the driving unit involved in this application;

[0026] Figure 6 This is a schematic diagram of the delay circuit involved in this application;

[0027] Figure 7 for Figure 6 The waveforms of the clock signals at various points in the delay circuit are shown.

[0028] Figure 8 This is a schematic diagram of another structure of the delay circuit involved in this application;

[0029] Figure 9 A schematic diagram of the drive circuit provided in this application;

[0030] Figure 10 for Figure 9 The waveforms of the clock signals at various points in the driving circuit are shown.

[0031] Figure 11 for Figure 9 The diagram shows the location of the driving circuit in the display panel.

[0032] Figure 12 Another schematic diagram of the driving circuit provided in this application;

[0033] Figure 13 Another schematic diagram of the driving circuit provided in this application;

[0034] Figure 14 for Figure 13 The diagram shows the location of the driving circuit in the display panel.

[0035] Figure 15 for Figure 13 The waveform diagram of the clock signal at various points in the driving circuit is shown.

[0036] Attached image captions:

[0037] 100 - Driver unit, 101 - First phase terminal, 102 - Second phase terminal, 103 - Input signal terminal, 104 - Output signal terminal, 105 - Reset signal terminal, 106 - Gate turn-off signal terminal, 107 - Initialization signal, 108 - Drive signal, 111 - Cascade module, 112 - Pull-down sustaining module, 113 - Output module, 200 - Delay circuit, 201 - First input terminal, 202 - Inverter, 203 - First buffer, 204 - First NAND gate. 205 - Second NAND gate, 206 - Second buffer, 207 - Third buffer, 211 - First output, 212 - Second output, 213 - Third output, 214 - Fourth output, 221 - First clock signal, 222 - Second clock signal, 223 - Third clock signal, 224 - Fourth clock signal, 300 - Driver cable, 301 - Transistor, 302 - N-type field-effect transistor, 303 - P-type field-effect transistor, 400 - Driver chip. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0039] Please see Figure 1 and Figure 2The driving circuit provided in this application includes: multiple driving cables 300, each driving cable 300 being used to connect multiple transistors 301; a driving unit 100, the driving unit 100 including an output signal terminal 104, the output signal terminal 104 being used to output a driving signal 108; and a delay circuit 200, the delay circuit 200 including a first input terminal 201, a first output terminal 211, a second output terminal 212, an inverter 202, a first buffer 203, a first NAND gate 204, and a second NAND gate 205; the first input terminal 201, the first output terminal 211, and the second output terminal 212 are electrically connected; the inverter 202 is connected between the first input terminal 201 and the first NAND gate 204, and the first buffer 203 is connected between the first input terminal 201 and the second NAND gate. Between 205, the output of the first NAND gate 204 is connected to the input of the second NAND gate 205, and the output of the second NAND gate 205 is connected to the input of the first NAND gate 204; the output signal terminal 104 is connected to the first input terminal 201, and the first output terminal 211 is connected between the first buffer 203 and the second NAND gate 205. The first output terminal 211 is used to output the first clock signal 221; the second output terminal 212 is connected to the side of the first NAND gate 204 away from the inverter 202. The second output terminal 212 is used to output the second clock signal 222, which is later than the first clock signal 221; in two adjacent drive cables 300, one drive cable 300 is connected to the first output terminal 211, and the other drive cable 300 is connected to the second output terminal 212.

[0040] The driving signal 108 output from the output signal terminal 104 of the driving unit 100 is input to the delay circuit 200 via the first input terminal 201, and then becomes a first clock signal 221 output from the first output terminal 211 to one driving cable 300, and a second clock signal 222 output from the second output terminal 212 to the next driving cable 300. Both the first clock signal 221 and the second clock signal 222 can turn on the transistor 301 on the driving cable 300, and the second clock signal 222 is later than the first clock signal 221. This ensures that one driving unit 100 can turn on the current row of pixels and wait for the current row of pixels to turn off before turning on the next row of pixels, thereby enabling one driving unit 100 to control two rows of pixels. By adding the delay circuit 200 to the driving unit 100, the driving signal 108 is transformed into the first clock signal 221 and the second clock signal 222, which is later than the first clock signal 221, so that one driving unit 100 can control two rows of pixels, thereby reducing the number of driving units 100 in the display panel. When driving the same row of pixels, this application requires fewer driving units 100 and has a smaller line area for the driving units, thereby reducing the bezel width of the display panel and lowering the power consumption of the display panel. With the same number of driving units, the driving units 100 of this application can drive more rows of pixels, thereby improving the resolution of the display panel and making the displayed image clearer.

[0041] This reduces the area occupied by the driving unit 100 in the display panel, thereby reducing the bezel width of the display panel. At the same time, the reduction in the number of driving units 100 also reduces the power consumption of the display panel.

[0042] Please see Figure 3 and Figure 4The driving unit 100 includes a first phase terminal 101, a second phase terminal 102, an input signal terminal 103, an output signal terminal 104, a reset signal terminal 105, and a gate turn-off signal terminal 106. The first phase terminal 101 is used to input a first-phase clock signal (Clock A, CLKA) to control the switching state of the transistors in the driving unit 100, thereby driving the timing of the gate signal. The second phase terminal 102 is used to input a second-phase clock signal (Clock B, CLKB) and works in conjunction with the first phase terminal 101 to ensure stable output and correct timing of the gate signal. The input signal terminal 103 is used to receive the output signal or frame start signal from the previous stage driving unit 100 as a trigger input for this stage circuit, realizing cascaded driving. The output signal terminal 104 is used to output a driving signal 108 to the next stage driving unit 100 or a delay circuit to control the opening and closing of pixels. The reset signal terminal 105 is used to restart the state of the driving unit 100 under a specific timing, ensuring that the circuit is in a stable initial state before the start of each scan cycle. The gate shutdown signal terminal 106 is used to control the shutdown timing of the gate signal, avoid signal residue or false triggering, and improve the stability of the display screen. The gate shutdown signal terminal 106 is connected to the common ground terminal VSS.

[0043] The input signal of each stage driver unit 100 is the output signal of the previous stage driver unit 100, and the reset signal of each stage driver unit 100 is the output signal of the next stage driver unit 100. For the first stage driver unit 100, since there is no previous stage GOA unit, the frame start signal is used as the input signal; for the last stage driver unit 100, since there is no next stage driver unit 100 to provide a reset signal, an additional redundant driver unit 100 is designed to provide a reset signal for the last line.

[0044] Please see Figure 4 and Figure 5In some feasible embodiments, the internal circuitry of the driving unit 100 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a capacitor C1. The first transistor T1 is connected to a gate high voltage (VGH), and the second transistor T2 is connected to a gate low voltage (VGL). The gates of both the first transistor T1 and the second transistor T2 are connected to the input signal terminal 103 to receive an initialization signal 107. The initialization signal 107 can be a frame start signal or an output signal from the previous driving unit 100. One end of the third transistor T3 is connected to the first phase terminal 101 and the second phase terminal 102 to receive a clock signal CLKB entering through the first phase terminal 101 or a clock signal CLK entering through the second phase terminal 102. The other end of the third transistor T3 is connected to the output signal terminal 104. A QB point is provided between the gates of the fourth transistor T4 and the fifth transistor T5, and the QB point is used to connect to the reset signal terminal 105. The fourth transistor T4 and the fifth transistor T5 are both connected to the gate turn-off signal terminal 106, and both the fourth transistor T4 and the fifth transistor T5 are connected to VGL.

[0045] The first transistor T1 and the second transistor T2 are both connected to the gate of the third transistor T3. A Q-point is provided between the gates of the first transistor T1, the second transistor T2, and the third transistor T3. The Q-point can control the output signal terminal 104 to output a high level or a low level. The first transistor T1 and the second transistor T2 pre-charge the capacitor C1. That is, the drive signal 108 output from the output signal terminal 104 of the previous row GOA unit is input to the first transistor T1 and the second transistor T2, turning on the first transistor T1 and the second transistor T2, and then pre-charging one end of the capacitor C connected to the Q-point. The drive signal 108 output from the output signal terminal 104 of the next row GOA unit is used as the reset signal of the GOA unit in this row and input to the Q-point, turning on the fourth transistor T4 and the fifth transistor T5. The turned-on fourth transistor T4 discharges the Q-point, i.e., one end of the capacitor C1, and the turned-on fifth transistor T5 discharges the output signal terminal 104, i.e., the other end of the capacitor C1. Functionally, a GOA unit can be further divided into several functional modules, where the first transistor T1 and the second transistor T2 constitute the cascade module 111, the fourth transistor T4 and the fifth transistor T5 constitute the pull-down sustaining module 112, and the third transistor T3 constitutes the output module 113.

[0046] In some feasible implementations, the transistor inside the driving unit 100 is an N-type field-effect transistor. An N-type field-effect transistor has a metal-oxide-semiconductor structure, and its main electrodes include a gate, a drain, and a source. Its conductive channel is made of N-type semiconductor material. The N-type field-effect transistor controls the current flow from the drain to the source through the gate voltage, thus it is a voltage-controlled device.

[0047] Please see Figure 6 In some feasible implementations, the delay circuit 200 includes a first input terminal 201, an inverter 202, a first buffer 203, a first NAND gate 204, and a second NAND gate 205. The inverter 202 is connected between the first input terminal 201 and the first NAND gate 204, the first buffer 203 is connected between the first input terminal 201 and the second NAND gate 205, the output terminal of the first NAND gate 204 is connected to the input terminal of the second NAND gate 205, and the output terminal of the second NAND gate 205 is connected to the input terminal of the first NAND gate 204.

[0048] The waveforms at points A, B, C, and D in the delay circuit 200 are all different. For example, please refer to... Figure 7 If initially the clock signal input to the first input terminal 201 is 1, then the clock signal at point A is 0, the clock signal at point B is 1, the clock signal at point C is 1, and the clock signal at point D is 0. When the clock signal input to the first input terminal 201 changes from 1 to 0, and assuming that each logic gate has the same delay, then... Figure 5 As shown in the waveform: when the clock signal input at the first input terminal 201 decreases, after a certain time Td, the clock signal at point A increases, and the clock signal at point B decreases accordingly; when the clock signal at point A increases to 1 and the clock signal at point B decreases to 0, the clock signal at point C begins to change. There is a delay Tn between the changes in the clock signal at point C and the clock signal at point D. The clock signal at point D only begins to increase when the clock signal at point C decreases to 0.

[0049] Please see Figure 8 In some feasible implementations, a second buffer 206 can be added to the first NAND gate 204, and a third buffer 207 can be added after the second NAND gate 205 to increase the delay time between points C and D in the delay circuit 200. See also... Figure 9 In the driving circuit provided in this application, after the driving unit is connected to the delay unit, a second buffer 206 can be added to the first NAND gate 204 and a third buffer 207 can be added after the second NAND gate 205 to increase the delay time between the first clock signal 221 and the second clock signal 222.

[0050] Please see Figure 10 and Figure 11In some feasible implementations, both the first clock signal 221 and the second clock signal 222 are positive clock signals, and the transistors 301 on each drive cable 300 are N-type field-effect transistors 302. The transistors connected to the drive cables 300 of existing display panels are generally N-type field-effect transistors 302, and the source signal lines of each row of N-type field-effect transistors 302 are connected to the driver chip 400. A positive clock signal is required to turn on the N-type field-effect transistors 302. When the drive unit 100 outputs a positive drive signal 108, the first clock signal 221 and the second clock signal 222 are the same and both are positive clock signals. Therefore, the N-type field-effect transistors 302 on the drive cable 300 can be directly turned on by the first clock signal 221 and the second clock signal 222 without the need for additional inverters or level conversion circuits, thereby reducing the area and power consumption of the drive circuit.

[0051] In some feasible implementations, the delay time of the second clock signal 222 relative to the first clock signal 221 depends on the resolution, refresh rate and architecture of the display panel, and this delay time can be adjusted according to the delay circuit 200. Taking a 720x1600 resolution, 60Hz refresh rate, and single-gate display panel as an example, the scanning time for driving one row of pixels in this display panel is 8.5 microseconds. Therefore, the delay time of the second clock signal 222 relative to the first clock signal 221 is also 8.5 microseconds. At this time, the period of the delay circuit 200 can be controlled to be 17 microseconds to accommodate the first clock signal 221, the second clock signal 222, and the delay between them. During this period, the first clock signal 221 can be controlled to be high in the first half of the period, for example, between 0 and 2 microseconds, and low for the rest of the time. The second clock signal 222 can be controlled to be high in the second half of the period, for example, between 15 and 17 microseconds, and low for the rest of the time. During the non-overlapping time of one cycle of the delay circuit 200, for example, between 2 and 15 microseconds, both the first clock signal 221 and the second clock signal 222 are low, ensuring that they do not overlap.

[0052] Please see Figure 9A second buffer 206 is connected between the second output terminal 212 and the first NAND gate 204. In some feasible implementations, the number of second buffers 206 can be multiple and even. By increasing or changing the number of second buffers 206, the delay time between the first clock signal 221 and the second clock signal 222 can be increased or decreased. Even if the resolution and refresh rate of the display panel are different, the delay time between the first clock signal 221 and the second clock signal 222 can be adjusted by the delay circuit 200 to ensure the uniformity of the displayed image and avoid brightness unevenness or crosstalk problems caused by timing errors. This means that the driving circuit provided in this application can be applied to a variety of display panels, and it also means that in different display panels, the driving unit 100 in this application can control two rows of pixels through the delay circuit 200, thereby reducing the number of driving units 100, reducing the number of traces of the driving units 100 at the edge of the display panel, and thus reducing the bezel width of the display panel, improving the market competitiveness of the product.

[0053] Please see Figure 12 The delay circuit 200 also includes a third output terminal 213 and a fourth output terminal 214. The third output terminal 213 is connected between the inverter 202 and the first NAND gate 204, and the fourth output terminal 214 is connected to the side of the second NAND gate 205 away from the first buffer 203. After the drive signal 108 of the drive unit 100 is input to the delay circuit 200 via the first input terminal 201, it can also output a third clock signal 223 via the third output terminal 213, or a fourth clock signal 224 via the fourth output terminal 214. Since both the third clock signal 223 and the fourth clock signal 224 are negative clock signals, when the transistors on each drive cable 300 are all N-type field-effect transistors 302, the first output terminal 211 and the second output terminal 212 are connected to the drive cable 300, while the third output terminal 213 and the fourth output terminal 214 are not connected to the drive cable 300. When the transistors on each drive cable 300 are all P-type field-effect transistors 303, the third output terminal 213 and the fourth output terminal 214 are connected to the drive cable 300, while the first output terminal 211 and the second output terminal 212 are not connected to the drive cable 300. Regardless of whether the transistors used in the display panel are a single N-type field-effect transistor 302 or a single P-type field-effect transistor 303, the drive circuit provided in this application can realize the function of one drive unit 100 controlling two rows of pixels simultaneously, thereby reducing the number of drive units 100 and the area occupied by the wiring of the drive units 100, thereby reducing the bezel width of the display panel and reducing the power consumption of the display panel.

[0054] Please see Figure 12A third buffer 207 is connected between the fourth output terminal 214 and the second NAND gate 205. The fourth clock signal 224 is later than the third clock signal 223. In some feasible implementations, the number of third buffers 207 can be multiple and even. By increasing or changing the number of third buffers 207, the delay time between the third clock signal 223 and the fourth clock signal 224 can be increased or decreased. When the third output terminal 213 and the fourth output terminal 214 are respectively connected to drive cables 300, even if the resolution and refresh rate of the display panel are different, the delay time between the third clock signal 223 and the fourth clock signal 224 can be adjusted by the delay circuit 200 to ensure the uniformity of the display screen and avoid uneven brightness or crosstalk problems caused by timing errors.

[0055] Please see Figure 11 and Figure 12 When each drive cable 300 has an N-type field-effect transistor 302, the third output terminal 213 can be connected to the gate-off signal terminal 106, and the fourth output terminal 214 can be connected to the gate-off signal terminal 106. When each drive cable 300 has an N-type field-effect transistor 302, the N-type field-effect transistor 302 needs to be turned on by a positive clock signal. When the current row drive unit 100 inputs the drive signal 108 to the corresponding delay circuit 200, since the first clock signal 221 output by the first output terminal 211 and the second clock signal 222 output by the second output terminal 212 are positive clock signals, and the third clock signal 223 output by the third output terminal 213 and the fourth clock signal 224 output by the fourth output terminal 214 are negative clock signals, the first output terminal 211 and the second output terminal 212 are respectively connected to a drive cable 300, and the third output terminal 213 and the fourth output terminal 214 are connected to the pull-down sustaining module 112 of the current row drive unit 100 through the gate shut-off terminal of the current row drive unit 100 to prevent the current row drive unit 100 from being accidentally turned on due to residual voltage.

[0056] When each drive cable 300 has an N-type field-effect transistor 302, the third output terminal 213 and the fourth output terminal 214 can be grounded or left floating, in addition to being connected to the gate shut-off signal terminal 106 of the drive unit 100. By directly grounding or leaving the third output terminal 213 and the fourth output terminal 214 floating, the routing of the third output terminal 213 and the fourth output terminal 214 is reduced, thereby reducing the complexity of the routing at the edge of the display panel, providing space for a narrower bezel design, and reducing the risk of signal interference caused by routing intersections or excessive density.

[0057] Please see Figure 13 and Figure 14The third output terminal 213 and the fourth output terminal 214 are each connected to a driving cable 300. The driving cables 300 connected to the first output terminal 211, the second output terminal 212, the third output terminal 213, and the fourth output terminal 214 are all different. The N-type field-effect transistor 302 controls the current flow from the drain to the source through the gate voltage. The P-type field-effect transistor 303 also has a metal-oxide-semiconductor structure, with its main electrodes including the gate, drain, and source, and its conductive channel is made of P-type semiconductor material. The P-type field-effect transistor 303 controls the current flow from the source to the drain through the gate voltage. When some of the driving cables 300 on the display panel have P-type field-effect transistors 303 and others have N-type field-effect transistors 302, the first clock signal 221 output from the first output terminal 211, the second clock signal 222 output from the second output terminal 212, the third clock signal 223 output from the third output terminal 213, and the fourth clock signal 224 output from the fourth output terminal 214 are each connected to one driving cable 300. The driving signal 108 output by the driving unit 100 is transformed into the first clock signal 221, the second clock signal 222, the third clock signal 223, and the fourth clock signal 224 after passing through the delay circuit 200. This allows one driving unit 100 to control four rows of pixels, further reducing the number of driving units 100 and the area occupied by the wiring of the driving units 100, thereby reducing the bezel width of the display panel and lowering the power consumption of the display panel.

[0058] Please see Figure 14The transistors include a P-type field-effect transistor 303 and an N-type field-effect transistor 302. In two adjacent drive cables 300, one drive cable 300 has a P-type field-effect transistor 303, and the other drive cable 300 has an N-type field-effect transistor 302. The drive cable 300 connecting the first output terminal 211 and the second output terminal 212 has an N-type field-effect transistor 302, and the drive cable 300 connecting the third output terminal 213 and the fourth output terminal 214 has a P-type field-effect transistor 303. When the first output terminal 211 or the second output terminal 212 needs to activate a pixel row, the first output terminal 211 or the second output terminal 212 outputs a high level. This high level is applied to the gate of the N-type field-effect transistor 302, turning it on and charging the pixel for display. When the first output terminal 211 or the second output terminal 212 needs to close a pixel row, it outputs a low level. This low level is applied to the gate of the N-type field-effect transistor 302, turning it off and extinguishing pixel discharge. When the third output terminal 213 or the fourth output terminal 214 needs to open a pixel row, it outputs a low level. This low level is applied to the gate of the P-type field-effect transistor 303, turning it on and enabling pixel charging and display. When the third output terminal 213 or the fourth output terminal 214 needs to close a pixel row, it outputs a high level. This high level is applied to the gate of the P-type field-effect transistor 303, turning it off and extinguishing pixel discharge.

[0059] In two adjacent drive cables 300, one drive cable 300 uses a P-type field-effect transistor 303, and the other drive cable 300 uses an N-type field-effect transistor 302, forming a pair of complementary metal-oxide-semiconductor inverters 202. Traditional drive circuits use a single type of transistor, typically an N-type field-effect transistor 302, to drive all pixel rows. During line-by-line scanning, when one row of pixels turns on and the next row is about to turn on, the voltage difference between the two rows may not be large enough, resulting in incomplete pixel activation, unstable brightness, and flickering perceived by the human eye. In this application, the N-type field-effect transistors 302 and P-type field-effect transistors are designed to alternate between rows, electrically staggering the on and off times of adjacent rows of pixels. This naturally creates a complementary phase relationship between the switching signals of adjacent rows of pixels. When one row of pixels is stably on, its adjacent row of pixels is stably off, with a clear voltage boundary between them. This greatly eliminates flickering caused by voltage overlap and improves image stability.

[0060] Please see Figure 15The first clock signal 221 output from the first output terminal 211 and the third clock signal 223 output from the third output terminal 213 are both positive clock signals, along with the drive signal 108. The second clock signal 222 output from the second output terminal 212 and the fourth clock signal 224 output from the fourth output terminal 214 are both negative clock signals. In some feasible implementations, the first clock signal 221 output from the first output terminal 211 and the third clock signal 223 output from the third output terminal 213 can simultaneously turn on the transistors on the drive cable 300 connected to them at the first moment. By adjusting the number of the second buffer 206 and the third buffer 207 in the delay circuit 200, the second clock signal 222 output from the second output terminal 212 and the fourth clock signal 224 output from the fourth output terminal 214 can also simultaneously turn on the transistors on the drive cable 300 connected to them at the second moment. Furthermore, the second moment is later than the first moment, so that the drive unit 100 can simultaneously turn on two rows of pixels, achieving a dual-gate effect. By adjusting the number of buffers in the delay circuit 200, the first clock signal 221 output from the first output terminal 211, the third clock signal 223 output from the third output terminal 213, the second clock signal 222 output from the second output terminal 212, and the fourth clock signal 224 output from the fourth output terminal 214 can be turned on at intervals, respectively, so that the driving unit 100 turns on only one row of pixels at a time, achieving the effect of a single gate.

[0061] This application also provides a display panel, including, for example: Figure 9 The driving circuit shown is described. In some feasible implementations, the transistors on each driving cable 300 in the display panel are N-type field-effect transistors 302. The driving signal 108 output by the driving unit 100 is input through the first input terminal 201 of the delay circuit 200 and becomes a first clock signal 221 output by the first output terminal 211 and a second clock signal 222 output by the second output terminal 212. The second clock signal 222 is later than the first clock signal 221. Both the first clock signal 221 and the second clock signal 222 can control the transistors on the driving cable 300 to turn on. With this architecture, one driving unit 100 in the display panel can control the turning on and off of two rows of pixels and turn on adjacent rows of pixels at intervals, achieving a single-gate effect. This reduces the number of driving units 100 and the line area occupied by the driving units 100 in the display panel, thereby reducing the bezel width of the display panel and also reducing the power consumption of the display panel.

[0062] In some feasible implementations, the transistors in the display panel include P-type field-effect transistors 303 and N-type field-effect transistors 302. The drive cables 300 in the display panel are arranged such that all transistors on one drive cable 300 are N-type field-effect transistors 302, while the transistors on adjacent drive cables 300 are all P-type field-effect transistors 303. This alternating arrangement of P-type and N-type field-effect transistors 303 allows the third output terminal 213 and the fourth output terminal 214 of the delay circuit 200 to also be connected to a drive cable 300. Therefore, the drive signal 108, after passing through the delay circuit 200, becomes a first clock signal 221, a second clock signal 222, a third clock signal 223, and a fourth clock signal 224. By controlling the number of second buffers 206 and third buffers 207 in the delay circuit 200, the first clock signal 221, the third clock signal 223, the second clock signal 222, and the fourth clock signal 224 can sequentially and intermittently control the activation of the transistors on the drive cables 300, achieving a single-gate effect. Alternatively, the first clock signal 221 and the third clock signal 223 can simultaneously turn on the transistors on their corresponding drive cables 300, and then the second clock signal 222 and the fourth clock signal 224 can control the turn-on of the transistors on their corresponding drive cables 300, achieving a dual-gate effect. This architecture allows one drive unit 100 in the display panel to control the on and off of four rows of pixels, significantly reducing the number of drive units 100 and the line area occupied by each drive unit 100 in the display panel, increasing the possibility of achieving a narrow bezel in the display panel, and greatly reducing the power consumption of the display panel.

[0063] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0064] Furthermore, the use of terms such as "first," "second," etc., in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0065] In this application, unless otherwise expressly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0066] Furthermore, the technical solutions of the various embodiments of this application can be combined with each other, but only if they are based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by this application.

[0067] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A driving circuit, characterized in that, include: Multiple drive cables, each of which is used to connect multiple transistors; A driving unit, the driving unit including an output signal terminal, the output signal terminal being used to output a driving signal; The delay circuit includes a first input terminal, a first output terminal, a second output terminal, an inverter, a first buffer, a first NAND gate, and a second NAND gate; The first input terminal, the first output terminal, and the second output terminal are electrically connected; The inverter is connected between the first input terminal and the first NAND gate, the first buffer is connected between the first input terminal and the second NAND gate, the output terminal of the first NAND gate is connected to the input terminal of the second NAND gate, and the output terminal of the second NAND gate is connected to the input terminal of the first NAND gate. The output signal terminal is connected to the first input terminal, the first output terminal is connected between the first buffer and the second NAND gate, and the first output terminal is used to output the first clock signal; The second output terminal is connected to the side of the first NAND gate away from the inverter, and the second output terminal is used to output a second clock signal that is later than the first clock signal; In two adjacent drive cables, one drive cable is connected to the first output terminal, and the other drive cable is connected to the second output terminal.

2. The driving circuit as described in claim 1, characterized in that, Both the first clock signal and the second clock signal are positive clock signals, and the transistors on each of the drive cables are N-type field-effect transistors.

3. The driving circuit as described in claim 1 or 2, characterized in that, A second buffer is connected between the second output terminal and the first NAND gate.

4. The driving circuit as described in claim 1, characterized in that, The delay circuit further includes a third output terminal and a fourth output terminal. The third output terminal is connected between the inverter and the first NAND gate, and the fourth output terminal is connected to the side of the second NAND gate away from the first buffer.

5. The driving circuit as described in claim 4, characterized in that, A third buffer is connected between the fourth output terminal and the second NAND gate.

6. The driving circuit as described in claim 4, characterized in that, The driving unit also includes a gate-off signal terminal. The transistors on each driving cable are N-type field-effect transistors. The third output terminal is connected to the gate-off signal terminal, and the fourth output terminal is connected to the gate-off signal terminal.

7. The driving circuit as described in claim 4, characterized in that, The transistors on each drive cable are N-type field-effect transistors, and the third output terminal is grounded and the fourth output terminal is grounded.

8. The driving circuit as described in claim 1, characterized in that, The delay circuit also includes a third output terminal and a fourth output terminal, each of which is connected to a driving cable. The driving cables connected to the first output terminal, the second output terminal, the third output terminal, and the fourth output terminal are all different.

9. The driving circuit as described in claim 8, characterized in that, The transistors include P-type field-effect transistors and N-type field-effect transistors. In two adjacent driving cables, the transistor on one driving cable is a P-type field-effect transistor and the transistor on the other driving cable is an N-type field-effect transistor. The transistor on the driving cable connecting the first output terminal and the second output terminal is an N-type field-effect transistor, and the transistor on the driving cable connecting the third output terminal and the fourth output terminal is a P-type field-effect transistor.

10. A display panel, characterized in that, Includes the drive circuit as described in any one of claims 1-9.

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