Image sensor

Abstract

An image sensor includes: a substrate having a first surface and a second surface; a deep element isolation pattern in the substrate to define a plurality of pixel regions; a shallow element isolation pattern adjacent to the first surface to define a first active region, a second active region, and a third active region separated between the plurality of pixel regions; a floating diffusion region in the first active region; a control source / drain region in the second active region; a source follower gate on the third active region; and a gate insulating film between the source follower gate and the third active region. The source follower gate and the gate insulating film extend to the control source / drain region. The source follower gate passes through the gate insulating film and is in direct contact with the control source / drain region.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0062792, filed on May 13, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to image sensors. Background Technology

[0003] An image sensor is a semiconductor device that converts light images into electrical signals. Recently, with the development of the computer and communications industries, the demand for image sensors with improved performance has increased in various fields such as digital cameras, camcorders, personal communication systems (PCS), gaming devices, security cameras, and medical miniature cameras. Image sensors can be classified into "charge-coupled device" (CCD) type and "complementary metal-oxide-semiconductor" (CMOS) type. CMOS image sensors have multiple pixels arranged in a two-dimensional pattern. Each pixel includes a photodiode (PD). The photodiode is used to convert incident light into an electrical signal. Summary of the Invention

[0004] An image sensor that minimizes parasitic capacitance is provided.

[0005] According to one aspect of this disclosure, an image sensor includes: a substrate having a first surface and a second surface opposite to the first surface; a deep element isolation pattern in the substrate to define a plurality of pixel regions; a shallow element isolation pattern adjacent to the first surface to define a first active region, a second active region, and a third active region, wherein the first active region, the second active region, and the third active region are spaced apart in the plurality of pixel regions; a floating diffusion region in the first active region; a control source / drain region in the second active region; a source follower gate on the third active region; and a gate insulating film between the source follower gate and the third active region; wherein the source follower gate and the gate insulating film extend to the control source / drain region, and wherein the source follower gate passes through the gate insulating film and is in direct contact with the control source / drain region.

[0006] According to one aspect of this disclosure, an image sensor includes: a substrate having a first surface and a second surface opposite to the first surface; a deep element isolation pattern in the substrate to define a plurality of pixel regions including a plurality of pixel groups; a shallow element isolation pattern adjacent to the first surface to define a first active region, a second active region, and a third active region, wherein the first active region, the second active region, and the third active region are spaced apart from at least one of the plurality of pixel groups; a photoelectric conversion region in at least one of the plurality of pixel regions; a floating diffusion region in at least one of the first active regions; a control source / drain region in the second active region; a source follower gate on the third active region; a gate insulating film between the source follower gate and the third active region; and a color filter and a microlens, sequentially stacked on the second surface of the substrate, wherein the first active regions are respectively disposed in at least one of the plurality of pixel regions of the plurality of pixel groups, wherein the source follower gate and the gate insulating film extend on the control source / drain region, and wherein the source follower gate passes through the gate insulating film and is in direct contact with the control source / drain region.

[0007] According to one aspect of this disclosure, an image sensor includes: a first substrate having a first surface and a second surface opposite to the first surface; a deep element isolation pattern in the first substrate to define a pixel region; a first shallow element isolation pattern adjacent to the first surface of the first substrate to define a first active region in the pixel region; a photoelectric conversion region in at least one of the pixel regions; an interlayer insulating film on the first surface of the first substrate; a second substrate disposed on the interlayer insulating film, wherein the second substrate has a third surface facing the first surface of the first substrate and a fourth surface opposite to the third surface; and a second shallow element isolation pattern. An isolation pattern is provided, adjacent to a third surface of a second substrate, to define a second active region and a third active region; floating diffusion regions are respectively located in the first active region; a control source / drain region is located in the second active region; a source follower gate is disposed on the third surface of the second substrate, wherein the source follower gate spans the third active region; and a gate insulating film is disposed between the third active region and the source follower gate, wherein the source follower gate and the gate insulating film extend over the control source / drain region, and wherein the source follower gate passes through the gate insulating film and is in direct contact with the control source / drain region. Attached Figure Description

[0008] The above and other aspects, features and advantages of specific embodiments of the present disclosure will become clearer from the following description taken in conjunction with the accompanying drawings.

[0009] Figure 1 This is a block diagram of an image sensor according to an embodiment of the present disclosure.

[0010] Figure 2 This is a circuit diagram of the pixel array of the image sensor disclosed herein.

[0011] Figure 3 This is a circuit diagram of a pixel array of an image sensor according to an embodiment of the present disclosure.

[0012] Figure 4 This is a plan view of an image sensor according to an embodiment of the present disclosure.

[0013] Figure 5 Is with Figure 4 The sectional view corresponding to line I-I'.

[0014] Figure 6 Is with Figure 4 The sectional view corresponding to line II-II'.

[0015] Figure 7 Is with Figure 4 The sectional view corresponding to line III-III'.

[0016] Figure 8 Is with Figure 4 The sectional view corresponding to line IV-IV'.

[0017] Figure 9 This is a cross-sectional view of an image sensor according to an embodiment of the present disclosure.

[0018] Figure 10 This is a plan view of an image sensor according to an embodiment of the present disclosure.

[0019] Figure 11 This is a plan view of an image sensor according to an embodiment of the present disclosure.

[0020] Figure 12 This is a plan view of an image sensor according to an embodiment of the present disclosure.

[0021] Figure 13 This is a plan view of an image sensor according to an embodiment of the present disclosure.

[0022] Figure 14 and Figure 15 This is a plan view of an image sensor according to an embodiment of the present disclosure.

[0023] Figure 16 This is a cross-sectional view of an image sensor according to an embodiment of the present disclosure.

[0024] Figure 17 This is a plan view of an image sensor according to an embodiment of the present disclosure.

[0025] Figure 18This is a cross-sectional view of an image sensor according to an embodiment of the present disclosure.

[0026] Figures 19A to 25C These are cross-sectional and plan views illustrating a method for manufacturing an image sensor according to an embodiment of the present disclosure. Detailed Implementation

[0027] The description merely illustrates the principles of this disclosure. Those skilled in the art will be able to design one or more arrangements, although these arrangements are not explicitly described herein, but embody the principles of this disclosure. Furthermore, all examples set forth herein are primarily intended for illustrative purposes only to aid the reader in understanding the principles of this disclosure and the concepts contributed by the inventors to advance the art, and should be construed as not being limited to such specific examples and conditions. Moreover, all statements regarding the principles, aspects, and embodiments of this disclosure set forth herein, as well as specific examples thereof, are intended to cover their equivalents.

[0028] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the scope of another embodiment. Singular expressions may include plural expressions unless explicitly different in the context. Terms used herein (including technical or scientific terms) may have the same meaning as commonly understood by one of ordinary skill in the art described in this disclosure. Terms used in this disclosure that are defined in a general dictionary may be interpreted with the same or similar meaning as in the context of related art, and are not to be interpreted in an ideal or overly formal sense unless explicitly defined in this disclosure. In some cases, even terms defined in this disclosure should not be construed as excluding embodiments of this disclosure.

[0029] In one or more embodiments of this disclosure described below, hardware methods are described as examples. However, since one or more embodiments of this disclosure involve techniques using both hardware and software, various embodiments of this disclosure do not exclude software-based methods.

[0030] Furthermore, in this disclosure, expressions greater than or less than may be used to determine whether a particular condition is met or fulfilled. However, this is merely a description for illustrative purposes and does not exclude descriptions of being greater than or equal to, or less than or equal to. A condition described as “more than or equal to” may be replaced with “more than”, a condition described as “less than or equal to” may be replaced with “less than”, and a condition described as “more than or equal to and less than” may be replaced with “more than and less than or equal to”.

[0031] When used with a list of items, the phrase "at least one of..." means that different combinations of one or more of the listed items may be used, and that only one item from the list may be required. For example, "at least one of A, B, and C" includes any of the following combinations: A, B, C, A and B, A and C, B and C, and A and B and C, and any variations thereof. As an additional example, the expression "at least one of A, b, or c" may indicate only A, only b, only c, both A and b, both A and c, both b and c, all of A, b, and c, or variations thereof. Similarly, the term "set" means one or more. Therefore, a set of items can be a single item or a combination of two or more items.

[0032] Figure 1 This is a block diagram of an image sensor according to an embodiment of the present disclosure. (Refer to...) Figure 1 The image sensor according to some embodiments of the present disclosure may include a pixel array 1, a row decoder 2, a row driver 3, a column decoder 4, a timing generator 5, a correlated double sampler (CDS) 6, an analog-to-digital converter (ADC) 7, and an input / output buffer (I / O buffer) 8.

[0033] Pixel array 1 may include a plurality of pixels arranged in a two-dimensional manner. According to one embodiment, some of the pixels may be configured to form pixel groups, and multiple pixel groups may be arranged in a two-dimensional manner in pixel array 1. Pixels can convert optical signals into electrical signals. Pixel array 1 may be driven by a plurality of drive signals (e.g., pixel selection signals, reset signals, and / or charge transfer signals) sent from row driver 3. The converted electrical signals may be provided to the associated dual sampler 6.

[0034] The row driver 3 can provide multiple drive signals to the pixel array 1 for driving multiple pixels based on the decoding results from the row decoder 2. When the pixels are arranged in a matrix, the drive signals can be provided on a row-by-row basis.

[0035] Timing generator 5 can provide timing signals and control signals to row decoder 2 and column decoder 4.

[0036] The correlated double sampler 6 can receive electrical signals generated from the pixel array 1, and can hold and sample the received signals. The correlated double sampler 6 can double sample a specific noise level and a signal level caused by the electrical signal to output a difference level corresponding to the difference between the noise level and the signal level.

[0037] The analog-to-digital converter 7 can convert the analog signal corresponding to the difference level output from the correlated dual sampler 6 into a digital signal, and can output a digital signal.

[0038] The input / output buffer 8 can latch digital signals and output the latched signals sequentially to the image signal processor based on the decoding results from the column decoder 4.

[0039] Figure 2 This is a circuit diagram of pixels included in a pixel array of an image sensor according to an embodiment of the present disclosure. Figure 3 This is a circuit diagram of a pixel group included in a pixel array of an image sensor according to an embodiment of the present disclosure.

[0040] Reference Figure 2 The pixel array may include multiple pixels PXL, and the pixels PXL may be arranged in a matrix. Each (or at least one) of the pixels PXL may include a transfer transistor TX and logic transistors CX, SX, and SFX. The logic transistors CX, SX, and SFX may include a control transistor CX, a selection transistor SX, and a source follower transistor SFX. The transfer gate of the transfer transistor TX may be connected to a transfer gate line TGL. Each (or at least one) of the pixels PXL may also include a photoelectric conversion element PD and a floating diffusion region FD.

[0041] A photoelectric conversion element (PD) can generate and accumulate photocharge in proportion to the amount of light incident from the outside. The PD can include a photodiode, phototransistor, photogate, pinned photodiode, or a combination thereof. A transfer transistor (TX) can transfer the photocharge generated from the PD to a floating diffusion region (FD). The floating diffusion region (FD) can receive and accumulate the photocharge generated from the PD.

[0042] The gate of a source follower transistor (SFX) can be connected to the floating diffusion region (FD). One source / drain electrode of the source follower transistor SFX can be connected to the power supply voltage node V. DD The source follower transistor SFX can be controlled based on the amount of photocharge accumulated in the floating diffusion region FD.

[0043] The control transistor CX can be used as a reset transistor to periodically reset the charge accumulated in the floating diffusion region FD. The gate of the control transistor CX can be connected to the reset gate line RGL. The source / drain electrodes of the control transistor CX can be connected to the floating diffusion region FD and the power supply voltage node V, respectively. DD For example, the power source / drain electrode of the control transistor CX can be connected to the power supply voltage node V. DD Furthermore, the control source / drain electrode of the control transistor CX can be connected to the floating diffusion region FD. When the control transistor CX is turned on, the power supply voltage node V DD The power supply voltage can be discharged to reset the floating diffusion region FD.

[0044] A source follower transistor (SFX) can be used as a source follower buffer amplifier. The SFX amplifies the potential change in the floating diffuser region (FD) and outputs the amplified potential change to the output line V. OUT .

[0045] The gate of the selector transistor SX can be connected to the select gate line SGL. The source / drain electrodes of the selector transistor SX can be connected to the other source / drain electrode of the source follower transistor SFX and the output line V, respectively. OUT The selection transistor SX of the pixel PXL to be read in rows can be selected by applying a selection signal via the corresponding selection gate line SGL. When the selection transistor SX is turned on, the potential change amplified by the source follower transistor SFX can be output to the output line V via the selection transistor SX. OUT .

[0046] Reference Figure 3 The pixel array may include multiple pixel groups PXLG, and each (or at least one) of the pixel groups PXLG may include photoelectric conversion elements and multiple transistors respectively disposed on the multiple pixels.

[0047] The multiple transistors may include the aforementioned transfer transistor TX, control transistor CX, source follower transistor SFX, and select transistor SX.

[0048] In one embodiment, the transmission transistor TX may be disposed in each (or at least one) of the pixels. For example, the transmission transistor TX of the pixel group PXLG may include the first transmission transistor TX1 to the eighth transmission transistor TX8. The photoelectric conversion elements PD1 to PD8 may also be disposed in the pixels of the pixel group PXLG respectively. In some embodiments, the first transmission transistor TX1 to the eighth transmission transistor TX8 may be respectively connected to the first transmission gate line TGL1 to the eighth transmission gate line TGL8.

[0049] In one embodiment, multiple control transistors CX can be disposed in the pixel group PXLG. For example, the control transistors CX may include a first control transistor CX1 and a second control transistor CX2. In this case, the first control transistor CX1 can be used as a reset transistor, and the second control transistor CX2 can be used as a dual-conversion gain transistor. The power supply source / drain electrode of the first control transistor CX1 can be connected to the power supply voltage node V. DD The control source / drain electrode of the second control transistor CX2 can be connected to the floating diffusion region FD, and the first control transistor CX1 and the second control transistor CX2 can be connected in series at the power supply voltage node V. DDBetween the floating diffusion region FD and the first control transistor CX1 and the second control transistor CX2. In one embodiment, at least one capacitor or at least one transistor may be connected to the common source / drain electrode between the first control transistor CX1 and the second control transistor CX2.

[0050] The pixels in the pixel group PXLG can share control transistors CX1 and CX2, floating diffusion region FD, source follower transistor SFX, and selection transistor SX.

[0051] In one embodiment, a pixel group PXLG comprising two control transistors CX1 and CX2 is disclosed, but embodiments of this disclosure are not limited thereto. In one embodiment, the pixel group PXLG may include a greater number of control transistors CX, and the conversion gain mode can be flexibly set by appropriately turning the control transistors CX on and off. In this case, the control transistors CX may include multiple common source / drain electrodes disposed between the control transistors. In some embodiments, the bias current Ibias can be drawn from the output line V OUT Output.

[0052] Figure 4 This is a plan view of an image sensor according to an embodiment of the present disclosure. Figure 5 Is with Figure 4 The sectional view corresponding to line I-I' Figure 6 Is with Figure 4 The sectional view corresponding to line II-II' Figure 7 Is with Figure 4 The sectional view corresponding to line III-III', and Figure 8 Is with Figure 4 The sectional view corresponding to line IV-IV'. Content repeated above will be omitted in the following text.

[0053] exist Figures 4 to 6 In this image sensor, a substrate 101 and a pixel group PXLG disposed on the substrate 101 may be a pixel group PXLG, which may be the smallest unit repeatedly arranged in a matrix in a pixel array. In one embodiment, a pixel group PXLG may include a pixel array arranged in a matrix of 2 Pixels PXL arranged in a 2-matrix configuration. In one embodiment, a pixel group PXLG may include pixels arranged in a 2-matrix configuration. 4. Pixels PXL arranged in a matrix. However, the number of pixels PXL included in a pixel group PXLG is not limited to this, and the pixel group PXLG can include a variety of numbers of pixels PXL.

[0054] In one embodiment, each (or at least one) of pixels PXL may include a pair of subpixels SPXL. For example, as Figure 4 As shown, pixel group PXLG can include 2 The first pixels PXL1 to the fourth pixels PXL4 are arranged in a matrix form, and the first pixels PXL1 to the fourth pixels PXL4 may include first sub-pixels SPXL1 to eighth sub-pixels SPXL8. However, the embodiments disclosed herein are not limited thereto.

[0055] The pixel group PXLG may include a photoelectric conversion region formed in the substrate 101, a transistor disposed on the substrate 101, various wirings disposed on the substrate 101, and a component isolation pattern.

[0056] Substrate 101 may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, a group II-VI compound semiconductor substrate, a group III-V compound semiconductor substrate, or a silicon-on-insulator (SOI) substrate. Substrate 101 may include impurities of a first conductivity type, and therefore, substrate 101 may have a first conductivity type. For example, the impurities of the first conductivity type may be group III elements. For example, the impurities of the first conductivity type may include p-type impurities (such as aluminum (Al), boron (B), indium (In), and / or gallium (Ga)).

[0057] Photoelectric conversion region (see) Figure 16 The 180 in the first conductivity type may include impurities of a second conductivity type, different from the first conductivity type, and therefore, the photoelectric conversion region may have a second conductivity type. For example, the second conductivity type may be a group V element. For example, impurities of the second conductivity type may include n-type impurities (such as phosphorus, arsenic, bismuth, and / or antimony).

[0058] The substrate 101 and the photoelectric conversion region can be a PN junction to form the aforementioned photoelectric conversion element PD. The substrate 101 can have a first surface 101F and a second surface opposite to the first surface 101F. The first surface 101F can be the front surface of the substrate, and the second surface can be the rear surface of the substrate. Light can be incident on the second surface of the substrate 101.

[0059] A deep element isolation pattern 111 may extend through the substrate 101 to define a plurality of pixel regions, and a shallow element isolation pattern 113 may be formed adjacent to a first surface 101F of the substrate to define a plurality of active regions in the plurality of pixel regions. In some embodiments, at least two of the plurality of pixel regions may form a pixel group, and the plurality of pixel regions may include a plurality of pixel groups.

[0060] A deep element isolation pattern 111 may be formed in the substrate 101 to surround each (or at least one) of the pixel regions when viewed from a plan view. For example, the deep element isolation pattern 111 may be formed by filling a deep trench formed via patterning the substrate 101 with an insulating material (i.e., deep trench isolation (DTI) technique). The pixel region surrounded by the deep element isolation pattern 111 may be a portion of the substrate 101.

[0061] The deep element isolation pattern 111 may be provided in a manner that extends through the substrate 101. For example, the deep element isolation pattern 111 may extend through the first and second surfaces of the substrate 101 and the substrate body between the first and second surfaces of the substrate 101.

[0062] In one embodiment, each (or at least one) of the pixel regions may be defined within each (or at least one) of the pixels PXL. Photoelectric conversion regions may be separately disposed within the pixel regions. In one embodiment, when each (or at least one) of the pixels PXL includes a pair of sub-pixels SPXL, each (or at least one) of the pixel regions may include a pair of sub-pixel regions. The pair of sub-pixel regions may be separated by at least one of various isolation techniques. For example, the pair of sub-pixel regions may be separated by a doped isolation technique. That is, a doped isolation region may be disposed between the pair of sub-pixel regions. In one embodiment, the pair of sub-pixel regions may be separated from each other by a doped isolation region and a deep element isolation pattern 111. That is, a doped isolation region and a deep element isolation pattern 111 may be disposed between the pair of sub-pixel regions. In one embodiment, only the deep element isolation pattern 111 may be disposed between the pair of sub-pixel regions. When each (or at least one) of the pixel regions includes a pair of sub-pixel regions, photoelectric conversion regions may be separately disposed within the pair of sub-pixel regions.

[0063] In one embodiment, the deep element isolation pattern 111 may include a conductive isolation film disposed in a deep trench and an insulating pad disposed between the substrate 101 and the conductive isolation film. The conductive isolation film may include a conductive material (such as a doped semiconductor material (e.g., doped polysilicon)). The conductive isolation film may be spaced apart from the substrate 101 by the insulating pad, and therefore, the conductive isolation film may be electrically isolated from the substrate 101 during operation of the image sensor.

[0064] The shallow component isolation pattern 113 can be disposed in a shallow trench recessed to a predetermined depth from the first surface 101F. For example, the shallow component isolation pattern 113 can be formed by a technique (i.e., shallow trench isolation (STI) using an insulating material technique to fill the shallow trench) and can not penetrate the substrate 101. The shallow component isolation pattern 113 may include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0065] In one embodiment, a shallow element isolation pattern 113 may define active regions spaced apart from each other within a pixel region. For example, the shallow element isolation pattern 113 may be disposed between active regions to electrically isolate the active regions from each other. Specifically, the shallow element isolation pattern 113 may electrically isolate a first active region and a second active region, a first active region and a third active region, a first active region and a fourth active region, a first active region and a fifth active region, a second active region and a fifth active region, a third active region and a fifth active region, and a fourth active region and a fifth active region. In some embodiments, the first active region, the second active region, and the third active region may be defined in at least one of a plurality of pixel regions.

[0066] In one embodiment, the deep element isolation pattern 111 may partially overlap with the shallow element isolation pattern 113. The overlapping portion of the deep element isolation pattern 111 and the shallow element isolation pattern 113 may correspond to a portion of the shallow element isolation pattern 113 or a portion of the deep element isolation pattern 111. Hereinafter, for ease of explanation, the overlapping portion of the deep element isolation pattern 111 and the shallow element isolation pattern 113 will be described as a portion of the shallow element isolation pattern 113. In one embodiment, the shallow element isolation pattern 113 may include a recessed region 120 defined by partially recessing the shallow element isolation pattern 113.

[0067] Gates TG, SFG1, SFG2, CG1, CG2, and SG can be disposed on a first surface 101F of substrate 101. An interlayer insulating film 170 can be disposed on the first surface 101F of substrate 101 to cover the gates. Wiring 163 can be disposed on interlayer insulating film 170. Each (or at least one) of wiring 163 can be electrically connected to a corresponding gate or sludge region (e.g., source / drain region or ground region) via contact plugs 161 passing through interlayer insulating film 170.

[0068] Each (or at least one) of the active regions may be a portion of a substrate 101 surrounded by a shallow element isolation pattern 113 when viewed from a planar perspective. The active regions may be defined from a first surface 101F of the substrate 101 to a predetermined depth. Each (or at least one) of the gates may be disposed on the corresponding active region. In one embodiment, a source / drain region, a floating diffusion region, and a ground region GND may be formed in the active regions. For example, a plurality of floating diffusion regions FD, the source / drain regions of a source follower transistor, the source / drain regions of a control transistor (control source / drain region 143 and common source / drain region 145), the source / drain region of a select transistor, and the ground region GND may be disposed in the active regions.

[0069] In one embodiment, the plurality of pixel regions may include first to fifth active regions spaced apart from each other. A floating diffusion region (FD) may be disposed in the first active region, and a control source / drain region and a power source / drain region may be disposed in the second active region. The control source / drain region and the power source / drain region may respectively correspond to reference... Figure 2 and Figure 3 The control source / drain electrode and power source / drain electrode are described. The third and fourth active regions may include source / drain regions respectively disposed in the third and fourth active regions, and the fifth active region may include a ground region GND. In one embodiment, when multiple control transistors are provided, the second active region may further include at least one common source / drain region disposed in the second active region. The common source / drain region may correspond to a reference. Figure 3 Described common source / drain electrodes.

[0070] Gates TG, SFG1, SFG2, CG1, CG2, and SG may comprise a conductive material (e.g., doped polysilicon). In one embodiment, gates TG, SFG1, SFG2, CG1, CG2, and SG may further comprise a metal-containing material (e.g., metal silicide) disposed on the doped polysilicon.

[0071] A gate insulating film 131 may be disposed between the active region and the gates TG, SFG1, SFG2, CG1, CG2, and SG, and a gate spacer 133 may be disposed on each (or at least one) of the side surfaces of the gates TG, SFG1, SFG2, CG1, CG2, and SG. In one embodiment, the gate insulating film 131 may extend along at least one of the gates when at least one of the gates TG, SFG1, SFG2, CG1, CG2, and SG extends onto another active region. In some embodiments, the gate insulating film 131 may be disposed between the transmission gate TG and the first active region.

[0072] The transfer gate TG can be disposed on a first active region on one side of the floating diffusion region FD. In one embodiment, the transfer gate TG can fill a gate trench formed in the first active region on one side of the floating diffusion region FD. In this case, the gate insulating film 131 can also be disposed between the transfer gate TG and the inner surface of the gate trench. When the transfer gate TG fills the gate trench, the transfer transistor can be a vertical channel transistor. In one embodiment, the transfer gate TG can be configured as an electrode in each pixel or each sub-pixel, but is not limited thereto. In one embodiment, the transfer gate TG can be configured as a pair of electrodes spaced apart from each other in each pixel or each sub-pixel.

[0073] Multiple first active regions can be defined. Each first active region can be defined within a pixel region. When each (or at least one) pixel region includes a pair of sub-pixel regions, the first active regions can be defined within the sub-pixel regions respectively.

[0074] The first control gate CG1 can be disposed on the second active region on one side of the power supply source / drain region, and the power supply voltage node V DD It can be connected to the power source / drain region. The first control gate CG1 can correspond to the reset gate. In some embodiments, the first control gate CG1 can be disposed on a second active region on one side of the control source / drain region 143, and the control source / drain region 143 and the first control gate CG1 can form a reset transistor.

[0075] The second control gate CG2 can be disposed on a second active region on one side of the control source / drain region 143. The second control gate CG2 can correspond to a dual-conversion gain gate. In some embodiments, the second control gate CG2 can be disposed on a second active region between the control source / drain region 143 and the first control gate CG1.

[0076] A common source / drain region 145 may be disposed in a second active region between the first control gate CG1 and the second control gate CG2. At least one capacitor or at least one transistor may be electrically connected to the common source / drain region 145. In some embodiments, the common source / drain region 145 and the first control gate CG1 may form a reset transistor, and the control source / drain region 143, the second control gate CG2, and the common source / drain region 145 may form a double-conversion gain transistor.

[0077] The source follower gates SFG1 and SFG2 may be disposed on the third active region and may extend over at least one of the first active region, the second active region, and the shallow element isolation pattern 113.

[0078] For example, the source follower gates SFG1 and SFG2 may extend over at least one of the floating diffusion region FD in the first active region, the control source / drain region 143 in the second active region, and the shallow element isolation pattern 113.

[0079] When the source follower gates SFG1 and SFG2 extend over the shallow element isolation pattern 113, the source follower gates SFG1 and SFG2 can fill the recessed region 120 defined in the shallow element isolation pattern 113.

[0080] For example, source follower gates SFG1 and SFG2 can fill the recessed region 120 in the shallow element isolation pattern 113 defined between the control source / drain region 143 and the floating diffusion region FD, and can also fill the recessed region in the shallow element isolation pattern 113 defined between the floating diffusion region FD and the second active region and / or between the floating diffusion region FD and the third active region. In some embodiments, the shallow element isolation pattern 113 at both sides of the third active region can be recessed to expose the two side surfaces of the third active region, and the source follower gates SFG1 and SFG2 and the gate insulating film 131 can be on the exposed two side surfaces of the third active region.

[0081] In one embodiment, the pixel regions of a pixel group may include a plurality of third active regions spaced apart from each other, and the source follower gates SFG1 and SFG2 may include a first source follower gate SFG1 and a second source follower gate SFG2 respectively disposed on the third active regions. In this case, the first source follower gate SFG1 and the second source follower gate SFG2 may extend to be directly connected to each other. That is, the first source follower gate SFG1 and the second source follower gate SFG2 may form a single body with no interface between the first source follower gate SFG1 and the second source follower gate SFG2. In this case, the integrally connected first source follower gate SFG1 and the second source follower gate SFG2 may fill the recessed region 120 in the shallow element isolation pattern 113 defined between the third active regions.

[0082] In one embodiment, the gate insulating film 131 may extend between the extensions of the source follower gates SFG1 and SFG2 and the substrate 101.

[0083] For example, the gate insulating film 131 may extend along at least one of the source follower gates SFG1 and SFG2 in the first active region, the second active region, and the shallow element isolation pattern 113. For example, the gate insulating film 131 may extend along the floating diffusion region FD in the first active region, the control source / drain region 143 in the second active region, and the shallow element isolation pattern 113 of the source follower gates SFG1 and SFG2.

[0084] In one embodiment, the source follower gates SFG1 and SFG2 can penetrate the gate insulating film 131 to directly contact the active region. According to one embodiment, the source follower gates SFG1 and SFG2 can penetrate the gate insulating film 131 to directly contact the control source / drain region 143 in the second active region. Alternatively, the source follower gates SFG1 and SFG2 can penetrate the gate insulating film 131 to directly contact the floating diffusion region FD in the first active region.

[0085] The select gate SG can be disposed on the fourth active region, and the source / drain regions can be disposed on both sides of the select gate SG in the fourth active region. The source / drain regions of the fourth active region can correspond to the source / drain electrodes of the select transistor, and can be connected to them respectively. Figure 3 The other source / drain electrode and output line V of the source follower transistor in the middle OUT .

[0086] As described above, the interlayer insulating film 170 can be disposed on the first surface 101F of the substrate 101, and the wiring 163 can be disposed on the interlayer insulating film 170. The wiring 163, as shown, can form a multilayer structure. In this case, multiple interlayer insulating films 170 can be sequentially stacked on the first surface 101F of the substrate 101. In one embodiment, the wiring can form a single-layer structure. In one embodiment, a bonding pad 165 can be disposed on the uppermost interlayer insulating film 170. The bonding pad 165 can be electrically connected to the corresponding wiring 163 via contact plugs 161.

[0087] Wiring 163 may include gate lines TGL, RGL, and SGL (see...) Figure 3 ), power supply voltage line V DD Output line V OUT (See Figure 3 This includes battery voltage lines, local connection lines, etc. Wiring 163 can be connected to the corresponding source / drain regions and the corresponding gate via contact plugs 161, thereby achieving... Figure 2 PXL pixels or Figure 3 The pixel group PXLG. In one embodiment, wiring 163 and contact plug 161 may not be connected to the source follower gates SFG1 and SFG2.

[0088] For example, the select gate SG can be connected to the corresponding wiring 163 via a contact plug 161 disposed on the select gate SG. The transmit gate TG can be connected to the corresponding wiring 163 via a contact plug 161 disposed on the transmit gate TG. The first control gate CG1 can be connected to the corresponding wiring 163 via a contact plug 161 disposed on the first control gate CG1. The second control gate CG2 can be connected to the corresponding wiring 163 via a contact plug 161 disposed on the second control gate CG2. The ground region GND can be connected to the corresponding wiring 163 via a contact plug 161 disposed on the ground region GND.

[0089] Additionally, one source / drain region of the source follower transistor located in the third active region can be electrically connected to one source / drain region of the select transistor located in the fourth active region via a corresponding contact plug 161 and a corresponding wiring 163. The other source / drain region of the select transistor can be electrically connected to a corresponding wiring 163 (e.g., output line V) via a corresponding contact plug 161. OUT The common source / drain region between the first control gate CG1 and the second control gate CG2 can be connected to at least one capacitor or at least one transistor via contact plug 161 and corresponding wiring 163. The other source / drain region of the source follower transistor and the power supply source / drain region of the first control transistor can be connected to the corresponding wiring 163 via corresponding contact plug 161, and the power supply voltage can be applied via the corresponding wiring 163.

[0090] Reference Figure 4 and Figure 5 The floating diffusion region FD and the control source / drain region 143 can be connected via source follower gates SFG1 and SFG2 extending from the third active region onto the shallow element isolation pattern 113. The recessed region 120 defined by recessing the shallow element isolation pattern 113 can be filled with the active follower gates SFG1 and SFG2.

[0091] In one embodiment, the gate insulating film 131 may be included between the source follower gates SFG1 and SFG2 and the control source / drain region 143, and the source follower gates SFG1 and SFG2 may pass through the gate insulating film 131 to directly contact the control source / drain region 143. Alternatively, the gate insulating film 131 may be included between the source follower gates SFG1 and SFG2 and the floating diffusion region FD, and the source follower gates SFG1 and SFG2 may pass through the gate insulating film 131 to directly contact the floating diffusion region FD. Furthermore, the gate insulating film 131 may even be included between the source follower gates SFG1 and SFG2 and the shallow element isolation pattern 113.

[0092] In one embodiment, the recessed region 120 may expose one side surface of the floating diffusion region FD and / or one side surface of the control source / drain region 143, and the source follower gates SFG1 and SFG2 filling the recessed region 120 may contact the exposed side surfaces of the floating diffusion region FD and the control source / drain region 143. That is, the gate insulating film 131 between the source follower gates SFG1 and SFG2 and the floating diffusion region FD can be removed, and the gate insulating film 131 between the source follower gates SFG1 and SFG2 and the control source / drain region 143 can also be removed. Additionally, the gate insulating film 131 between the source follower gates SFG1 and SFG2 and the shallow element isolation pattern 113 can also be removed.

[0093] Reference Figure 4 , Figure 6 and Figure 7 The source follower gate SFG1 can extend from the third active region to the first active region to connect to the floating diffusion region FD. The source follower gate SFG1 can also be disposed on the shallow element isolation pattern 113 between the third active region and the first active region, and the source follower gates SFG1 and SFG2 can fill the recessed region 120 defined by recessing the shallow element isolation pattern 113.

[0094] In one embodiment, the gate insulating film 131 may be disposed between the source follower gate SFG1 and the third active region, and the source follower gate SFG1 may pass through the gate insulating film 131 to be directly connected to the floating diffusion region FD. The portion of the source follower gate SFG1 passing through the gate insulating film 131 is not limited thereto. In one embodiment, the source follower gate SFG1 may pass through the gate insulating film 131 except for the recessed region 120 to be directly connected to the floating diffusion region FD.

[0095] Reference Figure 4 and Figure 8 The first source follower gate SFG1 of the first pixel PXL1 can extend from the third active region of the first pixel PXL1 to the first active region of the first pixel PXL1 to contact the floating diffusion region FD of the first pixel PXL1. The first source follower gate SFG1 of the first pixel PXL1 can also be disposed on the shallow element isolation pattern 113 between the third active region and the first active region in the first pixel PXL1, and the first source follower gate SFG1 can fill the recessed region 120 defined by recessing the shallow element isolation pattern 113.

[0096] Additionally, the second source follower gate SFG2 of the third pixel PXL3 can extend from the third active region of the third pixel PXL3 to the first active region of the third pixel PXL3 to contact the floating diffusion region FD of the third pixel PXL3. The second source follower gate SFG2 of the third pixel PXL3 can also be disposed on the shallow element isolation pattern 113 between the third active region and the first active region in the third pixel PXL3, and the second source follower gate SFG2 can fill the recessed region 120 defined by recessing the shallow element isolation pattern 113.

[0097] Furthermore, the first source follower gate SFG1 of the first pixel PXL1 and the second source follower gate SFG2 of the third pixel PXL3 can extend to connect with each other on the deep element isolation pattern 111 between the first pixel PXL1 and the third pixel PXL3. As described above, the first source follower gate SFG1 and the second source follower gate SFG2 can form a single body, with no interface between them. The integrally formed first source follower gate SFG1 and second source follower gate SFG2 can fill the recessed region 120 defined by recessing the shallow element isolation pattern 113 between the first pixel PXL1 and the third pixel PXL3. That is, the first source follower gate SFG1 of the first pixel PXL1 and the second source follower gate SFG2 of the third pixel PXL3 can form a single source follower gate in the pixel group PXLG.

[0098] Figure 9 This is a cross-sectional view of an image sensor including a shallow element isolation pattern with an extended recessed region, according to an embodiment of the present disclosure.

[0099] Reference Figure 6 and Figure 9 The size of the recessed area 120, defined by recessing the shallow element isolation pattern 113, can vary depending on the degree to which the shallow element isolation pattern 113 is recessed.

[0100] Figure 9 The concave area 120 can be compared to Figures 5 to 8 The depression is 120 mm deep. In this case, by Figure 9 The side surface of the third active region covered by the source follower gate SFG1 in the recessed region 120 can be wider. Therefore, it is limited to Figure 9 The width of the channel region in the third active region can be greater than that limited to Figure 6 The width of the channel region in the third active region is determined by the depth of the recessed region 120. As a result, the width of the channel region of the source follower transistor, including the source follower gate SFG1, can be adjusted by controlling the depth of the recessed region 120.

[0101] In the above embodiments, the source follower gate can be in direct contact with a control source / drain region 143 that serves as a source / drain region of a first control transistor (e.g., a reset transistor) or a source / drain region of a second control transistor (e.g., a dual-conversion gain transistor). Therefore, contact plugs and wiring for connecting the source follower gate and the control source / drain region 143 can be omitted. Alternatively, the source follower gate can be in direct contact with the floating diffusion region FD. Therefore, contact plugs and wiring for connecting the source follower gate and the floating diffusion region FD can be omitted.

[0102] Therefore, the parasitic capacitance between the source follower gate and the control source / drain region can be minimized, as can the parasitic capacitance between the source follower gate and the floating diffusion region (FD). Consequently, the capacitance of the floating node, composed of the electrically connected control source / drain region, source follower gate, and floating diffusion region, can be minimized, thereby improving the pixel's conversion gain.

[0103] Furthermore, the source follower gate can fill the recessed region of the shallow element isolation pattern. Therefore, the width of the channel region of the source follower transistor can be increased, thereby improving the performance of the source follower transistor. The image sensor according to one embodiment of this disclosure can be modified in various ways.

[0104] Figure 10 This is a plan view of an image sensor according to an embodiment of the present disclosure. (Refer to...) Figure 4 and Figure 10 , and the side of the transmission gate TG Figure 4 The first active region is different. Figure 10 The first active region can also be extended to be positioned on both sides of the transmission gate TG. When Figure 10 When the first active region extends, Figure 10 The second to fourth active regions can be smaller than Figure 4 The second to fourth active regions, and Figure 10 The fifth active region can be set in conjunction with... Figure 4 In different locations of the fifth active region.

[0105] As disclosed above, the first source follower gate SFG1 of the first pixel PXL1 and the second source follower gate SFG2 of the third pixel PXL3 can extend to be integrally connected between the first pixel PXL1 and the third pixel PXL3 on the deep element isolation pattern 111. The integrally formed first and second source follower gates (SFG1, SFG2) can fill the recessed region 120 formed at the boundary between the first pixel PXL1 and the third pixel PXL3.

[0106] Figure 4 The integrated source follower gate can span both the deep element isolation pattern and the shallow element isolation pattern between the second sub-pixel SPXL2 and the sixth sub-pixel SPXL6, while Figure 10 The integrated source follower gate can span deep element isolation patterns and shallow element isolation patterns between the first sub-pixel SPXL1 and the second sub-pixel SPXL2 and the fifth sub-pixel SPXL5 and the sixth sub-pixel SPXL6.

[0107] therefore, Figure 4 The shallow element isolation pattern may include a recessed area between the second sub-pixel SPXL2 and the sixth sub-pixel SPXL6, while Figure 10 The shallow element isolation pattern may include recessed areas between the first sub-pixel SPXL1 and the fifth sub-pixel SPXL5 and between the second sub-pixel SPXL2 and the sixth sub-pixel SPXL6.

[0108] Figure 11 This is a plan view of an image sensor according to an embodiment of the present disclosure. (Refer to...) Figure 10 and Figure 11 , Figure 11 The pixel group PXLG1 can be as disclosed above. Figure 4 and Figure 10 The pixel group PXLG is composed of the first pixel PXL1 to the fourth pixel PXL4. However, in Figure 11 In pixel group PXLG1, the pixel circuit region PXLCR can be set to be offset from the pixel region including the photoelectric conversion region.

[0109] For example, Figure 11 The first pixel group PXLG1 may include all of the following: two third active regions, two source follower gates SFG1 and SFG2, two fourth active regions, and a selection gate SG. However, the pixel circuit region PXLCR may include one third active region and one source follower gate SFG1 of the first pixel group PXLG1, and one third active region, one source follower gate SFG2, one fourth active region, and one selection gate SG of the second pixel group PXLG2. That is, Figure 11 The pixel circuit region PXLCR can be configured to transmit electrical signals from the transmission transistor of the first pixel group PXLG1 to the selection transistor of the second pixel group PXLG2 via the source follower transistors of the first pixel group PXLG1 and the second pixel group PXLG2.

[0110] Somewhat similar to an embodiment according to this disclosure Figure 10 The source follower gates SFG1 and SFG2, Figure 11The source follower gates SFG1 and SFG2 can span deep element isolation patterns between sub-pixels SPXL. For example, Figure 11 The source follower gates SFG1 and SFG2 can span the deep element isolation pattern and the shallow element isolation pattern between the fifth sub-pixel SPXL5 and the sixth sub-pixel SPXL6 ​​in the first pixel group PXLG1 and the first sub-pixel SPXL1 and the second sub-pixel SPXL2 in the second pixel group PXLG2.

[0111] therefore, Figure 11 The shallow element isolation pattern may include a recessed area between the fifth sub-pixel SPXL5 and the sixth sub-pixel SPXL6 ​​in the first pixel group PXLG1 and the first sub-pixel SPXL1 and the second sub-pixel SPXL2 in the second pixel group PXLG2.

[0112] Furthermore, for example, since the third active region and the fourth active region can be located outside the first pixel group PXLG1 and the first active region can be located inside the first pixel group PXLG1, therefore Figure 11 The source follower gates SFG1 and SFG2 may extend along a deep element isolation pattern in a third active region, and a floating diffusion region FD may be disposed on both sides of the source follower gates SFG1 and SFG2. In one embodiment, a shallow element isolation pattern that contacts the floating diffusion region FD on at least one side may include a recessed region, and the remaining shallow element isolation pattern may optionally include a recessed region.

[0113] Figure 12 This is a plan view of an image sensor including four photodiodes according to an embodiment of the present disclosure. (Refer to...) Figure 12 , Figure 12 The pixel group PXLG can consist of four pixels PXL1 to PXL4, and can include four transmission gates TG. Figure 4 , Figure 10 and Figure 11 The pixel group PXLG (which includes eight transmission gates TG in a single pixel group PXLG comprising eight sub-pixels SPXL) is different. Figure 12 The pixel group PXLG can consist of four pixels PXL1 to PXL4, each (or at least one) of which includes a transmission gate TG.

[0114] Figure 12The first pixel PXL1 may include a transmission gate TG, a select gate SG, and a ground region GND, which include a first active region, a fourth active region, and a fifth active region. The second pixel PXL2 may include a transmission gate TG and a first control gate CG1, which include a first active region and a second active region. The third pixel PXL3 may include a transmission gate TG and a source follower gate SFG, which include a first active region and a third active region. The fourth pixel PXL4 may include a transmission gate TG and a second control gate CG2, which include a first active region and a second active region.

[0115] Additionally, when viewed from a floor plan, Figure 12 The first active region can be configured to be connected to the source follower gate SFG, which extends to the center of the pixel group PXLG. In one embodiment, the first active regions of pixels PXL1 to PXL4 can be in direct contact with each other at the center of the pixel group PXLG to form a single body, or they can be spaced apart from each other while extending to the center of the pixel group PXLG.

[0116] In one embodiment, when Figure 12 When the first active regions in a pixel group PXLG are spaced apart from each other, a shallow element isolation pattern can be formed. Figure 12 Below the source follower gate SFG. The shallow element isolation pattern may include a recessed region, and the recessed region may be provided with a source follower gate SFG and a gate insulating film, and the source follower gate SFG may extend through the gate insulating film to directly contact the floating diffusion region FD of a plurality of first active regions.

[0117] A transfer gate TG may be disposed on each (or at least one) of the first active regions, but is not limited thereto. In one embodiment, the transfer gate TG of the first active region may comprise a pair of electrodes spaced apart from each other.

[0118] Unlike the embodiments described above, in Figure 12 In this context, multiple second active regions can be set in different pixels PXL. For example, Figure 12 The second active region may include a second active region disposed in the second pixel PXL2 and a second active region disposed in the fourth pixel PXL4. In this case, the common source / drain region between the first control gate CG1 and the second control gate CG2 can also be divided into two common source / drain regions. The common source / drain regions spaced apart from each other can be electrically connected by corresponding contact plugs 161 and corresponding wiring 163.

[0119] According to one embodiment, the second active region of the fourth pixel PXL4 can be in direct contact with a source follower gate SFG extending from the third active region along a deep element isolation pattern. For example, a shallow element isolation pattern stacked on the deep element isolation pattern of the pixel group PXLG can be in contact with the second active region of the fourth pixel PXL4, and the shallow element isolation pattern can include a recessed region defined by recessing the side of the shallow element isolation pattern that contacts the second active region. In this case, the source follower gate SFG extending along the deep element isolation pattern can fill the recessed region. That is, the source follower gate SFG can cover the shallow element isolation pattern exposed by the recess.

[0120] In one embodiment, the gate insulating film may be disposed between the source follower gate SFG and the shallow element isolation pattern and between the source follower gate SFG and the second active region, and the source follower gate SFG may pass through the gate insulating film to directly contact the control source / drain region in the second active region.

[0121] In one embodiment, the gate insulating film can be removed between the source follower gate SFG and the shallow element isolation pattern and between the source follower gate SFG and the second active region, and the source follower gate SFG can be in direct contact with the control source / drain region and the second active region in the shallow element isolation pattern.

[0122] As described above, the source follower gate SFG disposed on the third active region can extend from the third active region along the deep element isolation pattern and can contact the first active region and the second active region. When the source follower gate SFG is disposed above the deep element isolation pattern, the shallow element isolation pattern superimposed on the deep element isolation pattern corresponding to the position of the source follower gate SFG can be recessed to include the recessed region. That is, when viewed from a plan view, the shallow element isolation pattern superimposed on the deep element isolation pattern can include a recessed region in the region corresponding to the source follower gate SFG and the deep element isolation pattern, and the source follower gate SFG disposed in the corresponding region can fill the recessed region.

[0123] Figure 13 This is a plan view of an image sensor according to an embodiment of the present disclosure. Figure 14 and Figure 15 This is a plan view of an image sensor according to an embodiment of the present disclosure.

[0124] Reference Figures 13 to 15 , Figures 13 to 15 The pixel group PXLG can consist of eight pixels PXL1 to PXL8 and can include eight transmission gates TG. Figures 13 to 15 The active area in the middle is set with Figure 12 The active regions in the text are somewhat similar in location, but in Figures 13 to 15 In this context, since pixel group PXLG consists of eight pixels PXL1 to PXL8, the positions of some transistors may differ.

[0125] For example, Figures 13 to 15 The first pixel PXL1 and the seventh pixel PXL7 may include a transmission gate TG containing a first active region, a fifth active region and a spare active region, a ground region GND and a spare gate SpG. The second pixel PXL2 may include a transmission gate TG containing a first active region and a fourth active region and a select gate SG. The third pixel PXL3 to the fifth pixel PXL5 may include a transmission gate TG containing a first active region and a third active region and source follower gates SFG1 to SFG3. The sixth pixel PXL6 and the eighth pixel PXL8 may include a transmission gate TG containing a first active region and a second active region, a first control gate CG1 and a second control gate CG2.

[0126] Figures 13 to 15 Each (or at least one) in the first active region can have the same characteristics as... Figure 12 The shape of the first active region in the image is similar to that of the first active region. For example, when viewing pixel group PXLG from a planar view, Figures 13 to 15 Each (or at least one) of the first active regions can be configured to be connected to source follower gates SFG1 to SFG3 extending to the center of pixel group PXLG. Figures 13 to 15 In this context, multiple first active regions can be configured to correspond to the transmission gate TG, respectively.

[0127] exist Figures 13 to 15 In the diagram, when viewing pixel group PXLG from a planar view, some first active regions can be configured to connect to source follower gates SFG1 to SFG3 extending to the center of first pixels PXL1 to fourth pixels PXL4, and other first active regions can be configured to connect to source follower gates SFG1 to SFG3 extending to the center of fifth pixels PXL5 to eighth pixels PXL8. In this case, the first active regions of first pixels PXL1 to fourth pixels PXL4 can directly contact each other at the center of first pixels PXL1 to fourth pixels PXL4 to form a single body, or they can be spaced apart from each other while extending toward the center of first pixels PXL1 to fourth pixels PXL4. Similarly, the first active regions of fifth pixels PXL5 to eighth pixels PXL8 can directly contact each other at the center of fifth pixels PXL5 to eighth pixels PXL8 to form a single body, or they can be spaced apart from each other while extending toward the center of fifth pixels PXL5 to eighth pixels PXL8.

[0128] exist Figures 13 to 15 In this context, multiple second active regions can be set in different pixels. For example, in... Figures 13 to 15 In this configuration, the second active region may include a second active region disposed in the sixth pixel PXL6 and a second active region disposed in the eighth pixel PXL8. In this case, the common source / drain region between the first control gate CG1 and the second control gate CG2 can also be divided into two common source / drain regions. These spaced-apart common source / drain regions can be electrically connected via corresponding contact plugs and corresponding wiring.

[0129] According to one embodiment, the second active region of the sixth pixel PXL6 can be in direct contact with the source follower gates SFG1 to SFG3 extending from the third active region along the deep element isolation pattern. For example, a shallow element isolation pattern stacked on the deep element isolation pattern of the pixel group PXLG can be in contact with the second active region of the sixth pixel PXL6, and the shallow element isolation pattern can include a recessed region defined by recessing the side of the shallow element isolation pattern that contacts the second active region. In this case, the source follower gates SFG1 to SFG3 extending along the deep element isolation pattern can fill the recessed region. That is, the source follower gates SFG1 to SFG3 can cover the exposed shallow element isolation pattern by the recess.

[0130] In one embodiment, the gate insulating film may be disposed between the source follower gates SFG1 to SFG3 and the shallow element isolation pattern, and between the source follower gates SFG1 to SFG3 and the second active region, and the source follower gates SFG1 to SFG3 may pass through the gate insulating film to directly contact the control source / drain region in the second active region.

[0131] In one embodiment, the gate insulating film can be removed between the source follower gates SFG1 to SFG3 and the shallow element isolation pattern, and between the source follower gates SFG1 to SFG3 and the second active region, and the source follower gates SFG1 to SFG3 can be in direct contact with the control source / drain regions in the shallow element isolation pattern and the second active region.

[0132] As described above, the source follower gates SFG1 to SFG3 disposed on the third active region can extend from the third active region along the deep element isolation pattern and can contact the first active region and the second active region. When the source follower gates SFG1 to SFG3 are disposed above the deep element isolation pattern, the shallow element isolation pattern superimposed on the deep element isolation pattern corresponding to the positions of the source follower gates SFG1 to SFG3 can be recessed to include the recessed region. That is, when viewed from a plan view, the shallow element isolation pattern can include the recessed region at the position corresponding to the source follower gates SFG1 to SFG3 and the deep element isolation pattern, and the source follower gates SFG1 to SFG3 disposed at this position can fill the recessed region.

[0133] In one embodiment, source follower gates SFG1 to SFG3 can be respectively disposed in the third pixel PXL3 to the fifth pixel PXL5, and the first source follower gate SFG1 to the third source follower gate SFG3 can be selectively used.

[0134] In one embodiment, Figure 13 An embodiment is shown that selectively uses the first source follower gate SFG1. For example, Figure 13 The first source follower gate SFG1 can be extended from the third active region of the third pixel PXL3 along the deep element isolation pattern to be located at the center of the first pixel PXL1 to the fourth pixel PXL4 and the center of the fifth pixel PXL5 to the eighth pixel PXL8.

[0135] In one embodiment, Figure 14 An embodiment is shown that selectively uses a first source follower gate SFG1 and a second source follower gate SFG2. For example, Figure 14 The first source follower gate SFG1 can extend from the third active region of the third pixel PXL3 along the deep element isolation pattern, and Figure 14 The second source follower gate SFG2 can extend from the third active region of the fifth pixel PXL5 along the deep element isolation pattern. In this case, Figure 14 The first source follower gate SFG1 and the second source follower gate SFG2 can contact each other to form a single source follower gate, and the single source follower gate can fill the recessed area of ​​the shallow element isolation pattern stacked on the deep element isolation pattern.

[0136] Figure 14 The integrated source follower gate disclosed herein can extend to be disposed in the center of the first pixel PXL1 to the fourth pixel PXL4, and can also extend to be disposed in the center of the fifth pixel PXL5 to the eighth pixel PXL8.

[0137] In one embodiment, Figure 15 An embodiment is shown that selectively uses the first source follower gate SFG1 to the third source follower gate SFG3. For example, Figure 15 The first source follower gate SFG1 can extend from the third active region of the third pixel PXL3 along the deep element isolation pattern. Figure 15 The second source follower gate SFG2 can extend from the third active region of the fifth pixel PXL5 along the deep element isolation pattern, and the third source follower gate SFG3 can extend from the third active region of the fourth pixel PXL4 along the deep element isolation pattern. The first source follower gates SFG1 to the third source follower gate SFG3 can contact each other to form a single source follower gate, and the single source follower gate can fill a recessed region included in a shallow element isolation pattern stacked on the deep element isolation pattern.

[0138] Figure 15 The integrated source follower gate disclosed herein can extend to be disposed in the center of the first pixel PXL1 to the fourth pixel PXL4, and can also extend and be located in the center of the fifth pixel PXL5 to the eighth pixel PXL8.

[0139] Figure 16 and Figure 17 This is a cross-sectional view of an image sensor according to an embodiment of the present disclosure. (Refer to...) Figure 16 The image sensor may include a photoelectric conversion structure 10 and a peripheral structure 30. The photoelectric conversion structure 10 may include a first substrate 101 containing multiple photoelectric conversion regions 180, a deep element isolation pattern 111, a shallow element isolation pattern 113, a gate insulating film 131, a substrate insulating film 135 disposed on a second surface 101B of the first substrate 101, a contact plug 161, wiring 163, a bonding pad 165, an interlayer insulating film 170, microlenses LS disposed on the second surface 101B of the first substrate 101, and a color filter CF between the first substrate 101 and the multiple microlenses LS. The peripheral structure 30 may include a third substrate 105, a peripheral interlayer insulating film 175, and logic circuit elements 300.

[0140] The first substrate 101 may include a first surface 101F and a second surface 101B opposite to the first surface 101F, and the deep element isolation pattern 111 may pass through the first substrate 101 to define a pixel region.

[0141] A shallow element isolation pattern 113 may be disposed in the first substrate 101 and may be adjacent to the first surface 101F of the first substrate 101. The shallow element isolation pattern 113 may define an active region in a pixel region. For example, the shallow element isolation pattern 113 may define a first active region to a fifth active region in a pixel region.

[0142] A gate insulating film 131 may be disposed on a first surface 101F of the first substrate 101, and the gate insulating film 131 may be disposed between the first substrate 101 and the gates TG and SFG. In some embodiments, other gates CG1, CG2, and SG described in the above embodiments may also be disposed on the first surface 101F of the first substrate 101. In some embodiments, the source follower gate SFG may span a third active region.

[0143] A substrate insulating film 135 may be disposed on a second surface 101B of the first substrate 101. The substrate insulating film 135 may cover the second surface 101B of the first substrate 101 and may have a single-layer or multi-layer structure. For example, the substrate insulating film 135 may include a silicon-based insulating material (e.g., silicon oxide, silicon nitride, and / or silicon oxynitride) and / or an insulating metal oxide.

[0144] Color filters CF can be disposed on the substrate insulating film 135. In one embodiment, as shown, color filters CF can be disposed on the second surface 101B of the first substrate 101 to correspond to each (or at least one) of the pixels. In one embodiment, color filters CF can be configured to correspond to multiple pixels. Each (or at least one) of the color filters CF may include, but is not limited to, a red (R) color filter, a blue (B) color filter, and a green (G) color filter. In one embodiment, each (or at least one) of the color filters CF may include one of other color filters, such as a cyan (C) color filter, a yellow (Y) color filter, and a magenta (M) color filter. For example, 4, 9, and / or 16 color filters CF can be disposed in a pixel group.

[0145] An interlayer insulating film 170 may be disposed on a first surface 101F of a first substrate 101. The interlayer insulating film 170 may cover the first surface 101F of the first substrate 101 and may have a single-layer or multi-layer structure.

[0146] A microlens LS can be disposed on the second surface 101B of the first substrate 101. For example, the microlens LS can be disposed on a color filter CF. The microlens LS can include a lens pattern and a planarization portion. The planarization portion of the microlens LS can be disposed on the color filter CF. The lens pattern can be disposed on the planarization portion. The lens pattern can be integrally formed with the planarization portion and can be connected without an interface. The lens pattern can include the same material as the planarization portion. In one embodiment, the planarization portion can be omitted, and the lens pattern can be directly disposed on the color filter CF.

[0147] The lens pattern can be hemispherical. The lens pattern can focus incident light. The lens pattern can be positioned at a location corresponding to the photoelectric conversion region 180 of the first substrate 101. The microlens LS can be transparent to transmit light. The microlens LS can include organic materials (such as polymers). For example, the microlens LS can include photoresist materials or thermosetting resins.

[0148] The third substrate 105 may include a fifth surface 105F and a sixth surface opposite to the fifth surface 105F. An interlayer insulating film 175 may be disposed on the fifth surface 105F of the third substrate 105. The interlayer insulating film 175 may cover the fifth surface 105F of the third substrate 105 and may have a single-layer or multi-layer structure.

[0149] Logic circuit element 300 may include Figure 1 The row decoder 2, row driver 3, column decoder 4, timing generator 5, correlated double sampler (CDS) 6, analog-to-digital converter (ADC) 7, and input / output buffer 8.

[0150] Reference Figure 17 The image sensor may include a photoelectric conversion structure 10, an intermediate structure 20, and a peripheral structure 30. In one embodiment, the photoelectric conversion structure 10 may include a first gate insulating film 131 and a first shallow element isolation pattern 113. The intermediate structure 20 may be disposed between the photoelectric conversion structure 10 and the peripheral structure 30, and includes a second substrate 103, a second shallow element isolation pattern 115, gates CG2, SFG, SG, contact plugs 161, wiring 163, bonding pads 167, and an intermediate interlayer insulating film 173.

[0151] A first shallow element isolation pattern 113 may be disposed in a first surface 101F of a first substrate 101. The first shallow element isolation pattern 113 may be formed adjacent to the first surface 101F of the first substrate 101 and may define an active region in a pixel region. For example, the first shallow element isolation pattern 113 may define a first active region in a pixel region.

[0152] The second substrate 103 may include a third surface 103F and a fourth surface 103B opposite to the third surface 103F. A second shallow element isolation pattern 115 may be disposed in the second substrate 103. The second shallow element isolation pattern 115 may be formed adjacent to the third surface 103F of the second substrate 103 and may define an active region. For example, the second shallow element isolation pattern 115 may define a second active region to a fifth active region.

[0153] The first gate insulating film 131 can be disposed on the first surface 101F of the first substrate 101, and the first gate insulating film 131 can be disposed between the first substrate 101 and the gate TG.

[0154] The second gate insulating film 137 may be disposed on the third surface 103F of the second substrate 103, and the second gate insulating film 137 may be disposed between the second substrate 103 and the gates SFG, CG2, and SG. In some embodiments, the second gate insulating film 137 may be disposed between the third active region and the source follower gate SFG.

[0155] An interlayer insulating film 173 may be disposed on the third surface 103F of the second substrate 103. The interlayer insulating film 173 may cover the third surface 103F of the second substrate 103 and may have a single-layer or multi-layer structure.

[0156] Additionally, refer to Figure 16 The photoelectric conversion structure 10 and the peripheral structure 30 can be electrically connected via bonding pads 165 and 169. For example, bonding pads 165 and 169 can electrically connect a plurality of wirings 163 to logic circuit elements 300. An interlayer insulating film 170 can surround the first bonding pad 165 in the photoelectric conversion structure 10, and a peripheral interlayer insulating film 175 can surround the third bonding pad 169 in the peripheral structure 30. For example, the interlayer insulating film 170 can expose the top surface of the first bonding pad 165 in the photoelectric conversion structure 10, and the peripheral interlayer insulating film 175 can expose the bottom surface of the third bonding pad 169 in the peripheral structure 30.

[0157] Additionally, refer to Figure 17The photoelectric conversion structure 10 and the intermediate structure 20 can be electrically connected via bonding pads 165 and 167. For example, bonding pads 165 and 167 can electrically connect the wiring 163 of the photoelectric conversion structure 10 to the wiring of the intermediate structure 20. The interlayer insulating film 170 of the photoelectric conversion structure 10 can expose the top surface of the first bonding pad 165 in the photoelectric conversion structure 10, the intermediate interlayer insulating film 173 of the intermediate structure 20 can expose the bottom surface of the second bonding pad 167, and the third bonding pad 168 of the intermediate structure 20 can pass through the second substrate 103. The peripheral interlayer insulating film 175 of the peripheral structure 30 can expose the bottom surface of the third bonding pad 169 in the peripheral structure 30. In some embodiments, at least one of the floating diffusion regions FD can be electrically connected to the source follower gate SFG via the bonded first bonding pad 165 and the bonded second bonding pad 167 (i.e., the first bonding pad 165 and the second bonding pad 167 bonded to each other).

[0158] In one embodiment, the first to fourth bonding pads 165, 167, 168, and 169 may comprise copper. The first bonding pad 165 and the second bonding pad 167 may be bonded to each other using copper-copper bonding, and the third bonding pad 168 and the fourth bonding pad 169 may be bonded to each other using copper-copper bonding. In one embodiment, the bonded bonding pads 165 and 167 or 168 and 169 may form a single body with no interface between bonding pads 165 and 167 or 168 and 169. Additionally, the bonded interlayer insulating films among the plurality of interlayer insulating films 170, 173, and 175 may be bonded to form covalent bonds.

[0159] Figure 18 This is a plan view of an intermediate structure according to an embodiment of the present disclosure. (Refer to...) Figure 18 The intermediate structure may include the second to fifth active regions in the pixel group PXLG, the first control gate CG1 of the first control transistor, the second control gate CG2 of the second control transistor, the source follower gate SFG, the select gate SG, and the ground region GND. In one embodiment, since the photoelectric conversion region and the transmission gate of the transmission transistor are disposed in the photoelectric conversion structure, a plan view of the intermediate structure is not disclosed.

[0160] Figure 18 The source follower gate SFG can extend from the third active region to the second active region via a second shallow element isolation pattern to be disposed on the control source / drain region. The second shallow element isolation pattern between the second and third active regions can be recessed to expose the side surface of the control source / drain region, and the source follower gate SFG can cover the exposed side surface of the control source / drain region.

[0161] In one embodiment, a gate insulating film may be disposed between the source follower gate SFG and the second and third active regions, and the source follower gate SFG may pass through the gate insulating film to directly contact the second active region. In other words, the source follower gate SFG may pass through the gate insulating film to directly contact the control source / drain region.

[0162] Figures 19A to 25C These are cross-sectional and plan views illustrating a method for manufacturing an image sensor according to an embodiment of the present disclosure. Figure 19A It is a floor plan, and Figure 19B Is with Figure 19A The sectional view corresponding to line I-I'. (Refer to...) Figure 19A and Figure 19B A first photoresist pattern PR1 with a first opening OP1 can be formed on a substrate 101 having a deep element isolation pattern 111 and a shallow element isolation pattern 113. The first photoresist pattern PR1 can be used as an etching mask to recess the substrate 101 to form a plurality of gate trenches GTRs in the substrate 101. The gate trenches GTRs can be formed in a portion of the first active region and in the shallow element isolation pattern 113.

[0163] Figure 20A It's a floor plan. Figure 20B Is with Figure 20A The sectional view corresponding to line I-I', and Figure 20C Is with Figure 20A The sectional view corresponding to line II-II'. (Refer to...) Figures 20A to 20C The first photoresist pattern PR1 can be removed, and a second photoresist pattern PR2 with a second opening OP2 can be formed on the substrate 101. The second opening OP2 can expose a portion of the shallow element isolation pattern 113. The second photoresist pattern PR2 can be used as an etching mask to recess the shallow element isolation pattern 113 to form a recessed region 120. The shallow element isolation pattern 113 including the recessed region 120 can be limited to a shallow element isolation pattern that corresponds to the location of the source follower gate and contacts the floating diffusion region and / or the control source / drain region.

[0164] For example, the recessed region 120 may be formed in a shallow element isolation pattern 113 between the first active region and the second active region, in a shallow element isolation pattern 113 in contact with the first active region, in a shallow element isolation pattern 113 in contact with the control source / drain region in the second active region, in a shallow element isolation pattern 113 between the first active region and the control source / drain region, and in a shallow element isolation pattern 113 between the third active regions. Figure 20A The image shows a shallow element isolation pattern including a recessed region 120 according to one embodiment.

[0165] Figure 21A Is with Figure 20A The sectional view corresponding to line I-I', and Figure 21B Is with Figure 20A The sectional view corresponding to line II-II'. (Refer to...) Figures 21A to 21B The second photoresist pattern PR2 can be removed, and a gate insulating film 131 can be formed on the substrate 101. The gate insulating film 131 can be conformally formed on the first surface 101F of the substrate 101.

[0166] Figure 22A It's a floor plan. Figure 22B Is with Figure 22A The sectional view corresponding to line I-I', and Figure 22C Is with Figure 22A The sectional view corresponding to line II-II'. (Refer to...) Figures 22A to 22C A third photoresist pattern PR3 with a third opening OP3 can be formed on the substrate 101. Impurity ions can be implanted into the active region through the third opening OP3.

[0167] In one embodiment, an ion implantation process can be used to form a floating diffusion region (FD) and a source / drain region in the active region. For example, the floating diffusion region (FD) can be formed in a first active region, the control source / drain region, the common source / drain region, and the power source / drain region can be formed in a second active region, and the source / drain region can be formed in a third and a fourth active region.

[0168] Figure 23A It is a floor plan, and Figure 23B Is with Figure 23A The sectional view corresponding to line I-I'. (Refer to...) Figure 23A and Figure 23B The third photoresist pattern PR3 can be removed, and a fourth photoresist pattern PR4 with a fourth opening OP4 can be formed on the substrate 101. Impurity ions can be implanted into the first active region through the fourth opening OP4. The region where impurity ions are implanted can be a portion of the floating diffusion region FD. In other words, the impurity concentration in a portion of the floating diffusion region FD can be higher than the impurity concentration in other portions of the floating diffusion region FD. In one embodiment, a portion of the floating diffusion region FD with a higher impurity concentration can be in direct contact with the source follower gate described below.

[0169] Figure 24A It's a floor plan. Figure 24B Is with Figure 24A The sectional view corresponding to line I-I', and Figure 24C Is with Figure 24A The sectional view corresponding to line II-II'. (Refer to...) Figures 24A to 24C The fourth photoresist pattern PR4 can be removed, and a fifth photoresist pattern PR5 with a fifth opening OP5 can be formed on the substrate 101. The fifth opening OP5 can expose a portion of the gate insulating film 131. In one embodiment, the fifth opening OP5 can be superimposed with at least one of a portion of the control source / drain region 143, a portion of the floating diffusion region FD, and the recessed region 120. The fifth photoresist pattern PR5 can be used as an etching mask to remove the exposed portion of the gate insulating film 131.

[0170] Figure 25A It's a floor plan. Figure 25B Is with Figure 25A The sectional view corresponding to line I-I', and Figure 25C Is with Figure 25A The sectional view corresponding to line II-II'. (Refer to...) Figures 25A to 25C The fifth photoresist pattern PR5 can be removed. A conductive film can be formed on the first surface 101F of the substrate 101, and a patterning process can be performed on the conductive film to form a gate.

[0171] In one embodiment, a gate spacer 133 may be formed on a side surface of the gate. The gate spacer film may be conformally formed on a substrate 101 having the gate, and an anisotropic etching process may be performed on the gate spacer film to form the gate spacer 133.

[0172] As described above, according to embodiments of this disclosure, the source follower gate can be in direct contact with the control source / drain region and can be in direct contact with the floating diffusion region. Therefore, parasitic capacitance in the image sensor can be minimized. As a result, the performance of the image sensor can be enhanced because the conversion gain of the pixels can be improved.

[0173] Those skilled in the art will understand that various modifications and changes can be made to this disclosure without departing from the spirit and scope of the disclosure as set forth in the appended claims. For example, the above embodiments can be combined in various forms to a degree that is incompatible with each other.

Claims

1. An image sensor, comprising: A substrate having a first surface and a second surface opposite to the first surface; Deep element isolation patterns are used to define multiple pixel regions within a substrate; A shallow element isolation pattern is adjacent to a first surface to define a first active region, a second active region, and a third active region, wherein the first active region, the second active region, and the third active region are spaced apart in the plurality of pixel regions; The floating diffusion region is located in the first active region; Control the source / drain region in the second active region; The source follower gate is located in the third active region; and A gate insulating film is placed between the gate of the source follower and the third active region. In this design, the source follower gate and gate insulating film extend to control the source / drain region, and In this design, the source follower gate passes through the gate insulating film and is in direct contact with the control source / drain region.

2. The image sensor according to claim 1, wherein, The source follower gate and gate insulating film extend over the floating diffusion region, and In this configuration, the source follower gate passes through the gate insulating film and is in direct contact with the floating diffusion region.

3. The image sensor according to claim 2, wherein, Shallow element isolation pattern recesses are controlled between the source / drain regions and the floating diffusion region to define the recessed region, and The source follower gate fills the recessed region.

4. The image sensor according to claim 3, wherein, The recessed region exposes one side surface of the control source / drain region and one side surface of the floating diffusion region, and In this configuration, the gate of the source follower is in direct contact with the exposed side surface of the control source / drain region and the exposed side surface of the floating diffusion region.

5. The image sensor according to claim 2, wherein, A shallow element isolation pattern recess is formed between the floating diffusion region and the third active region to define the recessed region, and The source follower gate fills the recessed region.

6. The image sensor according to claim 1, further comprising: The first control gate is disposed on the second active region on one side of the control source / drain region. The source / drain region and the first control gate form a reset transistor.

7. The image sensor according to claim 1, further comprising: The first control gate is located on the second active region on one side of the control source / drain region; The second control gate is located in the second active region between the control source / drain region and the first control gate; as well as The common source / drain region is located in the second active region between the first control gate and the second control gate. The common source / drain region and the first control gate form a reset transistor, and The control source / drain region, the second control gate, and the common source / drain region form a dual-conversion gain transistor.

8. The image sensor according to claim 1, further comprising: The photoelectric conversion region is located in at least one of the plurality of pixel regions; as well as The transfer gate, on the first active region, The gate insulating film is located between the transmission gate and the first active region.

9. The image sensor according to claim 1, wherein, Shallow element isolation pattern recesses on both sides of the third active region expose the two side surfaces of the third active region, and In this context, the source follower gate and the gate insulating film are on the two exposed side surfaces of the third active region.

10. The image sensor according to claim 1, wherein, The first active region, the second active region, and the third active region are defined in at least one of the plurality of pixel regions.

11. The image sensor according to claim 1, wherein, At least two of the plurality of pixel regions form a pixel group. The plurality of pixel regions include a plurality of pixel groups. The first active region is defined in at least one of the plurality of pixel regions, and The second active region and the third active region are defined in at least one of the plurality of pixel groups.

12. The image sensor according to claim 11, wherein, At least one of the plurality of pixel groups includes a plurality of third active regions and a plurality of source follower gates respectively disposed on the plurality of third active regions, and Wherein, at least one of the multiple source follower gates of the multiple pixel groups forms an integral source follower gate.

13. The image sensor according to claim 1, wherein, At least one of the plurality of pixel regions includes a plurality of sub-pixel regions, and The first active region is defined in at least one of the plurality of sub-pixel regions.

14. An image sensor, comprising: A substrate having a first surface and a second surface opposite to the first surface; Deep element isolation patterns are defined in a substrate to define multiple pixel regions, said multiple pixel regions comprising multiple pixel groups; A shallow element isolation pattern is adjacent to a first surface to define a first active region, a second active region, and a third active region, wherein the first active region, the second active region, and the third active region are spaced apart in at least one of the plurality of pixel groups; The photoelectric conversion region is located in at least one of the plurality of pixel regions; A floating diffusion region, in at least one of the first active regions; Control the source / drain region in the second active region; The source follower gate is located in the third active region; A gate insulating film is located between the source follower gate and the third active region; and Color filters and microlenses are sequentially stacked on the second surface of the substrate. The first active region is respectively disposed in at least one of the plurality of pixel regions of the plurality of pixel groups. In this configuration, the source follower gate and gate insulating film extend over the control source / drain region, and In this design, the source follower gate passes through the gate insulating film and is in direct contact with the control source / drain region.

15. The image sensor according to claim 14, wherein, The source follower gate and gate insulating film extend over the floating diffusion region, and In this configuration, the source follower gate passes through the gate insulating film and is in direct contact with the floating diffusion region.

16. The image sensor according to claim 15, wherein, A shallow element isolation pattern recess is created between the floating diffusion region and the control source / drain region to define the recessed region, and The source follower gate fills the recessed region.

17. The image sensor of claim 14, further comprising: The first control gate is located on the second active region on one side of the control source / drain region; The second control gate is located in the second active region between the control source / drain region and the first control gate; as well as The common source / drain region is located in the second active region between the first control gate and the second control gate.

18. An image sensor, comprising: A first substrate has a first surface and a second surface opposite to the first surface; Deep element isolation patterns are used to define pixel regions in a first substrate; A first shallow element isolation pattern is adjacent to a first surface of a first substrate to define a first active region in a pixel region; Photoelectric conversion region, in at least one of the pixel regions; An interlayer insulating film is located on the first surface of the first substrate; A second substrate is disposed on an interlayer insulating film, wherein the second substrate has a third surface facing a first surface of the first substrate and a fourth surface opposite to the third surface; A second shallow element isolation pattern is adjacent to a third surface of a second substrate to define a second active region and a third active region; The floating diffusion region is located in the first active region; Control the source / drain region in the second active region; A source follower gate is disposed on a third surface of a second substrate, wherein the source follower gate spans a third active region; and A gate insulating film is disposed between the third active region and the gate of the source follower. In this configuration, the source follower gate and gate insulating film extend over the control source / drain region, and In this design, the source follower gate passes through the gate insulating film and is in direct contact with the control source / drain region.

19. The image sensor according to claim 18, wherein, A second shallow element isolation pattern recess is formed adjacent to the control source / drain region to define the recessed region, and The source follower gate fills the recessed region.

20. The image sensor of claim 18, further comprising: An intermediate interlayer insulating film is disposed on the third surface of the second substrate and covers the source follower gate; The first bonding pad is located in the upper part of the interlayer insulating film; as well as The second bonding pad is located in the lower part of the intermediate interlayer insulating film. Wherein, the first bonding pad is bonded to the second bonding pad, and In this context, at least one of the floating diffusion regions is electrically connected to the source follower gate via a first bonding pad and a second bonding pad that are bonded to each other.

Images