Image sensor

Abstract

To provide an image sensor with improved electrical and optical characteristics. [Solution] The image sensor of the present invention comprises a semiconductor substrate, a pixel isolation structure disposed within the semiconductor substrate and defining first and second pixel regions, a transmission gate electrode provided to the first pixel region, a floating diffusion region provided to the first pixel region on one side of the transmission gate electrode, a pixel gate electrode provided to the second pixel region, a source / drain region provided to the second pixel region on one side of the pixel gate electrode, a connecting conductive pattern disposed on the first surface of the semiconductor substrate and connecting the floating diffusion region and the source / drain region, including an edge portion adjacent to the outer wall, and a blocking pattern disposed between the edge portion of the connecting conductive pattern and the first surface of the semiconductor substrate.

Description

Technical Field

[0001] The present invention relates to an image sensor, and more particularly, to an image sensor with improved electrical and optical characteristics.

Background Art

[0002] An image sensor converts an optical image into an electrical signal. Recently, with the development of the computer and communication industries, the demand for image sensors with improved performance in various fields such as digital cameras, video cameras, PCS (Personal Communication System), game devices, security cameras, and medical micro cameras has been increasing.

[0003] Image sensors include charge-coupled devices (CCDs) and CMOS image sensors. Among these, CMOS image sensors have a simple driving method and can integrate a signal processing circuit on a single chip, enabling miniaturization of products. CMOS image sensors also have very low power consumption, making them easy to apply to products with limited battery capacity. In addition, since CMOS image sensors can use CMOS process technology compatibly, the manufacturing cost can be reduced. Therefore, as the use of CMOS image sensors becomes possible with high resolution along with technological development, their use has been increasing rapidly.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The present invention has been made in view of the above-mentioned prior art, and the object of the present invention is to provide an image sensor having improved electrical and optical characteristics. [Means for solving the problem]

[0006] An image sensor according to one aspect of the present invention, made to achieve the above objective, comprises a semiconductor substrate; a pixel isolation structure disposed within the semiconductor substrate and defining a first pixel region and a second pixel region; a transmission gate electrode provided to the first pixel region; a floating diffusion region provided to the first pixel region on one side of the transmission gate electrode; a pixel gate electrode provided to the second pixel region; a source / drain region provided to the second pixel region on one side of the pixel gate electrode; a connecting conductive pattern disposed on the first surface of the semiconductor substrate, connecting the floating diffusion region and the source / drain region, and including an edge portion adjacent to the outer wall; and a blocking pattern disposed between the edge portion of the connecting conductive pattern and the first surface of the semiconductor substrate.

[0007] To achieve the above objective, an image sensor according to another aspect of the present invention comprises a semiconductor substrate, a pixel isolation structure disposed within the semiconductor substrate and defining a first pixel region and a second pixel region, a photoelectric conversion region provided to the first pixel region and the second pixel region, a first transmission gate electrode and a first floating diffusion region on one side of the first transmission gate electrode provided to the first pixel region, a second transmission gate electrode and a second floating diffusion region on one side of the second transmission gate electrode provided to the second pixel region, and provided to the first pixel region and the second pixel region, respectively The semiconductor semiconductor comprises a pixel gate electrode and source / drain regions provided on both sides of each of the pixel gate electrode; a connecting conductive pattern connecting the first floating diffusion region and the second floating diffusion region and the first source / drain region within the source / drain region; and a blocking pattern disposed between the lower surface of the edge portion of the connecting conductive pattern and the first surface of the semiconductor substrate, wherein the connecting conductive pattern includes a first connecting portion in contact with the first floating diffusion region and the second floating diffusion region, and a second connecting portion extending from the first connecting portion and in contact with the first source / drain region.

[0008] An image sensor according to yet another aspect of the present invention made to achieve the above objectives includes: a semiconductor substrate having a first surface and a second surface opposite to the first surface; a pixel isolation structure disposed within the semiconductor substrate and defining a first pixel region to a fourth pixel region; a photoelectric conversion region provided within the semiconductor substrate in the first pixel region to the fourth pixel region; an element isolation film adjacent to the first surface of the semiconductor substrate; a transmission gate electrode provided in the first active portion of the first pixel region to the fourth pixel region; a floating diffusion region provided in the first active portion of the first pixel region to the fourth pixel region; a pixel transistor provided in the second active portion of the first pixel region to the fourth pixel region; and an image sensor disposed on the first surface of the semiconductor substrate and comprising the first pixel region to the fourth The element isolation film comprises a connecting conductive pattern that connects a floating diffusion region of four pixel regions and one first source / drain region in the pixel transistor, a blocking pattern disposed between the edge portion of the connecting conductive pattern and the first surface of the semiconductor substrate, a color filter disposed on the second surface of the semiconductor substrate corresponding to the pixel regions, a lattice structure disposed between the color filters and superimposed on the pixel isolation structure, and microlenses on the color filters, wherein the element isolation film defines the first active portion and the second active portion in each of the first to fourth pixel regions, and the connecting conductive pattern includes an edge portion adjacent to the outer wall and a pad portion in contact with the floating diffusion region and the first source / drain region.

[0009] Specific details of other embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0010] According to the present invention, by forming a connected conductive pattern that links floating diffusion regions that are separated from each other, it is possible to prevent the increase in capacitance and signal delay that occur when connecting using a metal layer, and to improve the conversion gain at the unit pixel level. Furthermore, it is possible to improve the wiring flexibility of the image sensor.

[0011] Furthermore, by placing a blocking pattern between the connected conductive pattern and the adjacent active pattern, electrical connection between the connected conductive pattern and the adjacent active pattern can be prevented. [Brief explanation of the drawing]

[0012] [Figure 1] This is a schematic diagram showing a unit pixel of a pixel array according to one embodiment of the present invention. [Figure 2] This is a plan view showing a unit pixel of a first example image sensor according to one embodiment of the present invention. [Figure 3A] This is a cross-sectional view taken along the line A-A' in Figure 2. [Figure 3B] This is an enlarged view of the P1 portion of Figure 3A. [Figure 4A] This is a cross-sectional view taken along the line B-B' in Figure 2. [Figure 4B] This is an enlarged view of section P2 in Figure 4A. [Figure 5A] This is a cross-sectional view of the first example, taken along the line C-C' in Figure 2. [Figure 5B] This is an enlarged view of section P3 in Figure 5A. [Figure 5C] This is a cross-sectional view of a modified example cut along the line C-C' in Figure 2. [Figure 6A] This is a cross-sectional view of the first example, taken along the line D-D' in Figure 2. [Figure 6B] This is a cross-sectional view of the second example, taken along the line D-D' in Figure 2. [Figure 6C] This is a cross-sectional view of the third example, taken along the line D-D' in Figure 2. [Figure 7] It is a plan view of a second example of an image sensor according to an embodiment of the present invention. [Figure 8] It is a plan view of a third example of an image sensor according to an embodiment of the present invention. [Figure 9] It is a plan view of a fourth example of an image sensor according to an embodiment of the present invention. [Figure 10] It is a plan view of a fifth example of an image sensor according to an embodiment of the present invention. [Figure 11] It is a plan view of a sixth example of an image sensor according to an embodiment of the present invention. [Figure 12] It is a diagram for explaining a method of manufacturing an image sensor according to an embodiment of the present invention, and is a cross-sectional view taken along line A-A' of FIG. 2. [Figure 13] It is a diagram for explaining a method of manufacturing an image sensor according to an embodiment of the present invention, and is a cross-sectional view taken along line A-A' of FIG. 2. [Figure 14] It is a diagram for explaining a method of manufacturing an image sensor according to an embodiment of the present invention, and is a cross-sectional view taken along line A-A' of FIG. 2. [Figure 15] It is a diagram for explaining a method of manufacturing an image sensor according to an embodiment of the present invention, and is a cross-sectional view taken along line A-A' of FIG. 2. [Figure 16] It is a diagram for explaining a method of manufacturing an image sensor according to an embodiment of the present invention, and is a cross-sectional view taken along line A-A' of FIG. 2. [Figure 17] It is a diagram for explaining a method of manufacturing an image sensor according to an embodiment of the present invention, and is a cross-sectional view taken along line A-A' of FIG. 2. [Figure 18] It is a diagram for explaining a method of manufacturing an image sensor according to an embodiment of the present invention, and is a cross-sectional view taken along line A-A' of FIG. 2. [Figure 19] It is a diagram for explaining a method of manufacturing an image sensor according to an embodiment of the present invention, and is a cross-sectional view taken along line A-A' of FIG. 2. [Figure 20] This is a plan view of an image sensor according to one embodiment of the present invention. [Figure 21] This is a schematic plan view of an image sensor including a semiconductor device according to one embodiment of the present invention. [Figure 22] This is a cross-sectional view of the first example, taken along the line I-I' in Figure 21. [Figure 23] This is a cross-sectional view of the second example, taken along the line I-I' in Figure 21. [Modes for carrying out the invention]

[0013] Hereinafter, specific examples of embodiments for implementing the image sensor of the present invention will be described in detail with reference to the drawings.

[0014] Figure 1 is a circuit diagram showing a unit pixel of a pixel array according to one embodiment of the present invention.

[0015] Referring to Figure 1, in this embodiment, the image sensor includes a plurality of unit pixels arranged in two dimensions, and each unit pixel PX converts an optical signal into an electrical signal.

[0016] Each unit pixel PX includes a photoelectric conversion circuit 1 and a pixel circuit 2.

[0017] The photoelectric conversion circuit 1 includes a plurality of photoelectric conversion groups (1a, 1b, 1c, 1d). The photoelectric conversion circuit 1 includes at least 4, 8, or 16 photoelectric conversion groups (1a, 1b, 1c, 1d). Each of the photoelectric conversion groups (1a, 1b, 1c, 1d) includes at least 2 photoelectric conversion elements (e.g., photodiodes), a plurality of transfer transistors, and a floating diffusion region. Each of the photoelectric conversion groups (1a, 1b, 1c, 1d) may include 4, 8, or 16 photoelectric conversion elements.

[0018] As an example, the photoelectric conversion circuit 1 includes first, second, third, and fourth photoelectric conversion groups (1a, 1b, 1c, 1d).

[0019] The first photoelectric conversion group 1a includes a first photodiode PD1, a second photodiode PD2, a first transmission transistor TX1, and a second transmission transistor TX2. The first and second transmission transistors (TX1, TX2) transmit the charge accumulated in the first and second photodiodes (PD1, PD2) to the floating diffusion region FD.

[0020] The second photoelectric conversion group 1b includes a third photodiode PD3, a fourth photodiode PD4, a third transmission transistor TX3, and a fourth transmission transistor TX4. The third and fourth transmission transistors (TX3, TX4) transmit the charge accumulated in the third and fourth photodiodes (PD3, PD4) to the floating diffusion region FD. The third photoelectric conversion group 1c includes a fifth photodiode PD5, a sixth photodiode PD6, a fifth transmission transistor TX5, and a sixth transmission transistor TX6. The fifth and sixth transmission transistors (TX5, TX6) transmit the charge accumulated in the fifth and sixth photodiodes (PD5, PD6) to the floating diffusion region FD. The fourth photoelectric conversion group 1d includes a seventh photodiode PD7, an eighth photodiode PD8, a seventh transmission transistor TX7, and an eighth transmission transistor TX8. The seventh and eighth transmission transistors (TX7, TX8) transmit the charge accumulated in the seventh and eighth photodiodes (PD7, PD8) to the floating diffusion region FD.

[0021] The first to fourth photoelectric conversion groups (1a, 1b, 1c, 1d) are commonly connected to the floating diffusion region FD. In other words, the first to eighth transmission transistors (TX1 to TX8) are commonly connected to the floating diffusion region FD.

[0022] Although the first to fourth photoelectric conversion groups (1a, 1b, 1c, 1d) are shown to each include two photodiodes, the present invention is not limited thereto, and each photoelectric conversion group may include four or eight photodiodes.

[0023] The transmission gate electrodes of the first to eighth transmission transistors (TX1 to TX8) are controlled by the first to eighth charge transmission signals (TG1 to TG8). In this specification, the transmission gate electrodes of each transmission transistor have a dual vertical gate structure. A dual vertical gate structure means that there are two vertical transmission gates corresponding to one photodiode. The same transmission control signal is applied to each of the two vertical transmission gates included in the dual vertical gate.

[0024] The floating diffusion region FD receives and cumulatively stores the charge generated by at least one of the first to eighth photodiodes (PD1 to PD8). The source follower transistor SF is controlled according to the amount of photocharge accumulated in the floating diffusion region FD.

[0025] The pixel circuit 2 includes a reset transistor (RX), a source follower transistor (SF), a selection transistor (SX), and a dual conversion gain transistor (DCX). In this embodiment, each unit pixel PX is disclosed to include four pixel transistors, but the present invention is not limited thereto, and the number of pixel transistors in each unit pixel PX can vary.

[0026] In detail, the reset transistor RX periodically resets the charge accumulated in the charge detection node (floating diffusion region FD) in response to the reset signal RG applied to the reset gate electrode. In detail, the source terminal of the reset transistor RX is connected to the double conversion gain transistor DCX or the floating diffusion region FD, and the drain terminal is connected to the pixel power supply voltage V PIX It is connected to the reset transistor RX and the double conversion gain transistor DCX, and the pixel power supply voltage V PIXThis charge is transferred to the floating diffusion region (FD). Consequently, the charge accumulated in the floating diffusion region (FD) is discharged, and the floating diffusion region (FD) is reset.

[0027] The dual conversion gain transistor DCX is connected between the floating diffusion region FD and the reset transistor RX. The dual conversion gain transistor DCX varies the conversion gain of a unit pixel PX by varying the capacitance of the floating diffusion region FD in response to the dual conversion gain control signal DCG.

[0028] Specifically, during image capture, low-light and high-light conditions are incident on the pixel array, and the dual-conversion-gain transistor DCX is turned on in high-light mode and turned off in low-light mode. The dual-conversion-gain transistor DCX provides different conversion gains for high-light and low-light modes.

[0029] When the dual-conversion-gain transistor DCX is turned on, the capacitance of the charge-detection node (floating diffusion region FD) increases, and the conversion gain decreases. When the dual-conversion-gain transistor DCX is turned off, the capacitance of the charge-detection node (floating diffusion region FD) decreases, and the conversion gain increases.

[0030] The source follower transistor SF is a source follower buffer amplifier that generates a source-drain current proportional to the amount of charge in the floating diffusion region FD input to the source follower gate electrode. The source follower transistor SF amplifies the potential change at the charge detection node and outputs the amplified signal to the output line Vout via the selection transistor SX. The drain terminal of the source follower transistor SF is connected to the pixel power supply voltage V PIX The source terminal of the source follower transistor SF is connected to the drain terminal of the selection transistor SX.

[0031] The selection transistor SX selects the unit pixel PX to read out row by row. When the selection transistor SX is turned on by the selection signal SG applied to the selection gate electrode, the electrical signal output to the source electrode of the source follower transistor SF is output to the output line V OUT Output to [this location].

[0032] Figure 2 is a plan view showing a unit pixel of a first example image sensor according to one embodiment of the present invention. Figures 3A, 4A, 5A, and 6A are cross-sectional views of a first example image sensor according to one embodiment of the present invention, which are cross-sectional views taken along lines A-A', B-B', C-C', and D-D' in Figure 2, respectively.

[0033] Figure 3B is an enlarged view of the P1 portion of Figure 3A. Figure 4B is an enlarged view of the P2 portion of Figure 4A. Figure 5B is an enlarged view of the P3 portion of Figure 5A. Figure 5C is a cross-sectional view of a modified example cut along the line C-C' in Figure 2, and Figures 6B and 6C are cross-sectional views of a modified example cut along the line D-D' in Figure 2.

[0034] Referring to Figures 2, 3A, 4A, 5A, and 6A, the image sensor according to this embodiment includes a photoelectric conversion circuit layer 10, a pixel circuit layer 20, and a light transmission layer 30.

[0035] The photoelectric conversion circuit layer 10 is positioned between the pixel circuit layer 20 and the light transmission layer 30 in a vertical view. The photoelectric conversion circuit layer 10 includes a semiconductor substrate 100, a pixel isolation structure PIS, an element isolation film STI, photoelectric conversion regions (110a, 110b, 110c, 110d), transmission gate electrodes (TG1, TG2, TG3, TG4), and floating diffusion regions (FD1, FD2).

[0036] The pixel circuit layer 20 includes pixel circuits (e.g., MOS transistors) electrically connected to the floating diffusion regions (FD1, FD2). In other words, the pixel circuit layer 20 includes the reset transistor RX, the selection transistor SX, the double conversion gain transistor DCX, and the source follower transistor SF, as previously described with reference to Figure 1, and includes wiring connected to the pixel circuits (2 in Figure 1).

[0037] In detail, the semiconductor substrate 100 has a first surface 100a (or front surface) and a second surface 100b (or back surface) that face each other. The semiconductor substrate 100 is a substrate on which a first conductivity type (e.g., p-type) bulk silicon substrate has a first conductivity type epitaxial layer formed on it, and is a substrate on which the bulk silicon substrate is removed during the manufacturing process of the image sensor, leaving only the p-type epitaxial layer. Alternatively, the semiconductor substrate 100 may be a bulk semiconductor substrate containing wells of the first conductivity type.

[0038] The semiconductor substrate 100 includes a plurality of pixel regions (PR1, PR2, PR3, PR4) defined by a pixel isolation structure PIS. The plurality of pixel regions (PR1, PR2, PR3, PR4) are arranged in a matrix shape along a first direction D1 and a second direction D2 that intersect each other.

[0039] The multiple pixel regions include first, second, third, and fourth pixel regions (PR1, PR2, PR3, PR4), where the first and second pixel regions P (PR1, PR2) are arranged adjacent to each other in the first direction D1, and the first and third pixel regions (PR1, PR3) are arranged adjacent to each other in the second direction D2. The second and fourth pixel regions (PR2, PR4) are adjacent to each other in the second direction D2, and the second and third pixel regions (PR2, PR3) are arranged diagonally. Here, the first and second directions (D1, D2) are parallel to the first surface 100a of the semiconductor substrate 100 and intersect each other. The third direction D3 is perpendicular to the first surface 100b of the semiconductor substrate 100.

[0040] As an example, the first to fourth pixel regions (PR1 to PR4) constitute one pixel group GPX. In this embodiment, a pixel group GPX containing four pixel regions is illustrated, but the present invention is not limited thereto. For example, a pixel group GPX may consist of six, eight, nine, or sixteen pixel regions.

[0041] Each of the first to fourth pixel regions (PR1 to PR4) is enclosed by a pixel separation structure PIS in a plan view. Each of the first to fourth pixel regions (PR1 to PR4) is defined by a pair of first parts Pa extending in the first direction D1 and a pair of second parts Pb extending in the second direction D2. The pixel separation structure PIS also includes a pair of third parts Pc in each of the first to fourth pixel regions (PR1 to PR4). The third parts Pc are separated from each other by extending from the first parts Pa in the second direction D2 or from the second parts Pb in the first direction D1.

[0042] As an example, the pixel isolation structure PIS penetrates the semiconductor substrate 100. In detail, the pixel isolation structure PIS has a length in a direction perpendicular to the surface of the semiconductor substrate 100 (i.e., in a third direction D3), and the length of the pixel isolation structure PIS is substantially the same as the vertical thickness of the semiconductor substrate 100. As another example, the pixel isolation structure PIS may extend perpendicularly from the first surface 100a to the second surface 100b of the semiconductor substrate 100 and be separated from the second surface 100b of the semiconductor substrate 100.

[0043] As an example, the pixel isolation structure PIS includes a liner insulating pattern 111, a embedding pattern 113, and a capping insulating pattern 115. The embedding pattern 113 penetrates a portion of the semiconductor substrate 100 perpendicularly, and the liner insulating pattern 111 is provided between the embedding pattern 113 and the semiconductor substrate 100. The capping insulating pattern 115 is positioned on top of the embedding pattern 113. The liner insulating pattern 111 and the capping insulating pattern 115 include at least one of silicon oxide, silicon oxynitride, and silicon nitride. The embedding pattern 113 includes an undoped polysilicon film or an impurity-doped polysilicon film. The embedding pattern 113 may include an air gap or a void. The capping insulating pattern 115 of the pixel isolation structure PIS contains the same insulating material as the element isolation film STI, and in some examples, the boundary between the capping insulating pattern 115 and the element isolation film STI may not be observed.

[0044] According to this embodiment, in each of the first to fourth pixel regions (PR1 to PR4), first and second photoelectric conversion regions (110a, 110b) are provided within the semiconductor substrate 100. Light incident from the outside is converted into an electrical signal in the first and second photoelectric conversion regions (110a, 110b).

[0045] The first and second photoelectric conversion regions (110a, 110b) are impurity regions doped with impurities of a second conductivity type (e.g., n-type), which is opposite to that of the first conductivity type semiconductor substrate 100. The first conductivity type semiconductor substrate 100 and the first and second photoelectric conversion regions (110a, 110b) constitute a pair of photodiodes. That is, a photodiode is formed by the junction between the first conductivity type semiconductor substrate 100 and the first or second photoelectric conversion region (110a, 110b). The first and second photoelectric conversion regions (110a, 110b) that constitute the photodiode generate and accumulate photocharge in proportion to the intensity of incident light.

[0046] In each of the first to fourth pixel regions (PR1 to PR4), there is a phase difference between the electrical signal output from the first photoelectric conversion region 110a and the electrical signal output from the second photoelectric conversion region 110b. The image sensor then measures the distance to the object by comparing the phase difference of the electrical signals output from the pair of first and second photoelectric conversion regions (110a, 110b), and can automatically correct the focus of the image sensor by determining whether the object is in focus, the degree of focus deviation, etc.

[0047] Each of the first and second photoelectric conversion regions (110a, 110b) has a first width in the first direction D1 and a first length in the second direction D2 that is greater than the first width. For example, the first length is approximately twice the first width.

[0048] The first and second photoelectric conversion regions (110a, 110b) are separated from each other in the first direction D1 via a third portion Pc of the pixel separation structure PIS. The third portion Pc of the pixel separation structure PIS physically reflects incident light at the edges of each of the first to fourth pixel regions (PR1 to PR4), thereby reducing crosstalk between the first and second photoelectric conversion regions (110a, 110b).

[0049] The element isolation film STI is positioned adjacent to the first surface 100a of the semiconductor substrate 100 in each of the first to fourth pixel regions (PR1 to PR4). The lower surface of the element isolation film STI is separated from the first and second photoelectric conversion regions (110a and 110b).

[0050] According to this embodiment, the element isolation film STI defines first and second active areas (ACT1, ACT2) in each of the first to fourth pixel regions (PR1 to PR4). The first and second active areas (ACT1, ACT2) are parts of the semiconductor substrate 100. In plan view, the first and second active areas (ACT1, ACT2) superimpose on the respective first and second photoelectric conversion regions (110a, 110b). In other words, each pixel region (PR1 to PR4) is provided with two first active areas ACT1 and two second active areas ACT2, but the present invention is not limited thereto.

[0051] The first active portion ACT1 and the second active portion ACT2 are separated from each other in the second direction D2 by the element isolation film STI and have different sizes and shapes. The first active portion ACT1 is shown in a T-shape, but the present invention is not limited thereto and can have a rectangular shape or various polygonal shapes. The second active portion ACT2 has a major axis in the second direction D2 and a minor axis in the first direction D1. Each of the second active portions ACT2 has a second length in the second direction D2 that is smaller than the first length of the first or second photoelectric conversion region (110a, 110b).

[0052] The first and second active parts (ACT1 and ACT2) of the third and fourth pixel regions (PR3 and PR4) are arranged in mirror symmetry with the first and second active parts (ACT1 and ACT2) of the first and second pixel P regions (PR1 and PR2).

[0053] The element isolation film STI is provided in a trench formed by recessing the first surface 100a of the semiconductor substrate 100. The element isolation film STI is formed of an insulating material.

[0054] As an example, referring together to Figures 3B, 4B, and 5B, the element isolation film STI includes a liner oxide film 101 and a liner nitride film 103 conformally covering the surface of the trench, and a filling oxide film 105 filling the trench in which the liner oxide film 101 and the liner nitride film 103 are formed. The filling oxide film 105 includes, for example, at least one of silicon oxide film, silicon oxynitride film, and silicon nitride film.

[0055] In each of the first to fourth pixel regions (PR1 to PR4), first and second transmission gate electrodes (TG1 and TG2) are positioned. The first and second transmission gate electrodes (TG1 and TG2) are each positioned on the first active portion ACT1. A portion of the first and second transmission gate electrodes (TG1 and TG2) is positioned in a trench formed by recessing the first surface 100a of the semiconductor substrate 100. A gate insulating film is interposed between the first and second transmission gate electrodes (TG1 and TG2) and the semiconductor substrate 100. Insulating spacers SP are positioned on both side walls of the first and second transmission gate electrodes (TG1 and TG2).

[0056] In this embodiment, each of the first and second transmission gate electrodes (TG1, TG2) has a dual vertical gate electrode structure including two vertical portions that extend into the semiconductor substrate. In one embodiment, the shape and position of the first and second transmission gate electrodes (TG1, TG2) can be varied in various ways.

[0057] In each of the first to fourth pixel regions (PR1 to PR4), a first floating diffusion region FD1 is provided within the first active region ACT1 on one side of the first transmission gate electrode TG1. A second floating diffusion region FD2 is provided within the first active region ACT1 on one side of the second transmission gate electrode TG2.

[0058] The first and second floating diffusion regions (FD1, FD2) are formed by doping the semiconductor substrate 100 with a dopant of the second conductivity type opposite to that of the semiconductor substrate 100. For example, the first and second floating diffusion regions (FD1, FD2) are n-type dopant regions.

[0059] Each of the first and second floating diffusion regions (FD1 and FD2) includes a first doping region FDa and a second doping region FDb within the first doping region FDa, where the dopant concentration in the second doping region FDb is higher than the dopant concentration in the first doping region FDa.

[0060] In each of the first, second, and fourth pixel regions (PR1, PR2, PR4), the first and second pixel gate electrodes (PG1, PG2) are respectively positioned on the second active region ACT2. In each of the first, second, and fourth pixel regions (PR1, PR2, PR4), the first pixel gate electrode PG1 is superimposed on the first photoelectric conversion region 110a, and the second pixel gate electrode PG2 is superimposed on the second photoelectric conversion region 110b.

[0061] In the third pixel region PR3, the pixel gate electrode PG is positioned on the second active region ACT2. In the third pixel region PR3, the pixel gate electrode PG is longer in the first direction D1 than the first and second gate electrodes (PG1, PG2). That is, the pixel gate electrode PG crosses the second active region ACT2 of the third pixel region PR3. The pixel gate electrode PG superimposes on portions of the first and second photoelectric conversion regions (110a, 110b) of the third pixel region PR3.

[0062] A first source / drain region SD1 is provided within the second active region ACT2 on one side of the first and second pixel gate electrodes (PG1, PG2) and the pixel gate electrode PG, and a second source / drain region SD2 is provided within the second active region ACT2 on the other side of the first and second pixel gate electrodes (PG1, PG2) and the pixel gate electrode PG.

[0063] In each of the first to fourth pixel regions (PR1 to PR4), the first and second pixel gate electrodes (PG1, PG2) and the pixel gate electrode PG constitute one of the pixel transistors described earlier with reference to Figure 1, namely the reset, source follower, double conversion gain, and selection transistors (RX, SF, DCX, SEL).

[0064] As an example, the first pixel gate electrode PG1 of the first pixel P region PR1 is supplied to the selection gate electrode as described with reference to Figure 1, and the pixel gate electrode PG of the third pixel region PR is supplied to the source follower gate electrode as described with reference to Figure 1. The first pixel gate electrode PG1 of the fourth pixel region PR4 is supplied to the double conversion gain gate electrode as described with reference to Figure 1. The second pixel gate electrode PG2 of the fourth pixel region PR4 is supplied to the reset gate electrode as described with reference to Figure 1. The functions of the first and second pixel gate electrodes (PG1, PG2) of the first to fourth pixel regions (PR1 to PR4) can be varied in various ways.

[0065] Insulating spacers SP are placed on both side walls of the first and second pixel gate electrodes (PG1, PG2).

[0066] Furthermore, a ground impurity region GR is provided between the first and second photoelectric conversion regions (110a, 110b) in each of the first to fourth pixel regions (PR1 to PR4). The ground impurity region GR is provided between the third portion Pc of the pixel isolation structure PIS. The ground impurity region GR is formed by doping with a dopant of the same first conductivity type as the semiconductor substrate 100.

[0067] According to one embodiment, a linked conductive pattern ICP is arranged on the first surface 100a of the semiconductor substrate 100 and is commonly connected to the first and second floating diffusion regions (FD1, FD2) provided to the first to fourth pixel regions (PR1 to PR4). The linked conductive pattern ICP is also commonly connected to the first source / drain region SD1 of a pixel transistor provided to at least one of the first to fourth pixel regions (PR1 to PR4). For example, the linked conductive pattern ICP is connected to the first source / drain region SD1 provided to one side of the first pixel gate electrode PG1 of the fourth pixel region PR4. For example, the linked conductive pattern ICP electrically connects the double conversion gain transistor (DCX in Figure 1) to the first and second floating diffusion regions (FD1, FD2).

[0068] Linked conductive pattern ICPs are formed from conductive materials. Linked conductive pattern ICPs are formed from single-crystal silicon or polysilicon doped with a second-type conductivity dopant. Linked conductive pattern ICPs also contain metallic materials such as tungsten, titanium, tantalum, and cobalt. In linked conductive pattern ICPs, the dopant concentration of the second-type conductivity dopant is higher than the dopant concentration in the second doping region FDb of the first and second floating diffusion regions (FD1, FD2).

[0069] The linked conductive pattern ICP has a first thickness on the first surface 100a of the semiconductor substrate 100, and each of the first and second pixel gate electrodes (PG1, PG2) has a second thickness on the first surface 100a of the semiconductor substrate 100. Here, the second thickness is greater than the first thickness.

[0070] In detail, the connected conductive pattern ICP includes an edge portion EP adjacent to its outer wall, and a pad portion PP in contact with the first and second floating diffusion regions (FD1, FD2) and the first source / drain region SD1. The connected conductive pattern ICP also includes a first connecting portion CP1 in contact with the first and second floating diffusion regions (FD1, FD2) in a plan view, and a second connecting portion CP2 extending from the first connecting portion CP1 and in contact with the first source / drain region SD1.

[0071] The first connecting portion CP1 is in direct contact with the second doping region FDb of the first and second floating diffusion regions (FD1, FD2) of the first to fourth pixel regions (PR1 to PR4). The second connecting portion CP2 is in direct contact with at least one of the first source / drain regions SD1, having a minimum width smaller than the minimum width of the first connecting portion CP1.

[0072] Referring to Figure 6A, the minimum width of the second connecting portion CP2 is substantially the same as the width W of the element isolation film STI. Referring to Figure 6B, the minimum width of the second connecting portion CP2 is greater than the width of the element isolation film STI. Referring to Figure 6C, the pad portion ICP of the connecting conductive pattern ICP is recessed into a portion of the element isolation film STI.

[0073] According to one embodiment, the linked conductive pattern ICP can have various shapes in a plan view depending on the arrangement structure of the pixel transistors.

[0074] Referring to Figures 3B, 4B, and 5B, the linked conductive pattern ICP has a first upper surface US1 in the edge portion EP and a second upper surface US2 in the pad portion PP. Here, with respect to the first surface 100a of the semiconductor substrate 100, the first upper surface US1 is located at a higher level than the second upper surface US2. The edge portion EP of the linked conductive pattern ICP is located on the first and second active portions (ACT1, ACT2) or on the element isolation film STI and the pixel isolation structure PIS, depending on its position.

[0075] The linked conductive pattern ICP has a first lower surface LS1 in contact with the element isolation film STI, first and second floating diffusion regions (FD1, FD2), and a second lower surface LS2 in contact with the first source / drain region SD1.

[0076] The first lower surface LS1 of the linked conductive pattern ICP is located at a lower level than the first surface 100a of the semiconductor substrate 100. Furthermore, the second lower surface LS2 of the linked conductive pattern ICP is located at a lower level than the upper surface of the device isolation film STI.

[0077] According to one embodiment, a blocking pattern BLK is arranged between the edge portion EP of the connected conductive pattern ICP and the semiconductor substrate 100, the element isolation film STI, or the pixel isolation structure PIS.

[0078] The blocking pattern BLK superimposes on the edge portion EP of the connecting conductive pattern ICP in a plan view. In other words, the blocking pattern BLK is positioned along the outer wall of the connecting conductive pattern ICP.

[0079] The blocking pattern BLK contains the same insulating material as the insulating spacers SP, which are placed on both side walls of the first and second transmission gate electrodes (TG1, TG2) and on both side walls of the first and second pixel gate electrodes (PG1, PG2). The blocking pattern BLK includes, for example, silicon oxide, silicon nitride, and / or silicon oxynitride. The blocking pattern BLK prevents the edge portion EP of the connecting conductive pattern ICP from contacting the first and second active portions (ACT1, ACT2).

[0080] Referring to Figures 3B, 4B, and 5B, the bottom surface of the blocking pattern BLK is located at a higher level than the bottom surface of the pad portion PP of the connecting conductive pattern ICP. The blocking pattern BLK has an outer wall SWa adjacent to the outer wall of the connecting conductive pattern ICP and an inner wall SWb opposite to the outer wall SWa. The outer wall SWa of the blocking pattern BLK is aligned perpendicularly to the outer wall of the connecting conductive pattern ICP. The inner wall SWb of the blocking pattern BLK has a predetermined slope with respect to the first surface 100a of the semiconductor substrate 100. The inner wall SWb of the blocking pattern BLK is in direct contact with the connecting conductive pattern ICP.

[0081] Referring to Figure 6A, the blocking pattern BLK is positioned between the second connecting portion CP2 of the connecting conductive pattern ICP and the device isolation film STI. Referring to Figures 5C and 6B, the blocking pattern BLK may be located on the boundary between the semiconductor substrate 100 and the device isolation film STI.

[0082] First and second etching stop films (140, 150) are sequentially laminated on the first surface 100a of the semiconductor substrate 100. The first and second etching stop films (140, 150) cover the first and second transmission gate electrodes (TG1, TG2), the first and second pixel gate electrodes (PG1, PG2), the pixel gate electrode PG, and the linked conductive pattern ICP with a uniform thickness. The first and second etching stop films (140, 150) contain silicon nitride. The second etching stop film 150 is thicker than the first etching stop film 140.

[0083] Referring to Figures 3B, 4B, and 5B, the first etching stop film 140 covers the outer wall SWa of the blocking pattern BLK and the outer wall of the connecting conductive pattern ICP with a uniform thickness.

[0084] The surface insulating film 102 is disposed on the first surface 100a of the semiconductor substrate 100, and a portion of the surface insulating film 102 is positioned between the first surface 100a of the semiconductor substrate 100 and the lower surface of the blocking pattern BLK. The surface insulating film 102 includes, for example, silicon oxide and / or silicon oxynitride.

[0085] The capping insulating film 131 conformally covers the surface of the linked conductive pattern ICP. The capping insulating film 131 is in contact with the outer wall of the linked conductive pattern ICP and the outer wall of the blocking pattern BLK. The capping insulating film 131 includes, for example, silicon oxide and / or silicon oxynitride.

[0086] An interlayer insulating film 210 is laminated on the first surface 100a of the semiconductor substrate 100, and the interlayer insulating film 210 covers the pixel transistors (RX, SF, DCX, SEL in Figure 1) and the first and second transmission gate electrodes (TG1, TG2) that constitute the pixel circuit (2 in Figure 1). The interlayer insulating film 210 includes, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0087] Within the interlayer insulating film 210, a contact plug 221 connected to a pixel circuit (2 in Figure 1) and wiring 222 connected to the contact plug 221 are arranged. One of the contact plugs 221 penetrates the interlayer insulating film 210 and the first and second etching stop films (140, 150) and is connected to a connecting conductive pattern ICP.

[0088] Referring to Figures 3A, 4A, 5A, and 6A, the light-transmitting layer 30 is placed on the second surface 100b of the semiconductor substrate 100. The light-transmitting layer 30 includes a flat insulating film 310, a lattice structure 320, a color filter (C / F) 330, and a microlens 340. The light-transmitting layer 30 collects and filters light incident from the outside and provides it to the photoelectric conversion circuit layer 10.

[0089] The flat insulating film 310 covers the second surface 100b of the semiconductor substrate 100. The flat insulating film 310 is formed of a transparent insulating material and includes multiple layers. The flat insulating film 310 is formed of an insulating material having a different refractive index than the semiconductor substrate 100. The flat insulating film 310 includes a metal oxide and / or silicon oxide.

[0090] The grid structure 320 is placed on the flat insulating film 310. The grid structure 320 has a grid shape in plan view, similar to the pixel separation structure PIS. The grid structure 320 superimposes the pixel separation structure PIS in plan view. That is, the grid structure 320 includes a first portion extending in a first direction D1 and a second portion extending in a second direction D2 across the first portion. The width of the grid structure 320 is substantially the same as or less than the minimum width of the pixel separation structure PIS.

[0091] The lattice structure 320 includes a light-shielding pattern and / or a low-refractive-index pattern. The light-shielding pattern includes a metallic material such as titanium, tantalum, or tungsten. The low-refractive-index pattern is formed of a material having a lower refractive index than the conductive pattern. The low-refractive-index pattern is formed of an organic material and has a refractive index of about 1.1 to 1.3. For example, the lattice structure is a polymer layer containing silica nanoparticles.

[0092] A color filter (C / F) 330 is formed corresponding to a pixel region PR. The color filter 330 fills the space defined by the grid structure 320. Depending on the unit pixel, the color filter 330 may include a red, green, or blue color filter, or a magenta, cyan, or yellow color filter. As another example, part of the color filter 330 may include a white color filter or an infrared filter.

[0093] A microlens 340 is placed on a color filter 330. The microlens 340 has a convex shape and a predetermined radius of curvature. The microlens 340 is made of a light-transmitting resin. The microlenses 340 are placed on the color filter 330 corresponding to each of the pixel regions PR. As another example, at least one of the microlenses 340 may be placed in common on at least two pixel regions PR.

[0094] Figures 7, 8, 9, 10, and 11 are plan views of various examples of image sensors according to one embodiment of the present invention. For the sake of simplicity, the explanation of technical features identical to those described earlier with reference to Figures 2, 3A, 4A, 5A, and 6A will be omitted, and the differences will be explained.

[0095] Referring to Figure 7, the pixel separation structure PIS includes a pair of first parts Pa and a pair of second parts Pb that define the first to fourth pixel regions (PR1 to PR4). It also includes a third part Pc that extends toward the center of each of the first to fourth pixel regions (PR1 to PR4). The third part Pc extends in the second direction D2 from one of the first parts Pa.

[0096] The third portion Pc of the pixel separation structure PIS is located between the first and second photoelectric conversion regions (110a, 110b) in each of the first to fourth pixel regions (PR1 to PR4). The third portion Pc is positioned between the second active regions ACT2.

[0097] The linked conductive pattern ICP is separated from the third part Pc of the pixel separation structure PIS in a plan view.

[0098] Referring to Figure 8, the pixel separation structure PIS includes, as previously described, a third portion Pc that extends in the second direction D2 from one of the first portions Pa in each of the first to fourth pixel regions (PR1 to PR4). Here, the third portion Pc is positioned between the first active portions ACT1, and a portion of the third portion Pc is superimposed on the connecting conductive pattern ICP.

[0099] Referring to Figure 9, the pixel separation structure PIS includes, as previously described, a third portion Pc that extends in the second direction D2 from one of the first portions Pa in each of the first to fourth pixel regions (PR1 to PR4). Here, the third portion Pc is positioned between the second active portions ACT2, and the first active portions, as described with reference to Figure 2, are connected to each other to form a common active portion ACT.

[0100] Furthermore, the common active portion ACT of the first pixel P region PR1 is connected to the common active portion ACT of the third pixel region PR3. A portion of the pixel separation structure PIS between the first pixel P region PR1 and the third pixel region PR3 is separated from each other. Similarly, the common active portion ACT of the second pixel region is connected to the common active portion ACT of the fourth pixel region PR4. A portion of the pixel separation structure PIS between the second pixel region and the fourth pixel region PR4 is separated from each other.

[0101] A floating diffusion region FD is provided within an open region between the first pixel P region PR1 and the third pixel region PR3, where the pixel separation structure PIS is omitted.

[0102] The first connecting portion CP1 of the connected conductive pattern ICP is connected to the floating diffusion region FD between the first and third pixel regions (PR1, PR3) and the floating diffusion region FD between the second and fourth pixel regions (PR3, PR4), and the second connecting portion CP2 of the connected conductive pattern extends from the first connecting portion CP1 and is connected to one of the first source / drain regions SD1.

[0103] The connected conductive pattern ICP includes an edge portion EP adjacent to its outer wall, and a blocking pattern BLK is positioned between the edge portion EP and the first surface 100a of the semiconductor substrate 100. That is, as described above, the blocking pattern BLK is superimposed on the edge portion EP of the connected conductive pattern ICP in a plan view.

[0104] Referring to Figure 10, the semiconductor substrate 100 includes a plurality of pixel group GPXs. Each pixel group GPX includes at least four, eight, or sixteen pixel regions PR. In each pixel group GPX, the pixel regions PR are arranged in a matrix shape along a first direction D1 and a second direction D2 that intersect each other.

[0105] The first to fourth pixel regions (PR1 to PR4) are provided with the first to fourth photoelectric conversion regions (110a to 110d), respectively.

[0106] On the first surface 100a of the semiconductor substrate 100, a first active area ACT1 and a second active area ACT2 are provided in each of the first to fourth pixel regions (PR1 to PR4) by an element isolation film STI. The first and second active areas (ACT1, ACT2) are defined by an element isolation film STI adjacent to the first surface 100a of the semiconductor substrate 100.

[0107] The first to fourth pixel regions (PR1 to PR4) are provided with the first to fourth transmission gate electrodes (TG1, TG2, TG3, TG4), respectively. Each of the first to fourth transmission gate electrodes (TG1, TG2, TG3, TG4) has a dual vertical gate electrode structure that includes two vertical portions that extend into the semiconductor substrate, as described earlier.

[0108] In each of the first to fourth pixel regions (PR1 to PR4), a pixel transistor is provided on the second active region ACT2.

[0109] The first to fourth floating diffusion regions (FD1 to FD4) are provided within the first active region on one side of the first to fourth transmission gate electrodes. The first to fourth floating diffusion regions are arranged adjacent to each other and are located in the central part of each pixel group GPX.

[0110] The first connecting portion CP1 of the connected conductive pattern ICP is connected to the first to fourth floating diffusion regions (FD1 to FD4) of the adjacent pixel group. The second connecting portion CP2 of the connected conductive pattern ICP extends from the first connecting portion CP1 and is connected to one of the first source / drain regions SD1.

[0111] The connected conductive pattern ICP includes an edge portion EP adjacent to its outer wall, and the blocking pattern BLK is positioned between the edge portion EP and the first surface 100a of the semiconductor substrate 100. That is, as described above, the blocking pattern BLK superimposes on the edge portion EP of the connected conductive pattern ICP in a plan view.

[0112] Referring to Figure 11, a common active part ACT is provided in common to the first to fourth pixel regions (PR1 to PR4), and a second active part ACT2 is provided for each pixel region.

[0113] The first to fourth transmission gate electrodes are provided on the common active portion ACT for the first to fourth pixel regions PR1 to PR4, respectively.

[0114] For each pixel group GPX, one common floating diffusion region CFD1 or CFD2 is provided within the common active region ACT. As an example, the common floating diffusion regions (CFD1, CFD2) are provided in common to at least four pixel regions PR. The first portion Pa of the pixel isolation structure PIS is separated in the first direction D1 via the common floating diffusion regions (CFD1, CFD2), and the second portion Pb is separated in the second direction D2 via the common floating diffusion region CFD. The floating diffusion region FD is provided within the semiconductor substrate 100 so as to be adjacent to the first to fourth transmission gate electrodes (TG1 to TG4).

[0115] The first connecting portion CP1 of the connected conductive pattern ICP connects the common floating diffusion regions (CFD1, CFD2) of the pixel group GPX to each other, and the second connecting portion CP2 of the connected conductive pattern ICP extends from the first connecting portion CP1 and connects to one of the first source / drain regions SD1 within the pixel group GPX.

[0116] Figures 12 to 19 are diagrams illustrating a method for manufacturing an image sensor according to one embodiment of the present invention, and are cross-sectional views taken along the line A-A' in Figure 2.

[0117] Referring to Figures 2 and 12, a semiconductor substrate 100 of a first conductivity type (e.g., p-type) is provided. As an example, the semiconductor substrate 100 includes an epitaxial layer. The semiconductor substrate 100 has a first surface 100a and a second surface 100b that face each other.

[0118] In contrast, the semiconductor substrate 100 may be a bulk semiconductor substrate containing wells of a first conductivity type. As another example, the semiconductor substrate 100 may be a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, or a silicon-germanium substrate.

[0119] In each pixel region PR, an element isolation film STI is formed adjacent to the first surface 100a of the semiconductor substrate 100, defining the active region on the semiconductor substrate 100. The element isolation film STI includes patterning the first surface 100a of the semiconductor substrate 100 to form a shallow first trench, forming a liner insulating film that conformally covers the inner wall of the first trench, and forming an insulating film that fills the first trench on which the liner insulating film has been formed. The element isolation film STI is formed before or after the formation of the photoelectric conversion regions (110a, 110b).

[0120] A pixel isolation structure PIS that defines a pixel region PR is formed on the semiconductor substrate 100. Forming the pixel isolation structure PIS includes patterning the first surface 100a of the semiconductor substrate 100 to form a second trench, forming a liner insulating film that conformally covers the inner wall of the second trench, depositing a semiconductor film to fill the second trench on which the liner insulating film has been formed, and flattening the liner insulating film and the embedding pattern 113 so that the first surface 100a of the semiconductor substrate 100 is exposed to form a liner insulating pattern 111, an embedding pattern 113, and a capping insulating pattern 115 within the second trench.

[0121] The second trench further includes extension trenches that extend toward the center of each pixel region (PR1 to PR4). The extension trenches extend in the second direction D2 within each pixel region PR and are separated from each other in the second direction D2.

[0122] The liner insulation pattern 111 and the capping insulation pattern 115 include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride. The embedding pattern 113 includes an impurity-doped polysilicon film and / or an undoped polysilicon film.

[0123] Next, the first photoelectric conversion region 110a and the second photoelectric conversion region 110b are formed within each pixel region (PR1 to PR4).

[0124] The first and second photoelectric conversion regions (110a, 110b) are formed in the semiconductor substrate 100 by doping each pixel region PR with an impurity of a second conductivity type (e.g., n-type) different from the first conductivity type. The first and second photoelectric conversion regions (110a, 110b) are separated from the first surface 100a and the second surface 100b of the semiconductor substrate 100. The first and second photoelectric conversion regions (110a, 110b) are formed before or after the formation of the pixel separation structure PIS.

[0125] Next, a first transmission gate electrode TG1 and a second transmission gate electrode TG2 are formed on the first active portion ACT1 of each pixel region PR. Forming the first and second transmission gate electrodes (TG1, TG2) includes patterning the first surface 100a of the semiconductor substrate 100 to form a gate recess region in each of the pixel regions PR, forming a gate insulating film conformally covering the inner wall of the gate recess region, forming a gate conductive film filling the gate recess region, and patterning the gate conductive film. Each of the first and second transmission gate electrodes (TG1, TG2) includes two vertical portions arranged within the semiconductor substrate 100.

[0126] The gate insulating film GIL includes a silicon oxide film, a silicon oxynitride film, or a silicon nitride film. The gate insulating film GIL is formed by carrying out a deposition process so as to conformally cover the inner wall of the vertical trench VT.

[0127] The first and second transmission gate electrodes (TG1, TG2) are formed by creating a gate conductive film that fills a vertical trench in which a gate insulating film (GIL) is formed, and then patterning the gate conductive film. The gate conductive film includes a doped polysilicon film, a metal silicide film, a conductive metal nitride film, or a metal film.

[0128] When forming the first and second transmission gate electrodes (TG1, TG2), the gate electrodes (RG, SG, SFG) of the pixel transistors are formed together in the second active portion ACT2 of each pixel region (PR1, PR2).

[0129] After forming the first and second transmission gate electrodes (TG1, TG2), a first doping region FDa is formed within the semiconductor substrate 100 on one side of the first and second transmission gate electrodes (TG1, TG2). The first doping region FDa is formed by ion implanting impurities of a second conductivity type using an ion implantation mask. Furthermore, when forming the first doping region FDa, the source / drain regions (not shown) of the pixel transistor are also formed.

[0130] Referring to Figure 13, the spacer insulating film 120 is deposited on the first surface of the semiconductor substrate. The spacer insulating film 120 covers the first and second transmission gate electrodes (TG1, TG2) and the pixel gate electrodes with a uniform thickness.

[0131] The spacer insulating film 120 includes, for example, silicon oxide, silicon nitride, silicon oxidnitride, silicon carbon nitride (SiCN), or silicon carbon oxidnitride (SiCON).

[0132] The spacer insulating film 120 is deposited, for example, through an ALD (Atomic Layer Deposition), PECVD (Plasma Enhanced CVD), LPCVD (Low Pressure CVD), or FCVD (Flowable Chemical Vapor Deposition) process.

[0133] Referring to Figures 2 and 14, a first mask pattern MP1 having an opening that exposes the region where the connected conductive pattern is formed is formed on the spacer insulating film 120.

[0134] The opening of the first mask pattern MP1 is superimposed on a portion of the first doping region FDa of each pixel region (PR1~PR4) and a portion of one of the first source / drain regions SD1 of the pixel transistor.

[0135] As an example, the first mask pattern MP1 is formed by coating a photoresist film onto the first surface 100a of the semiconductor substrate 100, and then performing exposure and development processes on the photoresist film.

[0136] Referring to Figures 2 and 15, the spacer insulating pattern 121 is formed by anisotropically etching the spacer insulating film 120 using the first mask pattern MP1 as an etching mask.

[0137] Referring to Figures 2 and 16, a second doping region FDb is formed within a portion of the first doping region FDa. The second doping region FDb is formed by ion implanting impurities of a second conductivity type using the spacer insulating pattern 121 as an ion implantation mask pattern.

[0138] Referring to Figures 2 and 17, the conductive film 130 is deposited over the entire surface of the semiconductor substrate with a substantially uniform thickness. The conductive film 130 is in direct contact with the second doping region FDb and covers the spacer insulating pattern 121.

[0139] The conductive film 130 includes, for example, a doped polysilicon film, a metal silicide film, a conductive metal nitride film, or a metal film. For example, the conductive film 130 is formed by depositing a semiconductor film, and impurities are doped in-situ when the semiconductor film is deposited. The dopant concentration in the conductive film 130 is lower than the dopant concentration in the second doping region FDb.

[0140] Referring to Figures 2 and 18, a second mask pattern MP2 is formed on the conductive film 130, and the second mask pattern MP2 overlaps one of the first and second floating diffusion regions (FD1, FD2) and the first source / drain region SD1.

[0141] Next, the conductive film 130 is anisotropically etched using the second mask pattern MP2 as an etching mask to form a linked conductive pattern ICP. After the linked conductive pattern ICP is formed, the second mask pattern MP2 is removed.

[0142] Referring to Figures 2 and 19, an etching process (e.g., etch-back) is performed on the entire surface of the semiconductor substrate 100 with respect to the spacer insulating pattern 121. As a result, a portion of the spacer insulating pattern 121 remains, forming insulating spacers SP on both side walls of the first and second transmission gate electrodes (TG1, TG2) and on both side walls of the pixel gate electrodes (PG1, PG2), and a blocking pattern BLK is formed on the edge portion EP of the connecting conductive pattern ICP.

[0143] Subsequently, as shown in Figure 3A, the first and second etching stop films (140, 150) are deposited sequentially on the first surface 100a of the semiconductor substrate 100 with a uniform thickness.

[0144] The first and second etching stop films (140, 150) are deposited, for example, through a PECVD (Plasma Enhanced CVD), LPCVD (Low Pressure CVD), or FCVD (Flowable Chemical Vapor Deposition) process. The first and second etching stop films (140, 150) contain silicon nitride or silicon oxynitride.

[0145] Figure 20 is a plan view of an image sensor according to one embodiment of the present invention.

[0146] Referring to Figure 20, the image sensor according to this embodiment includes first to third pixel groups (GPX1, GPX2, GPX3) arranged two-dimensionally along a first direction D1 and a second direction D2. In odd-numbered rows, the first and second pixel groups (GPX1, GPX2) are arranged alternately. In even-numbered rows, the second and third pixel groups (GPX2, GPX3) are arranged alternately. Each of the first to third pixel groups (GPX1, GPX2, GPX3) contains a 2x2 pixel region PR. The pixel separation structure PIS separates the first to third pixel groups (GPX1, GPX2, GPX3) from each other. In a planar view, the pixel separation structure PIS is inserted into each pixel group (GPX1, GPX2, GPX3) to separate the pixel region PR. However, the pixel separation structure PIS is cut at the center of each pixel group (GPX1, GPX2, GPX3), and the pixel regions PR belonging to one pixel group are connected to each other. The first pixel group GPX1 is covered by the first color filter CF1. The second pixel group GPX2 is covered by the second color filter CF2. The third pixel group GPX3 is covered by the third color filter CF3. The first color filter CF1 has one color from among red, green, and blue. The second color filter CF2 has another color from among red, green, and blue. The third color filter CF3 has another color from among red, green, and blue. Microlenses ML are placed on the first to third color filters (CF1, CF2, CF3). Each microlens ML corresponds to and superimposes on a pixel region PR. That is, one microlens ML is placed on one pixel PX. A 2x2 array of microlenses (ML) is arranged on each pixel group (GPX1, GPX2, GPX3). This arrangement of microlenses (ML) enhances the light-gathering efficiency in each pixel area (PR), resulting in a sharper image.

[0147] Figure 21 is a schematic plan view of an image sensor including a semiconductor device according to one embodiment of the present invention. Figures 22 and 23 are cross-sectional views of various examples of the image sensor according to one embodiment of the present invention, and are cross-sectional views taken along the line I-I' in Figure 21.

[0148] Referring to Figures 21 and 22, the image sensor includes a sensor chip C1 and a logic chip C2. Sensor chip C1 includes a pixel array area R1 and a pad area R2.

[0149] The pixel array region R1 includes a plurality of unit pixels P arranged two-dimensionally along a first direction D1 and a second direction D2 that intersect each other. Each unit pixel P includes a photoelectric conversion element and a readout element. An electrical signal generated by incident light is output from each unit pixel P in the pixel array region R1.

[0150] The pixel array region R1 includes a light-receiving region AR and a light-shielding region OB. The light-shielding region OB surrounds the light-receiving region AR in a plan view. In other words, the light-shielding region OB is positioned above, below, and to the left and right of the light-receiving region AR in a plan view. A reference pixel into which no light enters is provided in the light-shielding region OB, and the size of the electrical signal sensed by the unit pixel P is calculated by comparing the amount of charge sensed by the unit pixel P in the light-receiving region AR with the amount of charge sensed by the reference charge amount generated at the reference pixel.

[0151] Multiple conductive pads CP are arranged in the pad region R2, which are used for inputting and outputting control signals, photoelectric signals, etc. The pad region R2 surrounds the pixel array region R1 in a plan view to facilitate electrical connection with external elements. The conductive pads CP input and output electrical signals generated at the unit pixel P to and from external devices.

[0152] In the light-receiving region AR, the sensor chip C1 includes the same technical features as the image sensor described earlier. That is, the sensor chip C1 includes a photoelectric conversion circuit layer 10 between the pixel circuit layer 20 and the light-transmitting layer 30 in the vertical direction, as described earlier. The photoelectric conversion circuit layer 10 of the sensor chip C1 includes a semiconductor substrate 100, a pixel isolation structure PIS that defines the pixel region, and a photoelectric conversion region 110 provided within the pixel region, as described earlier. The pixel isolation structure PIS has substantially the same structure in the light-receiving region AR and the light-shielding region OB. The pixel isolation structure PIS is located within the semiconductor substrate 100 in the light-shielding region OB. An embedded pattern 113 within the pixel isolation structure PIS is electrically connected to a back contact plug PLG in the light-shielding region OB. A predetermined bias is applied to the embedded pattern 113 through the back contact plug PLG. The back contact plug PLG has a width greater than the width of the pixel isolation structure PIS. The back contact plug PLG includes a metal and / or a metal nitride. For example, the back contact plug PLG contains titanium and / or titanium nitride.

[0153] The contact pattern CT is embedded within the contact hole where the back contact plug PLG is formed. The contact pattern CT contains a different material from the back contact plug PLG. For example, the contact pattern CT contains aluminum (Al).

[0154] The contact pattern CT and the back contact plug PLG are electrically connected to the embedded pattern 113 of the pixel isolation structure PIS. A positive bias is applied to the embedded pattern 113 of the pixel isolation structure PIS through the contact pattern CT, and this positive bias is transmitted from the light-shielding region OB to the light-receiving region AR. Therefore, the dark current generated at the interface between the pixel isolation structure PIS and the semiconductor substrate 100 can be reduced.

[0155] The light-transmitting layer 30 includes a light-shielding region OB, a light-shielding pattern OBP, a filtering film 335, and an organic film 345. In this embodiment, the pixel separation structure PIS is continuously extended from the light-receiving region AR to the light-shielding region OB.

[0156] In the light-shielding region OB, the light-shielding pattern OBP is positioned on the upper surface of the flat insulating film 310. The light-shielding pattern OBP contains the same material as the conductive pattern of the lattice structure 320 in the light-receiving region AR. That is, the light-shielding pattern OBP includes metal patterns and metal oxide patterns. For example, the light-shielding pattern OBP includes titanium nitride and titanium oxynitride. The light-shielding pattern OBP is not extended into the light-receiving region AR.

[0157] The light-shielding pattern OBP blocks light from entering the photoelectric conversion area PD provided in the light-shielding area OB. In the reference pixel area of ​​the light-shielding area OB, the photoelectric conversion area PD does not output a photoelectric signal but outputs a noise signal. The noise signal is generated by electrons produced by heat generation or dark current, etc.

[0158] The filtering film 335 covers the light-shielding pattern OBP in the light-shielding region OB. The filtering film 335 blocks light of different wavelengths than the color filter 330. For example, the filtering film 335 blocks infrared light. The filtering film 335 includes, but is not limited to, a blue color filter.

[0159] The organic film 345 and the passivation film are provided on the filtering film 335 in the light-shielding region OB and the pad region R2. The organic film 345 contains the same material as the microlens 340.

[0160] In the light-shielding region OB, the first through-conductive pattern 511 penetrates the semiconductor substrate 100 and is electrically connected to the metal wiring of the pixel circuit layer 20 and the wiring structure 1111 of the logic chip C2. The first through-conductive pattern 511 has a first bottom surface and a second bottom surface located at different levels from each other. A first embedding pattern 521 is provided inside the first through-conductive pattern 511. The first embedding pattern 521 contains a low refractive index material and has insulating properties.

[0161] In pad region R2, a conductive pad CP is provided on the second surface 100b of the semiconductor substrate 100. The conductive pad CP is embedded within the second surface 100b of the semiconductor substrate 100. As an example, the conductive pad CP is provided within a pad trench formed in the second surface 100b of the semiconductor substrate 100 in pad region R2. The conductive pad CP includes a metal such as aluminum, copper, tungsten, titanium, tantalum, or an alloy thereof. In the image sensor mounting process, a bonding wire is bonded to the conductive pad CP. The conductive pad CP is electrically connected to an external device through the bonding wire.

[0162] In pad region R2, the second through-conductive pattern 520 penetrates the semiconductor substrate 100 and is electrically connected to the wiring structure 1111 of the logic chip C2. The second through-conductive pattern 520 extends onto the second surface 100b of the semiconductor substrate 100 and is electrically connected to the conductive pad CP. A portion of the second through-conductive pattern 520 covers the bottom surface and side walls of the conductive pad CP. A second embedding pattern 510 is provided inside the second through-conductive pattern 520. The second embedding pattern 510 contains a low refractive index material and has insulating properties. In pad region R2, a pixel isolation structure PIS is provided around the second through-conductive pattern 520.

[0163] The logic chip C2 includes a logic semiconductor substrate 1000, a logic circuit TR, a wiring structure 1111 connected to the logic circuit TR, and a logic interlayer insulating film 1100. The uppermost layer of the logic interlayer insulating film 1100 is bonded to the pixel circuit layer 20 of the sensor chip C1. The logic chip C2 is electrically connected to the sensor chip C1 through a first through-conductive pattern 511 and a second through-conductive pattern 520.

[0164] As an example, a sensor chip C1 and a logic chip C2 are electrically connected to each other through first and second through-hole conductive patterns (511, 520), but the present invention is not limited thereto.

[0165] According to the embodiment shown in Figure 23, the first and second through-conductive patterns shown in Figure 22 are omitted, and the sensor chip C1 and logic chip C2 are electrically connected by directly joining the bonding pads provided on the uppermost metal layer of the sensor chip C1 and logic chip C2 to each other.

[0166] In detail, on the sensor chip C1, the embedded pattern 113 of the pixel isolation structure PIS, which extends from the light-receiving area AR to the light-shielding area OB, is connected to the back contact plug PLG in the light-shielding area OB.

[0167] In addition, the sensor chip C1 includes a first bonding pad BP1 provided on the top metal layer of the pixel circuit layer 20, and the logic chip C2 includes a second bonding pad BP2 provided on the top metal layer of the wiring structure 1111. The first and second bonding pads (BP1, BP2) include at least one of the following materials, for example: tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), and titanium nitride (TiN).

[0168] The first bonding pad BP1 of sensor chip C1 and the second bonding pad BP2 of logic chip C2 are directly electrically connected to each other using a hybrid bonding method. Hybrid bonding refers to bonding in which two components containing the same material fuse at their interface. For example, if the first and second bonding pads (BP1, BP2) are made of copper (Cu), they are physically and electrically connected by copper (Cu)-copper (Cu) bonding. In addition, the insulating film surface of sensor chip C1 and the insulating film surface of logic chip C2 are joined by dielectric-dielectric bonding.

[0169] Although embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the embodiments described above, and can be modified and implemented in various ways without departing from the technical spirit of the present invention. [Explanation of Symbols]

[0170] 1. Photoelectric conversion circuit 1a, 1b, 1c, 1d: 1st to 4th Photoelectric Conversion Groups 2-pixel circuit 10 Photoelectric conversion circuit layer 20 pixel circuit layers 30 Light transmission layer 100 semiconductor substrates 100a, 100b First and second surfaces (front and back) of the semiconductor substrate 101 Liner oxide film 102 Surface insulating film 103 Liner Nitride Film 105 Embedded oxide film 110 Photoelectric conversion region 110a, 110b, 110c, 110d 1st to 4th photoelectric conversion area 111 Liner Insulation Pattern 113 Embedding Patterns 115 Capping Insulation Pattern 120 Spacer Insulator 121 Spacer Insulation Pattern 130 Conductive film 131 Capping insulating film 140, 150 First and second etching stop films 210 Interlayer insulating film 221 Contact Plug 222 Wiring 310 Flat insulating film 320 Lattice Structure 330 Color Filters (C / F) 335 Filtering film 340 Microlens 345 Organic film 510, 521 Second and first embedding patterns 511, 520 First and second through-conductive patterns 1000 Logic Semiconductor Substrates 1100 Logic interlayer insulating film 1111 Wiring structure ACT common active part ACT1, ACT2 1st, 2nd active part AR light receiving area BLK Blocking Pattern BP1, BP2: First and second bonding pads C1 Sensor Chip C2 Logic Chip CF1, CF2, CF3 First to Third Color Filters Common floating diffusion region of CFD1 and CFD2 CP conductive pads CP1, CP2 1st, 2nd connection part CT Contact Pattern DCG Double Transform Gain Control Signal DCX Double Conversion Gain Transistor EP edge section FD Floating Diffusion Region (Charge Detection Node) FD1, FD2 First and second floating diffusion regions FDa, FDb: Doping Areas 1 and 2 GPX Pixel Group GPX1, GPX2, GPX3 1st to 3rd pixel groups GR ground impurity region ICP Linked Conductive Pattern LS1, LS2 linked conductive pattern, first and second lower surfaces MP1, MP2 First and Second Mask Patterns OB shading area OBP Shading Pattern P, PX: Pixels Pa, Pb, Pc 1st to 3rd parts PD (Photoelectric Transformation) Region PD1-PD8: Photodiodes 1st-8th PG Pixel Gel Postpartum PG1, PG2, PG3, PG4 1st to 4th pixel gate electrode PIS (Pixel Isolation Structure) PLG Rear Contact Plug PP pad portion PR1, PR2, PR3, PR4: 1st to 4th pixel regions R1 Pixel Array Region R2 Pad Area RG reset signal RX Reset Transistor SD1, SD2: First and second source / drain regions SF Source Follower Transistor SG selection signal SP Insulation Spacer STI device isolation membrane SX Select Transistor SWa, SWb exterior, interior walls TG Transmission Terminal TG1~TG8: 1st to 8th charge electrode signals (transmission gate electrodes) TR logic circuit TX1~TX8 Transmission Transistors 1st~8th US1, US2 Linked conductive patterns, first and second upper surfaces Vout output line V PIX Pixel power supply voltage

Claims

1. Semiconductor substrate and A pixel separation structure disposed within the semiconductor substrate and defining a first pixel region and a second pixel region, A transmission gate electrode provided in the first pixel region, A floating diffuse region provided to the first pixel region on one side of the transmission gate electrode, A pixel gate electrode provided in the second pixel region, A source / drain region provided to the second pixel region on one side of the pixel gate electrode, A connecting conductive pattern is arranged on the first surface of the semiconductor substrate, connecting the floating diffusion region and the source / drain region, and including an edge portion adjacent to the outer wall, An image sensor characterized by comprising a blocking pattern disposed between the edge portion of the connected conductive pattern and the first surface of the semiconductor substrate.

2. The image sensor according to claim 1, characterized in that the blocking pattern is superimposed on the edge portion of the connected conductive pattern in a plan view.

3. The image sensor according to claim 1, characterized in that the inner wall of the blocking pattern is in contact with a part of the connecting conductive pattern.

4. The device further includes an element isolation film that defines the active portion in each of the first and second pixel regions, The image sensor according to claim 1, characterized in that the blocking pattern includes a first portion disposed on the active portion and a second portion disposed on the element separation film.

5. The connecting conductive pattern includes a pad portion in contact with the floating diffusion region and the source / drain region. The image sensor according to claim 1, characterized in that the bottom surface of the pad portion is located at a lower level than the bottom surface of the blocking pattern.

6. The connecting conductive pattern includes a pad portion in contact with the floating diffusion region and the source / drain region. The image sensor according to claim 1, characterized in that the upper surface of the edge portion is located at a higher level than the upper surface of the pad portion.

7. The floating diffusion region, the source / drain region, and the connecting conductive pattern include a dopant of the first conductivity type. The image sensor according to claim 1, characterized in that the concentration of the dopant in the linked conductive pattern is lower than the concentration of the dopant in the floating diffusion region.

8. The connecting conductive pattern includes a pad portion in contact with the floating diffusion region and the source / drain region. The image sensor according to claim 1, characterized in that the thickness of the pad portion is smaller than the thickness of the pixel gate electrode.

9. The system further includes insulating spacers positioned on both sides of the transmission gate electrode and on both sides of the pixel gate electrode, The image sensor according to claim 1, characterized in that the blocking pattern includes the same insulating material as the insulating spacer.

10. The floating diffusion region includes a first doping region and a second doping region within the first doping region. The dopant concentration in the second doping region is higher than the dopant concentration in the first doping region. The image sensor according to claim 1, characterized in that the linked conductive pattern is in contact with the second doping region of the floating diffusion region.

11. The present invention further includes an etching stop film that covers the transmission gate electrode and the pixel gate electrode with a uniform thickness, The image sensor according to claim 1, characterized in that a portion of the etching stop film covers the outer wall of the blocking pattern and the outer wall of the connecting conductive pattern with a uniform thickness.

12. Each of the first pixel region and the second pixel region further includes a first photoelectric conversion region and a second photoelectric conversion region disposed within the semiconductor substrate, The transmission gate electrode includes a first transmission gate electrode and a second transmission gate electrode in each of the first and second pixel regions. The floating diffusion region includes a first floating diffusion region and a second floating diffusion region in each of the first pixel region and the second pixel region. The first transmission gate electrode is positioned between the first photoelectric conversion region and the first floating diffusion region. The image sensor according to claim 1, characterized in that the second transmission gate electrode is disposed between the second photoelectric conversion region and the second floating diffusion region.

13. Semiconductor substrate and A pixel separation structure disposed within the semiconductor substrate and defining a first pixel region and a second pixel region, A photoelectric conversion area provided in the first pixel area and the second pixel area, respectively, A first transmission gate electrode provided in the first pixel region and a first floating diffusion region on one side of the first transmission gate electrode, A second transmission gate electrode provided in the second pixel region and a second floating diffusion region on one side of the second transmission gate electrode, A pixel gate electrode provided in the first pixel region and the second pixel region, and a source / drain region provided on both sides of each of the pixel gate electrodes, A connecting conductive pattern that connects the first floating diffusion region and the second floating diffusion region with the first source / drain region within the source / drain region, The system includes a blocking pattern disposed between the lower surface of the edge portion of the connecting conductive pattern and the first surface of the semiconductor substrate, The image sensor is characterized in that the connecting conductive pattern includes a first connecting portion in contact with the first floating diffusion region and the second floating diffusion region, and a second connecting portion extending from the first connecting portion and in contact with the first source / drain region.

14. The image sensor according to claim 13, characterized in that the outer wall of the connecting conductive pattern is aligned perpendicularly to the outer wall of the blocking pattern.

15. The image sensor according to claim 13, characterized in that a portion of the connecting conductive pattern has a lower surface at a lower level than the lower surface of the blocking pattern.

16. The image sensor according to claim 13, characterized in that the minimum width of the first connecting portion is greater than the minimum width of the second connecting portion.

17. The device further includes an element isolation film that defines a first active portion and a second active portion in each of the first and second pixel regions, The first floating diffusion region and the second floating diffusion region are arranged within the first active portion of the first pixel region and the second pixel region, The image sensor according to claim 13, characterized in that the source / drain region is arranged within the second active portion of the first pixel region and the second pixel region, respectively.

18. The first floating diffusion region, the second floating diffusion region, and the connecting conductive pattern include a dopant of the first conductivity type. The image sensor according to claim 13, characterized in that the concentration of the dopant in the linked conductive pattern is lower than the concentration of the dopant in the first floating diffusion region and the second floating diffusion region.

19. A semiconductor substrate having a first surface and a second surface facing the first surface, A pixel separation structure is disposed within the semiconductor substrate and defines the first to fourth pixel regions, The photoelectric conversion region provided within the semiconductor substrate in the first to fourth pixel regions, An element isolation film adjacent to the first surface of the semiconductor substrate, A transmission gate electrode provided in the first active portion of the first pixel region to the fourth pixel region, A floating diffusion region provided to the first active portion of the first pixel region to the fourth pixel region, A pixel transistor provided in the second active portion of the first to fourth pixel regions, A connecting conductive pattern is arranged on the first surface of the semiconductor substrate and connects the floating diffusion regions of the first pixel region to the fourth pixel region and one first source / drain region of the pixel transistor, A blocking pattern is disposed between the edge portion of the connected conductive pattern and the first surface of the semiconductor substrate, A color filter is arranged on the second surface of the semiconductor substrate corresponding to the pixel region, A grid structure is placed between the color filters and superimposed on the pixel separation structure, The color filter comprises a microlens on the aforementioned color filter, The element isolation film defines the first active portion and the second active portion in each of the first to fourth pixel regions, The image sensor is characterized in that the connected conductive pattern includes an edge portion adjacent to the outer wall and a pad portion in contact with the floating diffusion region and the first source / drain region.

20. The image sensor according to claim 19, characterized in that the thickness of the pad portion of the linked conductive pattern is smaller than the thickness of the pixel gate electrode of the pixel transistor.

Images