A high performance low power four-point flip flop self-restoring latch

Abstract

The application discloses a high-performance low-power four-point flip self-recovery latch, comprising six transmission gates, 19 Muller units and six clocked Muller units. The application adopts the mode that 19 Muller units and six clocked Muller units form four feedback loops, so that after a single event upset occurs in any one feedback loop, internal nodes can quickly recover to correct logic states through the Muller units and the clocked Muller units, and therefore 7315 four-point flip conditions that may occur in 22 internal nodes can be tolerated. The application uses more clocked Muller units, and therefore the application has a lower power consumption overhead, and is a high-performance low-power four-point flip self-recovery latch.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, specifically to the design of a quadruple node upset (QNU) self-recovery latch in the field of radiation hardening circuits, and more specifically to a high-performance, low-power quadruple node upset self-recovery latch. Technical Background

[0002] Single event effect (SEE) refers to radiation damage caused by high-energy particles passing through the active region of a microelectronic device, resulting in abnormal changes in the device's state. SEE includes single event flip, single event transient, single event burn-out, and single event gate penetration, among which single event flip is the most difficult to protect against.

[0003] A single event upset (SEU) is an effect where a high-energy particle strikes a memory cell, causing the logic value of that cell to flip directly. Based on the number of nodes affected, SEUs can be categorized as single-point flips, two-point flips, three-point flips, and four-point flips, among others.

[0004] Single Node Upset (SNU) refers to the situation where a single high-energy particle hits a memory cell, causing the logic value of a single sensitive node inside the memory cell to flip.

[0005] Double Node Upset (DNU) refers to the situation where, when a single high-energy particle hits a memory cell, the logic values ​​of two sensitive nodes inside the memory cell simultaneously flip due to the charge-sharing effect.

[0006] Triple Node Upset (TNU) refers to the situation where, when a single high-energy particle hits a memory cell, the logic values ​​of the three sensitive nodes inside the memory cell simultaneously flip due to the charge-sharing effect.

[0007] Quadruple Node Upset (QNU) refers to the situation where, when a single high-energy particle hits a memory cell, the logic values ​​of the four sensitive nodes inside the memory cell simultaneously flip due to the charge-sharing effect.

[0008] Latches are among the most commonly used sequential logic devices and are key components in digital systems, playing an irreplaceable role in the execution of system functions. However, with the shrinking size of integrated circuit processes, CMOS latches are becoming increasingly susceptible to quadruple node upsets (QNUs) in harsh radiation environments, leading to soft errors and circuit failure.

[0009] Traditional radiation-hardened latches are mostly only capable of single-point or double-point self-recovery, which is no longer suitable for harsh radiation environments. Summary of the Invention

[0010] To address the technical problems mentioned in the background section, this invention provides a high-performance, low-power four-point toggle self-recovery latch.

[0011] This invention employs the following technical solution: Based on the characteristic that the output logic value remains unchanged when the logic values ​​of two input signals are different, this invention presents a high-performance, low-power four-point toggle self-recovering latch. It includes: 6 transmission gates, 19 Muller units, and 6 clocked Muller units. The six transmission gates are the first transmission gate (125), the second transmission gate (126), the third transmission gate (127), the fourth transmission gate (128), the fifth transmission gate (129), and the sixth transmission gate (130). These six transmission gates are identical and have the same clock control signal. The 19 Muller units are the first Muller unit (100), the second Muller unit (101), the third Muller unit (102), the fourth Muller unit (103), the fifth Muller unit (104), the sixth Muller unit (105), the seventh Muller unit (106), the eighth Muller unit (108), the ninth Muller unit (110), the tenth Muller unit (112), the eleventh Muller unit (114), the twelfth Muller unit (115), the twelfth Muller unit (116), the eleventh Muller unit (117), the twelfth Muller unit (118), the twelfth Muller unit (119), the twelfth Muller unit (120), the eleventh Muller unit (111), the twelfth Muller unit (112), the eleventh Muller unit (113), the twelfth Muller unit (114), the twelfth Muller unit (115), the twelfth Muller unit (119), the twelfth Muller unit (110), the twelfth Muller unit (111), the twelfth Muller unit (112), the eleventh Muller unit (113), the twelfth Muller unit (114), the twelfth Muller unit (115), the twelfth Muller unit (111), the twelfth Muller unit (111), the twelf Unit (115), the thirteenth Muller unit (116), the fourteenth Muller unit (118), the fifteenth Muller unit (119), the sixteenth Muller unit (121), the seventeenth Muller unit (122), the eighteenth Muller unit (123), and the nineteenth Muller unit (124) are all structurally identical. The six clocked Muller units are: the first clocked Muller unit (107), the second clocked Muller unit (109), the third clocked Muller unit (111), the fourth clocked Muller unit (113), the fifth clocked Muller unit (117), and the sixth clocked Muller unit (120). These six clocked Muller units are all identical and have the same clock control signal. When the CLK signal is 1 and the CLKB signal is 0, the latch operates in the transparent period. All 6 transmission gates are on, and all 6 clocked Muller units are off. The input signal D is simultaneously propagated to the latch's internal nodes N2, N6, N9, N11, N13, and N16, with node N11 serving as the output terminal Q. When the CLK signal is 0 and the CLKB signal is 1, the latch operates in the hold period. All 6 transmission gates are off, and all 6 clocked Muller units are on. The data is latched within the feedback loop consisting of 19 Muller units and 6 clocked Muller units.

[0012] The first part is the input stage circuit, which consists of the first transmission gate (125), the second transmission gate (126), the third transmission gate (127), the fourth transmission gate (128), the fifth transmission gate (129), and the sixth transmission gate (130). All six transmission gates are connected to the external input signal D. The output of the first transmission gate (125) is connected to the internal node N2 of the latch, the output of the second transmission gate (126) is connected to the internal node N6 of the latch, the output of the third transmission gate (127) is connected to the internal node N9 of the latch, the output of the fourth transmission gate (128) is connected to the internal node N11 of the latch, the output of the fifth transmission gate (129) is connected to the internal node N13 of the latch, and the output of the sixth transmission gate (130) is connected to the internal node N16 of the latch.

[0013] When the CLK signal is 1 and the CLKB signal is 0, the latch is in the transparent period. The external input signal D is transmitted to the internal nodes N2, N6, N9, N11, N13, and N16 of the latch. Then, the inverted logic values ​​of N2 and N13 are written to the internal node N1 through the second Muller unit (101); the inverted logic values ​​of N2 and N6 are written to the internal node N3 through the third Muller unit (102); the inverted logic values ​​of N6 and N9 are written to the internal node N5 through the sixth Muller unit (105); and the inverted logic values ​​of N6 and N9 are written to the internal node N5 through the tenth Muller unit (105). Unit (112) writes the inverted logic values ​​of N11 and N13 to internal node N10; the eleventh Muller unit (114) writes the inverted logic values ​​of N13 and N16 to internal node N14; the thirteenth Muller unit (116) writes the inverted logic values ​​of N2 and N9 to internal node N17; the fourteenth Muller unit (118) writes the inverted logic values ​​of N11 and N13 to internal node N21; and the fifteenth Muller unit (119) writes the inverted logic values ​​of N6 and N16 to internal node N15. At this time, the logic value of the external input signal D has been written to internal nodes N2, N6, N9, N11, N13, and N16, and the inverted logic value of the external input signal D has been written to internal nodes N1, N3, N5, N10, N14, N15, N17, and N21. Then, the inverted logic values ​​of N1 and N3 are written to internal node N0 through the first Muller unit (100); the inverted logic values ​​of N3, N15 and N5, N17 are written to internal node N4 through the fourth Muller unit (103) and the fifth Muller unit (104) respectively; the inverted logic values ​​of N5 and N15 are written to internal node N7 through the twelfth Muller unit (115); and the inverted logic values ​​of N1 and N17 are written to internal node N7 through the sixteenth Muller unit. The inverted logic value is written to internal node N18; the inverted logic values ​​of N2 and N14 are written to internal node N20 through the nineteenth Muller unit (124); at this time, the logic value of the external input signal D has been written to internal nodes N0, N2, N4, N6, N7, N9, N11, N13, N16, N18, N20, and the inverted logic value of the external input signal D has been written to internal nodes N1, N3, N5, N10, N14, N15, N17, N21. Then, the inverted logic values ​​of N0, N20, N4, and N7 are written to the internal node N8 through the seventh Muller unit (106) and the ninth Muller unit (110); the inverted logic values ​​of N4 and N18 are written to the internal node N12 through the eighth Muller unit (108); and the inverted logic values ​​of N0, N18, N7, and N20 are written to the internal node N19 through the seventeenth Muller unit (122) and the eighteenth Muller unit (123).Thus, all 22 internal nodes of the latch have been written.

[0014] When the CLK signal is 1 and the CLKB signal is 0, the latch is in the transparent period, and the six clocked Muller units are turned off. When the CLK signal is 0 and the CLKB signal is 1, the latch is in the hold period, and the six clocked Muller units are turned on. The inverted logic values ​​of N5 and N10 are fed back to internal node N2 through the first clocked Muller unit (107); the inverted logic values ​​of N14 and N21 are fed back to internal node N6 through the second clocked Muller unit (109); the inverted logic values ​​of N8 and N19 are fed back to internal node N9 through the third clocked Muller unit (111); the inverted logic values ​​of N8 and N12 are fed back to internal node N13 through the fourth clocked Muller unit (113); the inverted logic values ​​of N12 and N19 are fed back to internal node N11 through the fifth clocked Muller unit (117); and the inverted logic values ​​of N10 and N17 are fed back to internal node N16 through the sixth clocked Muller unit (120). At this time, the 22 internal nodes are cyclically latched within the latch. Since all six clocked Muller units are off during the transparency period, the four-point flip-flop self-recovery latch of this invention has low power consumption.

[0015] The node connection relationships of each unit in this invention are as follows: the input nodes of the first Muller unit (100) are N1 and N3, and the output node is N0; the input nodes of the second Muller unit (101) are N2 and N13, and the output node is N1; the input nodes of the third Muller unit (102) are N13 and N6, and the output node is N3; the input nodes of the fourth Muller unit (103) are N3 and N15, and the output node is N4; the input nodes of the fifth Muller unit (104) are N5 and N17, and the output node is N4; the input nodes of the sixth Muller unit (105) are N6 and N9, and the output node is N5; the input nodes of the seventh Muller unit (106) are N1 and N13, and the output node is N0; the input nodes of the seventh Muller unit (106) are N1 and N13, and the output node is N1; the input nodes of the fifth Muller unit (104) are N5 and N17, and the output node is N4; the input nodes of the sixth Muller unit (105) are N6 and N9, and the output node is N5; the input nodes of the seventh Muller unit (106) are N1 and N13, and the output node is N0; the input nodes of the seventh Muller unit (106) are N1 and N13, and the output node is N0; the input nodes of the seventh Muller unit (105) are N1 and N13, and the output node is N0; the input nodes of the seventh Muller unit (106) are N1 and N13, and the output node is N1; the input nodes of the seventh Muller unit (105) are N1 and N13, and the output node is N1; the input nodes of the seventh Muller unit (106) are N1 and N13, and the output node is N1; the input nodes of The input nodes are N0, N20, and the output node is N8; the input nodes of the eighth Muller unit (108) are N4, N18, and the output node is N12; the input nodes of the ninth Muller unit (110) are N4, N7, and the output node is N8; the input nodes of the tenth Muller unit (112) are N11, N13, and the output node is N10; the input nodes of the eleventh Muller unit (114) are N13, N16, and the output node is N14; the input nodes of the twelfth Muller unit (115) are N5, N15, and the output node is N7; the input nodes of the thirteenth Muller unit (116) are N9, N2, and the output node is N17; the fourteenth Muller unit (117) is N8, N9, N20, and the output node is N8; the input nodes of the eleventh Muller unit (114) are N13, N16, and the output node is N14; the input nodes of the twelfth Muller unit (115) are N5, N15, and the output node is N7; the input nodes of the thirteenth Muller unit (116) are N9, N2, and the output node is N17; the input nodes of the fourteenth Muller unit (117) are N9, N20, and the output node is N18; the input nodes of the eleventh Muller unit (114) are N13, N16, and the output node is N14; the input nodes of the thirteenth Muller unit (115) are N5, N15, and the output node is N7; the input nodes of the thirteenth Muller unit (116) are N9, N20, and the output node is N17; the input nodes of the thirteenth Mu The input nodes of the fifteenth Muller unit (118) are N11 and N13, and the output node is N21; the input nodes of the fifteenth Muller unit (119) are N6 and N16, and the output node is N15; the input nodes of the sixteenth Muller unit (121) are N1 and N17, and the output node is N18; the input nodes of the seventeenth Muller unit (122) are N18 and N0, and the output node is N19; the input nodes of the eighteenth Muller unit (123) are N20 and N7, and the output node is N19; the input nodes of the nineteenth Muller unit (124) are N21 and N14, and the output node is N20; the input nodes of the first clock-controlled Muller unit (107 ... first clock-controlled Muller unit (107) are N11 and N13, and the output node is N21; the input nodes of the fifteenth Muller unit (119) are N6 and N16, and the output node is The input nodes of the first clocked Muller unit (109) are N5 and N10, and the output node is N2; the input nodes of the second clocked Muller unit (111) are N14 and N21, and the output node is N6; the input nodes of the third clocked Muller unit (111) are N8 and N19, and the output node is N9; the input nodes of the fourth clocked Muller unit (113) are N12 and N8, and the output node is N13; the input nodes of the fifth clocked Muller unit (117) are N19 and N12, and the output node is N11; the input nodes of the sixth clocked Muller unit (120) are N17 and N10, and the output node is N16; the output node of the first transmission gate (125) is N2; and the output node of the second transmission gate (126) is N6.The output node of the third transmission gate (127) is N9; the output node of the fourth transmission gate (128) is N11; the output node of the fifth transmission gate (129) is N13; the output node of the sixth transmission gate (130) is N16; the input terminal of all six transmission gates is the input signal D.

[0016] The core of this invention is a four-feedback loop latch circuit composed of 19 Muller units in the second part and 6 clocked Muller units in the third part. Each feedback loop has 2 to 3 Muller units nested with another feedback loop. Specifically, the eighth Muller unit (108), the tenth Muller unit (112), the thirteenth Muller unit (116), the first clocked Muller unit (107), the third clocked Muller unit (111), the fourth clocked Muller unit (113), and the fifth clocked Muller unit (117) are nested Muller units.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0018] The circuit structure of this invention is intuitive and easy to understand, and it boasts excellent performance, tolerating 7315 possible four-point flip-flops across 22 internal nodes. Secondly, the nested use of some Muller units enhances the circuit's radiation resistance. Thirdly, this invention utilizes six clocked Muller units, thus significantly reducing power consumption. In summary, this invention is a high-performance, low-power four-point flip-flop self-recovering latch. Attached Figure Description

[0019] Figure 1 This is the gate-level circuit structure of the latch described in this invention.

[0020] Figure 2 This refers to the transistor-level circuit and the corresponding gate-level circuit of the Muller unit described in this invention.

[0021] Figure 3 This refers to the transistor-level circuit and the corresponding gate-level circuit of the clocked Muller unit described in this invention.

[0022] Figure 4 These refer to the transistor-level circuit and the corresponding gate-level circuit of the transmission gate described in this invention.

[0023] Figure 5 The waveform diagrams for the five types of four-point flip faults of this invention are shown. Detailed Implementation

[0024] The present invention will now be further described in conjunction with the accompanying drawings and specific embodiments. It should be noted that, without conflict, the various embodiments or technical features described below can be arbitrarily combined to form new embodiments.

[0025] Example 1:

[0026] like Figure 1 As shown, the gate-level circuit of the four-point flip-flop self-recovery latch proposed in this invention has the following specific structure and fault-tolerant performance analysis:

[0027] The high-performance, low-power four-point toggle self-recovery latch proposed in this invention includes 6 transmission gates, 19 Muller units, and 6 clocked Muller units forming 4 feedback loops. Each feedback loop has 2 to 3 Muller units nested with another feedback loop.

[0028] Specifically, the eighth Muller unit (108), the tenth Muller unit (112), the thirteenth Muller unit (116), the first clocked Muller unit (107), the third clocked Muller unit (111), the fourth clocked Muller unit (113), and the fifth clocked Muller unit (117) are nested clocked Muller units.

[0029] The six transmission gates are the first transmission gate (125), the second transmission gate (126), the third transmission gate (127), the fourth transmission gate (128), the fifth transmission gate (129), and the sixth transmission gate (130). These six transmission gates are completely identical and have the same clock control signal.

[0030] The 19 Muller units are the first Muller unit (100), the second Muller unit (101), the third Muller unit (102), the fourth Muller unit (103), the fifth Muller unit (104), the sixth Muller unit (105), the seventh Muller unit (106), the eighth Muller unit (108), the ninth Muller unit (110), the tenth Muller unit (112), the eleventh Muller unit (114), the twelfth Muller unit (115), the thirteenth Muller unit (116), the fourteenth Muller unit (118), the fifteenth Muller unit (119), the sixteenth Muller unit (121), the seventeenth Muller unit (122), the eighteenth Muller unit (123), and the nineteenth Muller unit (124). These 19 Muller units have the same structure.

[0031] The six clocked Muller units are: the first clocked Muller unit (107), the second clocked Muller unit (109), the third clocked Muller unit (111), the fourth clocked Muller unit (113), the fifth clocked Muller unit (117), and the sixth clocked Muller unit (120). These six clocked Muller units are completely identical and have the same clock control signal.

[0032] Reference Figure 2 This refers to the transistor circuit and corresponding gate-level circuit of any Muller unit in this invention. Figure 2 As shown on the left, each Muller unit consists of a first PMOS transistor (201), a second PMOS transistor (202), a first NMOS transistor (204), and a second NMOS transistor (203). The source of the first PMOS transistor (201) is connected to the power supply VDD, the drain of the first PMOS transistor (201) is connected to the source of the second PMOS transistor (202), the gate of the first PMOS transistor (201) is connected to the input signal IN1, and the body of the first PMOS transistor (201) is connected to the power supply VDD. The drain of the second PMOS transistor (201) is connected to the output terminal Q, the gate of the second PMOS transistor (202) is connected to the input signal IN2, and the body of the second PMOS transistor (202) is connected to the power supply VDD. The source of an NMOS transistor (204) is connected to ground (GND). The drain of the first NMOS transistor (204) is connected to the source of a second NMOS transistor (203). The gate of the first NMOS transistor (204) is connected to the input signal IN2, and the body of the first NMOS transistor (204) is connected to ground (GND). The drain of the second NMOS transistor (203) is connected to the output terminal Q. The gate of the second NMOS transistor (203) is connected to the input signal IN1, and the body of the second NMOS transistor (203) is connected to ground (GND). This Muller cell structure outputs a signal inversely to IN1 and IN2 only when the two input signals IN1 and IN2 are the same. When IN1 and IN2 are different, the output signal Q remains unchanged. All 19 Muller cells used in this invention are identical.

[0033] Reference Figure 3 As shown, this is the transistor circuit and corresponding gate circuit of any clocked Muller unit in this invention. Figure 3As shown on the left, any clocked Muller unit consists of a first PMOS transistor (301), a second PMOS transistor (302), a third PMOS transistor (303), a first NMOS transistor (306), a second NMOS transistor (305), and a third NMOS transistor (304). In this configuration, the source of the first PMOS transistor (301) is connected to the power supply VDD, the drain of the first PMOS transistor (301) is connected to the source of the second PMOS transistor (302), the gate of the first PMOS transistor (301) is connected to the input signal IN1, and the body of the first PMOS transistor (301) is connected to the power supply VDD; the drain of the second PMOS transistor (302) is connected to the source of the third PMOS transistor (303), the gate of the second PMOS transistor (302) is connected to the input signal IN2, and the body of the second PMOS transistor (302) is connected to the power supply VDD; the drain of the third PMOS transistor (303) is connected to the output terminal Q, the gate of the third PMOS transistor (303) is connected to the clock signal CLK, and the body of the third PMOS transistor (303) is connected to the power supply VDD; the first The source terminal of NMOS transistor (306) is connected to ground signal GND. The drain terminal of the first NMOS transistor (306) is connected to the source terminal of the second NMOS transistor (305). The gate terminal of the first NMOS transistor (306) is connected to the input signal IN2. The body terminal of the first NMOS transistor (306) is connected to ground signal GND. The drain terminal of the second NMOS transistor (305) is connected to the source terminal of the third NMOS transistor (304). The gate terminal of the second NMOS transistor (305) is connected to the input signal IN1. The body terminal of the second NMOS transistor (305) is connected to ground signal GND. The drain terminal of the third NMOS transistor (304) is connected to the output terminal Q. The gate terminal of the third NMOS transistor (304) is connected to the complementary clock signal CLKB. The body terminal of the third NMOS transistor (304) is connected to ground signal GND. The clocked Muller unit only affects the output Q signal when the CLK signal is 0 and the CLKB signal is 1; when the CLK signal is 1 and the CLKB signal is 0, the output Q signal remains unchanged regardless of how the IN1 and IN2 signals change. The circuit structure of the six clocked Muller units used in this invention is identical.

[0034] Reference Figure 4 This refers to any transmission gate transistor circuit and its corresponding gate circuit in this invention. For example... Figure 4As shown on the left, each transmission gate consists of a first PMOS transistor (401) and a first NMOS transistor (402). The source of the first PMOS transistor (401) is connected to the input signal D, the drain of the first PMOS transistor (401) is connected to the output terminal Q, the gate of the first PMOS transistor (401) is connected to the complementary clock signal CLKB, and the body of the first PMOS transistor (401) is connected to the power supply VDD. The source of the first NMOS transistor (402) is connected to the input signal D, the drain of the first NMOS transistor (402) is connected to the output terminal Q, the gate of the first NMOS transistor (402) is connected to the clock signal CLK, and the body of the first NMOS transistor (402) is connected to the ground signal GND. When the CLK signal is 1 and the CLKB signal is 0, both the first PMOS transistor (401) and the first NMOS transistor (402) of the transmission gate are turned on, and the input signal D is written to the output terminal Q. When the CLK signal is 0 and the CLKB signal is 1, the first PMOS transistor (401) and the first NMOS transistor (402) of the transmission gate are turned off, and the input signal D cannot be written to the output terminal Q. The circuit structures of the six transmission gates used in this invention are all the same.

[0035] The fault-tolerance principle of this invention is as follows: Utilizing the characteristic that the output logic value remains unchanged after one of the input signal logic values ​​of a Muller unit or a clocked Muller unit flips, 19 Muller units and 6 clocked Muller units are connected in a specific manner to form four feedback loops. This enables the system to restore the correct logic value even after four-point flips in all 22 internal nodes. To further clarify the fault-tolerance principle, the HSPICE simulation waveforms for five different four-point flips are shown below. Figure 5 As shown.

[0036] The following section categorizes the four-point flip cases of this invention to provide a clearer understanding of its fault-tolerance principle. The latch of this invention has a total of 22 internal nodes, forming 4 feedback loops, thus possessing… Four-point flip combinations. To classify and explain the four-point flip, the ring containing the ninth Muller unit (110), the twelfth Muller unit (115), the thirteenth Muller unit (116), the fifteenth Muller unit (119), the third clocked Muller unit (111), and the sixth clocked Muller unit (120) is defined as ring A, including 6 internal nodes: N7, N8, N9, N15, N16, and N17; the ring containing the first Muller unit (100), the second Muller unit (101), the seventh Muller unit (106), the tenth Muller unit (112), the sixteenth Muller unit (121), the seventeenth Muller unit (122), the first clocked Muller unit (107), and the fifth clocked Muller unit (117) is defined as ring B, including N0 There are 7 internal nodes: N1, N2, N10, N11, N18, and N19. The ring containing the third Muller unit (102), the fourth Muller unit (103), the eighth Muller unit (108), the fourteenth Muller unit (118), the eighteenth Muller unit (123), the nineteenth Muller unit (124), and the fourth clocked Muller unit (113) is defined as ring C, which includes 6 internal nodes: N3, N4, N12, N13, N21, and N20. The ring containing the fifth Muller unit (104), the sixth Muller unit (105), the eleventh Muller unit (114), and the second clocked Muller unit (109) is defined as ring D, which includes 3 internal nodes: N5, N6, and N14. The classification of the four-point flipping cases of the latch of the present invention is shown in Table 1.

[0037] Table 1 Classification of the four-point flipping conditions of the latch of the present invention

[0038]

[0039]

[0040] Case 1: All four flipped nodes occur within a single ring, such as rings A, B, and C, resulting in 65 possible cases. In this case, if four nodes flip in any one ring, the states of the other three rings remain unchanged, so there is always one ring that can recover the flipped nodes. Assuming the four node flips occur within ring A, such as N7, N8, N9, and N17, the Muller unit located in ring A has only one input within ring A, while the other input is in another ring. Therefore, only one input of the Muller unit flips, and the output node of the Muller unit remains unchanged. The fault injection waveform in this case is as follows: Figure 5As shown in (①). Because ring A has 6 Muller units, nodes N7, N8, N9, and N17 can achieve self-recovery in sequence.

[0041] The second case: Three of the four flipped nodes are located within the same ring, and the remaining node is located anywhere within the three rings. There are 1184 possible scenarios. In this case, three nodes in one ring flip, and one node in another ring flips, such as N0, N1, N2, and N20 flipping. The fault injection waveform in this case is as follows: Figure 5 As shown in (②), N0, N1, and N2 are located within ring B, and N20 is located within ring C, which conforms to this classification. The Muller unit located in ring B has only one input path that is a node within ring B, and the other input path that is a node outside ring B. Because when only one input path of the Muller unit flips, the flip will not propagate to the output node, therefore the flips of N0, N1, N2, and N20 will not propagate to the next level node and can be recovered by the feedback loop.

[0042] The third case: Two of the four flipped nodes are located in the same ring, and the other two nodes are located in another ring, resulting in 1008 possible scenarios. In this case, two nodes in any one ring flip, and two nodes in another ring flip, such as N3, N4, N15, and N16 flipping. The fault injection waveform for this case is as follows: Figure 5 As shown in (③), N3 and N4 are located in ring B, and N15 and N16 are located in ring A, which conforms to this classification. The Muller unit located in ring B has only one input from a node inside ring B, and the other input from a node outside ring B; similarly, the Muller unit located in ring A, when only one input of the Muller unit flips, the flip will not propagate to the output node. It is worth noting that the fourth Muller unit has two inputs, N3 and N15, and both inputs flip. However, N3 and N15 can be recovered by the feedback loop, so node N4 can self-recover. In this case, the flips of N3, N4, N15, and N16 will not propagate to the next level node and can be recovered by the feedback loop.

[0043] The fourth case: Two of the four flipped nodes are located in the same ring, and the other two nodes are located in two other rings, resulting in 4302 possible cases. In this case, two nodes in any one ring flip, and one node in each of the other two rings flips, such as N10, N11, N12, and N14 flipping. The fault injection waveform for this case is as follows: Figure 5As shown in (④), N10 and N11 are located in ring B, N12 in ring C, and N14 in ring D, which conforms to this classification. For the Muller unit located in ring B, only one of its two inputs is a node inside ring B, and the other input is a node outside ring B. Similarly, for the Muller units located in rings C and D, when only one input of the Muller unit flips, the flip will not propagate to the output node. Therefore, the flips of N10, N11, N12, and N14 will not propagate to the next level node and can be recovered by the feedback loop.

[0044] The fifth case: one node in each of the four rings flips, resulting in 756 possible scenarios. In this case, one node in each of rings A, B, C, and D flips, such as N6, N7, N18, and N21. The fault injection waveform for this case is as follows: Figure 5 As shown in (⑤), N6 is located in ring D, N7 in ring A, N18 in ring B, and N21 in ring C, which conforms to this classification. Each Muller unit in each ring has only one input node flipped, therefore the output node does not flip.

[0045] In summary, this invention consists of 6 transmission gates, 19 Muller units, and 6 clocked Muller units. It can tolerate the simultaneous flipping of 4 internal nodes and can restore the flipped nodes to the correct logic value. Furthermore, this invention has low power consumption; therefore, it is a high-performance, low-power four-point flip-to-recovery latch.

[0046] The above embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of protection of the present invention. Any non-substantial changes and substitutions made by those skilled in the art based on the present invention shall fall within the scope of protection claimed by the present invention.

Claims

1. A high-performance, low-power four-point toggle self-recovery latch, characterized in that: Six transmission gates, 19 Muller units, and six clocked Muller units; The six transmission gates are identical and have the same clock control signal; The 19 Muller units described above have identical structures. The six clock-controlled Muller units are identical and have the same clock control signal; During the transparency period, 6 transmission gates are turned on and 6 clocked Muller units are turned off. The input signal D is simultaneously propagated to nodes N2, N6, N9, N11, N13, and N16 inside the latch, with node N11 serving as the output terminal Q. During the hold period, 6 transmission gates are turned off and 6 clocked Muller units are turned on. The data is latched within the feedback loop consisting of 19 Muller units and 6 clocked Muller units. The connection relationship of the six transmission gates in the latch is as follows: The input node of all six transmission gates is D; the output node of the first transmission gate (125) is N2; the output node of the second transmission gate (126) is N6; the output node of the third transmission gate (127) is N9; the output node of the fourth transmission gate (128) is N11; the output node of the fifth transmission gate (129) is N13; and the output node of the sixth transmission gate (130) is N16. The connection relationship of the 19 Muller units in the latch is as follows: The first Muller unit (100) has input nodes N1 and N3, and output node N0; the second Muller unit (101) has input nodes N2 and N13, and output node N1; the third Muller unit (102) has input nodes N2 and N6, and output node N3; the fourth Muller unit (103) has input nodes N3 and N15, and output node N4; the fifth Muller unit (104) has input nodes N5 and N17, and output node N0. The input nodes of the sixth Muller unit (105) are N6 and N9, and the output node is N5; the input nodes of the seventh Muller unit (106) are N0 and N20, and the output node is N8; the input nodes of the eighth Muller unit (108) are N4 and N18, and the output node is N12; the input nodes of the ninth Muller unit (110) are N4 and N7, and the output node is N8; the input nodes of the tenth Muller unit (112) are N11 and N13, The output node is N10; the input nodes of the eleventh Muller unit (114) are N13 and N16, and the output node is N14; the input nodes of the twelfth Muller unit (115) are N5 and N15, and the output node is N7; the input nodes of the thirteenth Muller unit (116) are N2 and N9, and the output node is N17; the input nodes of the fourteenth Muller unit (118) are N11 and N13, and the output node is N21; the fifteenth Muller unit (119) The input nodes of the sixteenth Muller unit (121) are N6 and N16, and the output node is N15; the input nodes of the seventeenth Muller unit (122) are N1 and N17, and the output node is N18; the input nodes of the seventeenth Muller unit (122) are N0 and N18, and the output node is N19; the input nodes of the eighteenth Muller unit (123) are N7 and N20, and the output node is N19; the input nodes of the nineteenth Muller unit (124) are N14 and N21, and the output node is N20. The connection relationships of the 6 clocked Muller units are as follows: The input nodes of the first clock-controlled Muller unit (107) are N5 and N10, and the output node is N2; the input nodes of the second clock-controlled Muller unit (109) are N14 and N21, and the output node is N6; the input nodes of the third clock-controlled Muller unit (111) are N8 and N19, and the output node is N9; the input nodes of the fourth clock-controlled Muller unit (113) are N8 and N12, and the output node is N13; the input nodes of the fifth clock-controlled Muller unit (117) are N12 and N19, and the output node is N11; the input nodes of the sixth clock-controlled Muller unit (120) are N10 and N17, and the output node is N16.

2. The high-performance, low-power four-point toggle self-recovery latch according to claim 1, characterized in that, The six transmission gates are identical and have the same clock control signal.

3. A high-performance, low-power four-point toggle self-recovery latch according to claim 1, characterized in that, The 19 Muller units are structurally identical.

4. A high-performance, low-power four-point toggle self-recovery latch according to claim 1, characterized in that: Each transmission gate consists of a first PMOS transistor (401) and a first NMOS transistor (402). The source terminal of the first PMOS transistor (401) is connected to the input signal D, the drain terminal of the first PMOS transistor (401) is connected to the output terminal Q, the gate terminal of the first PMOS transistor (401) is connected to the complementary clock signal CLKB, and the body terminal of the first PMOS transistor (401) is connected to the power supply VDD. The source terminal of the first NMOS transistor (402) is connected to the input signal D, the drain terminal of the first NMOS transistor (402) is connected to the output terminal Q, the gate terminal of the first NMOS transistor (402) is connected to the clock signal CLK, and the body terminal of the first NMOS transistor (402) is connected to the ground signal GND. Each transmission gate is turned on when the CLK signal is 1 and the CLKB signal is 0. The input signal D is simultaneously propagated to the internal nodes N2, N6, N9, N11, N13, and N16 of the latch, and the logic value of node N11 is used as the output terminal Q. When the CLK signal is 0 and the CLKB signal is 1, the six transmission gates are turned off, and the input signal D does not affect the logic values ​​of the internal nodes N2, N6, N9, N11, N13, and N16 and the output terminal Q.

5. A high-performance, low-power four-point toggle self-recovery latch according to claim 1, characterized in that: Each Muller unit consists of a first PMOS transistor (201), a second PMOS transistor (202), a first NMOS transistor (204), and a second NMOS transistor (203). The source of the first PMOS transistor (201) is connected to the power supply VDD, the drain of the first PMOS transistor (201) is connected to the source of the second PMOS transistor (202), the gate of the first PMOS transistor (201) is connected to the input signal IN1, and the body of the first PMOS transistor (201) is connected to the power supply VDD. The drain of the second PMOS transistor (201) is connected to the output terminal Q, and the gate of the second PMOS transistor (202) is connected to the input signal IN2. The body of the two PMOS transistors (202) is connected to the power supply VDD; the source of the first NMOS transistor (204) is connected to ground GND, the drain of the first NMOS transistor (204) is connected to the source of the second NMOS transistor (203), the gate of the first NMOS transistor (204) is connected to the input signal IN2, and the body of the first NMOS transistor (204) is connected to the ground signal GND; the drain of the second NMOS transistor (203) is connected to the output terminal Q, the gate of the second NMOS transistor (203) is connected to the input signal IN1, and the body of the second NMOS transistor (203) is connected to the ground signal GND. This Muller cell structure will only output a signal that is inversely related to IN1 and IN2 when the two input signals IN1 and IN2 are the same; when IN1 and IN2 are different, the output signal Q remains unchanged.

6. A high-performance, low-power four-point toggle self-recovery latch according to claim 1, characterized in that, Each clocked Muller unit consists of a first PMOS transistor (301), a second PMOS transistor (302), a third PMOS transistor (303), a first NMOS transistor (306), a second NMOS transistor (305), and a third NMOS transistor (304). The source of the first PMOS transistor (301) is connected to the power supply VDD, the drain of the first PMOS transistor (301) is connected to the source of the second PMOS transistor (302), the gate of the first PMOS transistor (301) is connected to the input signal IN1, and the body of the first PMOS transistor (301) is connected to the power supply VDD. The drain of the second PMOS transistor (302) is connected to the source of the third PMOS transistor (303), the gate of the second PMOS transistor (302) is connected to the input signal IN2, and the body of the second PMOS transistor (302) is connected to the power supply VDD. The drain of the third PMOS transistor (303) is connected to the output terminal Q, and the gate of the third PMOS transistor (303) is connected to the clock signal CLK. The body of the three PMOS transistors (303) is connected to the power supply VDD; the source of the first NMOS transistor (306) is connected to the ground signal GND, the drain of the first NMOS transistor (306) is connected to the source of the second NMOS transistor (305), the gate of the first NMOS transistor (306) is connected to the input signal IN2, and the body of the first NMOS transistor (306) is connected to the ground signal GND; the drain of the second NMOS transistor (305) is connected to the source of the third NMOS transistor (304), the gate of the second NMOS transistor (305) is connected to the input signal IN1, and the body of the second NMOS transistor (305) is connected to the ground signal GND; the drain of the third NMOS transistor (304) is connected to the output terminal Q, the gate of the third NMOS transistor (304) is connected to the complementary clock signal CLKB, and the body of the third NMOS transistor (304) is connected to the ground signal GND. This clocked Muller unit will only output the signal Q when the CLK signal is 0 and the CLKB signal is 1. The signal is inverted; when the CLK signal is 1 and the CLKB signal is 0, no matter how the IN1 and IN2 signals change, the signal at the output terminal Q will remain unchanged from the previous state.

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