CMOS image sensor pixels

Abstract

CMOS image sensor pixel (200) comprising: a photosensitive element (101) for generating a charge in response to incident light; a plurality of charge storage elements (103); a plurality of parallel-connected transmission gates (102), wherein each transmission gate (102) of the plurality of parallel-connected transmission gates (102) is placed in the photosensitive element (101) to enable the transfer of charge between the photosensitive element (101) and an associated charge storage element (103);one or more first electrical connections (201) to bring at least two of the plurality of charge storage elements (103) into mutual electrical contact in order to enable the reading of the cumulative total charge in the at least two of the plurality of charge storage elements; one or more second electrical connections (202) to control the plurality of transmission gates in parallel; a reset transistor (106); a gain transistor (107); and a select transistor (108), wherein the reset transistor (106), gain transistor (107) and select transistor (108) are shared by at least two of the plurality of charge storage elements (103).

Description

Technical field

[0001] The present invention relates to a CMOS image sensor pixel. background

[0002] Four-transistor CMOS image sensors (4TCIS) have been widely used since the 1980s. 4TCIS are increasingly used in mobile devices, with a primary focus on miniaturizing individual pixels. While small pixels are desirable for mobile devices, larger pixels are often required for many scientific, medical, and industrial applications where sensitivity is critical. 4TCIS pixels incorporate a transmission gate, which offers several advantages, such as enabling correlated double sampling to eliminate reset noise.However, the integration of a transfer gate can lead to a phenomenon known as image delay, which occurs when the time it takes electrons in a photodiode to travel from the creation point to the transfer gate exceeds the transfer gate pulse width, which defines the period during which the transfer gate is open.

[0003] Although image delay often has a strongly negative impact on the usefulness of the pixel, current inventors are unaware of any repeatable and flexible design for a 4TCIS pixel specifically aimed at reducing or eliminating image delay.

[0004] The inventors are aware that it would be desirable to provide a 4TCIS pixel whose size can be upscaled without significant image delay. Embodiments of the present invention aim to provide such a 4TCIS pixel. Brief description

[0005] Aspects of the invention are set out in the claims. Brief description of the drawings

[0006] Some embodiments of the invention are described below for illustrative purposes only and with reference to the accompanying drawings, wherein:

[0007] Fig. 1 shows a state-of-the-art 4TCIS pixel;

[0008] Fig. 2 shows a 4TCIS pixel according to an embodiment of the present invention;

[0009] Fig. 3 shows a 4TCIS pixel according to an alternative embodiment of the present invention;

[0010] Fig. Figure 4 shows a circuit diagram that represents a 4TCIS pixel of the in Fig. 2 corresponds to the illustrated embodiment;

[0011] Fig. Figure 5 shows a 4TCIS pixel according to an alternative embodiment of the present invention. Detailed description

[0012] Pixels of CMOS image sensors with 4 transistors (4TCIS) are well-known according to the state of the art and are becoming increasingly common, being used in devices such as digital cameras and mobile phones.

[0013] They can be used. 4TCIS pixels are described, for example, in patents US 5,625,210 A and US 8,138,535 B2.

[0014] With reference to Fig. 1. 4TCIS pixels known according to the state of the art 100 typically a light-sensitive element 101 such as a clip-on photodiode, a floating diffusion 103 , a transmission gate 102and a group of display electronics 105 on, which has a reset transistor 106 , an amplifying transistor 107 and a selection transistor 108 exhibits. The suspended diffusion 103 is connected to the amplification transistor 107 tied together 104 The transmission gate 102 is connected to a voltage source 109 tied together 110 , which allows for the controlled opening and closing of the transmission gate 102 made possible.

[0015] An alternative, the CMOS image sensor pixel with 3 transistors, is similar to the 4TCIS except for the exclusion of the transmission gate. 102 The integration of a transmission gate 102It possesses distinct advantages, such as enabling correlated double sampling to eliminate reset noise. Therefore, the 4TCIS pixel is often preferable to the simpler 3-transistor pixel. However, current inventors have recognized that the 4TCIS pixels known in the prior art suffer from a detrimental phenomenon known as image delay, and that this problem becomes increasingly pronounced as the size of the photosensitive element increases. 101 This increases, which may be necessary to improve the pixel's sensitivity. Image lag occurs when the time elapsed in the light-sensitive element increases. 101 generated electrons to reach the transmission gate 102 is required, is longer than the width of the voltage pulse that is applied to the transmission gate 102 is created to facilitate the transfer of charge into suspended diffusion 103to control. This results in not all of the generated charge being read out in a single frame, and can lead to phenomena such as ghosting when the pixels are used in an image sensor.

[0016] One aspect of the present invention is to shorten, regardless of pixel size, the path that the electrons generated by light have to travel to reach a transmission gate, compared to existing 4TCIS pixel designs. 102 to achieve this, thereby reducing or completely eliminating image delay. This is accomplished by using multiple transmission gates. 102 in combination with several floating diffusions 103 This is achieved by placing components in mutual electrical contact. Furthermore, it is possible through the use of multiple transmission gates. 102 possible in all areas of the light-sensitive element 101to achieve a significant electric guiding field, thereby enabling the transfer of electrons faster than with just a single transmission gate. 102 would be used.

[0017] Fig. Figure 2 illustrates a layout view of a 4TCIS pixel. 200 , which uses several transmission gates according to an embodiment of the present invention. According to this exemplary embodiment, the pixel comprises a single light-sensitive element. 101 on, for example, a mounted photodiode. Several transmission gates. 102 are contained in the individual light-sensitive element 101 placed. In the embodiment of Fig. There are a total of 4 ring-type transmission gates. 102 with an octagonal geometry in the light-sensitive element 101 placed. The in Fig. The embodiment shown in Figure 2 is purely exemplary and alternative configurations are being considered, e.g. by using a different number of transmission gates (at least two) arranged in an alternative manner and / or each having a different geometry.

[0018] The individual charge storage elements, e.g., floating diffusion areas 103 , are brought into mutual electrical contact due to the fact that they are connected to a group of first electrical, preferably ohmic, connections 201 are interconnected. This leads to an increase in the charge storage capacity of the combined floating diffusion, which is advantageous because large pixels may require a greater charge storage capacity. The cumulative total charge in the combined floating diffusion can be handled by a single group of readout devices. 105 be read out.

[0019] In the exemplary embodiment of Fig. 2 is the plural of transmission gates 102 by a group of second electrical, preferably ohmic connections 202 interconnected so that the transmission gates can be operated in parallel. Each transmission gate 102 It features a gate for controlling the state of the transmission gate, i.e., open or closed, in response to an applied voltage. For this purpose, a voltage source is required. 109 with the majority of transmission gates 102 tied together 110 , to open and close the transmission gates 102 to enable the voltage source 109 It can be operated by a control unit. It is also intended that the transmission gates 102 Alternatively, they could be controlled separately, so that they are not connected in parallel. The first and second electrical connections 201 and202 They can each have discrete, separate sections or can each consist of a single continuous section (such as a continuous ring- or C-shaped structure). The group of first electrical connections 201 is from the second group of electrical connections 202 electrically insulated.

[0020] Fig. Figure 3 illustrates a layout view of a 4TCIS pixel. 300 , which includes several transmission gates 102 according to an alternative embodiment of the present invention. According to this exemplary embodiment, the pixel has 300 four different light-sensitive elements 101 on, for example, attached photodiodes. Each light-sensitive element 101 is a transmission gate 102 belonging to the exemplary embodiment of Fig. 3 a ring transmission gate 102is the central element in the light-sensitive element 102 is, although other positions and / or geometries of the transmission gate are being considered. As in the embodiment of Fig. 2 are the four charge storage elements, e.g., floating diffusion areas. 103 , together by a group of first electrical, preferably ohmic connections 201 connected, thereby placing them in mutual electrical contact. The cumulative total charge in the combined suspended diffusion can be detected by a single group of readout devices. 105 can be read out. The four transmission gates 102 are interconnected by a group of second electrical, preferably ohmic, connections 202 connected (again electrically by the first group of electrical connections) 201 isolated), to the transmission gates 102 to put them in mutual electrical contact. Although Fig. Figure 3 illustrates a 4TCIS pixel that has a 2 × 2 arrangement of light-sensitive elements; it will be clear to the person skilled in the art that other arrangements are possible which also fall within the scope of protection of the claimed invention.

[0021] Fig. 4 is a circuit diagram illustrating the embodiment of a Fig. This corresponds to the 2 illustrated 4TCIS pixels. The transmission gate 102 is a transistor unit, where a voltage applied to the gate controls the transmission gate. 102 This enables. In this embodiment, the gates of the four transmission gates 102 connected in parallel 202 This makes it possible to control them simultaneously.

[0022] Fig. Figure 5 illustrates a layout view of a 4TCIS pixel. 500 , which includes several transmission gates 102according to an alternative embodiment of the present invention (a variation of the embodiment of Fig. 3, where identical features also have identical functions). According to the exemplary embodiment of Fig. 5 occupies the group of the first electrical connections 201 and the group of second electrical connections 202 , each of which is preferably a resistive connection, different layers with the pixel structure. They are in turn electrically isolated from each other.

[0023] A known technique for increasing the sensitivity of a 4TCIS without increasing image delay is the so-called binning method. Here, several adjacent 4TCIS pixels can be addressed in groups, e.g., 2 × 2. By averaging the outputs of several pixels, improved sensitivity under low-light conditions can be achieved, albeit at the expense of reduced resolution. In such a 2 × 2 configuration, each pixel has 4 transistors, so a 2 × 2 group of pixels would have a total of 16 transistors. According to the present invention, a single pixel with the same net size as the 2 × 2 group has a total of 7 transistors: 4 transmission gate transistors and 3 shared transistors for performing reset, amplification, and selection.Therefore, 4TCIS pixels according to the present invention can achieve a higher fill factor compared to conventional 4TCIS pixels used in a binning scheme as described above. Furthermore, 4TCIS pixels according to the present invention are expected to be less expensive and easier to manufacture compared to 4TCIS pixels using a binning arrangement, due to the reduced number of transistor units required per pixel unit.

[0024] A further advantage of the 4TCIS pixel according to the present invention is that the pixel size can be scaled up without significant re-optimization of the pixel design. For prior art 4TCIS pixels, implementing a different pixel size often requires optimizing the layout for that specific size.

[0025] Although the invention has been described with reference to preferred embodiments as set forth above, it should be clear that these embodiments are for illustrative purposes only and that the claims are not limited to these embodiments. A person skilled in the art may make modifications and alternatives with respect to the disclosure which shall be deemed to fall within the scope of protection of the claims set forth in the Annex. Any feature disclosed or illustrated in this specification may be incorporated into the invention, either alone or in any suitable combination with any other feature disclosed or illustrated herein.

Claims

[1] CMOS image sensor pixels, comprising: a light-sensitive element for generating a charge in response to incident light; a plurality of charge storage elements; a plurality of transfer gates to enable the transfer of charge between the photosensitive element and an associated charge storage element; and one or more first electrical connections to bring at least two of the majority of charge storage elements into mutual electrical contact. [2] CMOS image sensor pixel according to claim 1, wherein the one or more first electrical connections are ohmic connections in a conductive layer. [3] CMOS image sensor pixel according to claim 1 or 2, further comprising one or more second electrical connections for controlling the plurality of transmission gates. [4] CMOS image sensor pixel according to claim 3, wherein the plurality of transmission gates are connected in parallel. [5] CMOS image sensor pixel according to one of claims 1 to 4, comprising four transmission gates which are placed within the boundary of the light-sensitive element and are positioned such that the four transmission gates form the vertices of a parallelogram. [6] CMOS image sensor pixel according to any one of claims 1 to 5, wherein the light-sensitive element has an attached photodiode. [7] CMOS image sensor pixel according to any one of claims 1 to 6, wherein each charge storage element has a floating diffusion area. [8] CMOS image sensor pixel according to one of claims 1 to 7, further comprising: a reset transistor; an amplification transistor; and a selection transistor. [9] CMOS image sensor pixel according to claim 8, wherein the reset transistor, gain transistor and selection transistor are shared by at least two of the plurality of charge storage elements. [10] Image sensor comprising one or more CMOS image sensor pixels according to any of the preceding claims. [11] CMOS image sensor pixels, comprising: an arrangement of two or more light-sensitive elements, each configured to generate a charge in response to incident light; a plurality of charge storage elements; a plurality of transfer gates to enable the transfer of charge between the two or more photosensitive elements and an associated charge storage element, each transfer gate comprising a gate for controlling the state of the transfer gate in response to an applied voltage; one or more first electrical connections to bring at least two of the plurality of charge storage elements into mutual electrical contact; and one or more second electrical connections to put the majority of gates into mutual electrical contact. [12] CMOS image sensor pixel according to claim 11, wherein the one or more first electrical connections are ohmic connections in a conductive layer. [13] CMOS image sensor pixel according to claim 11 or 12, wherein one or more second electrical connections are ohmic connections in a conductive layer. [14] CMOS image sensor pixel according to one of claims 11 to 13, wherein each light-sensitive element has an attached photodiode. [15] CMOS image sensor pixel according to one of claims 11 to 14, wherein each charge storage element has a floating diffusion area. [16] CMOS image sensor pixel according to one of claims 11 to 15, further comprising: a reset transistor; an amplification transistor; and a selection transistor. [17] CMOS image sensor pixel according to claim 16, wherein the reset transistor, gain transistor and selection transistor are shared by at least two of the plurality of charge storage elements. [18] CMOS image sensor pixel according to one of claims 11 to 17, comprising four light-sensitive elements arranged in a 2 × 2 configuration. [19] Image sensor comprising one or more CMOS image sensor pixels according to any one of claims 11 to 18. [20] CMOS image sensor pixels, comprising: an arrangement of two or more light-sensitive elements, each configured to generate a charge in response to incident light; a plurality of charge storage elements; a plurality of transmission gates to enable the transfer of charge between each of the two or more photosensitive elements and an associated charge storage element; one or more first electrical connections to bring at least two of the plurality of charge storage elements into mutual electrical contact; and one or more second electrical connections for parallel control of the majority of transmission gates. [21] CMOS image sensor pixel according to claim 20, further comprising a control unit configured to control the plurality of transmission gates simultaneously.

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