Cmos image sensor and method of forming the same
By first forming a nitrogen-doped region and then an arsenic-doped region within the semiconductor substrate of a CMOS image sensor, the crystal defect problem caused by heavy atom arsenic doping process is solved, white pixels and leakage current are reduced, and device quality is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GALAXYCORE SHANGHAI
- Filing Date
- 2021-08-20
- Publication Date
- 2026-05-29
Smart Images
Figure CN115911063B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a CMOS image sensor and a method for forming the same. Background Technology
[0002] Image sensors are semiconductor devices that convert optical images into electrical signals. CMOS image sensors (CIS) have been widely used in various fields due to their advantages of low power consumption and high signal-to-noise ratio.
[0003] Among them, white pixel (WP) and dark current are considered key parameters for evaluating the performance of CIS devices.
[0004] Specifically, in semiconductor manufacturing processes, one of the reasons for the increase in the number of white pixels is defects. For example, during the formation of N-type source / drain regions in a semiconductor substrate, a step of adding heavy atom arsenic (As) doping is added to reduce ohmic contact resistance.
[0005] Because the implantation of heavy arsenic atoms can cause ion implantation damage in the silicon lattice, resulting in crystal defects, if there is no relatively long heat treatment in the subsequent process to repair these defects, these defects can lead to large dark currents or even white spots in the image sensor.
[0006] There is an urgent need for a method to fabricate CMOS image sensors that can improve device quality without altering existing heavy atom arsenic doping processes. Summary of the Invention
[0007] The technical problem solved by this invention is to provide a CMOS image sensor and a method for forming the same, which can effectively improve the device quality of the CMOS image sensor without changing the existing heavy atom arsenic doping process.
[0008] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a CMOS image sensor, comprising: providing a semiconductor substrate; forming a plurality of N-type source / drain regions within the semiconductor substrate; wherein forming the plurality of N-type source / drain regions within the semiconductor substrate includes: forming a plurality of arsenic-doped regions within the semiconductor substrate; wherein, before forming the plurality of arsenic-doped regions within the semiconductor substrate, the method further comprises: forming a plurality of nitrogen-doped regions within the semiconductor substrate, wherein the nitrogen-doped regions correspond one-to-one with the arsenic-doped regions, and the corresponding nitrogen-doped regions and arsenic-doped regions have overlapping regions.
[0009] Optionally, before forming a plurality of N-type source / drain regions in the semiconductor substrate, the method further includes: forming a lightly doped N-type region; wherein the nitrogen-doped region is formed before or after forming the lightly doped N-type region.
[0010] Optionally, before forming a plurality of lightly doped N-type regions in the semiconductor substrate, the method further includes: forming a first mask layer on the surface of the semiconductor substrate; wherein the lightly doped N-type regions and the nitrogen-doped regions are both formed using the first mask layer as a mask.
[0011] Optionally, forming multiple N-type source / drain regions in the semiconductor substrate further includes: performing one or more N-type doped ion implantations, wherein the energy and / or implanted ion concentration of the multiple N-type ion implantations are different; wherein the step of forming the nitrogen-doped region in the semiconductor substrate is before or after the step of the one or multiple N-type doped ion implantations, or between the steps of the multiple N-type doped ion implantations.
[0012] Optionally, forming the nitrogen-doped region in the semiconductor substrate includes: implanting nitrogen ions to form the nitrogen-doped region; forming the arsenic-doped region in the semiconductor substrate includes: implanting arsenic ions to form the arsenic-doped region; wherein the implantation depth of at least one N-type dopant ion implantation is greater than or equal to the nitrogen ion implantation depth; and / or, the nitrogen ion implantation depth is greater than or equal to the arsenic ion implantation depth.
[0013] Optionally, before forming the N-type source / drain region in the semiconductor substrate, the method further includes: forming a second mask layer on the surface of the semiconductor substrate; wherein the N-type source / drain region and the nitrogen-doped region are both formed using the second mask layer as a mask.
[0014] Optionally, the parameters of the nitrogen-doped region formation process are selected from one or more of the following: the implanted ions include nitrogen ions; the implanted ion concentration is from 1E13 atoms / cm² to 1E16 atoms / cm².
[0015] Optionally, after forming the N-type source / drain region, the forming method further includes: annealing the semiconductor substrate; wherein the process parameters of the annealing process are selected from one or more of the following: annealing temperature of 1000°C to 1200°C; annealing time of 1 second to 300 seconds.
[0016] Optionally, a gate structure is formed on the surface of the semiconductor substrate, the gate structure including: a gate dielectric layer and a gate layer located on the surface of the gate dielectric layer; before forming the N-type source / drain region, the forming method further includes: forming offset sidewalls on the sidewall surface of the gate structure; the N-type source / drain region is located in the semiconductor substrate on both sides of the partial gate structure.
[0017] To address the aforementioned technical problems, embodiments of the present invention provide a CMOS image sensor, comprising: a semiconductor substrate; a plurality of N-type source / drain regions located within the semiconductor substrate; and a plurality of nitrogen-doped regions located within the semiconductor substrate; wherein each N-type source / drain region includes an arsenic-doped region, the nitrogen-doped region and the arsenic-doped region correspond one-to-one, and the corresponding nitrogen-doped region and the arsenic-doped region have overlapping areas.
[0018] Optionally, the N-type source / drain region includes one or more N-type source / drain sub-regions; wherein the implantation depth forming at least one N-type source / drain sub-region is greater than or equal to the implantation depth forming the nitrogen-doped region; and / or, the implantation depth forming the nitrogen-doped region is greater than or equal to the implantation depth forming the arsenic-doped region.
[0019] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:
[0020] In this embodiment of the invention, by forming a nitrogen-doped region before forming an arsenic-doped region in the semiconductor substrate, wherein the nitrogen-doped region corresponds one-to-one with the arsenic-doped region and the corresponding nitrogen-doped region and the arsenic-doped region have overlapping areas, the influence of the charge generated by the pixel itself can be effectively reduced, thereby alleviating the white pixel problem. Furthermore, since the nitrogen-doped region is formed first and the arsenic-doped region is formed later, the damage to the crystal lattice caused by the implanted arsenic ions can be effectively reduced during the formation of the arsenic-doped region. On the one hand, the leakage current between the source / drain terminal and the substrate is effectively reduced; on the other hand, the gate-induced drain leakage (GIDL) caused by the damage is effectively reduced. Thus, without changing the existing heavy atom arsenic doping process, the device quality of the CMOS image sensor is effectively improved.
[0021] Furthermore, the nitrogen-doped region is formed before or after the formation of the N-type lightly doped region (LDD), so that the first mask layer can be reused with the N-type lightly doped region for nitrogen ion implantation, thereby effectively reducing the complexity of research and development and process, and lowering the improvement cost.
[0022] Furthermore, the step of forming the nitrogen-doped region in the semiconductor substrate before or after the single or multiple N-type doped ion implantation steps, or between the multiple N-type doped ion implantation steps, can enable the nitrogen-doped region to reuse the second mask layer for nitrogen ion implantation with the N-type source / drain region and the arsenic doped region, further reducing the complexity of research and development and the process, and lowering the improvement cost.
[0023] Furthermore, the implantation depth of at least one N-type doped ion implantation is greater than or equal to the nitrogen ion implantation depth, which can isolate the device outside the N-type source / drain region from the nitrogen-doped region, effectively avoiding additional impact on the device performance of the CMOS image sensor due to nitrogen ion implantation.
[0024] Furthermore, in this embodiment of the invention, the nitrogen ion implantation depth is greater than or equal to the arsenic ion implantation depth, which can enable the implanted nitrogen ions to improve the problems caused by arsenic doping to a greater extent, more effectively reduce the influence of the charge generated by the pixel itself, alleviate the white pixel problem, more effectively reduce the damage to the crystal lattice caused by the implanted arsenic ions, and effectively reduce leakage current. Attached Figure Description
[0025] Figure 1 This is a flowchart of a method for forming a CMOS image sensor according to an embodiment of the present invention;
[0026] Figures 2 to 5 This is a schematic diagram of the device cross-sectional structure corresponding to each step in a method for forming a CMOS image sensor according to an embodiment of the present invention;
[0027] Figures 6 to 9 This is a schematic diagram of the device cross-sectional structure corresponding to each step in another method for forming a CMOS image sensor in an embodiment of the present invention. Detailed Implementation
[0028] In semiconductor manufacturing processes, in order to reduce ohmic contact resistance, a step of adding heavy atom arsenic (As) doping is added during the formation of N-type source and drain regions in the semiconductor substrate. This may cause lattice damage, leading to problems such as white pixels and dark current. It is necessary to improve device quality without changing the existing heavy atom arsenic doping process.
[0029] In this embodiment of the invention, by forming a nitrogen-doped region before forming an arsenic-doped region in the semiconductor substrate, the nitrogen-doped region corresponds one-to-one with the arsenic-doped region, and the corresponding nitrogen-doped region and arsenic-doped region have overlapping areas. This can effectively reduce the influence of the charge generated by the pixel itself, thereby alleviating the white pixel problem. Furthermore, since the nitrogen-doped region is formed first and the arsenic-doped region is formed later, the damage to the crystal lattice caused by the implanted arsenic ions can be effectively reduced during the formation of the arsenic-doped region, effectively reducing leakage current, especially GIDL caused by damage. Thus, without changing the existing heavy atom arsenic doping process, the device quality of the CMOS image sensor can be effectively improved.
[0030] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0031] Reference Figure 1 , Figure 1 This is a flowchart of a method for forming a CMOS image sensor according to an embodiment of the present invention. The method for forming the CMOS image sensor may include steps S11 to S13:
[0032] Step S11: Provide a semiconductor substrate;
[0033] Step S12: Form multiple nitrogen-doped regions in a semiconductor substrate, wherein the nitrogen-doped regions correspond one-to-one with the arsenic-doped regions, and the corresponding nitrogen-doped regions and arsenic-doped regions have overlapping areas;
[0034] Step S13: Form multiple arsenic-doped regions within the semiconductor substrate.
[0035] The following is combined Figures 2 to 5 The steps described above will be explained.
[0036] Figures 2 to 5 This is a schematic diagram of the device cross-sectional structure corresponding to each step in a method for forming a CMOS image sensor according to an embodiment of the present invention.
[0037] Reference Figure 2 A semiconductor substrate 100 is provided, the semiconductor substrate 100 including a photodiode region 110, a dielectric layer 101 is formed on the surface of the semiconductor substrate 100, and a gate structure 120 is formed on the surface of the dielectric layer 101. The gate structure 120 may include a gate dielectric layer (not shown) and a gate layer (not shown) located on the surface of the gate dielectric layer.
[0038] In specific implementations, the semiconductor substrate 100 can be a silicon substrate, or the material of the semiconductor substrate 100 can also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate. The semiconductor substrate 100 can also be a silicon substrate with an insulator surface or a germanium substrate with an insulator surface, or a substrate with an epitaxy layer (Epi layer) grown on it. In a non-limiting embodiment, the semiconductor substrate 100 can be a lightly doped semiconductor substrate, and the doping type is opposite to that of the drain region. Specifically, deep well implantation can be achieved by ion implantation into the semiconductor substrate 100.
[0039] The type of the photodiode region 110 can be opposite to the doping type of the semiconductor substrate 100. If the photodiode region 110 is N-type, then the doping ions of the semiconductor substrate 100 are P-type ions, such as B, Ga, or In; conversely, if the doping ions of the photodiode region 110 are P-type, then the doping ions of the semiconductor substrate 100 are N-type ions, such as P, As, or Sb.
[0040] Furthermore, the dielectric layer 101 is used to protect the semiconductor substrate 100, and its material can be selected from: a stacked layer of silicon oxide and silicon nitride, silicon oxide and silicon nitride, and the material of the gate dielectric layer can be SiO2.
[0041] Among them, silicon oxide can be, for example, SiO2, and silicon nitride can be, for example, Si3N4.
[0042] Reference Figure 3 A first mask layer 161 is formed on the surface of the semiconductor substrate 100; using the first mask layer 161 as a mask, an N-type lightly doped region 131 and a nitrogen-doped region 132 are formed in the semiconductor substrate 100.
[0043] exist Figure 3 In the specific embodiment shown, before or after the formation of the N-type lightly doped region 131, a nitrogen-doped region 132 is formed in the semiconductor substrate 100 using the first mask layer 161 as a mask.
[0044] In this embodiment of the invention, the nitrogen-doped region 132 is formed before or after the formation of the N-type lightly doped region 131, so that the first mask layer 161 can be reused with the N-type lightly doped region 131 to implant nitrogen ions, thereby effectively reducing the complexity of research and development and process, and reducing the improvement cost.
[0045] Furthermore, the N-type lightly doped region 131 may contain N-type dopant ions, and N-type dopant ions are implanted into the semiconductor substrate 100 to obtain the N-type lightly doped region 131.
[0046] Furthermore, the implantation parameters for N-type doped ion implantation into the semiconductor substrate 100 may include one or more of the following:
[0047] The implanted ions include phosphorus (P) ions;
[0048] The injected energy is 10 keV to 30 keV, for example, 20 keV;
[0049] The injection dose was 1E12atom / cm 2 Up to 1E14 atom / cm 2 For example, 1E13atom / cm 2 .
[0050] Furthermore, the nitrogen-doped region 132 may contain nitrogen ions, and nitrogen ion implantation is performed into the semiconductor substrate 100 to obtain the nitrogen-doped region 132.
[0051] Furthermore, the implantation parameters for nitrogen ion implantation into the semiconductor substrate 100, i.e., the parameters of the formation process of the nitrogen-doped region 132, may include one or more of the following:
[0052] The implanted ions include nitrogen (N) ions;
[0053] The injected energy is 5 keV to 15 keV, for example, 10 keV;
[0054] The injection dose was 1E14 atom / cm 2 Up to 1E16 atom / cm 2 For example, 4E15atom / cm 2 ;
[0055] Reference Figure 4 Remove the first mask layer 161 (refer to) Figure 3 An offset sidewall (spacer) 121 is formed on the sidewall surface of the gate structure 120.
[0056] In specific implementation, conventional processes can be used to remove the first mask layer 161 and form the offset sidewall 121, and this is not limited in the embodiments of the present invention.
[0057] Reference Figure 5 A second mask layer 162 is formed on the surface of the semiconductor substrate 100. Using the second mask layer 162 as a mask, a plurality of N-type source / drain regions are formed in the semiconductor substrate 100. Each N-type source / drain region may include an arsenic-doped region 133 and one or more N-type source / drain implantation regions (not shown).
[0058] It is understood that since the semiconductor substrate 100 may have multiple gate structures 120 and there are channels between the gate structures 120, N-type source / drain regions can be formed in at least a portion of the channels according to design requirements. That is, multiple N-type source / drain regions can be located in different channels. In a single channel, the N-type source / drain region may include an arsenic-doped region 133 and one or more N-type source / drain sub-regions.
[0059] Furthermore, within a single channel, if an N-type lightly doped region and a nitrogen-doped region have been previously formed, the N-type source / drain region may have overlapping areas with the previously formed N-type lightly doped region and / or nitrogen-doped region 132.
[0060] Furthermore, the step of forming multiple N-type source / drain regions in the semiconductor substrate 100 may include: performing one or more N-type doped ion implantations in the semiconductor substrate 100, wherein the energy and / or implanted ion concentration of the multiple N-type ion implantations are different; and forming multiple arsenic doped regions 133 in the semiconductor substrate 100.
[0061] It should be noted that, in the embodiments of the present invention, the formation order between the arsenic-doped region 133 and the N-type source / drain region is not restricted, but the formation order of the nitrogen-doped region 132 and the arsenic-doped region 133 is required to be sequential.
[0062] As in Figures 2 to 5 In the illustrated method for forming a CMOS image sensor, the nitrogen-doped region 132 is formed based on a first mask layer before or after the formation of the lightly doped N-type region 131. Therefore, the arsenic-doped region 133 must be formed after the nitrogen-doped region 132.
[0063] As a non-limiting example, two N-type doped ion implantations can be performed within a single channel to form a first N-type source / drain region (not shown) and a second N-type source / drain region (not shown).
[0064] The implantation parameters for the first N-type doped ion implantation may include one or more of the following:
[0065] The implanted ions include phosphorus (P) ions;
[0066] The injected energy is 20 keV to 30 keV, for example, 25 keV;
[0067] The injection dose was 150 E3 atom / cm. 2 Up to 250E3atom / cm 2 For example, 200E3atom / cm 2 .
[0068] The implantation parameters for the second N-type doped ion implantation may include one or more of the following:
[0069] The implanted ions include phosphorus (P) ions;
[0070] The injected energy is 2 keV to 8 keV, for example, 5 keV;
[0071] The injection dose was 200E5atom / cm. 2 Up to 300E5atom / cm 2 For example, 250E5atom / cm 2 .
[0072] Furthermore, the step of forming a plurality of arsenic-doped regions 133 within the semiconductor substrate 100 may include:
[0073] The implanted ions include arsenic (As) ions;
[0074] The injected energy is 15 keV to 25 keV, for example, 20 keV;
[0075] The injection dose was 150E5atom / cm. 2 Up to 250E5atom / cm 2 For example, 200E5atom / cm 2 .
[0076] like Figure 5 As shown, the N-type source / drain regions are located within the semiconductor substrates 100 on both sides of the partial gate structure 120. Since the N-type source / drain regions are affected by the offset sidewalls 121 during the formation of the N-type source / drain regions, it can be considered that the N-type source / drain regions are located within the semiconductor substrates 100 on both sides of the offset sidewalls 121 of the partial gate structure 120.
[0077] In this embodiment of the invention, before forming the arsenic-doped region 133 in the semiconductor substrate 100, a nitrogen-doped region 132 is formed. The nitrogen-doped region 132 corresponds one-to-one with the arsenic-doped region 133, and the corresponding nitrogen-doped region 132 and arsenic-doped region 133 have overlapping areas. This can effectively reduce the influence of the charge generated by the pixel itself, thereby alleviating the white pixel problem. Furthermore, since the nitrogen-doped region 132 is formed first and the arsenic-doped region 133 is formed later, the damage to the crystal lattice caused by the implanted arsenic ions can be effectively reduced during the formation of the arsenic-doped region 133, effectively reducing leakage current, especially GIDL caused by damage. Thus, without changing the existing heavy atom arsenic doping process, the device quality of the CMOS image sensor can be effectively improved.
[0078] Reference Figures 6 to 9 , Figures 6 to 9 This is a schematic diagram of the device cross-sectional structure corresponding to each step in another method for forming a CMOS image sensor in an embodiment of the present invention.
[0079] in, Figure 6 Is Figure 2 Based on, related Figure 2 For more details on the semiconductor devices shown, please refer to the previous description; they will not be repeated here.
[0080] Reference Figure 6 A first mask layer 261 is formed on the surface of the semiconductor substrate 100; using the first mask layer 261 as a mask, an N-type lightly doped region 231 is formed in the semiconductor substrate 100.
[0081] Furthermore, the N-type lightly doped region 231 may contain N-type dopant ions, and N-type dopant ions are implanted into the semiconductor substrate 100 to obtain the N-type lightly doped region 131.
[0082] The implantation parameters for implanting N-type doped ions into the semiconductor substrate 100 can be referred to the previous description and will not be repeated here.
[0083] Reference Figure 7 Remove the first mask layer 261 (refer to) Figure 6 Offset sidewalls 221 are formed on the sidewall surface of the gate structure 120.
[0084] In specific implementation, conventional processes can be used to remove the first mask layer 261 and form the offset sidewall 221, but this is not limited in the embodiments of the present invention.
[0085] Reference Figure 8 A second mask layer 262 is formed on the surface of the semiconductor substrate 100; a plurality of nitrogen-doped regions 232 are formed in the semiconductor substrate 100 using the second mask layer 262 as a mask.
[0086] Furthermore, the nitrogen-doped region 232 may contain nitrogen ions, and nitrogen ion implantation is performed into the semiconductor substrate 100 to obtain the nitrogen-doped region 232.
[0087] The implantation parameters for nitrogen ion implantation into the semiconductor substrate 100 can be referred to in the previous text and will not be repeated here.
[0088] Reference Figure 9 Using the second mask layer 262 as a mask, a plurality of N-type source / drain regions are formed in the semiconductor substrate 100, wherein each N-type source / drain region may include an arsenic-doped region 233 and one or more N-type source / drain sub-regions (not shown).
[0089] It is understood that since the semiconductor substrate 100 may have multiple gate structures 120 and there are channels between the gate structures 120, N-type source / drain regions can be formed in at least a portion of the channels according to design requirements. That is, multiple N-type source / drain regions can be located in different channels. In a single channel, the N-type source / drain region may include an arsenic-doped region and one or more N-type source / drain sub-regions.
[0090] Furthermore, within a single channel, if an N-type lightly doped region and a nitrogen-doped region have been previously formed, the N-type source / drain region may have overlapping areas with the previously formed N-type lightly doped region and / or nitrogen-doped region 232.
[0091] Furthermore, the step of forming multiple N-type source / drain regions in the semiconductor substrate 100 may include: performing one or more N-type doped ion implantations in the semiconductor substrate 100, wherein the energy and / or implanted ion concentration of the multiple N-type ion implantations are different; and forming multiple arsenic doped regions 233 in the semiconductor substrate 100.
[0092] The implantation parameters for one or more N-type doped ion implantations can be referred to in the previous text, and the implantation parameters for forming multiple arsenic doped regions 233 can also be referred to in the previous text, and will not be repeated here.
[0093] It should be particularly pointed out that, although in Figures 6 to 9 In the method for forming a CMOS image sensor shown, a nitrogen-doped region 232 is formed first, followed by an N-type source / drain region and an arsenic-doped region 233. However, in a specific implementation, a nitrogen-doped region 232 can also be formed between the formation of multiple N-type source / drain regions.
[0094] Specifically, in this application, there is only a requirement regarding the order in which the nitrogen-doped region 232 and the arsenic-doped region 233 are formed. Specifically, the nitrogen-doped region 232 must be formed first, followed by the arsenic-doped region 233.
[0095] It is understandable that if the N-type source / drain regions are formed first, followed by the arsenic-doped regions 233, then nitrogen-doped regions 232 can be formed before and between the formation of each N-type source / drain region; if the arsenic-doped regions 233 are formed first, followed by the N-type source / drain regions, then nitrogen-doped regions 232 can only be formed before the formation of arsenic-doped regions 233; if a portion of the N-type source / drain regions are formed first, then the arsenic-doped regions 233 are formed, and finally another portion of the N-type source / drain regions are formed, then nitrogen-doped regions 232 can be formed before or between the first-formed N-type source / drain regions.
[0096] Further, the step of forming multiple N-type source / drain regions in the semiconductor substrate 100 may include: performing one or more N-type doped ion implantations, wherein the energy and / or implanted ion concentration of the multiple N-type ion implantations are different; wherein the step of forming the nitrogen-doped region 232 in the semiconductor substrate is performed before or after the step of the one or multiple N-type doped ion implantations, or between the steps of the multiple N-type doped ion implantations.
[0097] In this embodiment of the invention, the step of forming the nitrogen-doped region in the semiconductor substrate before or after the single N-type doped ion implantation or multiple N-type doped ion implantation steps, or between the multiple N-type doped ion implantation steps, can enable the nitrogen-doped region 232 to reuse the second mask layer 262 with the N-type source / drain region and the arsenic-doped region 233 to implant nitrogen ions, further reducing the complexity of research and development and the process, and lowering the improvement cost.
[0098] In this embodiment of the invention, by forming a nitrogen-doped region 232 before forming an arsenic-doped region 233 in the semiconductor substrate, the nitrogen-doped region 232 corresponds one-to-one with the arsenic-doped region 233, and the corresponding nitrogen-doped region 232 and arsenic-doped region 233 have overlapping areas. This can effectively reduce the influence of the charge generated by the pixel itself, thereby alleviating the white pixel problem. Furthermore, since the nitrogen-doped region 232 is formed first and the arsenic-doped region 233 is formed later, the damage to the crystal lattice caused by the implanted arsenic ions can be effectively reduced during the formation of the arsenic-doped region 233, effectively reducing leakage current, especially GIDL caused by damage. Thus, without changing the existing heavy atom arsenic doping process, the device quality of the CMOS image sensor can be effectively improved.
[0099] It should be noted that, in the embodiments of the present invention, the number of times the nitrogen-doped region is formed is not limited.
[0100] In one specific embodiment of the present invention, considering production costs and efficiency, and the fact that no significant advantage has been found in forming nitrogen-doped regions multiple times in different steps, nitrogen-doped regions can be formed only in one of the aforementioned optional steps.
[0101] Further, forming the nitrogen-doped region in the semiconductor substrate includes: implanting nitrogen ions to form the nitrogen-doped region 132 (nitrogen-doped region 232); forming the arsenic-doped region 133 (arsenic-doped region 233) in the semiconductor substrate includes: implanting arsenic ions to form the arsenic-doped region 133 (arsenic-doped region 233); wherein the implantation depth of at least one N-type dopant ion implantation is greater than or equal to the nitrogen ion implantation depth; and / or, the nitrogen ion implantation depth is greater than or equal to the arsenic ion implantation depth.
[0102] In this embodiment of the invention, the implantation depth of at least one N-type doped ion implantation is greater than or equal to the nitrogen ion implantation depth, which can isolate the device outside the N-type source / drain region from the nitrogen-doped region 132 (nitrogen-doped region 232), effectively avoiding additional impact on the device performance of the CMOS image sensor due to nitrogen ion implantation.
[0103] In this embodiment of the invention, the nitrogen ion implantation depth is greater than or equal to the arsenic ion implantation depth, which can enable the implanted nitrogen ions to improve the problems caused by arsenic doping to a greater extent, more effectively reduce the influence of the charge generated by the pixel itself, alleviate the white pixel problem, more effectively reduce the damage to the crystal lattice caused by the implanted arsenic ions, and effectively reduce leakage current.
[0104] Furthermore, after forming the N-type source / drain regions, the formation method may further include: annealing the semiconductor substrate; wherein the process parameters of the annealing process may be selected from one or more of the following:
[0105] The annealing temperature is 1000℃ to 1200℃;
[0106] Annealing time ranges from 1 second to 300 seconds.
[0107] In this embodiment of the invention, by setting an annealing step, the damage caused by the lattice can be repaired after the formation of arsenic doped region 133 (arsenic doped region 233), further reducing leakage current, especially reducing GIDL caused by damage, which is beneficial to better improve the device quality of CMOS image sensor.
[0108] Furthermore, the semiconductor substrate 100 may include an interface (IO) device region and a core device region, and the nitrogen-doped region 132 (nitrogen-doped region 232) may be located only within the IO device region.
[0109] Specifically, compared to the core device region, the devices in the I / O device region have a greater impact on the performance of the pixels. Therefore, forming nitrogen-doped regions 132 only in the I / O device region can more effectively improve device quality with minimal changes to the existing CMOS image sensor fabrication process.
[0110] In this embodiment of the invention, a CMOS image sensor may also be provided, as shown below. Figure 5 It may include: a semiconductor substrate 100; a plurality of N-type source / drain regions (not shown) located within the semiconductor substrate 100; a plurality of nitrogen-doped regions 132 located within the semiconductor substrate 100; wherein each N-type source / drain region includes an arsenic-doped region 133, the nitrogen-doped region 132 and the arsenic-doped region 133 are in one-to-one correspondence, and the corresponding nitrogen-doped region 132 and the arsenic-doped region 133 have overlapping regions.
[0111] Furthermore, the N-type source / drain region includes one or more N-type source / drain sub-regions; wherein the implantation depth for forming at least one N-type source / drain sub-region is greater than or equal to the implantation depth for forming the nitrogen-doped region 132; and / or, the implantation depth for forming the nitrogen-doped region 132 is greater than or equal to the implantation depth for forming the arsenic-doped region 133.
[0112] For details regarding the principles, implementation, and beneficial effects of this CMOS image sensor, please refer to the preceding text and... Figures 1 to 9 The description of the method for forming a CMOS image sensor shown is not repeated here.
[0113] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a CMOS image sensor, characterized in that, include: Provide semiconductor substrates; Multiple N-type source / drain regions are formed within the semiconductor substrate; The formation of multiple N-type source / drain regions within the semiconductor substrate includes: Multiple arsenic-doped regions are formed within the semiconductor substrate; Prior to forming multiple arsenic-doped regions within the semiconductor substrate, the method further includes: Multiple nitrogen-doped regions are formed in the semiconductor substrate, and the nitrogen-doped regions correspond one-to-one with the arsenic-doped regions. The corresponding nitrogen-doped regions and arsenic-doped regions have overlapping areas but do not completely overlap. The implantation depth of the nitrogen-doped regions is greater than the implantation depth of the arsenic-doped regions.
2. The method for forming a CMOS image sensor according to claim 1, characterized in that, Before forming multiple N-type source / drain regions within the semiconductor substrate, the method further includes: Formation of N-type lightly doped regions; The nitrogen-doped region is formed before or after the formation of the N-type lightly doped region.
3. The method for forming a CMOS image sensor according to claim 2, characterized in that, Before forming multiple lightly doped N-type regions within the semiconductor substrate, the method further includes: A first mask layer is formed on the surface of the semiconductor substrate; The N-type lightly doped region and the nitrogen-doped region are both formed using the first mask layer as a mask.
4. The method for forming a CMOS image sensor according to claim 1, characterized in that, Forming multiple N-type source / drain regions within the semiconductor substrate further includes: One or more N-type doped ion implantations are performed, and the energy and / or the implanted ion concentration are different for each N-type ion implantation. The step of forming the nitrogen-doped region in the semiconductor substrate is performed before or after the single N-type doped ion implantation or multiple N-type doped ion implantation steps, or between the multiple N-type doped ion implantation steps.
5. The method for forming a CMOS image sensor according to claim 4, characterized in that, Forming the nitrogen-doped region within the semiconductor substrate includes: implanting nitrogen ions to form the nitrogen-doped region; Forming an arsenic-doped region within the semiconductor substrate includes: implanting arsenic ions to form the arsenic-doped region; Among them, the implantation depth of at least one N-type doped ion implantation is greater than or equal to the nitrogen ion implantation depth; And / or, The nitrogen ion implantation depth is greater than or equal to the arsenic ion implantation depth.
6. The method for forming a CMOS image sensor according to claim 4, characterized in that, Before forming the N-type source / drain region within the semiconductor substrate, the method further includes: A second mask layer is formed on the surface of the semiconductor substrate; The N-type source / drain region and the nitrogen-doped region are both formed using the second mask layer as a mask.
7. The method for forming a CMOS image sensor according to claim 1, characterized in that, The parameters of the process for forming the nitrogen-doped region are selected from one or more of the following: The implanted ions include nitrogen ions; The implanted ion concentration ranged from 1E13 atoms / cm² to 1E16 atoms / cm².
8. The method for forming a CMOS image sensor according to claim 1, characterized in that, After forming the N-type source / drain region, the forming method further includes: The semiconductor substrate is annealed. The process parameters for the annealing treatment are selected from one or more of the following: The annealing temperature is 1000℃ to 1200℃; Annealing time ranges from 1 second to 300 seconds.
9. The method for forming a CMOS image sensor according to claim 1, characterized in that, A gate structure is formed on the surface of the semiconductor substrate, the gate structure comprising: a gate dielectric layer and a gate layer located on the surface of the gate dielectric layer; Before forming the N-type source / drain region, the forming method further includes: forming offset sidewalls on the sidewall surface of the gate structure; The N-type source / drain regions are located within the semiconductor substrate on both sides of the partial gate structure.
10. A CMOS image sensor, characterized in that, The CMOS image sensor is obtained using the method for forming a CMOS image sensor as described in any one of claims 1 to 9, comprising: Semiconductor substrate; Multiple N-type source / drain regions are located within the semiconductor substrate; Multiple nitrogen-doped regions are located within the semiconductor substrate; Each N-type source / drain region includes an arsenic-doped region, and the nitrogen-doped region corresponds one-to-one with the arsenic-doped region. The corresponding nitrogen-doped region and the arsenic-doped region have overlapping areas but do not completely overlap. The implantation depth of the nitrogen-doped region is greater than the implantation depth of the arsenic-doped region.
11. The CMOS image sensor according to claim 10, characterized in that, The N-type source / drain region includes one or more N-type source / drain sub-regions; Wherein, the implantation depth for forming at least one N-type source / drain region is greater than or equal to the implantation depth for forming the nitrogen-doped region.