A low power dynamic latching comparator

Abstract

The application discloses a kind of low-power dynamic latching comparators, belong to comparator circuit structure technical field, comprising: 7 transmission gates, 2 inverters, 2 two-input nor gates, first sampling capacitor and second sampling capacitor;2 inverters are connected in head and tail to constitute amplification circuit, 2 two-input nor gates are connected to each other to form dynamic latch circuit, 7 transmission gates are composed of first transmission gate to seventh transmission gate, by specific connection relationship and timing control, first sampling capacitor and second sampling capacitor are collected input signal and reference signal respectively through first transmission gate and second transmission gate, then input signal and reference signal are transmitted to both ends of amplification circuit to compare, amplification circuit amplifies comparison result, then final result is latched into dynamic latch circuit;The application used are all simple gate circuit and MOM capacitor, amplification circuit is only connected in head and tail by 2 inverters, and circuit scale is small, so that power consumption is greatly reduced.

Description

Technical Field

[0001] This invention relates to a low-power dynamic latch comparator, belonging to the technical field of comparator circuit structure. Background Technology

[0002] With the rapid development of the semiconductor industry, comparators are now widely used in almost all industries. A comparator (also known as a voltage comparator) is a type of integrated circuit. A voltage comparator is used to compare the magnitudes of two input voltages.

[0003] Currently, the circuits used in high-precision comparators are typically very large, which also results in high power consumption. Summary of the Invention

[0004] The purpose of this invention is to provide a low-power dynamic latch comparator to solve the problem of high power consumption in the prior art.

[0005] To achieve the above objectives, the present invention employs the following technical solution:

[0006] This invention provides a low-power dynamic latch comparator, comprising: 7 transmission gates, 2 inverters, 2 two-input NOR gates, a first sampling capacitor, and a second sampling capacitor; the 2 inverters are connected end-to-end to form an amplifier circuit, the 2 two-input NOR gates are interconnected to form a dynamic latch circuit, the 7 transmission gates consist of the first transmission gate to the seventh transmission gate, the first sampling capacitor is connected before and after the first transmission gate and the third transmission gate respectively, the third transmission gate is also connected to the fifth transmission gate in parallel, the amplifier circuit, and the dynamic latch circuit, and then sequentially connected to the fourth transmission gate, the second sampling capacitor, and the second transmission gate, the sixth transmission gate is also connected between the third transmission gate and the dynamic latch circuit, and the seventh transmission gate is also connected between the dynamic latch circuit and the fourth transmission gate;

[0007] The first sampling capacitor and the second sampling capacitor respectively acquire the input signal and the reference signal through the first transmission gate and the second transmission gate. Then, the input signal and the reference signal are transmitted to both ends of the amplifier circuit for comparison. The amplifier circuit amplifies the comparison result and then latches the final result into the dynamic latch circuit.

[0008] Furthermore, before acquiring the signal, the amplifier circuit is pre-set, including: enabling the switch control signal of the fifth transmission gate, opening the fifth transmission gate, and making the potentials at both ends of the amplifier circuit equal.

[0009] Furthermore, before acquiring the signal, the switching control signals of the first transmission gate and the second transmission gate are enabled, the first transmission gate and the second transmission gate are turned on, so that the input signal and the reference signal are sampled by the first sampling capacitor and the second sampling capacitor respectively, and then the first transmission gate and the second transmission gate are turned off, so that the potential on the first sampling capacitor and the second sampling capacitor remains stable.

[0010] Furthermore, the input signal and the reference signal are transmitted to both ends of the amplifier circuit for comparison. The amplifier circuit amplifies the comparison result, including:

[0011] Enable the switching control signals of the third and fourth transmission gates, open the third and fourth transmission gates, and simultaneously disconnect the fifth transmission gate. Transmit the input signal and the reference signal to the two ports of the amplifier circuit respectively. Then, the amplifier circuit amplifies the difference between the input signal and the reference signal. The port of the amplifier circuit connected to the third transmission gate is the X port, and the port connected to the fourth transmission gate is the Y port.

[0012] If the input signal is greater than the reference signal, the difference is amplified to the power supply voltage at the X port of the amplifier circuit, while the Y port of the amplifier circuit becomes a low potential connected to the power supply ground; if the input signal is less than the reference signal, the difference is amplified to the power supply voltage at the Y port of the amplifier circuit, while the X port of the amplifier circuit becomes a low potential connected to the power supply ground.

[0013] Furthermore, the final result is latched into the dynamic latch circuit, including:

[0014] Enable the switching control signals of the sixth and seventh transmission gates. After the sixth and seventh transmission gates are turned on, connect the X port of the amplifier circuit to one input of a two-input NOR gate, and connect the Y port of the amplifier circuit to one input of another two-input NOR gate. Then, the output potential of the two two-input NOR gates in the dynamic latch circuit can reflect the magnitude of the input signal and the reference signal.

[0015] Finally, disconnecting the sixth and seventh transmission gates latches the final result into the dynamic latch circuit.

[0016] Furthermore, both the first sampling capacitor and the second sampling capacitor are connected to the power supply ground.

[0017] Compared with the prior art, the beneficial effects achieved by the present invention are:

[0018] This invention provides a low-power dynamic latch comparator, consisting of only 7 transmission gates, 2 inverters, 2 two-input NOR gates, and 2 sampling capacitors. It utilizes simple gate-level circuitry and MOM capacitors, and unlike traditional high-gain operational amplifiers which are more complex to design, the amplification circuit in this design is simply two inverters connected end-to-end. This reduces design complexity and circuit size, resulting in a significant reduction in power consumption. Furthermore, the circuit structure of this invention exhibits good symmetry, effectively saving circuit area during layout and routing. The voltage resolution of this design can reach 1mV, making it applicable to general Flash ADCs. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a low-power dynamic latch comparator provided in an embodiment of the present invention. Detailed Implementation

[0020] The present invention will be further described below with reference to the accompanying drawings. The following embodiments are only used to illustrate the technical solution of the present invention more clearly, and should not be used to limit the scope of protection of the present invention.

[0021] like Figure 1 As shown, the present invention provides a low-power dynamic latch comparator, which includes 7 transmission gates, 2 inverters, 2 two-input NOR gates and 2 sampling capacitors.

[0022] The seven transmission gates TG0, TG1, TG2, TG3, TG4, TG5, and TG6 function as switches.

[0023] Two inverters (the first inverter and the second inverter) are connected end to end to form an amplifier circuit. Two two-input NOR gates are connected to each other to form a dynamic latch circuit. Seven transmission gates are composed of the first transmission gate to the seventh transmission gate.

[0024] The input terminal of the first transmission gate TG0 is connected to the input signal Vin. The output terminal of the first transmission gate TG0 is connected to the upper plate of the first sampling capacitor C0. The lower plate of the first sampling capacitor C0 is connected to the power supply ground VSS. The upper plate of the first sampling capacitor C0 is also connected to the input terminal of the third transmission gate TG2. The output terminal of the third transmission gate TG2 is connected to the input terminals of the fifth transmission gate TG4 and the sixth transmission gate TG5, and also to the output terminal of the first inverter INV0 and the input terminal of the second inverter INV1. The output terminal of the sixth transmission gate TG5 is connected to one input terminal of the two-input NOR gate NOR0. The other input terminal of the two-input NOR gate NOR0 is connected to the output terminal of the two-input NOR gate NOR1. The output port Q, one input of the two-input NOR gate NOR1 is connected to the output port QB of the two-input NOR gate NOR0, the other input of the two-input NOR gate NOR1 is connected to the output of the seventh transmission gate TG6, the input of the seventh transmission gate TG6 is connected to the output of the fourth transmission gate TG3, the output of the fifth transmission gate TG4, the output of the first inverter INV0 and the input of the second inverter INV1, the input of the fourth transmission gate TG3 is connected to the upper plate of the second sampling capacitor C1, the lower plate of the second sampling capacitor C1 is connected to the power supply ground VSS, the upper plate of the second sampling capacitor C1 is also connected to the output of the second transmission gate TG1, and the input of the second transmission gate TG1 is connected to the reference signal Vref.

[0025] Figure 1In the middle, CK0 and CKB0 are control signals that control the opening or closing of the two transmission gates TG0 and TG1. If CK0 is connected to a low potential, then CKB0 is connected to a high potential, and if CK0 is connected to a high potential, then CKB0 is connected to a low potential.

[0026] CK1, CKB1: Control signals that control the opening or closing of the two transmission gates TG2 and TG3. If CK1 is connected to a low potential, then CKB1 is connected to a high potential; if CK1 is connected to a high potential, then CKB1 is connected to a low potential.

[0027] CK2, CKB2: Control signals that control the opening or closing of the transmission gate TG4. If CK2 is connected to a low potential, then CKB2 is connected to a high potential; if CK2 is connected to a high potential, then CKB2 is connected to a low potential.

[0028] CK3, CKB3: Control signals that control the opening or closing of the two transmission gates TG5, TG6. If CK3 is connected to a low potential, then CKB3 is connected to a high potential; if CK3 is connected to a high potential, then CKB3 is connected to a low potential.

[0029] Q and QB: Q is the output signal of the two-input NOR gate NOR1, the output signal of the dynamic latch circuit, and the output signal of the entire comparator. A high level indicates that the input signal Vin is greater than the reference signal Vref, and a low level indicates that the input signal Vin is less than the reference signal Vref. QB is the output signal of the two-input NOR gate NOR0, and its output result is the opposite of Q.

[0030] Both transmission gates TG0 and TG1 are controlled to open or close by CK0 and CKB0; both transmission gates TG2 and TG3 are controlled to open or close by CK1 and CKB1; the fifth transmission gate TG4 is controlled to open or close by CK2 and CKB2; both transmission gates TG5 and TG6 are controlled to open or close by CK3 and CKB3.

[0031] This low-power dynamic latch comparator completes the comparison between the input signal Vin and the reference signal Vref in the following five steps (initially, all 7 transmission gates are in the off state):

[0032] Step 1: Enable the switching control signals CK2 and CKB2 of the fifth transmission gate TG4, turn on the fifth transmission gate TG4, make the potentials at both ends of the amplifier circuit equal, and complete the preset setting of the amplifier circuit.

[0033] Step 2: Enable the switching control signals of the first transmission gate TG0 and the second transmission gate TG1, turn on the first transmission gate TG0 and the second transmission gate TG1, so that the input signal Vin and the reference signal Vref are sampled by the first sampling capacitor C0 and the second sampling capacitor C1 respectively, and then turn off the first transmission gate TG0 and the second transmission gate TG1 to keep the potential on the first sampling capacitor C0 and the second sampling capacitor C1 stable.

[0034] Step 3: Enable the switching control signals of the third transmission gate TG2 and the fourth transmission gate TG3, turn on the third transmission gate TG2 and the fourth transmission gate TG3, and simultaneously turn off the fifth transmission gate TG4. Transmit the input signal Vin and the reference signal Vref to the X port and Y port of the amplifier circuit, respectively. Then, the amplifier circuit amplifies the difference between the input signal Vin and the reference signal Vref. If the input signal Vin is greater than the reference signal Vref, the difference between the input signal Vin and the reference signal Vref is amplified to the power supply voltage at the X port of the amplifier circuit, while the Y port of the amplifier circuit becomes a low potential connected to the power supply ground. If the input signal Vin is less than the reference signal Vref, the difference between the reference signal Vref and the input signal Vin is amplified to the power supply voltage at the Y port of the amplifier circuit, while the X port of the amplifier circuit becomes a low potential connected to the power supply ground.

[0035] Step 4: Enable the switching control signals of the sixth transmission gate TG5 and the seventh transmission gate TG6, turn on the sixth transmission gate TG5 and the seventh transmission gate TG6, connect the X port of the amplifier circuit to one input of the two-input NOR gate NOR0 in the dynamic latch circuit, and connect the Y port of the amplifier circuit to one input of the two-input NOR gate NOR1 in the dynamic latch circuit. If the X port of the amplifier circuit is high and the Y port is low, then the output Q of the dynamic latch circuit is high and QB is low, which means that the input signal Vin is greater than the reference signal Vref; if the X port of the amplifier circuit is low and the Y port is high, then the output Q of the dynamic latch circuit is low and QB is high, which means that the input signal Vin is less than the reference signal Vref.

[0036] Step 5: Disconnect the sixth transmission gate TG5 and the seventh transmission gate TG6 to latch the comparison result in the dynamic latch circuit.

[0037] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A low-power dynamic latch comparator, characterized in that, include: Seven transmission gates, two inverters, two two-input NOR gates, a first sampling capacitor, and a second sampling capacitor; Two inverters connected end-to-end form an amplifier circuit. Two two-input NOR gates are connected to each other to form a dynamic latch circuit. Seven transmission gates are composed of the first transmission gate to the seventh transmission gate. The upper plate of the first sampling capacitor is connected to the first transmission gate and the third transmission gate respectively. The lower plate of the first sampling capacitor is connected to the power supply ground. The third transmission gate is also connected to the fifth transmission gate, the amplifier circuit, and the dynamic latch circuit in parallel. Then, the fourth transmission gate and the upper plate of the second sampling capacitor are connected in sequence. The upper plate of the second sampling capacitor is also connected to the second transmission gate. The sixth transmission gate is also connected between the third transmission gate and the dynamic latch circuit. The seventh transmission gate is also connected between the dynamic latch circuit and the fourth transmission gate. The lower plate of the second sampling capacitor is connected to the power supply ground. The first sampling capacitor and the second sampling capacitor respectively acquire the input signal and the reference signal through the first transmission gate and the second transmission gate. Then, the input signal and the reference signal are transmitted to both ends of the amplifier circuit for comparison. The amplifier circuit amplifies the comparison result and then latches the final result into the dynamic latch circuit.

2. The low-power dynamic latch comparator according to claim 1, characterized in that, Before acquiring the signal, the amplifier circuit is pre-set, including: enabling the switch control signal of the fifth transmission gate, opening the fifth transmission gate, and making the potentials at both ends of the amplifier circuit equal.

3. A low-power dynamic latch comparator according to claim 1, characterized in that, Before acquiring the signal, enable the switching control signals of the first transmission gate and the second transmission gate, open the first transmission gate and the second transmission gate, so that the input signal and the reference signal are sampled by the first sampling capacitor and the second sampling capacitor respectively, and then disconnect the first transmission gate and the second transmission gate to keep the potential on the first sampling capacitor and the second sampling capacitor stable.

4. A low-power dynamic latch comparator according to claim 1, characterized in that, The input signal and reference signal are transmitted to both ends of the amplifier circuit for comparison. The amplifier circuit amplifies the comparison result, including: Enable the switching control signals of the third and fourth transmission gates, open the third and fourth transmission gates, and simultaneously disconnect the fifth transmission gate. Transmit the input signal and the reference signal to the two ports of the amplifier circuit respectively. Then, the amplifier circuit amplifies the difference between the input signal and the reference signal. The port of the amplifier circuit connected to the third transmission gate is the X port, and the port connected to the fourth transmission gate is the Y port. If the input signal is greater than the reference signal, the difference is amplified to the power supply voltage at the X port of the amplifier circuit, while the Y port of the amplifier circuit becomes a low potential connected to the power supply ground; if the input signal is less than the reference signal, the difference is amplified to the power supply voltage at the Y port of the amplifier circuit, while the X port of the amplifier circuit becomes a low potential connected to the power supply ground.

5. A low-power dynamic latch comparator according to claim 4, characterized in that, The final result is latched into the dynamic latch circuit, including: Enable the switching control signals of the sixth and seventh transmission gates. After the sixth and seventh transmission gates are turned on, connect the X port of the amplifier circuit to one input of a two-input NOR gate, and connect the Y port of the amplifier circuit to one input of another two-input NOR gate. Then, the output potential of the two two-input NOR gates in the dynamic latch circuit can reflect the magnitude of the input signal and the reference signal. Finally, disconnecting the sixth and seventh transmission gates latches the final result into the dynamic latch circuit.

Images