Low-offset low-leakage sampling hold circuit and control method
By designing a low offset and low leakage current sample-and-hold circuit, and utilizing a common-mode voltage generation circuit and switching technology, the problems of low accuracy and severe leakage current in the sample-and-hold circuit were solved, achieving high-precision and long-term voltage information storage.
Patent Information
- Application Number
- CN202511009698.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-22
- Publication Date
- 2025-11-18
AI Technical Summary
Existing sample-and-hold circuits have low accuracy and serious leakage current, which affects system efficiency and the long-term storage of voltage information.
A low offset and low leakage current sample-and-hold circuit is designed, including a common-mode voltage generation circuit, a pre-sample-and-hold control circuit, and an output-stage sample-and-hold circuit. By generating a common-mode voltage with driving capability and combining it with switching technology, the offset voltage signal is canceled, thereby improving the accuracy of sampling information and reducing leakage current.
It improves the accuracy and retention time of sampling information, extends the retention time of voltage information, and reduces average power consumption.
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Figure CN120979412A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application relates to a low-offset low-leakage sampling and holding circuit and a control method, and belongs to the technical field of sampling integrated circuits. BACKGROUND
[0002] In an energy collection type power management chip, a self-powered system is generally used, and the entire system is powered by the energy itself without an external power supply. In order to reduce the average power consumption of the system and enable the system to normally operate, the internal power consumption modules of the system need to be periodically turned off, and the key node information of the modules is stored by using a sampling and holding circuit, so that the entire system can normally operate. However, the precision of the commonly used sampling and holding circuit is low, which affects the working efficiency of the system, and because of the leakage of the sampling and holding circuit switch and the storage capacitor itself, the voltage information cannot be stored for a long time, so the working efficiency of the existing sampling and holding circuit is low. SUMMARY
[0003] The application solves the technical problem of providing a low-offset low-leakage sampling and holding circuit, which simultaneously samples input voltage information and offset voltage information, and offsets the offset voltage in the pre-holding stage to improve the precision of the sampling information.
[0004] The application adopts the following technical scheme to solve the above technical problem: the application designs a low-offset low-leakage sampling and holding circuit, which comprises a common-mode voltage generation circuit and a pre-sampling and holding control circuit, wherein the common-mode voltage generation circuit is used to generate a common-mode voltage VCM with driving capability and output the common-mode voltage VCM to the pre-sampling and holding control circuit; the pre-sampling and holding control circuit is used to combine the common-mode voltage VCM and perform sampling and holding on the input voltage VIN received by the pre-sampling and holding control circuit, and output voltage information VOUT.
[0005] As a preferred technical scheme of the application, the low-offset low-leakage sampling and holding circuit further comprises an output stage sampling and holding circuit, which is used to receive the voltage information VOUT output by the pre-sampling and holding control circuit, perform a signal processing operation meeting the long-time storage requirement of the signal, realize final sampling and holding, and output target voltage information VSAMPLE.
[0006] As a preferred technical scheme of the present application: the common-mode voltage generating circuit comprises an operational amplifier AMP1, a resistor R1, a resistor R2 and a capacitor C1, wherein the inverting input terminal of the operational amplifier AMP1 is used for connecting a reference voltage Vref, the non-inverting input terminal of the operational amplifier AMP1, one end of the resistor R1 and one end of the resistor R2 are connected together, the output terminal of the operational amplifier AMP1, the other end of the resistor R1 and the upper plate of the capacitor C1 are connected together and constitute the output terminal of the common-mode voltage generating circuit for outputting a common-mode voltage VCM; the other end of the resistor R2 and the lower plate of the capacitor C1 are grounded; the high-level terminal of the operational amplifier AMP1 is connected to a power supply VDD, and the low-level terminal of the operational amplifier AMP1 is grounded VSS.
[0007] As a preferred technical scheme of the present application: the pre-sampling holding control circuit comprises a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a switch S1, a switch S2, a switch S3, a switch S4 and an operational amplifier AMP2, wherein the upper plate of the capacitor C2 is connected to the input terminal of the switch S1 and constitutes the input terminal of the pre-sampling holding control circuit for receiving an input voltage VIN, and the lower plate of the capacitor C2 is grounded VSS; the output terminal of the switch S1, the upper plate of the capacitor C3 and the input terminal of the switch S4 are connected together; the lower plate of the capacitor C3, the output terminal of the switch S2 and the upper plate of the capacitor C4 are connected together, the lower plate of the capacitor C4, the inverting input terminal of the operational amplifier AMP2 and the input terminal of the switch S3 are connected together; the input terminal of the switch S2 is connected to the non-inverting input terminal of the operational amplifier AMP2 and constitutes the driving input terminal of the pre-sampling holding control circuit for receiving the common-mode voltage VCM output from the common-mode voltage generating circuit; the output terminal of the switch S4, the output terminal of the switch S3, the output terminal of the operational amplifier AMP2 and the upper plate of the capacitor C5 are connected together and constitute the output terminal of the pre-sampling holding control circuit for outputting a voltage information VOUT, and the lower plate of the capacitor C5 is grounded VSS; the high-level terminal of the operational amplifier AMP2 is connected to the power supply VDD, and the low-level terminal of the operational amplifier AMP2 is grounded VSS; the size of the capacitor C3 is equal to the size of the capacitor C4, the control terminal of the switch S1, the control terminal of the switch S2 and the control terminal of the switch S3 are connected to a control signal ctrl1 respectively, the control terminal of the switch S4 is connected to a control signal ctrl2, and the control signal ctrl1 and the control signal ctrl2 are mutually inverted.
[0008] As a preferred technical scheme of the present application: the output stage sample and hold circuit comprises NMOS tube M1, NMOS tube M2, NMOS tube M3, PMOS tube M4, PMOS tube M5, PMOS tube M6, NMOS tube M7, NMOS tube M8, capacitor C6, wherein the source of the NMOS tube M1 constitutes the input end of the output stage sample and hold circuit for receiving the voltage information VOUT output by the pre-sampling and holding control circuit; the gate of the NMOS tube M1 is connected with the gate of the NMOS tube M2, and the connected position is connected with the control signal ctrl3; the drain of the NMOS tube M1, the source of the NMOS tube M2 and the source of the NMOS tube M3 are connected; the gate of the NMOS tube M3 is connected with the control signal ctrl4; the drain of the NMOS tube M3, the gate of the PMOS tube M6, the drain of the PMOS tube M6 and the drain of the NMOS tube M8 are connected; the source of the PMOS tube M4 is connected with the power supply VDD, the gate of the PMOS tube M4 is connected with the bias voltage vb, the drain of the PMOS tube M4, the source of the PMOS tube M5 and the source of the PMOS tube M6 are connected; the drain of the PMOS tube M5, the drain of the NMOS tube M7, the gate of the NMOS tube M7 and the gate of the NMOS tube M8 are connected; the drain of the NMOS tube M2, the gate of the PMOS tube M5 and the upper plate of the capacitor C6 are connected and constitute the output end of the output stage sample and hold circuit for outputting the target voltage information VSAMPLE; the lower plate of the capacitor C6, the source of the NMOS tube M7 and the source of the NMOS tube M8 are connected and grounded VSS.
[0009] As a preferred technical scheme of the present application: the switch S1, the switch S2, the switch S3 and the switch S4 are the same switch structure, and the switch structure comprises PMOS tube M9, PMOS tube M10, PMOS tube M11, NMOS tube M12, NMOS tube M13, NMOS tube M14 and inverter U1, wherein the drain of the PMOS tube M9, the source of the PMOS tube M9, the drain of the PMOS tube M10, the source of the NMOS tube M12, the drain of the NMOS tube M12, the source of the NMOS tube M13 are connected and constitute the input end of the switch structure; the source of the PMOS tube M11, the drain of the PMOS tube M11, the source of the PMOS tube M10, the drain of the NMOS tube M14, the source of the NMOS tube M14 and the drain of the NMOS tube M13 are connected and constitute the output end of the switch structure; the input end of the inverter U1, the gate of the PMOS tube M9, the gate of the PMOS tube M11 and the gate of the NMOS tube M13 are connected and constitute the control end of the switch structure for receiving the clock control signal; the output end of the inverter U1, the gate of the PMOS tube M10, the gate of the NMOS tube M12 and the gate of the NMOS tube M14 are connected.
[0010] As a preferred technical solution of the present application: the operational amplifier AMP1 and the operational amplifier AMP2 are the same operational amplifier structure, the operational amplifier structure includes PMOS tube M15, PMOS tube M16, PMOS tube M17, PMOS tube M18, PMOS tube M19, PMOS tube M20, PMOS tube M21, NMOS tube M22, NMOS tube M23, NMOS tube M24, NMOS tube M25, wherein the gate of PMOS tube M15 is connected with bias voltage VP, the source of PMOS tube M15, the source of PMOS tube M18 and the source of PMOS tube M19 are connected, and the high level end of the operational amplifier structure is connected with power supply VDD; the drain of PMOS tube M15, the source of PMOS tube M16 and the source of PMOS tube M17 are connected; the gate of PMOS tube M16 is the positive input end of the operational amplifier structure, and the gate of PMOS tube M17 is the negative input end of the operational amplifier structure; the drain of PMOS tube M16, the drain of NMOS tube M24 and the source of NMOS tube M22 are connected; the drain of PMOS tube M17, the drain of NMOS tube M25 and the source of NMOS tube M23 are connected; the gate of PMOS tube M18, the gate of PMOS tube M19, the drain of PMOS tube M20 and the drain of NMOS tube M22 are connected; the drain of PMOS tube M18 is connected with the source of PMOS tube M20; the drain of PMOS tube M19 is connected with the source of PMOS tube M21; the gate of PMOS tube M20 is connected with the gate of PMOS tube M21, and is connected with bias voltage vb1; the drain of PMOS tube M21 is connected with the drain of NMOS tube M23, and is the output end of the operational amplifier structure; the gate of NMOS tube M22 is connected with the gate of NMOS tube M23, and is connected with bias voltage vb2; the gate of NMOS tube M24 is connected with the gate of NMOS tube M25, and is connected with bias voltage vb3; the source of NMOS tube M24 is connected with the source of NMOS tube M25, and is the low level end of the operational amplifier structure.
[0011] Corresponding to the above, the present application also solves the technical problem of providing a control method of a low-offset low-leakage sample-and-hold circuit, which performs a pre-sampling stage and a pre-holding stage through switching, reduces the working offset of the circuit, prolongs the saving time of input voltage information, and improves the precision of sampling information.
[0012] The present application adopts the following technical solution to solve the above technical problems: the present application designs a control method of a low-offset low-leakage sample-and-hold circuit, including a pre-sampling holding control circuit control method as follows:
[0013] Firstly, the switch S1, the switch S2 and the switch S3 connected to the control signal ctrl1 are all closed, and the switch S4 connected to the control signal ctrl2 is opened, the pre-sampling holding control circuit executes the pre-sampling stage, the input voltage information in the input voltage VIN is collected on the capacitor C3, the offset voltage information is collected on the capacitor C4, and the offset voltage information is equivalent to the voltage source V os to the positive input end of the operational amplifier AMP2, then the voltage information VOUT is as follows:
[0014]
[0015] Wherein, A represents the open loop gain of the operational amplifier AMP2;
[0016] Then, the switch S1, the switch S2 and the switch S3 connected to the control signal ctrl1 are all opened, and the switch S4 connected to the control signal ctrl2 is closed, the pre-sampling holding control circuit executes the pre-holding stage, then the voltage information VOUT is as follows:
[0017]
[0018] Compared with the prior art, the low-offset low-leakage sampling holding circuit and the control method have the following technical effects:
[0019] The low-offset low-leakage sampling holding circuit and the control method are designed, which comprises a common-mode voltage generating circuit, a pre-sampling holding control circuit and an output stage sampling holding circuit. Firstly, the common-mode voltage generating circuit generates the common-mode voltage VCM with driving capability for the pre-sampling holding control circuit. Then, the pre-sampling holding control circuit combines the common-mode voltage VCM, samples the input voltage information and the offset voltage information for the input voltage VIN, and offsets the offset voltage in the pre-holding stage, so as to improve the precision of the sampling information and output the voltage information VOUT. Finally, the output stage sampling holding circuit processes the voltage information VOUT and outputs the target voltage information VSAMPLE meeting the long-time storage requirement of the signal. The pre-sampling holding control circuit is designed, the switches are reasonably switched to reduce the offset, the voltage difference between the switches in the output stage sampling holding circuit is reduced, and then the leakage is reduced, so that the storage time of the input voltage information is prolonged. BRIEF DESCRIPTION OF DRAWINGS
[0020] Figure 1 is the schematic diagram of the low-offset low-leakage sampling holding circuit designed by the application;
[0021] Figure 2 is the schematic diagram of the switch structure in the low-offset low-leakage sampling holding circuit designed by the application;
[0022] Figure 3This is a schematic diagram of the operational amplifier structure in the low offset and low leakage current sample-and-hold circuit designed in this invention;
[0023] Figure 4 This is a schematic diagram of the pre-sampling stage of the low offset and low leakage current sample-and-hold circuit control method designed in this invention;
[0024] Figure 5 This is a schematic diagram of the pre-hold stage of the low offset and low leakage current sampling and holding circuit control method designed in this invention. Detailed Implementation
[0025] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.
[0026] This invention designs a low offset, low leakage current sample-and-hold circuit, such as... Figure 1 As shown, it specifically includes a common-mode voltage generation circuit, a pre-sample and hold control circuit, and an output-stage sample and hold circuit. The common-mode voltage generation circuit generates a common-mode voltage VCM with driving capability and outputs it to the pre-sample and hold control circuit. The pre-sample and hold control circuit combines the common-mode voltage VCM with the received input voltage VIN to perform sampling and holding, and outputs voltage information VOUT. The output-stage sample and hold circuit receives the voltage information VOUT output by the pre-sample and hold control circuit, performs signal processing operations that meet the requirements for long-term signal storage, achieves final sampling and holding, and outputs target voltage information VSAMPLE.
[0027] In practical applications, specific designs are carried out for each of the above circuits, such as... Figure 1 As shown, the common-mode voltage generation circuit includes an operational amplifier AMP1, resistors R1 and R2, and a capacitor C1. The inverting input of operational amplifier AMP1 is connected to the reference voltage Vref. The non-inverting input of operational amplifier AMP1, one end of voltage R1, and one end of voltage R2 are connected together. The output of operational amplifier AMP1, the other end of resistor R1, and the upper plate of capacitor C1 are connected together, forming the output of the common-mode voltage generation circuit, which is used to output the common-mode voltage VCM. The other end of resistor R2 and the lower plate of capacitor C1 are both grounded. The high-level terminal of operational amplifier AMP1 is connected to the power supply VDD, and the low-level terminal of operational amplifier AMP1 is grounded to VSS.
[0028] For presample and hold control circuits, in practical applications, such as Figure 1As shown, the specific design includes capacitor C2, capacitor C3, capacitor C4, capacitor C5, switch S1, switch S2, switch S3, switch S4, operational amplifier AMP2, wherein the upper plate of capacitor C2 is connected with the input end of switch S1 and constitutes the input end of the pre-sampling and holding control circuit for receiving input voltage VIN, the lower plate of capacitor C2 is grounded VSS; the output end of switch S1, the upper plate of capacitor C3 and the input end of switch S4 are connected; the lower plate of capacitor C3, the output end of switch S2 and the upper plate of capacitor C4 are connected, the lower plate of capacitor C4, the reverse input end of operational amplifier AMP2 and the input end of switch S3 are connected; the input end of switch S2 is connected with the forward input end of operational amplifier AMP2 and constitutes the driving input end of the pre-sampling and holding control circuit for receiving common-mode voltage VCM output from the common-mode voltage generating circuit; the output end of switch S4, the output end of switch S3, the output end of operational amplifier AMP2 and the upper plate of capacitor C5 are connected and constitute the output end of the pre-sampling and holding control circuit for outputting voltage information VOUT, the lower plate of capacitor C5 is grounded VSS; the high level end of operational amplifier AMP2 is connected with power supply VDD, the low level end of operational amplifier AMP2 is grounded VSS; the size of capacitor C3 is equal to the size of capacitor C4, the control end of switch S1, the control end of switch S2 and the control end of switch S3 are respectively connected with control signal ctrl1, the control end of switch S4 is connected with control signal ctrl2, control signal ctrl1 and control signal ctrl2 are mutually inverse.
[0029] As to the output stage sampling and holding circuit, in practical application, for example, Figure 1As shown, the specific design includes NMOS transistor M1, NMOS transistor M2, NMOS transistor M3, PMOS transistor M4, PMOS transistor M5, PMOS transistor M6, NMOS transistor M7, NMOS transistor M8, and capacitor C6, wherein the source of the NMOS transistor M1 constitutes an input end of an output stage sample and hold circuit, for receiving voltage information VOUT output by a pre-sample and hold control circuit; the gate of the NMOS transistor M1 is connected with the gate of the NMOS transistor M2, and the connection position is connected with a control signal ctrl3; the drain of the NMOS transistor M1, the source of the NMOS transistor M2, and the source of the NMOS transistor M3 are connected; the gate of the NMOS transistor M3 is connected with a control signal ctrl4; the drain of the NMOS transistor M3, the gate of the PMOS transistor M6, the drain of the PMOS transistor M6, and the drain of the NMOS transistor M8 are connected; the source of the PMOS transistor M4 is connected with a power supply VDD, the gate of the PMOS transistor M4 is connected with a bias voltage vb, and the drain of the PMOS transistor M4, the source of the PMOS transistor M5, and the source of the PMOS transistor M6 are connected; the drain of the PMOS transistor M5, the drain of the NMOS transistor M7, the gate of the NMOS transistor M7, and the gate of the NMOS transistor M8 are connected; the drain of the NMOS transistor M2, the gate of the PMOS transistor M5, and the upper plate of the capacitor C6 are connected, and constitute an output end of the output stage sample and hold circuit for outputting target voltage information VSAMPLE; the lower plate of the capacitor C6, the source of the NMOS transistor M7, and the source of the NMOS transistor M8 are connected, and grounded to VSS.
[0030] The common mode voltage generation circuit, the pre-sample and hold control circuit, and the output stage sample and hold circuit are combined to build a low-offset low-leakage sample and hold circuit, which is applied in practice, and for the switches S1, S2, S3, and S4, the same switch structure is designed, such as Figure 2As shown, the switch structure includes PMOS M9, PMOS M10, PMOS M11, NMOS M12, NMOS M13, NMOS M14, and inverter U1, wherein the drain of PMOS M9, the source of PMOS M9, the drain of PMOS M10, the source of NMOS M12, the drain of NMOS M12, and the source of NMOS M13 are connected together and constitute an input terminal of the switch structure; the source of PMOS M11, the drain of PMOS M11, the source of PMOS M10, the drain of NMOS M14, the source of NMOS M14, and the drain of NMOS M13 are connected together and constitute an output terminal of the switch structure; the input terminal of inverter U1, the gate of PMOS M9, the gate of PMOS M11, and the gate of NMOS M13 are connected together and constitute a control terminal of the switch structure for receiving a clock control signal; and the output terminal of inverter U1, the gate of PMOS M10, the gate of NMOS M12, and the gate of NMOS M14 are connected together.
[0031] And the operational amplifier AMP1 and the operational amplifier AMP2 involved in the common-mode voltage generation circuit and the pre-sampling holding control circuit respectively are specifically designed, and the same operational amplifier structure is adopted, such as Figure 3As shown, the specific design of the operational amplifier structure includes PMOS tube M15, PMOS tube M16, PMOS tube M17, PMOS tube M18, PMOS tube M19, PMOS tube M20, PMOS tube M21, NMOS tube M22, NMOS tube M23, NMOS tube M24, and NMOS tube M25. The gate of PMOS tube M15 is connected to bias voltage VP, the source of PMOS tube M15, the source of PMOS tube M18, and the source of PMOS tube M19 are connected together to form a high-level terminal of the operational amplifier structure connected to power supply VDD. The drain of PMOS tube M15, the source of PMOS tube M16, and the source of PMOS tube M17 are connected together. The gate of PMOS tube M16 forms a positive input terminal of the operational amplifier structure, and the gate of PMOS tube M17 forms a negative input terminal of the operational amplifier structure. The drain of PMOS tube M16, the drain of NMOS tube M24, and the source of NMOS tube M22 are connected together. The drain of PMOS tube M17, the drain of NMOS tube M25, and the source of NMOS tube M23 are connected together. The gate of PMOS tube M18, the gate of PMOS tube M19, the drain of PMOS tube M20, and the drain of NMOS tube M22 are connected together. The drain of PMOS tube M18 is connected to the source of PMOS tube M20. The drain of PMOS tube M19 is connected to the source of PMOS tube M21. The gate of PMOS tube M20 is connected to the gate of PMOS tube M21, and is connected to bias voltage vb1. The drain of PMOS tube M21 is connected to the drain of NMOS tube M23, and forms an output terminal of the operational amplifier structure. The gate of NMOS tube M22 is connected to the gate of NMOS tube M23, and is connected to bias voltage vb2. The gate of NMOS tube M24 is connected to the gate of NMOS tube M25, and is connected to bias voltage vb3. The source of NMOS tube M24 is connected to the source of NMOS tube M25, and forms a low-level terminal connected to ground VSS.
[0032] In actual application, the common-mode voltage generating circuit applies the operational amplifier AMP1 to amplify the reference voltage Vref to half of the power supply voltage. Since the common-mode voltage VCM is not an ideal voltage source, charges will be coupled to the capacitor C1 when the signal is switched. By increasing C1, the transient voltage variation of the common-mode voltage VCM can be reduced. In addition, the design of equal size of capacitor C3 and capacitor C4 makes the larger the capacitance of capacitor C3 and capacitor C4, the smaller the error introduced by parasitic effects and low-frequency noise, and the more accurate the sampled voltage information.
[0033] Then, for the actual application of the low-offset and low-leakage sampling and holding circuit, a corresponding control method is designed. First, the control signal ctrl1 controls the switches S1, S2, and S3 connected thereto to be closed, and the control signal ctrl2 controls the switch S4 connected thereto to be open. The pre-sampling and holding control circuit performs a pre-sampling stage, as shown in FIG. 6.Figure 4 As shown, the input voltage information in the input voltage VIN is collected on the capacitor C3, the offset voltage information is collected on the capacitor C4, and the offset voltage information is converted into an equivalent voltage source V os to the positive input terminal of the operational amplifier AMP2, then the voltage information VOUT is as follows:
[0034]
[0035] wherein A represents the open-loop gain of the operational amplifier AMP2.
[0036] The switch S1, the switch S2 and the switch S3 connected to the pre-sampling holding control circuit are all opened by the control signal ctrl1, and the switch S4 connected to the pre-sampling holding control circuit is closed by the control signal ctrl2, so that the pre-sampling holding control circuit performs a pre-holding stage, as shown in FIG. 4. Figure 5 As shown, the voltage information VOUT is as follows:
[0037]
[0038] Further, the design of the output stage sampling holding circuit reduces the leakage current by clamping the voltage of the key node, prolongs the holding time of the voltage information, reduces the switching frequency of the whole sampling holding circuit, and greatly reduces the average power consumption.
[0039] In actual application, the leakage of the pre-sampling holding control circuit is mainly through the junction formed by the drain, the substrate and the source of the switch tube, and is proportional to the voltage difference between the junctions. The output stage sampling holding circuit realizes low leakage and long time holding of the signal by maintaining the small voltage difference between the drain and the source of the NMOS tube M1 and the drain and the substrate of the NMOS tube M2. The voltage difference between the drain and the source or the substrate of the NMOS tube M1 and the NMOS tube M2 is the input offset voltage of the five-tube operational amplifier composed of the PMOS tube M4, the PMOS tube M5, the PMOS tube M6, the NMOS tube M7 and the NMOS tube M8, which effectively reduces the leakage current. The tail current source M4 of the five-tube operational amplifier can control the consumption current at the level of nano-ampere, and has basically no static power consumption.
[0040] The low-offset low-leakage sampling and holding circuit and control method designed by the application comprises a common-mode voltage generating circuit, a pre-sampling and holding control circuit and an output stage sampling and holding circuit. The common-mode voltage generating circuit generates a common-mode voltage VCM with driving capability for the pre-sampling and holding control circuit. Then, the pre-sampling and holding control circuit combines the common-mode voltage VCM to sample input voltage information and offset voltage information for the input voltage VIN, and offsets the offset voltage signal in the pre-holding stage to improve the precision of the sampling information and output the voltage information VOUT. Finally, the output stage sampling and holding circuit processes the voltage information VOUT to output the target voltage information VSAMPLE that meets the long-time storage requirement of the signal. The application designs the pre-sampling and holding control circuit, reasonably switches the switches to reduce the offset, reduces the voltage difference between the stages of the switch tubes in the output stage sampling and holding circuit, further reduces the leakage, prolongs the storage time of the input voltage information, and compared with the common structure, the offset can be reduced to one sixth of the original, and more than 90% of the voltage information can be maintained within 8s of holding time.
[0041] The embodiments of the application are described in detail above with reference to the drawings, but the application is not limited to the above-described embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the purpose of the application.
Claims
1. A low offset, low leakage current sample-and-hold circuit, characterized in that: It includes a common-mode voltage generation circuit and a pre-sample and hold control circuit. The common-mode voltage generation circuit generates a common-mode voltage VCM with driving capability and outputs it to the pre-sample and hold control circuit. The pre-sample and hold control circuit combines the common-mode voltage VCM with the received input voltage VIN to perform sampling and holding, and outputs voltage information VOUT.
2. The low offset, low leakage current sample-and-hold circuit according to claim 1, characterized in that: It also includes an output stage sample-and-hold circuit, which receives the voltage information VOUT output by the pre-sample-and-hold control circuit, performs signal processing operations that meet the requirements for long-term signal storage, achieves final sampling and holding, and outputs the target voltage information VSAMPLE.
3. The low offset, low leakage current sample-and-hold circuit according to claim 1, characterized in that: The common-mode voltage generation circuit includes an operational amplifier AMP1, resistors R1 and R2, and a capacitor C1. The inverting input of operational amplifier AMP1 is connected to a reference voltage Vref. The non-inverting input of operational amplifier AMP1, one end of voltage R1, and one end of voltage R2 are connected together. The output of operational amplifier AMP1, the other end of resistor R1, and the upper plate of capacitor C1 are connected together to form the output of the common-mode voltage generation circuit, which is used to output the common-mode voltage VCM. The other end of resistor R2 and the lower plate of capacitor C1 are both grounded. The high-level terminal of operational amplifier AMP1 is connected to the power supply VDD, and the low-level terminal of operational amplifier AMP1 is grounded to VSS.
4. The low offset and low leakage current sample-and-hold circuit according to claim 3, characterized in that: The pre-sample and hold control circuit includes capacitors C2, C3, C4, and C5, switches S1, S2, S3, and S4, and operational amplifier AMP2. The upper plate of capacitor C2 is connected to the input terminal of switch S1, forming the input terminal of the pre-sample and hold control circuit for receiving the input voltage VIN. The lower plate of capacitor C2 is grounded to VSS. The output terminal of switch S1, the upper plate of capacitor C3, and the input terminal of switch S4 are connected. The lower plate of capacitor C3, the output terminal of switch S2, and the upper plate of capacitor C4 are connected. The lower plate of capacitor C4, the inverting input terminal of operational amplifier AMP2, and the input terminal of switch S3 are connected. The input terminal of switch S2 is connected to the non-inverting input terminal of operational amplifier AMP2, forming the pre-sample and hold control circuit. The drive input terminal of the control circuit is used to receive the common-mode voltage VCM output from the common-mode voltage generation circuit; the output terminals of switch S4, switch S3, operational amplifier AMP2, and the upper plate of capacitor C5 are connected to form the output terminal of the pre-sample and hold control circuit, which is used to output voltage information VOUT, and the lower plate of capacitor C5 is grounded to VSS; the high-level terminal of operational amplifier AMP2 is connected to the power supply VDD, and the low-level terminal of operational amplifier AMP2 is grounded to VSS; the size of capacitor C3 is equal to that of capacitor C4; the control terminals of switch S1, switch S2, and switch S3 are all connected to control signal ctrl1, and the control terminal of switch S4 is connected to control signal ctrl2. Control signals ctrl1 and ctrl2 are inverses of each other.
5. The low offset, low leakage current sample-and-hold circuit according to claim 2, characterized in that: The output stage sample-and-hold circuit includes NMOS transistors M1, M2, M3, M4, M5, M6, M7, and M8, and capacitor C6. The source of NMOS transistor M1 forms the input terminal of the output stage sample-and-hold circuit, used to receive the voltage information VOUT output by the pre-sample-and-hold control circuit. The gate of NMOS transistor M1 is connected to the gate of NMOS transistor M2, and the connection point is connected to the control signal ctrl3. The drain of NMOS transistor M1, the source of NMOS transistor M2, and the source of NMOS transistor M3 are connected together. The gate of NMOS transistor M3 is connected to the control signal ctrl4. The drain of NMOS transistor M3, the gate of PMOS transistor M6, and P... The drains of MOSFET M6 and NMOS transistor M8 are connected together; the source of PMOS transistor M4 is connected to the power supply VDD, the gate of PMOS transistor M4 is connected to the bias voltage vb, and the drains of PMOS transistor M4, the source of PMOS transistor M5, and the source of PMOS transistor M6 are connected together; the drains of PMOS transistor M5, the drains of NMOS transistor M7, the gate of NMOS transistor M7, and the gate of NMOS transistor M8 are connected together; the drain of NMOS transistor M2, the gate of PMOS transistor M5, and the upper plate of capacitor C6 are connected together, forming the output terminal of the output stage sample-and-hold circuit used to output the target voltage information VSAMPLE; the lower plate of capacitor C6, the source of NMOS transistor M7, and the source of NMOS transistor M8 are connected together and grounded to VSS.
6. The low offset, low leakage current sample-and-hold circuit according to claim 4, characterized in that: Switches S1, S2, S3, and S4 are identical switching structures, each including a PMOS transistor M9, PMOS transistor M10, PMOS transistor M11, NMOS transistor M12, NMOS transistor M13, NMOS transistor M14, and an inverter U1. The drain and source of PMOS transistor M9, the drain of PMOS transistor M10, the source and drain of NMOS transistor M12, and the source of NMOS transistor M13 are connected together to form the input terminal of the switching structure. The source of PMOS transistor M11... The drain of PMOS transistor M11, the source of PMOS transistor M10, the drain of NMOS transistor M14, the source of NMOS transistor M14, and the drain of NMOS transistor M13 are connected together to form the output terminal of the switch structure; the input terminal of inverter U1, the gate of PMOS transistor M9, the gate of PMOS transistor M11, and the gate of NMOS transistor M13 are connected together to form the control terminal of the switch structure for receiving clock control signals; the output terminal of inverter U1, the gate of PMOS transistor M10, the gate of NMOS transistor M12, and the gate of NMOS transistor M14 are connected together.
7. The low offset, low leakage current sample-and-hold circuit according to claim 4, characterized in that: The operational amplifiers AMP1 and AMP2 are identical operational amplifier structures, including PMOS transistors M15, M16, M17, M18, M19, M20, M21, NMOS transistors M22, M23, M24, and M25. The gate of PMOS transistor M15 is connected to the bias voltage VP. The source and PMOS transistor of PMOS transistor M15 are connected to the bias voltage VP. The sources of transistors M18 and M19 are connected together to form the high-level terminal of the operational amplifier structure, which is connected to the power supply VDD. The drains of PMOS transistors M15, M16, and M17 are connected together. The gate of PMOS transistor M16 forms the positive input terminal of the operational amplifier structure, and the gate of PMOS transistor M17 forms the inverting input terminal. The drains of PMOS transistor M16, M24, and M22 are connected together. Connect the drain of PMOS transistor M17, the drain of NMOS transistor M25, and the source of NMOS transistor M23; connect the gate of PMOS transistor M18, the gate of PMOS transistor M19, the drain of PMOS transistor M20, and the drain of NMOS transistor M22; connect the drain of PMOS transistor M18 to the source of PMOS transistor M20; connect the drain of PMOS transistor M19 to the source of PMOS transistor M21; connect the gate of PMOS transistor M20 to the source of PMOS transistor M21. The gates of the PMOS transistor M21 and NMOS transistor M23 are connected and biased by voltage vb1; the drain of the PMOS transistor M21 is connected to the drain of the NMOS transistor M23, forming the output terminal of the operational amplifier structure; the gates of the NMOS transistor M22 and NMOS transistor M23 are connected and biased by voltage vb2; the gates of the NMOS transistor M24 and NMOS transistor M25 are connected and biased by voltage vb3; the source of the NMOS transistor M24 and the source of the NMOS transistor M25 are connected, forming the low-level terminal VSS of the operational amplifier structure.
8. The control method for the low offset and low leakage current sample-and-hold circuit as described in claim 4, characterized in that, The control method, including the pre-sample and hold control circuit, is as follows: First, control signal ctrl1 closes all connected switches S1, S2, and S3, while control signal ctrl2 opens connected switch S4. The pre-sampling and holding control circuit then performs a pre-sampling phase, acquiring input voltage information from input voltage VIN onto capacitor C3 and offset voltage information onto capacitor C4. The offset voltage information is then converted to an equivalent voltage source V. os When connected to the positive input terminal of op-amp AMP2, the voltage information VOUT is as follows: Where A represents the open-loop gain of op-amp AMP2; Then, control signal ctrl1 controls the connected switches S1, S2, and S3 to open, and control signal ctrl2 controls the connected switch S4 to close. The pre-sampling and holding control circuit executes the pre-holding phase, and the voltage information VOUT is as follows: