Microstructure conflict-oriented instruction generation method and device and instruction generator

Abstract

The invention provides a microstructure conflict-oriented instruction generation method and device and an instruction generator. Hardware resources of a processor are abstracted into an accessible or occupied model, instruction description information is taken as a unit, each instruction in a target instruction set is converted into structural data, and an instruction description table is generated; then, based on a conflict constraint condition input by a user, screening from the instruction description table to obtain a conflict instruction set, constructing a conflict instruction pair from the conflict instruction set in a pairwise combination mode, traversing a target instruction sequence, and placing the constructed conflict instruction pair in the target instruction sequence to obtain a conflict instruction set; and finally, filling the positions of the conflict-free instruction pairs with conflict-free instructions to obtain a final complete target instruction sequence. According to the method, the conflict constraint condition can be preset according to the user demand, the controllability and the fine granularity of generating the conflict instruction are enhanced, and the technical advantages of improving the generation efficiency of the instruction sequence and improving the universality and the expandability of the instruction generation device are further achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of processor verification and performance analysis, and more particularly, to a microstructure conflict-oriented instruction generation method and device and an instruction generator. BACKGROUND

[0002] In the process of processor architecture design, verification and performance evaluation, an instruction generator is an important tool, which can automatically construct various instruction sequences, run on a processor simulation model or hardware platform, and detect the behavior characteristics of the processor in terms of functional correctness, exception handling, performance bottlenecks, etc.

[0003] Existing general-purpose instruction generators, such as RISCV-DV, FORCE-RISCV, etc., are based on random instruction stream generation tools, which usually focus on covering the diversity of instruction sets to trigger different functional modules and execution paths as much as possible. However, such general-purpose generators have certain limitations in constructing specific processor microstructure-related conflict scenarios. SUMMARY

[0004] The present application aims to provide a microstructure conflict-oriented instruction generation method, device and instruction generator, which solves the technical problems of poor controllability, insufficient accuracy, low generation efficiency and poor adaptability of existing instruction generators in generating specific types of microstructure conflict scenarios.

[0005] The present application is implemented by adopting the following technical solutions: A microstructure conflict-oriented instruction generation method is proposed, comprising: S1, establishing an abstract model of processor hardware resources; S2, generating an instruction description table for each instruction in the target instruction set; S3, selecting a conflict instruction set from the instruction description table based on conflict constraint conditions; S4, constructing conflict instruction pairs in a two-by-two combination manner from the conflict instruction set, and placing conflict instruction pairs in the target instruction sequence; S5, filling non-conflict instructions in the non-conflict instruction pair placement position of the target instruction sequence; S6, outputting the complete target instruction sequence and verifying.

[0006] In some embodiments of the present application, when modeling processor hardware resources, S1 further comprises: Each type of hardware resource is abstracted as a resource unit that can be accessed or occupied, and the constraint relationship between each type of hardware resource is defined.

[0007] In some embodiments of the present application, S2 specifically comprises: analyze each instruction in the target instruction set to generate a plurality of instruction description information; the instruction description information comprises instruction operation code and format information, hardware resource type and quantity required by the instruction, timing characteristics of the instruction, and data dependency of the instruction; organize each instruction into an instruction description table based on the instruction description information.

[0008] In some embodiments of the application, S3 specifically comprises: receive a conflict constraint condition input by a user; wherein the conflict constraint condition at least comprises a conflict type, a conflict strength, a conflict frequency, and an instruction sequence length; select an instruction from the instruction description table according to the conflict type.

[0009] In some embodiments of the application, in S5, the non-conflict instruction is set to: not occupy the same hardware resource as the target conflict, not introduce a new data dependency relationship, and maintain the overall executability and legality of the target instruction sequence.

[0010] An instruction generation device for microstructure conflicts is proposed, comprising: a hardware resource modeling module for establishing an abstract model of processor hardware resources; an instruction modeling module for generating an instruction description table for each instruction in the target instruction set; a conflict selection module for selecting a conflict instruction set based on conflict constraints; an instruction sequence generation module for constructing a conflict instruction pair in a two-by-two combination manner from the conflict instruction set, and placing the conflict instruction pair in the target instruction sequence; and filling non-conflict instructions in the non-conflict instruction pair placement position of the target instruction sequence; an output module for outputting a complete target instruction sequence and verifying.

[0011] In some embodiments of the application, when modeling the hardware resources of the processor, the hardware resource modeling module abstracts each type of hardware resource into a resource unit that can be accessed or occupied, and defines the constraint relationship between each type of hardware resource.

[0012] In some embodiments of the application, the instruction modeling module comprises: an analysis unit for analyzing each instruction in the target instruction set to generate a plurality of instruction description information; the instruction description information comprises instruction operation code and format information, hardware resource type and quantity required by the instruction, timing characteristics of the instruction, and data dependency of the instruction; a modeling unit for organizing each instruction into an instruction description table based on the instruction description information.

[0013] In some embodiments of the application, the device further comprises: An input module is configured to receive a conflict constraint input by a user, wherein the conflict constraint comprises at least a conflict type, a conflict intensity, a conflict frequency, and an instruction sequence length. The conflict selection module selects instructions from the instruction description table according to the conflict type.

[0014] The application provides an instruction generator comprising the microstructure conflict-oriented instruction generation device.

[0015] Compared with the prior art, the instruction generation method, device and instruction generator have the following advantages and positive effects: the hardware resources of a processor are abstracted into a model that can be accessed or occupied, and each instruction in a target instruction set is converted into structure data in units of instruction description information to generate an instruction description table; then, a conflict instruction set is selected from the instruction description table based on a conflict constraint input by a user, conflict instruction pairs are constructed from the conflict instruction set in a two-by-two combination manner, and the constructed conflict instruction pairs are placed in a target instruction sequence by traversing the target instruction sequence; finally, non-conflict instructions are filled in positions without conflict instruction pairs to obtain a final complete target instruction sequence. The instruction generation method can preset conflict constraints according to user requirements, avoids uncontrollable problems caused by random generation of conflict instructions, and can accurately adjust conflict modes, thereby improving the pertinence of verification coverage. In the process of constructing the target instruction sequence, the instruction pairs meeting the conflict constraint are directly selected, and non-conflict instructions are filled in the remaining positions, thereby avoiding the processes of multiple generation and selection and significantly improving the generation efficiency of the target instruction sequence. By abstracting the hardware resources into a model, the instruction generation device can be flexibly adapted to different processor pipeline stages and execution unit structures, and only needs to adjust modeling data according to different requirements without modifying the generation logic, thereby improving the versatility and scalability of the instruction generation device.

[0016] Other features and advantages of the application will become more apparent from the following detailed description of the application when read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0017] The accompanying drawings, which are part of this application, serve to further understand the application, and the illustrative embodiments and descriptions of the application are used to explain the application but do not constitute an improper limitation on the application. Obviously, the accompanying drawings in the following description are only some embodiments, and other drawings can be obtained from the drawings by those skilled in the art without creative labor.

[0018] Figure 1 The microstructure conflict-oriented instruction generation method provided by the application is illustrated; Figure 2 The functional structure of the microstructure conflict-oriented instruction generation device provided by the application is illustrated. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments will be clearly and completely described below with reference to the accompanying drawings. The following embodiments are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0020] This invention addresses the microstructure conflict scenarios generated by instruction generators, such as data conflicts and structural conflicts. It proposes an instruction generation method for microstructure conflicts, which can efficiently generate instruction sequences that meet specified conflict types, conflict intensities, and occurrence frequencies based on preset constraints.

[0021] Specifically, such as Figure 1 As shown, it includes: S1: Establish an abstract model of processor hardware resources.

[0022] Modeling hardware resources. Hardware resources (i.e., microstructures) include Register File (RF), Arithmetic Logic Unit (ALU), Load Store Unit (LSU), Floating Point Unit (FPU), Branch Unit (BU), Pipeline Stage, and shared resources (such as caches and memory access channels).

[0023] During modeling, each type of hardware resource is abstracted into a resource unit that can be accessed or occupied, and the constraint relationships between each type of hardware resource are defined; for example, the LSU can only accept a limited number of memory access requests within the same cycle.

[0024] S2: Generate an instruction description table for each instruction in the target instruction set.

[0025] The target instruction set is the set of all instructions supported by the kernel to be verified. In a RISC-V-based kernel, it supports basic arithmetic and logical operations, memory access instructions, and control instructions. Optionally, it also includes integer multiplication instructions, floating-point extension instructions, and custom extension instructions. The instruction description table contains the following fields: 1. Basic information: Opcode and instruction format.

[0026] 2. Resource information: The type, quantity, and duration of hardware resources occupied by the instruction.

[0027] 3. Timing information: execution delay and pipeline stage occupancy.

[0028] 4. Dependency information: read-after-write (RAW), write-after-read (WAR), write-after-write (WAW), and data dependency.

[0029] In this step, by analyzing each instruction in the target instruction set, a plurality of instruction description information is generated, each instruction is organized as structured data, i.e., an instruction description table, so as to facilitate the subsequent generation process.

[0030] S3: Based on the conflict constraint condition, a conflict instruction set is selected from the instruction description table.

[0031] The constraint conditions required by the user input, such as conflict type, conflict strength, conflict frequency, and instruction sequence length, are obtained. The conflict type is, for example, data conflict, structural conflict, etc., and the conflict strength is, for example, dependency distance, concurrency degree, etc.

[0032] According to the conflict type input by the user, the relevant instructions are selected from the instruction description table generated in S2. For example, if the conflict type is LSU structural conflict, all instructions using the load store unit, such as LW, SW, etc., are selected.

[0033] S4: A conflict instruction pair is constructed in a two-by-two combination manner from the conflict instruction set, and the conflict instruction pair is placed in the target instruction sequence.

[0034] From the instruction set selected in S3, a plurality of conflict instruction pairs are generated by randomly combining two by two.

[0035] For each conflict instruction pair, the target instruction sequence is traversed to find the relative position where the conflict instruction pair can be placed, i.e., the period when the two instructions are executed at the same time, to ensure that the conflict instruction pair is triggered in time sequence. For example, the two LSU instructions are arranged to be transmitted in the same period of the pipeline, triggering structural conflict.

[0036] The target instruction sequence is the final output instruction sequence, which is composed of conflict instruction pairs and non-conflict instructions. In the initial stage, the target instruction sequence is a placeholder sequence without specific instructions.

[0037] For a group of conflict instruction pairs, there may be more than one relative position where they can be placed. The present application generates a plurality of target instruction sequences for a group of conflict instruction pairs for all possible conflict positions.

[0038] S5: Non-conflict instructions are filled in the non-conflict instruction pair placement position of the target instruction sequence.

[0039] In non-critical positions, i.e. non-critical positions other than the placement of conflict instructions, non-conflict instructions are placed to ensure that no additional conflicts will occur in non-critical positions, so as to ensure the legality and integrity of the target instruction sequence.

[0040] These non-conflict instructions have the following characteristics: 1. Do not occupy the same hardware resources as the target conflict.

[0041] 2. Do not introduce new data dependency relationships.

[0042] 3. Maintain the overall executability and legality of the target instruction sequence.

[0043] S6: Output the complete target instruction sequence.

[0044] The generated target instruction sequence is output in a predetermined format, such as an assembly instruction sequence or a binary machine code sequence.

[0045] The target instruction sequence can be run through a simulator to confirm the conflict triggering situation and ensure that it meets the user's expected conflict type and constraint conditions.

[0046] In combination with the above-mentioned instruction generation method for microstructure conflicts, the present application also proposes an instruction generation device for microstructure conflicts, as shown in Figure 2 consisting of a hardware resource modeling module 1, an instruction modeling module 2, a conflict selection module 3, an instruction sequence generation module 4 and an output module 5. Specifically: The hardware resource modeling module 1 is used to establish an abstract model of the internal hardware resources of the processor, describing the usage rules of resources such as registers, execution units and pipelines. These abstract models of hardware resources include but are not limited to: register files, execution units (arithmetic logic units, memory access units, floating point units, etc.), pipeline stages and shared resources (such as caches and memory access channels).

[0047] In the modeling process, each type of hardware resource is abstracted into a resource unit that can be accessed or occupied, and the constraint relationship between resources is defined.

[0048] The instruction modeling module 2 is used to parse the target instruction set and generate instruction description information, and based on the instruction description information, each instruction is organized into structured data to generate an instruction description table.

[0049] Each instruction occupies hardware resources and execution characteristics are recorded in the instruction description table. Specifically, each instruction in the target instruction set is analyzed, and the generated instruction description information includes at least the following fields: 1, Basic information: Opcode, Format.

[0050] 2, Resource information: Type, number, and duration of hardware resources occupied by the instruction.

[0051] 3, Timing information: Execution delay and pipeline stage occupation.

[0052] 4, Dependency information: Read After Write (RAW), Write After Read (WAR), Write After Write (WAW), and data dependency.

[0053] The above instruction description information is organized into structured data for subsequent generation process.

[0054] The conflict selection module 3 is configured to filter the relevant conflict instruction set from the instruction description table according to the conflict constraints such as the conflict type, conflict strength, conflict frequency, and instruction sequence length input by the user.

[0055] The instruction sequence generation module 4 is composed of a combination generation unit 41 and a filling unit 42. The combination generation unit 41 is configured to randomly combine two conflict instructions from the filtered instruction set to form a conflict instruction pair, and place the conflict instruction pair in the target instruction sequence. The filling unit 42 is configured to fill non-conflict instructions that do not cause additional conflicts in non-critical positions where non-conflict instruction pairs are placed, to ensure the legality and executability of the sequence.

[0056] The output module 5 is configured to output the complete target instruction sequence, and optionally verify the conflict effect in the simulator.

[0057] In some embodiments of the present application, the hardware resource modeling module 1 abstracts each type of hardware resource as a resource unit that can be accessed or occupied when modeling the hardware resources of the processor, and defines the constraint relationship between each type of hardware resource.

[0058] In some embodiments of the present application, the instruction modeling module 2 includes: The target instruction set analysis unit 21 is configured to analyze each instruction in the target instruction set to generate a plurality of instruction description information. The instruction description information includes instruction opcode and format information, the type and number of hardware resources required by the instruction, the timing characteristics of the instruction, and the data dependency of the instruction.

[0059] The modeling unit 22 is configured to organize each instruction into an instruction description table based on the instruction description information.

[0060] In some embodiments of the present application, the instruction generation device further includes: The input module 6 is used for inputting conflict constraint conditions by a user; wherein the conflict constraint conditions at least include a conflict type, a conflict strength, a conflict frequency and an instruction sequence length; and the conflict selection module 3 selects instructions from the instruction description table according to the conflict type.

[0061] Compared with the general instruction generator, the instruction generation method and device for microstructure conflict provided by the present application have the following advantages: 1. The controllability of the conflict type is enhanced. The present application can generate a conflict instruction pair sequence of a specified type according to the constraint conditions input by a user through accurate modeling of instructions and hardware resources, thereby avoiding the uncontrollable problem caused by random generation.

[0062] 2. The fine adjustment of conflict characteristics is realized. The present application can control the frequency, dependency distance and duration cycle of conflicts according to the set parameters, thereby realizing fine-grained adjustment of the conflict mode and improving the pertinence of verification coverage.

[0063] 3. The generation efficiency is improved. The present application directly selects instructions that meet the conflict conditions in the instruction sequence construction process, and fills the remaining positions with non-conflict instructions, thereby avoiding multiple generation and screening processes and significantly improving the sequence generation efficiency.

[0064] 4. The architecture adaptability is enhanced. The present application can flexibly adapt to different processor pipeline stage numbers and execution unit structures through abstract modeling of hardware resources, thereby improving the universality and scalability of the tool without modifying the generation logic.

[0065] The present application also provides an instruction generator, which generates an instruction sequence that meets specified conflict types, conflict strengths and occurrence frequencies through the instruction generation device for microstructure conflict, thereby efficiently verifying the conflict scenario with high controllability, high accuracy and high adaptability.

[0066] It should be pointed out that the above description is not a limitation of the present application, and the present application is not limited to the above examples. Changes, modifications, additions or replacements made by ordinary skilled in the art within the essential scope of the present application should also be within the protection scope of the present application.

Claims

1. A method for generating instructions oriented towards microstructure conflicts, characterized in that, include: S1, establish an abstract model of processor hardware resources; S2, for each instruction in the target instruction set, generate an instruction description table; S3, based on conflict constraints, filter the set of conflicting instructions from the instruction description table; S4, construct conflict instruction pairs from the selected conflict instruction set by combining them in pairs, and traverse the target instruction sequence to place conflict instruction pairs; S5, fill the non-conflicting instruction pair placement position in the target instruction sequence with non-conflicting instructions; S6 outputs the complete target instruction sequence.

2. The instruction generation method for microstructure conflict as described in claim 1, characterized in that, When modeling processor hardware resources, S1 also includes: Each type of hardware resource is abstracted into a resource unit that can be accessed or occupied, and the constraint relationships between each type of hardware resource are defined.

3. The instruction generation method for microstructure conflict as described in claim 1, characterized in that, S2 specifically includes: Each instruction in the target instruction set is analyzed to generate several instruction description information; the instruction description information includes instruction opcode and format information, the type and quantity of hardware resources required by the instruction, the timing characteristics of the instruction, and the data dependencies of the instruction. Each instruction is organized into an instruction description table based on the instruction description information.

4. The instruction generation method for microstructure conflict as described in claim 1, characterized in that, S3 specifically includes: Receive conflict constraints input by the user; wherein, the conflict constraints include at least the conflict type, conflict intensity, conflict frequency, and instruction sequence length; Filter instructions from the instruction description table based on the conflict type.

5. The instruction generation method for microstructure conflict as described in claim 1, characterized in that, In S5, the conflict-free instructions are set to: not occupy the same hardware resources as the target, not introduce new data dependencies, and maintain the overall executability and legality of the target instruction sequence.

6. An instruction generation device for microstructure conflict, characterized in that, include: The hardware resource modeling module is used to build an abstract model of the processor hardware resources; The instruction modeling module is used to generate an instruction description table for each instruction in the target instruction set; The conflict selection module is used to filter conflicting instruction sets from the instruction description table based on conflict constraints. The instruction sequence generation module is used to construct conflicting instruction pairs from the conflicting instruction set in a pairwise combination manner, and to traverse the target instruction sequence to place conflicting instruction pairs; and to fill the non-conflicting instruction pair placement positions in the target instruction sequence with non-conflicting instructions. The output module is used to output the complete target instruction sequence and verify it.

7. The instruction generation apparatus for microstructure conflict as described in claim 6, characterized in that, When modeling processor hardware resources, the hardware resource modeling module abstracts each type of hardware resource into a resource unit that can be accessed or occupied, and defines the constraint relationships between each type of hardware resource.

8. The instruction generation apparatus for microstructure conflict as described in claim 6, characterized in that, The instruction modeling module includes: The target instruction set analysis unit is used to analyze each instruction in the target instruction set and generate several instruction description information; the instruction description information includes instruction opcode and format information, the type and quantity of hardware resources required by the instruction, the timing characteristics of the instruction, and the data dependencies of the instruction. Modeling units are used to organize each instruction into an instruction description table based on instruction description information.

9. The instruction generation apparatus for microstructure conflict as described in claim 6, characterized in that, The device further includes: An input module is used for user input of conflict constraints; wherein the conflict constraints include at least conflict type, conflict intensity, conflict frequency, and instruction sequence length; The conflict selection module filters instructions from the instruction description table based on the conflict type.

10. An instruction generator, characterized in that, Includes the instruction generation apparatus for microstructure conflict as described in any one of claims 6-9.

Images