Method for generating SPICE netlist through circuit diagram driven by multi-mode large model

Abstract

The invention discloses a method for generating an SPICE netlist by a circuit diagram driven by a multi-modal large model. The method comprises the following steps: completing construction from a circuit image to an SPICE netlist data set; supervising and finely tuning the circuit-to-netlist model; a step-by-step reasoning normal form in a track guiding reinforcement learning stage; a multi-level reward mechanism in the track guide reinforcement learning stage evaluates the performance of the circuit-to-netlist model from the aspects of reasoning quality, netlist generation accuracy and logic consistency; a reflection learning mechanism in a track-guided reinforcement learning stage; and carrying out overall optimization in a trajectory-guided reinforcement learning stage. According to the method, the precision of conversion from the circuit image to the SPICE netlist and the reasoning consistency can be improved by utilizing a track guide reinforcement learning normal form and integrating step-by-step reasoning, a multi-level reward mechanism and an inverse learning mechanism.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, in particular to a multi-modal large model driven circuit diagram generation SPICE netlist method. BACKGROUND

[0002] Application of artificial intelligence technology in circuit image to SPICE netlist conversion: Circuit images usually contain component layout and connection structure, while SPICE netlist provides a more structured circuit description. Circuit images are usually composed of different components, lines and connection points, which are laid out and connected through certain rules and constraints. While SPICE netlist describes the behavior of the circuit through mathematical models, it can provide the electrical connection relationship between each component and its characteristics (such as resistance, current, voltage, etc.), making the analysis and simulation of the circuit more efficient and accurate. With the rapid development of deep learning, more and more research is devoted to converting circuit images into SPICE netlists for further analysis. For example, the method proposed in “From Schematics to Netlists–Electrical Circuit Analysis Using Deep-Learning Methods” successfully converts these image information into SPICE netlists by decomposing circuit images into multiple steps, including component detection, wiring detection and text recognition. “Amsnet: Netlist dataset for ams circuits” uses a data-driven approach to train a deep learning model to directly map circuit images to SPICE netlists. These studies show that deep learning technology has great potential in the field of circuit image conversion and can effectively improve the automatic analysis capability of circuit images. However, although these methods have made some progress, existing models still face several challenges, especially when dealing with circuit images with high complexity and interwoven connections. Circuit diagrams often contain multiple overlapping elements, complex wiring and different levels of connections, which make it difficult for traditional visual language models and deep learning methods to accurately understand the topology of the circuit diagram. Especially in some cases involving complex symbols, dynamic electrical connections and multi-level circuit design, the model may not be able to effectively capture the relationships between components, leading to reasoning errors or omissions. In addition, existing methods often rely on standardized and simplified circuit image inputs and are difficult to handle real-world circuit diagrams with irregular layouts and diverse symbols. These limitations significantly constrain the reasoning ability of deep learning models, especially when faced with higher precision requirements and complex circuit designs, the model often cannot meet the needs of practical applications. Therefore, how to improve the performance of existing models in complex circuit image analysis, especially in accurately understanding and reasoning the topology of the circuit, is still a technical challenge that needs to be solved.

[0003] Visual language models for circuit image analysis: Visual language models have demonstrated excellent multi-modal understanding and reasoning capabilities in image analysis tasks, particularly when dealing with circuit images. These models combine image and text information, enabling them to effectively parse complex components, connections, and symbols in circuit images. By combining visual perception with language understanding, visual language models can more accurately identify elements in circuit diagrams and their functional relationships, improving the efficiency and accuracy of image analysis. For example, the MAPS article combines physical perception models with simulation processes, enhancing the modeling and reasoning capabilities of visual language models in the physical domain of circuits through the use of supervised fine-tuning techniques. This approach not only improves the understanding of complex components in circuit images but also facilitates the simulation and optimization of circuit designs. The Auto-SPICE article significantly improves the accuracy of analog circuit netlist generation by introducing techniques such as circuit labeling, prompt tuning, and network list verification. These advancements demonstrate the great potential of visual language models in circuit image analysis, enabling more efficient automated circuit design and simulation. However, current methods based on visual language models mainly rely on surface image information, often focusing on explicit features of circuit images while ignoring deep-seated implicit logic and structural patterns in circuit images. Circuit images are not just composed of simple components and connection lines but also contain various potential logical relationships and complex electrical functions, which are crucial for netlist generation. Existing models often fail to delve into these implicit information due to the lack of effective reasoning mechanisms, leading to inaccurate and inconsistent netlist generation results. Therefore, improving the reasoning capabilities of visual language models to better understand complex structures and logical relationships in circuit diagrams is an important challenge in current research. SUMMARY

[0004] The purpose of the present application is to provide a multi-modal large model driven circuit diagram generation SPICE netlist method to solve the problems raised in the background art.

[0005] To achieve the above-mentioned purpose, the present application provides the following technical solutions:

[0006] A multi-modal large model driven circuit diagram generation SPICE netlist method, comprising:

[0007] Step 1, complete the construction of the circuit image to SPICE netlist dataset;

[0008] Step 2, supervised fine-tuning of the circuit to netlist model;

[0009] Step 3, a step-by-step reasoning paradigm in the trajectory-guided reinforcement learning phase, simulating the reasoning process of humans when analyzing circuit diagrams through step-by-step decision-making, the reasoning process including identifying ports, components, and their connection relationships;

[0010] Step 4, the multi-level reward mechanism of the trajectory-guided reinforcement learning phase evaluates the performance of the circuit-to-netlist model from the aspects of inference quality, accuracy of generated netlist, and logic consistency, respectively;

[0011] Step 5, the reflection learning mechanism of the trajectory-guided reinforcement learning phase helps the circuit-to-netlist model adjust the inference trajectory through the hints of the reference answer when the circuit-to-netlist model encounters sparse rewards or incorrect inference paths, so as to avoid the circuit-to-netlist model falling into a local optimal solution or producing incorrect inference results;

[0012] Step 6, the overall optimization of the trajectory-guided reinforcement learning phase, the circuit-to-netlist model gradually identifies the ports, components, and their connection relationships in the circuit diagram, and finally generates a complete SPICE netlist.

[0013] Further, the step 1 comprises:

[0014] Constructing high-quality circuit image data, then accurately labeling the components in the circuit images, and training a target detection model on the labeled circuit image data for automatic detection of components and bounding box labeling;

[0015] Finally, human experts recheck the data to ensure accuracy.

[0016] Further, the step 2 comprises:

[0017] The circuit-to-netlist model is trained through supervised fine-tuning, so that the circuit-to-netlist model can extract key circuit components, ports, and their electrical connections from circuit images and corresponding SPICE netlists.

[0018] Further, the step 3 comprises:

[0019] Using the circuit-to-netlist model to identify the names, types, and relative coordinates of the ports and devices;

[0020] Based on the results of identifying the names, types, and relative coordinates of the ports and devices, the circuit-to-netlist model establishes the electrical connections between the devices and ports;

[0021] The following dynamic inference mechanism is set: if the obtained reward score is lower than a predefined threshold, the subsequent inference steps will not obtain any reward; The dynamic inference mechanism is represented as:

[0022]

[0023] wherein, is the inference state at the inference step t∈{0,1,2,3}. is the inference state at inference step i, and is the inference state update and reward function at inference step t, is the threshold value varying with training step, , are the reward scores at inference steps t, t-1, respectively.

[0024] Further, the step 4 comprises:

[0025] A multi-level reward mechanism is proposed, which decomposes the global reward signal into three fine-grained rewards in the "inference-answer-logic", and defines the multi-level reward score as:

[0026]

[0027] where α, β, γ, δ are four hyperparameters, R total is the multi-level reward score, R think is the step-by-step inference reward, R answer is the netlist accuracy reward, R logic is the Graph consistency reward.

[0028] Further, the step 4 further comprises:

[0029] Setting of the step-by-step inference reward: based on the step-by-step inference paradigm, the three inference steps are scored using structured metrics to quantify the compliance of the inference chain; in the identification stage of the port and device, the dual rewards of the semantic space and the geometric space are adopted in the unified format "name (type) [[bbox]]"; the semantic reward is to match the same "name (type)" to obtain a certain score, and the geometric reward is to calculate the average intersection of the normalized bounding box to obtain a certain score, and each total score is 1 point; in the connection relationship verification stage, the "node <id>connections are described in the format of "Device Name"; design a list reward mechanism to get scores by matching list length and aligning elements; all scores range from 0 to 1.

[0030] Further, the step 4 further comprises:

[0031] Netlist accuracy reward setting: construct a set matching based continuous reward function that maps the SPICE netlist list to the connection set between devices and ports with regularization constraints; the netlist accuracy reward is derived by comparing the equivalent connections between the real SPICE netlist set C gt and the generated SPICE netlist set C pred , thus rewarding the correctly matched node set in the generated SPICE netlist; the reward score of the netlist accuracy reward is represented as:

[0032]

[0033] wherein, represents the intersection.

[0034] Further, the step 4 further comprises:

[0035] Graph consistency reward setting: extract the SPICE network list and the reasoning connection graph using the depth-first search algorithm, compare the adjacency relationship of nodes to determine their equivalence; in the constructed Graph graph, each endpoint represents a port or device in the circuit image, and the edge represents the connectivity between the endpoints; by comparing the overlapping part of the corresponding edges in the reasoning connection Graph graph G and the SPICE netlist Graph graph G, the similarity is calculated and the Graph consistency reward is provided, and the Graph consistency reward score is represented as:

[0036]

[0037] wherein, and are the i-th edge and the j-th edge of the Graph graph and the Graph graph , represents the indicator function that judges whether the two edges are equal;

[0038] Format reward setting: the format reward encourages the circuit-to-netlist model to adopt a structured reasoning process, requiring it to output the reasoning steps within the <think>and< / think> tag, and the content of the reasoning needs to clearly include <port>and< / port> , <device>and< / device> , and <connection>and< / connection> tags; the final answer is located in the <answer>and< / answer> The score formula for format reward is:

[0039]

[0040] wherein Format Correct represents that the format of the circuit-to-netlist model output answer is correct, and Otherwise represents otherwise.

[0041] Further, the step 5 comprises:

[0042] A reflective learning is proposed, when all reward values are lower than a preset specific reward threshold, a reference answer is actively provided as a prompt for low reward samples, encouraging the circuit-to-netlist model to perform reverse correction engineering on the reasoning trajectory according to the connection relationship and electrical properties in the SPICE netlist;

[0043] Based on the improved reward results, the final score is adjusted by calculating the difference between the reflective reward and the original reward, and only when positive improvement occurs, additional rewards are given;

[0044] If no positive improvement is made, a relative penalty is introduced to guide the circuit-to-netlist model to further optimize the reasoning process;

[0045] The final reward score is represented as:

[0046]

[0047] wherein, is the reflective reward score of the reference answer, is a reference reward weight parameter, and ε1 is a stability constant, is a specific score threshold, and max represents the maximum value.

[0048] Further, the step 6 comprises:

[0049] The trajectory-guided reinforcement learning training paradigm optimizes the reasoning trajectory and the accuracy of generating SPICE netlist answers based on the difference relationship within the group;

[0050] Given a query , from the old policy , generate samples , wherein represents a single generated sample, and the trajectory-guided reinforcement learning goal is:

[0051]

[0052] wherein, is the objective function, is the expected value of the objective function, KL divergence, is the output distribution of the current circuit netlist model, is the output distribution of the reference model, the loss function can be defined as:

[0053]

[0054] where min denotes taking the minimum value, and clip denotes clipping.

[0055] Normalized advantage is defined as:

[0056]

[0057] where, is the score of the i-th generated sample, β and ε2 are default hyperparameters, mean represents the calculation of the mean, and std represents the calculation of the standard deviation.

[0058] Compared with the prior art, the beneficial effects of the present application are:

[0059] The present application proposes a reasoning framework based on a multi-modal large model for automatic conversion of circuit netlists. The framework uses the TGRL (Trajectory Guided Reinforcement Learning) paradigm, integrating step-by-step reasoning, multi-level reward mechanisms, and reflective learning mechanisms to improve the accuracy and consistency of circuit image to SPICE netlist conversion. First, the framework uses step-by-step reasoning to break down the complex circuit image conversion task into multiple steps of recognizing ports, devices, and connection relationships, effectively reducing errors and inconsistencies in the reasoning process. Next, through the multi-level reward mechanism, not only the accuracy of the netlist generation is evaluated, but also the logical consistency of the reasoning process is considered to ensure that the generated netlist is not only accurate but also consistent with the actual structure of the circuit. Finally, the reflective learning mechanism is introduced to help the model correct reasoning biases through backward feedback and the guidance of reference answers, avoiding the model from falling into local optimal solutions and improving the stability and reliability of the reasoning process.

[0060] The present application surpasses the performance of existing methods in terms of netlist generation accuracy and reasoning consistency. Compared with traditional methods, the present application exhibits higher accuracy and better generalization ability when dealing with complex circuit images. Future work will focus on further improving the universality and adaptability of the framework to adapt to a wider range of circuit types and application scenarios, promoting its wide application in circuit design, optimization, and fault diagnosis, and further improving the intelligent level of the electronic design automation (EDA) field. BRIEF DESCRIPTION OF DRAWINGS

[0061] Figure 1 A flow chart of a multi-modal large model driven circuit diagram generation SPICE netlist method.

[0062] Figure 2 A trend chart of the reward score of the training step and the generation of the SPICE netlist in the embodiment. Figure 2 A is the trend of the inference accuracy score as the training step increases; B is the trend of the netlist accuracy score as the training step increases. DETAILED DESCRIPTION

[0063] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the scope of protection of the present application.

[0064] Please refer to Figure 1 A multi-modal large model driven circuit diagram generation SPICE netlist method, comprising the following corrections:

[0065] Step 1, complete the construction of the circuit image to SPICE netlist dataset, specifically including:

[0066] In the step of constructing the circuit image to SPICE netlist dataset, the present application systematically constructs 3,100 high-quality circuit image data from public resources, covering analog, digital and mixed signal designs from simple to complex systems. Then, the components in these images are accurately labeled, and a target detection model, preferably YOLO11 model, is trained on the labeled circuit image data for automatic detection of components and bounding box labeling. Considering the complexity of circuit topology and connection, human expert intervention is added to ensure accuracy. Specifically, domain experts establish correct connection relationships according to electrical principles and generate corresponding SPICE netlists. Each data entry follows a standardized JSON structure, contains three main inference steps, and has undergone strict quality control of circuit image to SPICE netlist.

[0067] Step 2, supervise the fine-tuning of the circuit to netlist model, specifically including:

[0068] In the supervised fine-tuning (SFT) step, the circuit-to-netlist model is trained through supervised fine-tuning, enabling the circuit-to-netlist model to extract key circuit elements, ports, and electrical connections between them from circuit images and corresponding SPICE netlists. The goal is to help the circuit-to-netlist model initially understand the structure and composition of the circuit and improve its ability to identify circuit components and their connection relationships. This process lays the foundation for subsequent reasoning and analysis, ensuring that the circuit-to-netlist model can effectively process complex circuit image information.

[0069] Step 3, the step-by-step reasoning paradigm of the trajectory-guided reinforcement learning phase, simulates the reasoning process of humans when analyzing circuit diagrams through step-by-step decision-making, and the reasoning process includes identifying ports, components, and their connection relationships, specifically including:

[0070] In the step-by-step reasoning paradigm of the trajectory-guided reinforcement learning (TGRL), the circuit-to-netlist model identifies the names, types, and relative coordinates of ports and devices. Based on the results of identifying the names, types, and relative coordinates of ports and devices, the circuit-to-netlist model establishes electrical connections between device ports. To prevent the continuation of incorrect reasoning paths, if the reward score obtained by any step is lower than a predefined threshold, subsequent reasoning steps will not receive any reward. This dynamic reasoning mechanism can be represented as:

[0071]

[0072] where, is the reasoning state at reasoning step t∈{0,1,2,3}, is the reasoning state at reasoning step i, and is the reasoning state update and reward function at reasoning step t, is the threshold value that changes with training steps, , are the reward scores of reasoning steps t and t-1, respectively.

[0073] Step 4, the multi-level reward mechanism of the trajectory-guided reinforcement learning phase, respectively evaluates the performance of the circuit-to-netlist model from the aspects of reasoning quality, accuracy of generated netlists, and logical consistency, specifically including:

[0074] In the step of the step-by-step inference paradigm in trajectory-guided reinforcement learning (TGRL), the traditional single reward mechanism usually only focuses on the final SPICE netlist quality, ignoring the inference quality and logical consistency. This may lead to a "random optimization" strategy, in which the circuit-to-netlist model improves the SPICE netlist quality by random simplification rather than stable optimization, thereby disrupting the learning of the circuit physical and electrical characteristics and reducing the explainability of the inference process. Considering that the inference chain may be logically inconsistent with the hint or the final SPICE netlist, this bias exacerbates the accumulation of errors. Therefore, the present application proposes a multi-level reward mechanism that decomposes the global reward signal into three fine-grained rewards in "inference-answer-logic". The present application defines the multi-level reward score as:

[0075]

[0076] wherein α, β, γ, δ are four hyperparameters, respectively set to 0.4, 0.2, 0.2, 0.2. total is the multi-level reward score, R think is the step-by-step inference reward, answer is the netlist accuracy reward, and R logic is the Graph consistency reward.

[0077] Step 4.1, step-by-step inference reward (R think ): Based on the step-by-step inference paradigm, the present application uses structured metrics to score the three inference steps to quantify the adherence of the inference chain. In the identification stage of the port and device, a unified format "name (type) [[bbox]]" is adopted to give double rewards to the semantic space and the geometric space. The semantic reward is 0.5 points for matching the same "name (type)", and the geometric reward is 0.5 points for calculating the average intersection of normalized bounding boxes (mIoU≥0.5), with each total score being 1 point. In the connection relationship verification stage, the "node <id>connections in the format of "[device name - port]" which is considered as a list of device and port pairs. The invention designs a list reward mechanism to obtain 1 point by matching the list length and aligning elements. All scores range from 0 to 1. This reward enhances the spatial understanding ability of the visual language circuit-to-netlist model and evaluates the correctness of the inference chain.

[0078] Step 4.2, Netlist accuracy reward (R answer ): To constrain the topological accuracy of the generated SPICE netlist and provide a more stable reward signal for small-scale sets, the invention constructs a continuous reward function based on set matching. This method applies regularization constraints to map the SPICE netlist list (e.g., "[VDD node1],[Vb node2], [R1 node1node2 resistor]") to the connection set between devices and ports (e.g., "(VDD, R1), (Vb, R1)"). The reward is obtained by comparing the proportion of equivalent connections between the true SPICE netlist set Cgt and the generated SPICE netlist set Cpred, thereby rewarding the correctly matched node set in the generated SPICE netlist. The reward score of the netlist accuracy reward can be represented as:

[0079]

[0080] where, represents the intersection.

[0081] Step 4.3, Graph consistency reward (R logic ): Since the generated inference chain is not directly assessable due to its different format from the SPICE netlist, the invention uses a unified graph structure to quantify their similarity, thereby enhancing the logical consistency between the inference and the answer. Specifically, the invention uses the depth-first search (DFS) algorithm to extract the SPICE netlist list and the inference connection graph. To eliminate node naming differences (e.g., mapping "node1" in the SPICE netlist to "node5" in the inference graph as equivalent nodes), the invention compares the adjacency relationships of nodes to determine their equivalence. Even if the node names are different, as long as they are connected to the same node type and share the same connection pattern, they can be considered equivalent. In the graph, each endpoint represents a port or device in the circuit image, while the edge represents the connectivity between endpoints. By comparing the overlapping parts of the corresponding edges in the inference connection Graph G and the SPICE netlist Graph G, the invention calculates the similarity and provides the reward. The reward score can be represented as:

[0082]

[0083] where, and respectively are Graphs and Graphs the i-th edge and the j-th edge of Graphs represent an indicator function that judges whether the two edges are equal.

[0084] Step 4.4, Format Reward (R format ): The format reward encourages the circuit-to-netlist model to adopt a structured reasoning process, requiring it to output reasoning steps within <think>and< / think> tags, and explicitly including <port>and< / port> , <device>and< / device> , and <connection>and< / connection> tags in the content of the reasoning. The final answer is located between <answer>and< / answer> tags. The score formula for the format reward is:

[0085]

[0086] where Format Correct indicates that the format of the answer output by the circuit-to-netlist model is correct, and Otherwise indicates otherwise.

[0087] Step 5, the reflection learning mechanism of the trajectory guidance reinforcement learning phase, when the circuit-to-netlist model encounters sparse rewards or incorrect reasoning paths, the circuit-to-netlist model is guided to adjust the reasoning trajectory through the hints of the reference answer, thereby avoiding the circuit-to-netlist model falling into a local optimal solution or producing incorrect reasoning results, specifically including:

[0088] In the reflection learning mechanism in the trajectory guidance reinforcement learning (TGRL), in the task of converting a circuit to a netlist, it can be observed that the reasoning reward obtained by the circuit-to-netlist model in the initial exploration stage is very low. Due to the sparsity of reward feedback and the accumulation of errors, the circuit-to-netlist model is difficult to obtain sufficient positive feedback and is prone to fall into a local optimum or stop learning. In order to solve this problem, the present invention proposes a reflective learning, when all reward values are lower than a preset specific reward threshold, actively providing a reference answer as a hint for low reward samples, encouraging the circuit-to-netlist model to perform reverse correction engineering on the reasoning trajectory according to the connection relationship and electrical properties in the SPICE netlist. Based on the improved reward results, the present invention adjusts the final score by calculating the difference between the reflection reward and the original reward, and only gives additional rewards when positive improvements are made. If no positive improvements are made, a relative penalty is introduced to guide the circuit-to-netlist model to further optimize the reasoning process. The final reward score can be expressed as:

[0089]

[0090] where, To reflect the answer for the reward score, To reference the reward weight parameter, set to 0.6, epsilon1 is a stable constant, set to 1e-6, To a specific score threshold, set to 0.7.

[0091] Step 6, the overall optimization of the trajectory guidance reinforcement learning phase is carried out, and the circuit conversion netlist model is generated by gradually identifying the ports, elements and their connection relationship in the circuit diagram, and finally a complete SPICE netlist is generated, including:

[0092] In the overall optimization step of trajectory guidance reinforcement learning (TGRL), the TGRL training paradigm in the present application optimizes the inference trajectory and the answer accuracy based on the difference relationship within the group. Given a query , generate samples from the old policy , where represents a single generated sample, the TGRL target of the present application is:

[0093]

[0094] Where, is the target function, is the expected value of the target function, is the calculation of KL divergence, is the output distribution of the current circuit conversion netlist model, is the output distribution of the reference model, and the loss function can be defined as:

[0095]

[0096] Where, min represents the minimum value, and clip represents clipping.

[0097] The normalized advantage can be defined as:

[0098]

[0099] Where, is the score of the i-th generated sample, beta and epsilon2 are default hyperparameters, mean represents the calculation of the mean, and std represents the calculation of the standard deviation.

[0100] Embodiment

[0101] 1. Experimental dataset: The present application uses a two-stage model training on a circuit image-SPICE netlist dataset, which includes 2,500 training pairs and 600 test pairs. In the training process, the supervised fine-tuning stage is performed on a 1000-subsample set, and TGRL uses the complete training set. The present application evaluates the accuracy of the SPICE netlist on the above test set and the published AMSNet dataset, and evaluates the accuracy of the downstream circuit question and answer effect on the published AMSBench dataset.

[0102] 2. Experimental details: The present application uses Qwen2.5-VL-7B as the basis for fine-tuning the model, starting with full-parameter supervised fine-tuning in the first stage, and then continuing to fine-tune the model after supervised fine-tuning for 200 steps of TGRL. In the two-stage training process, the batch size is set to 16, 8 samples per training step, the initial learning rate is 1e-6, and the weight decay is 0.01. Training is performed on 8 NVIDIA A100 GPUs.

[0103] 3. Experimental evaluation index: The present application evaluates the conversion accuracy of circuit images to SPICE netlists from two dimensions: the Jaccard similarity between the predicted and true SPICE netlists is used to calculate the answer accuracy, while the logical consistency is measured by comparing the predicted SPICE netlist with the intermediate connection inference through Jaccard similarity. For the quality assurance task of circuit images, the present application uses accuracy as an evaluation index.

[0104] 4. Experimental results:

[0105] (1) TGRL learning paradigm results:

[0106] Table 1 compares the results of using different fine-tuning paradigms on Qwen2.5-VL 7B. The present application compares the accuracy of the SPICE netlist within 200 steps. The results show that the accuracy of the TGRL paradigm is 25.39% higher than that of the traditional supervised fine-tuning at 200 steps, but the supervised fine-tuning has overfitting phenomenon in the subsequent steps. In addition, the accuracy of TGRL is 19.94% higher than that of the group relative strategy optimization (GRPO) technology based on reinforcement learning. The results show that in the complex circuit-to-netlist conversion task, TGRL steadily improves the model performance, significantly enhancing the model's generalization and robustness. Figure 2 The table shows the inference steps and reward scores for generating SPICE netlists in TGRL for 200 steps. The results show that all aspects have stable improvements as training progresses.

[0107] Table 1 Qwen2.5-VL 7B performance using TGRL and other tuning methods on the dataset constructed by the present application.

[0108]

[0109] (2) The question and answer results of the circuit image:

[0110] The present application evaluates the question and answer accuracy of multiple circuit image question and answer scenarios on the AMSBench dataset to evaluate the effect of the model of the present application on downstream tasks. The present application compares the results of using only circuit images and using circuit images and SPICE netlist simultaneously. As shown in Table 2, in the identification connection scenario, the improvement rate of Gemini2.5-pro is 10.97%, and the improvement rate of Qwen2.5-VL 72B is 9.2%. And the results show that integrating SPICE netlist information significantly improves the performance of multiple circuit image question and answer scenarios, verifying the auxiliary role of SPICE netlist in this task, and further confirming the effectiveness of the SPICE netlist generation method in supporting reasoning and improving question and answer accuracy.

[0111] Table 2 Comparison of question and answer accuracy of visual language models on multiple downstream tasks on the AMSBench dataset.

[0112]

[0113] (3) Ablation experiment:

[0114] The present application conducts ablation research to verify the effectiveness of the reward function and the reflective learning mechanism.

[0115] ① Soft reward vs. hard reward: The present application uses three levels of format constraints (w / o: no format constraint, soft: only constraint thinking and answer, strict: constraint thinking, port, device, connection and answer together) to evaluate their influence on the accuracy and logical consistency of SPICE netlist conversion. As shown in Table 3, deleting the constraint reduces the accuracy to 39.21%, while stricter constraints will significantly improve both indicators. This shows that the step-by-step reasoning paradigm effectively regulates the reasoning trajectory and improves task performance.

[0116] Table 3 Ablation experiment of format reward under different constraint types.

[0117]

[0118] (ii) Design of step-by-step reasoning reward: The effectiveness of step-by-step reasoning reward is evaluated in three key steps: port identification, device identification, and connection inference. Port and device identification includes type classification and location recognition. As shown in Table 4, the accuracy of SPICE netlist can be improved from 45.76% to 48.13% and the logical consistency can be improved by about 22% in combination with port and device identification. After adding connection inference, both indicators are significantly improved. The results emphasize the key role of step-by-step constraints in improving the quality of SPICE netlist while maintaining logical consistency.

[0119] Table 4. Smile experiment of the three steps in the inference process.

[0120]

[0121] (iii) Design of Bbox and type: Table 5 evaluates the impact of type classification and location recognition on accuracy. When deleting port and device type classification (w / o type of port / device), the SPICE netlist precision drops to 47%, and the logical consistency cannot be maintained. This shows that identifying component types and port attributes is the basis for understanding circuit structure and determining functional relationships in the inference process. When removing location recognition (w / o bbox of port / device), the SPICE netlist precision drops to 49%. This result shows that type classification and location recognition play different and complementary roles in circuit image interpretation, with type information being more critical to building an overall structural framework, and spatial information ensuring accurate inference of location relationships.

[0122] Table 5. Ablation experiment of independent operation.

[0123]

[0124] (iv) Design of reasoning logic strategy: To evaluate the impact of step-by-step reasoning paradigm and logical consistency constraints, Table 5 reports the ablation results. Deleting the "port-device-connection" track (w / o step-by-step reasoning) reduces the accuracy of the SPICE netlist to 35.38%, indicating that the lack of structured reasoning disrupts the inference chain and damages the generation of the SPICE netlist. Ignoring the logical consistency reward (w / o logical consistency) also reduces the accuracy, highlighting the importance of maintaining consistency between the inference process and the SPICE netlist output to obtain reliable results.

[0125] (v) Design of reflective learning mechanism strategy: As shown in Table 5, after removing reflective learning, the accuracy of the SPICE netlist decreases from 73.27% to 65.76%, and the logical consistency decreases from 85.76% to 70.10%. Figure 2 ​Further illustration of its impact on reward scores is provided. Results show that the reflective learning mechanism effectively reduces early reasoning errors, improving score performance. In later stages, it ensures consistency between the reasoning trace and the SPICE netlist output, preventing error accumulation and ensuring stable, logical SPICE netlist generation.

[0126] While embodiments of the present application have been shown and described with reference to particular embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope of the application. The scope of the application is defined by the appended claims and their equivalents.< / id> < / id>

Claims

1. A method for generating SPICE netlists from circuit diagrams driven by a multimodal large model, characterized in that, include: Step 1: Complete the construction of the SPICE netlist dataset from the circuit diagram; Step 2: Perform supervised fine-tuning of the circuit-to-netlist model; Step 3, the step-by-step reasoning paradigm of the trajectory-guided reinforcement learning stage, simulates the reasoning process of humans when analyzing circuit diagrams through step-by-step decision-making. The reasoning process includes identifying ports, components and their connection relationships. Step 4: The multi-level reward mechanism in the trajectory-guided reinforcement learning stage evaluates the performance of the circuit-to-netlist model in terms of inference quality, accuracy of generated netlists, and logical consistency. Step 5: The reflective learning mechanism in the trajectory-guided reinforcement learning stage. When the circuit-to-netlist model encounters sparse rewards or incorrect inference paths, the reference answer helps the circuit-to-netlist model adjust its inference trajectory, thereby avoiding the circuit-to-netlist model from getting stuck in local optima or producing incorrect inference results. Step 6: Perform overall optimization of the trajectory-guided reinforcement learning stage. The circuit-to-netlist model gradually identifies ports, components and their connections in the circuit diagram, and finally generates a complete SPICE netlist.

2. The method for generating SPICE netlists from circuit diagrams driven by a multimodal large model according to claim 1, characterized in that, Step 1 includes: High-quality circuit image data is constructed. Subsequently, the components in these circuit images are accurately labeled, and a target detection model is trained on the labeled circuit image data for automatic detection of components and bounding box annotations. Finally, human experts were brought in to review the data again to ensure accuracy.

3. The method for generating SPICE netlists from circuit diagrams driven by a multimodal large model according to claim 1, characterized in that, Step 2 includes: The circuit-to-netlist model, through supervised fine-tuning training, enables the model to extract key circuit elements, ports, and their electrical connections from circuit images and corresponding SPICE netlists.

4. The method for generating SPICE netlists from circuit diagrams driven by a multimodal large model according to claim 1, characterized in that, Step 3 includes: Use a circuit-to-netlist model to identify the names, types, and relative coordinates of ports and devices; Based on the identified port and device names, types and relative coordinates, the circuit-to-netlist model establishes the electrical connections between devices and ports. The following dynamic reasoning mechanism is set: if the reward score obtained is lower than a predefined threshold, no reward will be obtained for subsequent reasoning steps; This dynamic reasoning mechanism is represented as follows: ， in, Let t be the reasoning state at reasoning step t∈{0,1,2,3}. Let i be the reasoning state at reasoning step i. and Let be the reasoning state update and reward function for reasoning step t. The threshold that changes with the training steps. , These are the reward scores for reasoning steps t and t-1, respectively.

5. The method for generating SPICE netlists from circuit diagrams driven by a multimodal large model according to claim 1, characterized in that, Step 4 includes: A multi-level reward mechanism is proposed, which decomposes the global reward signal into three fine-grained rewards in "reasoning-answer-logic". The multi-level reward score is defined as follows: ， Where α, β, γ, and δ are four hyperparameters, R total R provides multi-tiered reward scores. think For progressive reasoning rewards, R answer As a reward for netlist accuracy, R logic Rewards are given for graph consistency.

6. The method for generating SPICE netlists from circuit diagrams driven by a multimodal large model according to claim 5, characterized in that, Step 4 also includes: The step-by-step reasoning reward is set as follows: Based on the step-by-step reasoning paradigm, a structured metric is used to score the three reasoning steps to quantify the compliance of the reasoning chain. In the port and device identification stage, a unified format "name (type) [[bbox]]" is adopted to provide dual rewards in both semantic and geometric spaces. The semantic reward is a score for matching the same "name (type)," and the geometric reward is a score for calculating the average intersection of the normalized bounding boxes, with each reward totaling 1 point. In the connection verification stage, "node" is used as the basis for the reward. <id> Describe the connection in the format "[device name]"; design a list reward mechanism to obtain a number of points by matching the list length and aligning elements; all scores range from 0 to 1.< / id> 7. The method for generating SPICE netlists from circuit diagrams driven by a multimodal large model according to claim 5, characterized in that, Step 4 also includes: Netlist accuracy reward setting: A continuous reward function based on set matching is constructed. This function applies regularization constraints to map the SPICE netlist list to the connection set between devices and ports. The netlist accuracy reward is calculated by comparing the actual SPICE netlist set C. gt With the generated SPICE netlist set C pred The reward score for the correct set of nodes in the generated SPICE netlist is derived from the proportion of equivalent connections between nodes; the reward score for netlist accuracy is expressed as: ， in, The intersection represents the point of contact.

8. The method for generating SPICE netlists from circuit diagrams driven by a multimodal large model according to claim 5, characterized in that, Step 4 also includes: The graph consistency reward is defined as follows: A depth-first search algorithm is used to extract the SPICE network list and the inference connection graph, and the adjacency of nodes is compared to determine their equivalence. In the constructed graph, each endpoint represents a port or device in the circuit diagram, and edges represent the connectivity between endpoints. The similarity is calculated and a graph consistency reward is provided by comparing the overlapping parts of corresponding edges in the inference connection graph G and the SPICE network list graph G. The graph consistency reward score is expressed as: ， in, and These are Graph diagrams. and Graph The i-th edge and the j-th edge, This is an indicator function that determines whether two edges are equal. Formatting Rewards: Formatting rewards encourage circuit-to-netlist models to employ structured reasoning processes, requiring them to... <think> and< / think> The reasoning steps should be output within the tags, and the reasoning content should explicitly include... <port> and< / port> , <device>and< / device> ,as well as <connection> and< / connection> Tags; the final answer is located at <answer> and< / answer> Between tags; the formula for the format reward score is: ， Here, "Format Correct" indicates that the output answer of the circuit-to-netlist model is in the correct format, and "Otherwise" indicates otherwise.

9. The method for generating SPICE netlists from circuit diagrams driven by a multimodal large model according to claim 1, characterized in that, Step 5 includes: A reflective learning approach is proposed, which proactively provides reference answers as hints of low-reward samples when all reward values ​​are below a preset specific reward threshold. This encourages the circuit-to-netlist model to perform reverse correction engineering on the inference trajectory based on the connection relationships and electrical properties in the SPICE network list. Based on the improved reward results, the final score is adjusted by calculating the difference between the reflective reward and the original reward, and additional rewards are only given when there is positive improvement. If no positive improvements are made, a relative penalty is introduced to guide the circuit-to-netlist model to further optimize the inference process; Final reward score Represented as: ， in, Reward points are awarded for reflecting on the reference answer. For reference reward weight parameters, ε1 is a stability constant. For a specific score threshold, max indicates taking the maximum value.

10. The method for generating SPICE netlists from circuit diagrams driven by a multimodal large model according to claim 1, characterized in that, Step 6 includes: The trajectory-guided reinforcement learning training paradigm optimizes the accuracy of inference trajectories and generated SPICE netlist answers based on the differences within groups; Given a query From the old strategy Generated in Sample ,in Representing a single generated sample, the trajectory-guided reinforcement learning objective is: ， in, Let be the objective function. Let be the expected value of the objective function. For the calculation of KL divergence, The output distribution of the current circuit-to-netlist model, For the output distribution of the reference model, the loss function It can be defined as: ， Where min means taking the minimum value, and clip means clipping; Standardization advantages Defined as: ， in, ε is the score of the i-th generated sample. β and ε2 are default hyperparameters. mean represents the calculation of the mean, and std represents the calculation of the standard deviation.

Images