Dynamic self-adaptive NAND Flash reading method and system based on artificial intelligence, medium and equipment

Abstract

The invention discloses a dynamic self-adaptive NAND Flash reading method and system based on artificial intelligence, a medium and equipment, and relates to the technical field of solid-state storage, the method comprises the following steps: S1, initiating a reading request, reading page data by using default voltage, decoding the page data through an LDPC algorithm, constructing a feature vector and performing preprocessing, inputting the voltage into a pre-trained neural network model, and carrying out voltage prediction; s2, carrying out fine sampling on the predicted voltage, reconstructing accurate threshold voltage distribution, and calculating a log-likelihood ratio; s3, designing a shared bottom layer backbone network, enabling a neural network model to have independent output branches, predicting the voltage, and evaluating the long-term health state of the block; and S4, designing an online transfer learning mechanism, and enabling the neural network model to quickly adapt to a new environment by using a small amount of new data. According to the method, the delay is greatly reduced, the power consumption is remarkably saved, data loss is prevented through early warning of bad blocks, and the write amplification factor is reduced to 1.26 through dynamic read interference suppression.

Description

Technical Field

[0001] This invention relates to the field of solid-state storage technology, and more specifically to a dynamic adaptive NAND flash reading method, system, medium, and device based on artificial intelligence. Background Technology

[0002] NAND Flash is the core storage medium of modern solid-state drives (SSDs). With the development of 3D NAND technology, the number of bits stored in a single storage cell is increasing (e.g., 3 bits for TLC, 4 bits for QLC, and 5 bits for PLC). QLC / PLC needs to distinguish more states within a very narrow voltage window (16 for QLC and 32 for PLC), making it extremely sensitive to minute changes in the threshold voltage (Vt). The threshold voltage (Vt) is a key parameter for determining the data state (e.g., 00, 01, 10, 11) stored in a NAND Flash storage cell, and the amount of stored charge determines the level of Vt. It is affected by the following factors: 1) Temperature: Temperature changes cause Vt to drift (e.g., a ±30℃ change can cause a 40-60mV drift); 2) Device aging: Increased write / erase cycles (P / ECycle) reduce the cell's charge retention ability, causing Vt distribution to widen or drift; 3) Read interference: The voltage stress generated when reading a cell can slightly alter the charge of neighboring cells. 4) Process deviation: Under advanced manufacturing processes, there are differences in the Vt reference between different chips.

[0003] The current mainstream solution is "static voltage adjustment table (ΔV table) + voltage retry (Read Retry) + soft decision decoding (LDPC)". Its workflow is as follows: initial read failure → fine-tuning the reference voltage based on the preset ΔV table and reading again (one voltage retry) → if it still fails, retrying with a different ΔV value → data obtained after multiple retries is sent to the LDPC decoder for strong error correction. Because the ΔV table is static, it cannot compensate for real-time and dynamic Vt drift caused by temperature fluctuations, device aging, read interference, etc., resulting in a low probability of successful first reads. Frequent voltage retry mechanisms must be initiated, leading to excessively high read latency (an increase of 200-400μs). Because the original bit error rate of the data obtained after voltage retry is still high, soft decision decoders such as LDPC must perform multiple iterative calculations to correct errors, resulting in wasted computing resources and increased power consumption (LDPC power consumption can account for 30% of the total SSD power consumption). Because the bad block management strategy is reactive (marking only after the unit has completely failed), it cannot cope with the sudden and batch failures of QLC / PLC units, which leads to the risk of data loss and a decrease in yield. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a dynamic adaptive NAND Flash reading method, system, medium and device based on artificial intelligence.

[0005] The objective of this invention is achieved through the following technical solution: In the first aspect, this application discloses a dynamic adaptive NAND Flash reading method based on artificial intelligence, including the following steps: S1. Initiate a read request, read page data using the default voltage, decode it using the LDPC algorithm, construct a feature vector and perform preprocessing, then input it into a pre-trained neural network model for voltage prediction; S2. Based on the voltage predicted in step S1, perform fine sampling to reconstruct the accurate threshold voltage distribution and calculate the log-likelihood ratio. S3. Design a shared underlying backbone network so that the neural network model in step S1 has two independent output branches for predicting voltage and evaluating the long-term health status of the block, thereby achieving early warning of bad blocks. S4. Design an online transfer learning mechanism to enable the neural network model in step S1 to quickly adapt to a new environment using a small amount of new data.

[0006] Based on the first aspect, step S1 specifically includes the following steps: S11. If the first read of the target page fails, the system immediately constructs a feature vector X to reflect the current specific block and specific conditions. The specific block represents the block where the target page is located, and the specific conditions represent the real-time environment and working state that affect the threshold voltage of the block. The feature vector X includes the real-time chip temperature T, the cumulative number of erase and write operations N_pe, the data retention time T_ret, the recent read interference count N_read, the historical successful read voltage V_read_hist, and the historical raw bit error rate RBER_hist. S12. Standardize the feature vector constructed in step S11 by X_normalized = (X - X_mean) / X_std to obtain the standardized feature vector X_normalized, where X_mean represents the feature mean and X_std represents the feature standard deviation. S13. Input the standardized feature vector X_normalized into the pre-trained neural network model, and calculate the voltage offset ΔV_predicted through nonlinear transformation; S14. Based on the preset scaling factor, denormalize ΔV_predicted to obtain the denormalized voltage offset ΔV_predicted'. Then add it to the default read voltage V_default to generate the final read voltage V_opt, and use it to reread the target page.

[0007] Based on the first aspect, step S2 specifically includes the following steps: S21. Fine sampling centered on the predicted voltage: with the final read voltage V_opt obtained in step S14 as the center point, sampling points are set in its neighborhood with voltage interval ΔV_step. The controller uses these voltage values ​​to sample and read the same page multiple times in sequence, and records the original data of each read. S22. Based on the sampled voltage V_i obtained in step S21, count the number of memory cells judged as logic '1' (Count_1(V_i)) and the number of memory cells judged as logic '0' (Count_0(V_i)) in the entire page; use kernel density estimation to fit the conditional probability density function curves f(V | S=0) and f(V | S=1), where f(V | S=0) represents the probability density of the threshold voltage measurement value V when the stored data is actually '0', and f(V | S=1) represents the probability density of the threshold voltage measurement value V when the stored data is actually '1'. S23. Calculate the log-likelihood ratio LLR(V) using the formula LLR(V) = ln [ f(V | S=0) / f(V | S=1) ], where ln represents the natural logarithm function.

[0008] Based on the first aspect, step S3 specifically includes the following steps: S31. The shared underlying backbone network includes multiple hidden layers, and the output branch includes a health score head and a ΔV prediction head. The shared underlying backbone network extracts feature representations from the input feature vector X through the hidden layers, and then inputs them into the health score head and the ΔV prediction head. The health score head outputs a block health status score Health_Score, and the ΔV prediction head outputs a voltage offset ΔV_predicted. The health score head and the ΔV prediction head are output in parallel. S32. The block health status score Health_Score output by the health score head is limited to the range (0, 1) by using the Sigmoid activation function. Health_Score = Sigmoid(W_h · h_shared + b_h); where h_shared represents the feature representation extracted from the input feature vector X by the hidden layer of the shared underlying backbone network; W_h represents the weight of the health score head; and b_h represents the bias parameter of the health score head. S33. Obtain the health labels required for model training through the internal monitoring data of the flash memory controller to ensure the objectivity and availability of the labels. The sources of the labels include final failure labels, voltage prediction error labels, and bit error rate degradation labels. The final failure label indicates the final marked state of the block. The voltage prediction error label is represented by the normalized value of |ΔV_predicted - ΔV_actual| in the historical data, where ΔV_actual represents the actual voltage at the time of successful decoding. The bit error rate degradation label is represented by the slope of the original bit error rate as it increases with the number of erase / write cycles or time. S34. Preset early warning threshold θ, and calculate Health_Score in real time for each block being read; If Health_Score < θ, the system classifies the block as a high-risk block and immediately triggers an active handling process, including: 1) Early warning reporting: Record high-risk block information in the firmware log; 2) Data migration: Start a background task to migrate all valid data in this block to a reserved healthy free block; 3) Block isolation: After the data migration is completed, the high-risk block is marked as "retired" or "read-only" and will no longer be used to store new data.

[0009] Based on the first aspect, step S4 specifically includes the following steps: S41. After the read operation, the system encapsulates the relevant data of this operation into an experience tuple and stores it in a circular buffer database. The experience tuple includes input features, execution actions, and result feedback. The input features represent the feature vector X that triggered this operation; the execution actions represent the final read voltage offset ΔV_used; and the result feedback represents the result label of this operation. S42. After the system is idle in the background or the number of accumulated experience tuples reaches a first preset threshold, it starts an online learning loop, including: 1) Data sampling: Randomly sample a small batch of empirical data from the circular buffer database; 2) Loss calculation: The difference between ΔV_predicted and ΔV_actual in the model is calculated using the mean squared error (MSE). Loss = MSE(ΔV_predicted, ΔV_actual); 3) Parameter update: Using the gradient descent algorithm, the error is backpropagated at a learning rate lower than the second preset threshold to update the weight parameters W and bias b of the neural network model. S43. If a new batch or a new process NAND Flash chip is encountered, the system executes a transfer learning process, including: 1) Model loading: The system loads a general neural network model pre-trained on historical chip data as the initial model; 2) Small amount of data collection: In the initial stage of running on the new chip, the system collects a first preset number of read failure cases and their corresponding successful voltage data to form a new device adaptation dataset; 3) Targeted fine-tuning: Adapt the dataset to the new device and perform step S42 on the last all layers or the second preset number of layers of the initial model; 4) Rapid deployment: After targeted fine-tuning over a preset time, the initial model can be accurately adapted to the new chip, enabling it to be used out of the box.

[0010] Secondly, this application discloses an artificial intelligence-based dynamic adaptive NAND Flash reading system, which, when applied to the aforementioned artificial intelligence-based dynamic adaptive NAND Flash reading method, includes: The neural network model inference and voltage prediction module is used to construct feature vectors and perform preprocessing, which are then input into a pre-trained neural network model for voltage prediction. The log-likelihood ratio calculation module is used to perform fine sampling based on the predicted voltage, reconstruct the accurate threshold voltage distribution, and calculate the log-likelihood ratio. The health score acquisition and early warning module is used to predict voltage and assess the long-term health status of the block, enabling early warning of bad blocks. The online transfer learning and model adaptation module enables neural network models to quickly adapt to new environments using a small amount of new data.

[0011] Thirdly, this application discloses a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the method described above.

[0012] Fourthly, this application discloses an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method described above.

[0013] The beneficial effects of this invention are: 1) This application uses AI to accurately predict and reduce the number of voltage retries from an average of 5.8 times to 1.3 times, thereby reducing the read latency from about 500μs to 190μs and improving the real-time performance of the system.

[0014] 2) This application reduces the number of LDPC iterations to 4.7 by optimizing the log-likelihood ratio LLR, a reduction of 49%, which directly reduces the computational load and reduces the related power consumption by 38%.

[0015] 3) Improve reliability and lifespan. Early warning of bad blocks (94% accuracy) prevents data loss before it occurs. Dynamic read interference suppression reduces the write amplification factor (WAF) to 1.26, reducing unnecessary write wear and improving overall yield by 7.2%.

[0016] 4) The online learning framework enables the system to maintain high accuracy (ΔV prediction error <12mV) over an extremely wide temperature range (-40℃~125℃) and can quickly adapt to new processes, solving the core pain point of insufficient generalization of traditional solutions. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating the AI-based dynamic adaptive NAND Flash reading method according to an embodiment of the present invention. Detailed Implementation

[0018] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] This application discloses a dynamic adaptive NAND Flash reading method, system, medium, and device based on artificial intelligence, which is used to solve the problems of high-density NAND flash in the prior art. Flash memory (such as QLC and PLC) faces reliability, latency, and energy efficiency bottlenecks in complex real-world applications, including: 1) Static parameter adaptability defects: Traditional solutions relying on preset static voltage adjustment tables cannot dynamically adapt to changes in temperature, device aging, and data retention time, leading to inaccurate reference voltage readings; 2) Excessive latency from multiple voltage retries: Due to inaccurate voltages, multiple attempts at different voltages are required for reading (voltage retries), significantly increasing read latency; 3) Wasted resources in soft-decision decoding: Due to the high error rate of raw data, soft-decision decoders (such as LDPC) require multiple iterations to correct errors, consuming significant computational resources and time, and increasing power consumption; 4) Lagging bad block management: Traditional bad block management can only mark bad blocks after the memory cell has completely failed, making it impossible to predict and intervene in advance, resulting in a high risk of data loss; 5) Accumulated read interference: Read operations can interfere with neighboring cells, and frequent reads can lead to error accumulation. Traditional solutions lack effective dynamic suppression methods; 6) Insufficient cross-scenario generalization: Optimized parameters for specific batches or manufacturing processes cannot be quickly migrated to new chips, requiring lengthy recalibration for each new production run. This invention aims to fundamentally replace the traditional static ΔV meter solution by using an artificial intelligence dynamic prediction system to accurately predict the optimal read voltage for each block, and even each page, in real time. Based on this, a complete dynamic adaptive read management system is constructed to achieve the following functions: 1) significantly reducing voltage retries and lowering read latency; 2) providing high-quality soft information, reducing LDPC iterations and lowering power consumption; 3) enabling early prediction and active isolation of bad blocks, improving reliability and yield; 4) possessing self-learning capabilities, enabling rapid adaptation to new processes and chips. A flowchart of the method is shown below. Figure 1 As shown, the method includes the following steps: S1. Initiate a read request, read page data using the default voltage, decode it using the LDPC algorithm, construct a feature vector and perform preprocessing, then input it into a pre-trained neural network model for voltage prediction; LDPC algorithm is an advanced error correction code algorithm used to correct data errors in NAND Flash, usually using soft decision decoding, which has powerful performance but complex computation. S2. Based on the voltage predicted in step S1, perform fine sampling to reconstruct the accurate threshold voltage distribution and calculate the log-likelihood ratio. S3. Design a shared underlying backbone network so that the neural network model in step S1 has two independent output branches for predicting voltage and evaluating the long-term health status of the block, thereby achieving early warning of bad blocks. S4. Design an online transfer learning mechanism to enable the neural network model in step S1 to quickly adapt to a new environment using a small amount of new data.

[0020] For example, step S1 specifically includes the following steps: S11. If the initial read of the target page fails, the system immediately constructs a feature vector X to reflect the current specific block and specific conditions. The specific block represents the block where the target page is located, and the specific conditions represent the real-time environment and operating state that affect the threshold voltage of the block. The feature vector X includes the real-time chip temperature T, the cumulative erase / write count N_pe, the data retention time T_ret, the recent read interference count N_read, the historical successful read voltage V_read_hist, and the historical raw bit error rate RBER_hist. The real-time chip temperature T is obtained through a built-in temperature sensor, and its unit is degrees Celsius (°C). Temperature changes are a key environmental factor that causes threshold voltage drift. The cumulative erase / write count N_pe is read from the metadata area of ​​the flash memory controller and refers to the number of complete erase-write cycles that the block has undergone since its use. This value directly reflects the wear and aging degree of the storage cell; the data retention time T_ret is calculated by the system real-time clock and the last programmed timestamp recorded in the metadata, and its unit is hours (h). Charge leakage over time is a major cause of threshold voltage drift; the recent read interference count N_read records the total number of times the block has been read in the recent time window, reflecting the cumulative impact of read interference stress on the threshold voltage; the historical successful read voltage V_read_hist calculates the moving average of the voltage used in the most recent (e.g., 10) successful read operations of the block, and its unit is millivolts (mV). It reflects the long-term drift trend of the threshold voltage of the block; the historical raw bit error rate RBER_hist records the raw bit error rate value when the block was last successfully decoded, serving as an indirect indicator of channel quality and cell health status; S12. Standardize the feature vector constructed in step S11 by X_normalized = (X - X_mean) / X_std to obtain the standardized feature vector X_normalized, where X_mean represents the feature mean and X_std represents the feature standard deviation. S13. Input the standardized feature vector X_normalized into the pre-trained neural network model, and calculate the voltage offset ΔV_predicted through nonlinear transformation; in this embodiment, a three-layer network is used for calculation, and the calculation process is as follows: First hidden feature: h1 = ReLU(W1*X_normalized + b1); Second hidden feature: h2 = ReLU(W2* h1 + b2); Output layer: ΔV_predicted = W3*h2 + b3; Where: W1, W2, W3 are the weight matrices of each layer obtained from model training; b1, b2, b3 are the corresponding bias vectors; ReLU is the rectified linear unit activation function, which is expressed as ReLU(x) = max(0, x), used to introduce nonlinearity so that the model can learn complex mapping relationships; S14. Based on a preset scaling factor, denormalize ΔV_predicted to obtain the denormalized voltage offset ΔV_predicted'. Then, add it to the default read voltage V_default to generate the final read voltage V_opt, which is then used to reread the target page. The denormalized voltage offset ΔV_predicted' is a voltage value with actual physical meaning (in mV).

[0021] For example, to improve the efficiency of subsequent LDPC soft-decision decoding, fine sampling is performed based on the predicted voltage to reconstruct the accurate threshold voltage distribution, and high-reliability soft information (log-likelihood ratio LLR) is calculated accordingly. Step S2 specifically includes the following steps: S21. Fine sampling centered on the predicted voltage: Taking the final read voltage V_opt obtained in step S14 as the center point, sampling points are set in its neighborhood with a voltage interval ΔV_step. In this embodiment, the voltage interval ΔV_step can be set to 5mV. The controller uses these voltage values ​​to sample and read the same page multiple times in sequence, and records the original data of each read. S22. Based on the sampled voltage V_i obtained in step S21, count the number of memory cells judged as logic '1' (Count_1(V_i)) and the number of memory cells judged as logic '0' (Count_0(V_i)) in the entire page; using non-parametric methods such as kernel density estimation, fit two smooth and continuous conditional probability density function curves f(V | S=0) and f(V | S=1), where f(V | S=0) represents the probability density of the threshold voltage measurement value V when the stored data is actually '0', and f(V | S=1) represents the probability density of the threshold voltage measurement value V when the stored data is actually '1'; this step transforms discrete statistical data into a continuous probability distribution, laying the foundation for accurate LLR calculation; S23. Calculate the log-likelihood ratio LLR(V) using the formula LLR(V) = ln [ f(V | S=0) / f(V | S=1) ], where ln represents the natural logarithm function. The sign of the LLR value indicates whether the bit is '0' (positive) or '1' (negative), and its absolute value indicates the reliability of the judgment. The LLR calculated based on the accurate distribution of the threshold voltage Vt has a much higher reliability than traditional estimates based on an ideal Gaussian distribution, greatly helping the LDPC decoder to converge quickly. The log-likelihood ratio (LLR) is a type of soft information used in soft-decision decoding, representing the confidence level of whether a bit is 0 or 1. The more accurate the LLR, the higher the decoding efficiency.

[0022] For example, step S3 specifically includes the following steps: S31. The shared underlying backbone network includes multiple hidden layers, and the output branches include a health score head and a ΔV prediction head. The shared underlying backbone network extracts feature representations from the input feature vector X through the hidden layers. These features are the common basis for voltage prediction and health assessment. Then, they are input into the health score head and the ΔV prediction head. The health score head outputs a block health status score Health_Score, and the ΔV prediction head outputs a voltage offset ΔV_predicted. The ΔV prediction head is a regression task branch that is connected after the backbone network. The health score head is a classification or regression task branch that is output in parallel with the ΔV prediction head. S32. The block health status score Health_Score output by the health score head is limited to the range (0, 1) by using the Sigmoid activation function. Health_Score = Sigmoid(W_h · h_shared + b_h); where h_shared represents the feature representation extracted from the input feature vector X by the hidden layer of the shared underlying backbone network; W_h represents the weight of the health score head, and b_h represents the bias parameter of the health score head; the Sigmoid function maps continuous values ​​to the (0,1) interval, the closer the score is to 1, the healthier it is, and the closer it is to 0, the higher the risk of failure; S33. The health labels required for model training are not manually labeled. They are obtained through internal monitoring data of the flash memory controller, ensuring the objectivity and availability of the labels. The sources of the labels include final failure labels, voltage prediction error labels, and bit error rate degradation labels. The final failure label indicates the final marked state of the block, including bad blocks (label 0) or always remaining normal (label 1). The voltage prediction error label is represented by the normalized value of |ΔV_predicted - ΔV_actual| from historical data. The larger the error, the lower the health score. ΔV_actual represents the actual voltage at the time of successful decoding. The bit error rate degradation label is represented by the slope of the original bit error rate as it increases with the number of erase / write cycles or time. The faster the degradation, the lower the health score. S34. Preset early warning threshold θ (e.g., 0.5), and calculate Health_Score in real time for each block being read; If Health_Score < θ, the system classifies the block as a high-risk block and immediately triggers an active handling process, including: 1) Early warning reporting: Record high-risk block information in the firmware log; 2) Data migration: Start a background task to migrate all valid data in this block to a reserved healthy free block; 3) Block isolation: After the data migration is completed, the high-risk block is marked as "retired" or "read-only" and will no longer be used to store new data; This mechanism enables a shift from "passively responding to failures" to "actively preventing failures," significantly improving data reliability and the overall yield of the storage array.

[0023] For example, to achieve rapid adaptation of NAND Flash chips across different batches and process nodes, and to enable continuous system optimization throughout its lifecycle, an online transfer learning framework is introduced. This framework allows pre-trained neural network models to quickly adapt to new environments using a small amount of new data, without the time-consuming and costly process of training from scratch. Step S4 specifically includes the following steps: S41. After the read operation, the system encapsulates the relevant data of this operation into an empirical tuple and stores it in a circular buffer database (empirical playback cache). The empirical tuple includes input features, execution actions, and result feedback. The input features represent the feature vector X that triggered this operation; the execution actions represent the final read voltage offset ΔV_used; and the result feedback represents the result label of this operation, such as: LDPC decoding successful, LDPC decoding failed; the number of LDPC iterations required for successful decoding; and the actual voltage ΔV_actual at the time of successful decoding (estimated through a small amount of additional sampling). S42. After the system is idle in the background or the number of accumulated experience tuples reaches a first preset threshold, it starts an online learning loop, including: 1) Data sampling: Randomly sample a small batch of empirical data from the circular buffer database; 2) Loss calculation: The difference between ΔV_predicted and ΔV_actual in the model is calculated using the mean squared error (MSE). Loss = MSE(ΔV_predicted, ΔV_actual); 3) Parameter update: Use gradient descent algorithm (such as Adam optimizer) to backpropagate the error at a learning rate lower than the second preset threshold to update the weight parameters W and bias b of the neural network model (mainly the ΔV prediction head); the use of small learning rate and random sampling is to avoid the model "forgetting" the general knowledge it has learned and to ensure the stability of learning. S43. If a new batch or a new process NAND Flash chip is encountered, the system executes a transfer learning process, including: 1) Model loading: The system loads a general neural network model pre-trained on historical chip data as the initial model; 2) Small amount of data collection: In the initial stage of running on the new chip, the system collects a first preset number of read failure cases and their corresponding successful voltage data to form a new device adaptation dataset; 3) Targeted fine-tuning: Adapt the dataset to the new device and perform step S42 on all the last layers or the second preset number of layers of the initial model (especially the ΔV prediction head); 4) Rapid deployment: After targeted fine-tuning within a preset time (usually 48 hours), the initial model can be accurately adapted to the new chip, achieving high performance out of the box; This mechanism ensures that the core AI capabilities of this invention have strong generalization and practicality, and can continue to evolve with the rapid iteration of NAND Flash technology.

[0024] For example, consider a scenario involving reading a 256-layer 3D NAND Flash: Triggering condition: The host requests to read data from Block 1005, Page 253. The controller reads the page using the default voltage, but the low-density parity check (LDPC) decoder reports an error that cannot be corrected, and the first read fails.

[0025] Feature Extraction: The system immediately initiates the artificial intelligence prediction process. The current chip temperature is read from the temperature sensor as 85℃. The erase / write cycles for Block 1005 are read from the metadata area as 3050. The average read voltage value for the last 10 reads of this block is recorded as XV. The data retention time for this page (i.e., the time since the last write) is 30 days.

[0026] Artificial intelligence inference: The above features (temperature = 85℃, erase / write cycles = 3050, average read voltage = XV, retention time = 30 days) are input into a pre-trained Long Short-Term Memory (LSTM) network model. The model quickly infers the current optimal voltage offset ΔV = +45mV.

[0027] Voltage retry: The controller adjusts the reference voltage to the default value of +45mV and reads the page again. This time, the data is sent to the LDPC decoder, and error correction is successful after only 3 iterations, and the data is read correctly.

[0028] Learning and updating: The system records this successful case (feature value + final successful voltage value) at the end of the training dataset for online fine-tuning of the subsequent model, making the prediction more and more accurate over time.

[0029] This embodiment demonstrates how the present invention transforms a failed read into a highly efficient successful read through AI dynamic prediction, avoiding multiple blind voltage retries and significantly reducing latency and power consumption.

[0030] This application also discloses an AI-based dynamic adaptive NAND Flash reading system, which applies the aforementioned AI-based dynamic adaptive NAND Flash reading method, including: The neural network model inference and voltage prediction module is used to construct feature vectors and perform preprocessing, which are then input into a pre-trained neural network model for voltage prediction. The log-likelihood ratio calculation module is used to perform fine sampling based on the predicted voltage, reconstruct the accurate threshold voltage distribution, and calculate the log-likelihood ratio. The health score acquisition and early warning module is used to predict voltage and assess the long-term health status of the block, enabling early warning of bad blocks. The online transfer learning and model adaptation module enables neural network models to quickly adapt to new environments using a small amount of new data.

[0031] By way of example, the present invention also provides a computer-readable storage medium storing a computer program, wherein the computer program is configured to perform the steps in any of the above method embodiments when it is run.

[0032] For example, the aforementioned computer-readable storage media may include, but are not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0033] By way of example, the present invention also provides an electronic device including a memory and a processor, the memory storing a computer program and the processor being configured to run the computer program to perform the steps in any of the above method embodiments.

[0034] For example, the above-mentioned electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0035] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A dynamic adaptive NAND Flash read method based on artificial intelligence, characterized in that, Includes the following steps: S1. Initiate a read request, read page data using the default voltage, decode it using the LDPC algorithm, construct a feature vector and preprocess it, then input it into a pre-trained neural network model for voltage prediction; S2. Based on the voltage predicted in step S1, perform fine sampling to reconstruct the accurate threshold voltage distribution and calculate the log-likelihood ratio. S3. Design a shared underlying backbone network so that the neural network model in step S1 has two independent output branches for predicting voltage and evaluating the long-term health status of the block, thereby achieving early warning of bad blocks. S4. Design an online transfer learning mechanism to enable the neural network model in step S1 to quickly adapt to a new environment using a small amount of new data.

2. The AI-based dynamic adaptive NAND Flash read method according to claim 1, characterized in that, Step S1 specifically includes the following steps: S11. If the first read of the target page fails, the system immediately constructs a feature vector X to reflect the current specific block and specific conditions. The specific block represents the block where the target page is located, and the specific conditions represent the real-time environment and working state that affect the threshold voltage of the block. The feature vector X includes the real-time chip temperature T, the cumulative number of erase and write operations N_pe, the data retention time T_ret, the recent read interference count N_read, the historical successful read voltage V_read_hist, and the historical raw bit error rate RBER_hist. S12. Standardize the feature vector constructed in step S11 to X_normalized = (X - X_mean) / X_std, and obtain the standardized feature vector X_normalized, where X_mean represents the feature mean and X_std represents the feature standard deviation. S13. Input the standardized feature vector X_normalized into the pre-trained neural network model, and calculate the voltage offset ΔV_predicted through nonlinear transformation; S14. Based on the preset scaling factor, denormalize ΔV_predicted to obtain the denormalized voltage offset ΔV_predicted'. Then add it to the default read voltage V_default to generate the final read voltage V_opt, and use it to reread the target page.

3. The AI-based dynamic adaptive NAND Flash read method according to claim 2, characterized in that, Step S2 specifically includes the following steps: S21. Fine sampling centered on the predicted voltage: with the final read voltage V_opt obtained in step S14 as the center point, sampling points are set in its neighborhood with voltage interval ΔV_step. The controller uses these voltage values ​​to sample and read the same page multiple times in sequence, and records the original data of each read. S22. Based on the sampled voltage V_i obtained in step S21, count the number of memory cells judged as logic '1' (Count_1(V_i)) and the number of memory cells judged as logic '0' (Count_0(V_i)) in the entire page; use kernel density estimation to fit the conditional probability density function curves f(V | S=0) and f(V | S=1), where f(V | S=0) represents the probability density of the threshold voltage measurement value V when the stored data is actually '0', and f(V | S=1) represents the probability density of the threshold voltage measurement value V when the stored data is actually '1'. S23. Calculate the log-likelihood ratio LLR(V) using the formula LLR(V) = ln [ f(V | S=0) / f(V | S=1) ], where ln represents the natural logarithm function.

4. The AI-based dynamic adaptive NAND Flash read method according to claim 3, characterized in that, Step S3 specifically includes the following steps: S31. The shared underlying backbone network includes multiple hidden layers, and the output branch includes a health score head and a ΔV prediction head. The shared underlying backbone network extracts feature representations from the input feature vector X through the hidden layers, and then inputs them into the health score head and the ΔV prediction head. The health score head outputs a block health status score Health_Score, and the ΔV prediction head outputs a voltage offset ΔV_predicted. The health score head and the ΔV prediction head are output in parallel. S32. The block health status score Health_Score output by the health score head is limited to the range (0, 1) by using the Sigmoid activation function. Health_Score = Sigmoid(W_h · h_shared + b_h); where h_shared represents the feature representation extracted from the input feature vector X by the hidden layer of the shared underlying backbone network; W_h represents the weight of the health score head; and b_h represents the bias parameter of the health score head. S33. Obtain the health labels required for model training through the internal monitoring data of the flash memory controller to ensure the objectivity and availability of the labels. The sources of the labels include final failure labels, voltage prediction error labels, and bit error rate degradation labels. The final failure label indicates the final marked state of the block. The voltage prediction error label is represented by the normalized value of |ΔV_predicted - ΔV_actual| in the historical data, where ΔV_actual represents the actual voltage at the time of successful decoding. The bit error rate degradation label is represented by the slope of the original bit error rate as it increases with the number of erase / write cycles or time. S34. Preset early warning threshold θ, and calculate Health_Score in real time for each block being read; If Health_Score < θ, the system classifies the block as a high-risk block and immediately triggers an active handling process, including: 1) Early warning reporting: Record high-risk block information in the firmware log; 2) Data migration: Start a background task to migrate all valid data in this block to a reserved healthy free block; 3) Block isolation: After the data migration is completed, the high-risk block is marked as "retired" or "read-only" and will no longer be used to store new data.

5. The AI-based dynamic adaptive NAND Flash read method according to claim 4, characterized in that, Step S4 specifically includes the following steps: S41. After the read operation, the system encapsulates the relevant data of this operation into an experience tuple and stores it in a circular buffer database. The experience tuple includes input features, execution actions, and result feedback. The input features represent the feature vector X that triggered this operation; the execution actions represent the final read voltage offset ΔV_used; and the result feedback represents the result label of this operation. S42. After the system is idle in the background or the number of accumulated experience tuples reaches a first preset threshold, it starts an online learning loop, including: 1) Data sampling: Randomly sample a small batch of empirical data from the circular buffer database; 2) Loss calculation: The difference between ΔV_predicted and ΔV_actual in the model is calculated using the mean squared error (MSE). Loss = MSE(ΔV_predicted, ΔV_actual); 3) Parameter update: Using the gradient descent algorithm, the error is backpropagated at a learning rate lower than the second preset threshold to update the weight parameters W and bias b of the neural network model. S43. If a new batch or a new process NAND Flash chip is encountered, the system executes a transfer learning process, including: 1) Model loading: The system loads a general neural network model pre-trained on historical chip data as the initial model; 2) Small amount of data collection: In the initial stage of running on the new chip, the system collects a first preset number of read failure cases and their corresponding successful voltage data to form a new device adaptation dataset; 3) Targeted fine-tuning: Adapt the dataset to the new device and perform step S42 on the last all layers or the second preset number of layers of the initial model; 4) Rapid deployment: After targeted fine-tuning over a preset time, the initial model can be accurately adapted to the new chip, enabling it to be used out of the box.

6. An AI-based dynamic adaptive NAND Flash read system, employing the AI-based dynamic adaptive NAND Flash read method according to any one of claims 1-5, characterized in that, include: The neural network model inference and voltage prediction module is used to construct feature vectors and perform preprocessing, which are then input into a pre-trained neural network model for voltage prediction. The log-likelihood ratio calculation module is used to perform fine sampling based on the predicted voltage, reconstruct the accurate threshold voltage distribution, and calculate the log-likelihood ratio. The health score acquisition and early warning module is used to predict voltage and assess the long-term health status of the block, enabling early warning of bad blocks. The online transfer learning and model adaptation module enables neural network models to quickly adapt to new environments using a small amount of new data.

7. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the method according to any one of claims 1-5.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, it implements the method according to any one of claims 1-5.

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