System and method for providing multiple code rates across resource units in communication system

Abstract

The disclosure relates to systems and methods for providing multiple code rates across resource units in a communication system. In some embodiments, an apparatus may include a transmitter and one or more processors. The one or more processors may identify a plurality of resource units (RUs) for transmitting respective data streams within one or more wireless channels. The one or more processors may determine respective target code rates for the plurality of RUs based at least on signal quality differences between transmissions across the plurality of RUs. The respective target code rates may be different from each other and from a base code rate of a low density parity check (LDPC) code. The one or more processors may encode, by an LDPC encoder, the respective data streams using the LDPC code having the base code rate to generate respective encoded data streams at the respective target code rate. The transmitter may transmit the respective encoded data streams using the plurality of respective RUs.

Description

[0001] Cross-reference of related applications

[0002] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 651,710, filed May 24, 2024, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] This disclosure generally relates to systems and methods for improving the encoding / decoding process of a communication system, including but not limited to systems and methods for providing multiple code rates on resource units (RUs) in a communication system for interference mitigation. Background Technology

[0004] Error correction codes enable the reliable exchange of information data between a transmitter communication system and a receiver communication system. The transmitter communication system encodes the information data to obtain codewords. A codeword is the encoded information data. The transmitter communication system transmits the codeword to the receiver communication system. Due to noise in the communication channel, the transmission received by the receiver communication system may differ from the transmitted codeword. Encoding the information data allows the receiver communication system, with an appropriate decoding process, to recover the information data from the received transmission even in the presence of this noise. For example, the transmitter communication system transmits a parity bit to the receiver communication system. The parity bit allows the receiver communication system to verify whether the received transmission is a valid codeword and to correct errors in the transmission if the received transmission is not a valid codeword. In one approach, generating the parity bit involves a complex process. Summary of the Invention

[0005] On one hand, this disclosure provides an apparatus comprising: a transmitter and one or more processors, wherein the one or more processors are configured to: identify a plurality of RUs for transmitting corresponding data streams in one or more wireless channels; determine corresponding target code rates for the plurality of RUs based at least on signal quality differences between transmissions across the plurality of RUs, wherein the corresponding target code rates are different from each other and different from the basic code rate of a low-density parity-check (LDPC) code; and encode the corresponding data streams using the LDPC code having the basic code rate via an LDPC encoder to generate corresponding encoded data streams at the corresponding target code rates; and wherein the transmitter is configured to transmit the corresponding encoded data streams using the plurality of corresponding RUs.

[0006] On the other hand, this disclosure provides a method comprising: identifying, by one or more processors, a plurality of RUs for transmitting a corresponding data stream in one or more wireless channels; determining, by the one or more processors, a corresponding target code rate for the plurality of RUs based at least on signal quality differences between transmissions across the plurality of RUs, wherein the corresponding target code rates are different from each other and different from the base code rate of an LDPC code; encoding the corresponding data streams using the LDPC code having the base code rate by an LDPC encoder to generate a corresponding encoded data stream at the corresponding target code rate; and transmitting the corresponding encoded data streams using the corresponding RUs by a transmitter.

[0007] On the other hand, this disclosure provides an apparatus comprising: a transmitter and one or more processors, wherein the one or more processors are configured to: identify a plurality of RUs for transmitting a corresponding data stream in one or more wireless channels; determine a corresponding number of bits for the plurality of RUs based at least on signal quality differences between transmissions across the plurality of RUs, wherein the corresponding number of bits is different from each other; and modulate the corresponding data stream using the corresponding number of bits to generate a corresponding modulated data stream, wherein the transmitter is configured to transmit the corresponding modulated data stream using the corresponding RU. Attached Figure Description

[0008] The various objectives, aspects, features, and advantages of this disclosure will become more apparent and better understood through a detailed description taken in conjunction with the accompanying drawings, in which similar reference numerals identify corresponding elements throughout. In the drawings, similar reference numerals generally indicate identical, functionally similar, and / or structurally similar elements.

[0009] Figure 1 It is a diagram depicting an instance communication environment having a communication system according to one or more embodiments.

[0010] Figure 2 It is a schematic block diagram of a computing system according to one or more embodiments.

[0011] Figure 3 It is a graph depicting an instance index matrix according to one or more embodiments.

[0012] Figure 4 It is a diagram depicting an instance shifted identity matrix according to one or more embodiments for generating a parity check matrix.

[0013] Figure 5 It is a graph depicting an instance parity check matrix according to one or more embodiments.

[0014] Figure 6 It is a graph depicting an instance index matrix according to one or more embodiments.

[0015] Figure 7It is a diagram depicting the structure of groups according to one or more implementation schemes.

[0016] Figure 8 It is a diagram depicting the allocation structure of resource units (RUs) in a 20MHz bandwidth according to one or more implementation schemes.

[0017] Figure 9 It is a diagram depicting different modulation and coding configurations across different RUs according to one or more embodiments.

[0018] Figure 10 It is a diagram depicting an instance coding and modulation system across an RU according to one or more embodiments.

[0019] Figure 11A and Figure 11B It is a diagram depicting instance parameters of different multi-rate LDPC codes according to one or more embodiments.

[0020] Figure 12A and Figure 12B It is a block diagram depicting instance input and output parameters for a multi-rate LDPC code according to one or more embodiments.

[0021] Figures 13A to 13C It is a diagram depicting an instance of data segmentation by a Media Access Control (MAC) layer or a Physical (PHY) layer according to one or more embodiments.

[0022] Figure 14 It is a diagram depicting an example process of encoding data at two bit rates using a single LDPC encoder according to one or more embodiments.

[0023] Figure 15 It is a diagram depicting an instance process of encoding data at two rates based on different code block lengths using different LDPC encoders according to one or more embodiments.

[0024] Figure 16 It is a diagram depicting another instance of the process of encoding data at two rates based on different code block lengths using different LDPC encoders according to one or more embodiments.

[0025] Figure 17 This is a flowchart illustrating a process for providing multiple bitrates across RUs according to an embodiment.

[0026] Details of various embodiments of the method and system are set forth in the accompanying drawings and the following description. Detailed Implementation

[0027] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, a first feature communicating or communicatively coupled to a second feature may include embodiments in which the first feature directly communicates with or is directly coupled to the second feature, and may also include embodiments in which an additional feature may intervene between the first and second features, such that the first feature indirectly communicates with or is indirectly coupled to the second feature. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0028] Although the various embodiments disclosed herein are described as encoding and / or decoding data for wireless communication (e.g., wireless local area networks (WLANs) conforming to any IEEE 802.11 standard, including IEEE 802.11bn), the principles disclosed herein are applicable to other types of communication (e.g., wired communication) or any process performing encoding for error correction codes (e.g., low-density parity-check (LDPC) codes, forward error correction (FEC) codes).

[0029] I. LDPC-based encoding / decoding system

[0030] Typically, the parity matrix of the code represents an equation for determining whether an error has occurred during transmission. More formally, for all valid codewords (i.e., bits generated error-free by the encoder), the following equation holds:

[0031] Hc=0……………(Equation 1)

[0032] In Equation 1, "H" is the parity check matrix, "c" is the codeword vector, and "0" is an all-zero vector. The parity check matrix H is a way of describing codes.

[0033] The generation matrix G of the code satisfies the following equation:

[0034] sG=c……………(Equation 2)

[0035] In Equation 2, "s" is the information bit vector, "G" is the generator matrix, and "c" is the codeword corresponding to "s". In some implementations, the system (e.g., containing...) Figure 1 The communication system 108 of the decoder 160 can use Equation 2 to decode the codeword c to obtain the decoded data s.

[0036] The parity check matrix and generator matrix of the code are related according to the matrix equations described above. Generally, if the parity check matrix is ​​low-density, the corresponding generator matrix will be high-density, and vice versa. Therefore, LDPC codes are characterized by a low-density parity check matrix and a high-density generator matrix. The density of the matrix is ​​related to the number of operations required to implement one of the above equations. Although it was recognized by 1995 that LDPC codes could be used to transmit data with very few errors (i.e., with an error rate as good as or better than turbo codes), a drawback of LDPC codes is that their generator matrices are high-density, making the encoding computationally intensive and impractical for many applications.

[0037] In some implementations, the parity check matrix may have a quasi-cyclic structure, such as the parity check matrix of a QC-LDPC code (n = 3888, k = 2916, R = 3 / 4). For example, given the lift size z, the parity check matrix may have multiple submatrices such that each submatrix is ​​a cyclically shifted version of an identity matrix of size (z x z), where z = 162. In some implementations, the lift may be performed in a hierarchical manner, where the lift is 162 / W, and then W, where W is an integer, to achieve an overall lift of 162. The parity check matrix can be represented in two equivalent forms: (1) a parity check matrix H and (2) a block matrix or exponential matrix P = E(H).

[0038] In some implementations, the parity check matrix H can be a binary matrix of size m x n (where each of m and n is an integer). The elements of the parity check matrix are binary values. Given the block length n and the code rate R, the LDPC code (or QC-LDPC code) LDPC(n,R) satisfies the following equation:

[0039] k = nR……………(Equation 3)

[0040] m=n(1-R)……………(Equation 4)

[0041] In some embodiments, a block matrix or an exponent matrix (QC-LDPC exponent matrix) can be obtained. Given the lifting size z, the exponent matrix P = E(H) can have a size of m / z x n / z. If n = 24z (e.g., n = 3888, z = 162), then the size of P = E(H) is 24(1 - R) x 24 (= n(1 - R) / z x n / z). The elements of the exponent matrix can be integer values corresponding to the cyclic shift values of an identity matrix of size z x z. The parity-check matrix H can be a sparse binary matrix that can be derived from the exponent matrix P = E(H). The generator matrix G can have a size of n x k in binary form (e.g., the elements of the generator matrix G are binary values). The exponent matrix P = E(H) can have a structure that includes multiple sub-matrices (e.g., A, B, C, D, E, T).

[0042] In some embodiments, a binary QC-LDPC code LDPC(n,R) can be characterized by the null space of an n(1-R) x n parity-check matrix H. The parity-check matrix H can be a binary sparse matrix that includes a set of circulant matrices of size z x z. The parity-check matrix H of the QC-LDPC code can be equivalently represented by an exponent matrix P = E(H). This representation can help illustrate the graphical structure of the underlying code as a base graph and shift coefficients.

[0043] In some embodiments, the parity-check matrix H can be generated from the exponent matrix P = E(H). The exponent matrix P = E(H) can include shift values d (as elements) in the range 0 <= d < z and d = -1. For example, if z = 7, then the shift values d can include –1, 0, 1, 2, 3, 4, 5, 6. The shift value d = 0 can correspond to (or map to) an identity matrix of size z x z represented by I(z). The shift value d = -1 can correspond to (or map to) a zero matrix of size z x z represented by 0*I(z) (all elements are 0). Any other integer value d in [1, z - 1] can correspond to (or map to) a matrix that is cyclically right-shifted from I(z). The parity-check matrix H can be obtained from the exponent matrix P = E(H) by expanding the exponent matrix such that each element (as the shift value d) of the exponent matrix is replaced by a matrix corresponding to the shift value.

[0044] In some embodiments, the exponent matrix P = E(H) can include multiple elements The multiple elements correspond to values, where and satisfy the following equation:

[0045]

[0046] The exponential matrix (or permutation matrix) P = E(H) can be represented as follows:

[0047]

[0048] The parity check matrix H can be obtained by replacing each element of the matrix with a matrix C(d) corresponding to the shift value (as the shift value d):

[0049]

[0050] For example, matrix C(1) can be represented as follows:

[0051]

[0052] In some implementations, the encoder may use a generator matrix (e.g., using Equation 2) to generate codewords. In some implementations, the encoder may use a parity check matrix (instead of a generator matrix) to generate codewords from the information bit vector. After obtaining the parity check matrix H, the parity check matrix H may have submatrices A, B, C, D, T, and E. The upper region O of the submatrix T may correspond to the region where the matrix contains all zeros, and the other regions may represent positions that may contain 1s.

[0053] In some implementations, the codeword c can be obtained through the following expression:

[0054] c = [s p1 p2]…………(Equation 10),

[0055] Where “s” is the information bit vector to be encoded, “p1” is the vector of the first g parity bits and “p2” is the vector of the remaining mg parity bits.

[0056] Vectors p1 and p2 can be obtained through the following equations:

[0057] Φ=-ET -1 B+D…………(Equation 11);

[0058] p1 T =-Φ -1 (-ET -1 A+C)s T ...(Equation 12); and

[0059] p2 T =-T -1 (As T +Bp1 T (Equation 13).

[0060] Although the various embodiments disclosed herein are described as encoding data for wireless communication (e.g., wireless local area networks (WLANs) conforming to any IEEE 802.11 standard), the principles disclosed herein are applicable to other types of communication (e.g., wired communication) or any process that performs encoding against LDPC codes.

[0061] refer to Figure 1 This illustration depicts an example communication environment 100 including communication systems (or communication devices) 105, 108 according to one or more embodiments. In one embodiment, communication system 105 includes a baseband circuit system 110 and a transmitter circuit system 120, and communication system 108 includes a baseband circuit system 150 and a receiver circuit system 140. On one hand, communication system 105 is considered a transmitter communication system, and communication system 108 is considered a receiver communication system. These components operate together to exchange data (e.g., messages or frames) over a wireless medium. In one or more embodiments, these components are embodied as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or any combination thereof. In some embodiments, communication systems 105, 108 include more than Figure 1 The components shown may include more, fewer, or different components. For example, each of communication systems 105, 108 includes a transceiver circuitry to allow bidirectional communication between or with other communication systems. In some embodiments, each of communication systems 105, 108 may have components similar to... Figure 2 The configuration shown in the image is similar to that of the computing system 2000.

[0062] The baseband circuitry 110 of the communication system 105 is a circuitry system that generates baseband data 115 for transmission. The baseband data 115 contains information data (e.g., signals) at a baseband frequency for transmission. In one method, the baseband circuitry 110 includes an encoder 130 that encodes the data and generates or outputs parity bits. On one hand, the baseband circuitry 110 (or encoder 130) obtains a generator matrix or a parity matrix, or uses a previously generated generator matrix or a previously generated parity matrix, and encodes the information data by applying the information data to the generator matrix or parity matrix to obtain codewords. In some embodiments, the baseband circuitry 110 stores one or more generator matrices or one or more parity matrices conforming to any IEEE 802.11 standard for WLAN communication. The baseband circuitry 110 retrieves the stored generator matrix or the stored parity matrix in response to detecting information data to be transmitted or in response to receiving an instruction to encode the information data. In one method, baseband circuitry 110 generates parity bits based on a portion of a generation matrix or using a parity check matrix, and appends the parity bits to information bits to form a codeword. Baseband circuitry 110 generates baseband data 115 containing the codeword for communication system 108 and provides baseband data 115 to transmitter circuitry 120.

[0063] The transmitter circuitry 120 (generally referred to as a transmitter) of the communication system 105 includes or corresponds to a circuitry that receives baseband data 115 from the baseband circuitry 110 and transmits a wireless signal 125 based on the baseband data 115. In one configuration, the transmitter circuitry 120 is coupled between the baseband circuitry 110 and an antenna (not shown). In this configuration, the transmitter circuitry 120 up-converts the baseband data 115 from the baseband circuitry 110 to a carrier signal to generate a wireless signal 125 at a radio frequency (RF) frequency (e.g., 10 MHz to 60 GHz), and transmits the wireless signal 125 through the antenna.

[0064] The receiver circuitry 140 of communication system 108 is a circuitry that receives radio signal 125 from communication system 105 and obtains baseband data 145 from the received radio signal 125. In one configuration, receiver circuitry 140 is coupled between baseband circuitry 150 and an antenna (not shown). In this configuration, receiver circuitry 140 receives radio signal 125 through the antenna and down-converts the radio signal 125 to an RF frequency according to a carrier signal to obtain baseband data 145 from the radio signal 125. Receiver circuitry 140 then provides the baseband data 145 to baseband circuitry 150.

[0065] The baseband circuitry system 150 of the communication system 108 includes or corresponds to a circuitry system that receives baseband data 145 from the receiver circuitry system 140 and obtains information data from the received baseband data 145. In one embodiment, the baseband circuitry system 150 includes a decoder 160 that extracts information and parity bits from the baseband data 145. The decoder 160 decodes the baseband data 145 to obtain information data generated by the baseband circuitry system 110 of the communication system 105.

[0066] In some implementations, each of the baseband circuit system 110 (including encoder 130), transmitter circuit system 120, receiver circuit system 140, and baseband circuit system 150 (including decoder 160) may be one or more processors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or any combination thereof.

[0067] Figure 2 This is a schematic block diagram of a computing system according to an embodiment. The illustrated example computing system 2000 includes: one or more processors 2010 that communicate directly or indirectly with memory 2060 via a communication system 2040 (e.g., a bus); at least one network interface controller 2030 having a network interface port for connecting to a network (not shown); and other components, such as input / output (“I / O”) components 2050. Typically, the processors 2010 will execute instructions (or computer programs) received from memory. The illustrated processors 2010 are incorporated into or connected to cache memory 2020. In some examples, instructions are read from memory 2060 into cache memory 2020 and executed by processor 2010 from cache memory 2020. The computing system 2000 may not necessarily contain... Figure 2 All of these components shown herein may contain Figure 2 Other components not shown in the image.

[0068] More specifically, processor 2010 may be any logic circuit system that processes instructions (e.g., instructions fetched from memory 2060 or cache 2020). In many embodiments, processor 2010 is a microprocessor unit or a dedicated processor. Computing system 2000 may be based on any processor or processor group capable of operating as described herein. Processor 2010 may be a single-core or multi-core processor. Processor 2010 may be multiple different processors.

[0069] Memory 2060 may be any means suitable for storing computer-readable data. Memory 2060 may be a means with fixed storage or a means for reading removable storage media. Examples include all forms of volatile memory (e.g., RAM), non-volatile memory, media and memory devices, semiconductor memory devices (e.g., EPROM, EEPROM, SDRAM, and flash memory devices), magnetic disks, magneto-optical disks, and optical disks (e.g., CD ROM, DVD-ROM, or Blu-ray ROM). (Optical disc). The computing system 2000 may have any number of memory devices 2060.

[0070] The cache memory 2020 is typically in the form of computer memory placed adjacent to the processor 2010 to achieve fast read times. In some embodiments, the cache memory 2020 is part of the processor 2010, or on the same chip as the processor 2010. In some embodiments, there are multiple levels of cache 2020, such as L2 and L3 cache layers.

[0071] Network interface controller 2030 manages data exchange via network interfaces (sometimes referred to as network interface ports). Network interface controller 2030 handles the physical and data link layers of the OSI model for network communication. In some embodiments, the tasks of some network interface controllers are handled by one or more of the processors 2010. In some embodiments, network interface controller 2030 is part of processor 2010. In some embodiments, computing system 2000 has multiple network interfaces controlled by a single controller 2030. In some embodiments, computing system 2000 has multiple network interface controllers 2030. In some embodiments, each network interface is a connection point of a physical network link (e.g., a Cat-5 Ethernet link). In some embodiments, network interface controller 2030 supports wireless network connectivity and the interface port is a wireless (e.g., radio) receiver or transmitter (e.g., for the IEEE 802.11 protocol, Near Field Communication "NFC", Bluetooth, ANT, or any other wireless protocol). In some embodiments, network interface controller 2030 implements one or more network protocols, such as Ethernet. Typically, the computing system 2000 exchanges data with other computing devices via a network interface through a physical or wireless link. The network interface can be directly linked to another device or linked to another device via an intermediary device (e.g., a network device that connects the computing system 2000 to a data network (e.g., the Internet), such as a hub, bridge, switch, or router).

[0072] The computing system 2000 may include one or more input or output (“I / O”) devices, or provide interfaces thereto. Input devices include, but are not limited to, keyboards, microphones, touchscreens, foot pedals, sensors, MIDI devices, and pointing devices such as mice or trackballs. Output devices include, but are not limited to, video displays, speakers, Braille-enabled terminals, lights, MIDI devices, and 2D or 3D printers.

[0073] Other components may include I / O interfaces, external serial device ports, and any additional coprocessors. For example, computing system 2000 may include interfaces (e.g., a Universal Serial Bus (USB) interface) for connecting input devices, output devices, or additional memory devices (e.g., portable flash drives or external media drives). In some embodiments, computing system 2000 includes additional devices such as coprocessors, for example, a math coprocessor that assists processor 2010 in performing high-precision or complex calculations.

[0074] Component 2090 can be configured to connect to external media, display 2070, input device 2080, or any other component or combination thereof in computing system 2000. Display 2070 can be a liquid crystal display (LCD), organic light-emitting diode (OLED) display, flat panel display, solid-state display, cathode ray tube (CRT) display, projector, printer, or other display device now known or hereafter developed for outputting defined information. Display 2070 can serve as an interface for a user to view the operation of processor 2010, or particularly as an interface to software stored in memory 2060.

[0075] Input device 2080 can be configured to allow a user to interact with any of the components of computing system 2000. Input device 2080 can be a keypad, keyboard, cursor control device such as a mouse or joystick. Furthermore, input device 2080 can be a remote control, touchscreen display (which can be a combination of display 2070 and input device 2080), or any other device operable to interact with computing system 2000, such as any device operable to act as an interface between the user and computing system 2000.

[0076] Figure 3 This is a diagram depicting an instance exponent matrix (QC-LDPC exponent matrix) 300 according to one or more embodiments. Given the lifting size z, the exponent matrix 300 may have a size of m / z x n / z. If n = 24z (e.g., n = 3888, z = 162), then the size of P = E(H) is 24(1-R) ​​x 24 (= n(1-R) / z x n / z). The elements of the exponent matrix may be integer values ​​corresponding to the cyclic shift values ​​of an identity matrix of size z x z. The parity check matrix H (see...) Figure 5) may be a sparse binary matrix derivable from the exponent matrix P = E(H). The generator matrix G may have a size of n x k in binary form (e.g., the elements of the generator matrix G are binary values). Refer to Figure 3 , the exponent matrix P = E(H) may have a structure that includes multiple sub-matrices (e.g., A310, B312, C 316, D 318, E 320, T 314).

[0077] Figure 4 FIG. 400 depicts example shift identity matrices 409, 410, 411, 412, 413, 414, 415, 416 for generating a parity check matrix according to one or more embodiments. The parity check matrix H may be generated from the exponent matrix P = E(H) (e.g., exponent matrix 300) or may be identified using a codebook. As shown in Equation 7, the exponent matrix P = E(H) may include shift values d (as elements) within the range 0 <= d < z and d = -1. For example, referring to the equation, if z = 7, then the shift values d may include -1, 0, 1, 2, 3, 4, 5, 6 (see Figure 4 ). The shift value d = 0 may correspond to (or map to) an identity matrix of size z x z represented by I(z) (e.g., matrix 410). The shift value d = -1 may correspond to (or map to) a zero matrix of size z x z represented by 0*I(z) (all elements are 0) (e.g., matrix 409). Any other integer value d in [1, z - 1] may correspond to (or map to) a matrix that is circularly right-shifted from I(z) (e.g., matrices 411, 412, 413, 414, 415, 416). As shown in Equation 8, the parity check matrix H may be obtained from the exponent matrix P = E(H) by expanding the exponent matrix P such that each element (as the shift value d) of the exponent matrix P is replaced by a matrix corresponding to the shift value.

[0078] Figure 5 FIG. depicts an example parity check matrix 500 according to one or more embodiments. In some embodiments, an encoder (e.g., encoder 130) may generate a codeword using a generator matrix (e.g., using Equation 2). In some embodiments, an encoder (e.g., encoder 130) may use a parity check matrix (instead of a generator matrix) to generate a codeword from an information bit vector. After obtaining the parity check matrix H (e.g., using a codebook), the parity check matrix H (e.g., parity check matrix 500) may have sub-matrices A 510, B 512, C 516, D 518, T 514, E 520. The upper region O 515 of the sub-matrix T 514 (e.g., Figure 5 the white region in ) may correspond to the region where the matrix contains all 0s, and the other regions (e.g., Figure 5The gray area in the diagram can represent a position that may contain 1. The parity check matrix 500 can be of size m x n, where the submatrix D 518 is of size g x g, and the submatrix T is of size (mg) x (mg). In some implementations, given the information bit vector s to be encoded, the encoder can obtain the codeword c using equations 10, 11, 12, and 13.

[0079] Figure 6 This is a diagram depicting an instance exponent matrix (QC-LDPC exponent matrix) 600 according to one or more embodiments. Given the lifting size z, the exponent matrix 600 may have a size of m / z x n / z. If n = 48z (e.g., n = 3888, z = 81), then for n = 3888... The size of the matrix is ​​48(1-R) ​​x 48 (=n(1-R) / z x n / z). The elements of the exponent matrix can be integer values ​​corresponding to the cyclic shift values ​​of the identity matrix of size z x z. The parity check matrix H can be derived from the exponent matrix. The derived sparse binary matrix. The generating matrix G can have a size of n x k in binary form (e.g., the elements of the generating matrix G are binary values). Reference Figure 6 exponential matrix It can have multiple submatrices (e.g., The structure of ).

[0080] II. Resource Units in Communication Systems

[0081] Figure 7 This is a diagram depicting the structure or format of a packet 700 (e.g., an Enhanced Long-Range (ELR) packet) according to one or more embodiments. The packet 700 may be a Physical Layer Protocol Data Unit (PPDU) containing a preamble 701 and a data payload 703. The preamble may contain a legacy preamble that is WLAN-compatible (e.g., IEEE 802.11be-compatible). The preamble may contain an ELR preamble that can be used to detect ERL packets (e.g., by means of a sequence of specific position values). The data payload may be encoded using a Forward Error Correction (FEC) scheme 710, modulated using a digital modulation scheme 720 and a channel modulation scheme (e.g., Orthogonal Frequency Division Multiplexing Access (OFDMA) 730). In some embodiments, the FEC scheme may be implemented using LDPC codes. Resource Units (RUs) or Distributed Resource Units (dRUs) may be defined, allocated, designed, and / or configured for OFDMA channels. A resource unit refers to a group of subcarriers (or tones) within an OFDMA channel, or any frequency bandwidth unit within the frequency bandwidth of a communication channel or communication system. Data payloads can be transmitted using a defined / allocated / designed / configured RU or dRU 740.

[0082] Figure 8 This is a diagram depicting the allocation structure 800 of resource units (RUs) in a 20MHz bandwidth according to one or more embodiments. The 20MHz channel can be divided into multiple RUs, each RU containing a number of subcarriers (or tones). For example, the 256 subcarriers of the 20MHz channel can be allocated / divided into (1) RUs containing 26 subcarriers (referred to as "26-RU" 810), (2) RUs containing 52 subcarriers (referred to as "52-RU" 820), or (3) RUs containing 106 subcarriers (referred to as "106-RU" 830). Figure 8 As shown, the 26-RU 810 may include nine 26-RUs, including 26-RU1 811, 26-RU2 812, 26-RU3 813, 26-RU4 814, 26-RU5 815, 26-RU6 816, 26-RU7 817, 26-RU8 818 and 26-RU9 819. The 52-RU 820 may include four 52-RUs, including 52-RU1 821, 52-RU2 822, 52-RU3 823 and 52-RU4 824, such that (1) 52-RU1 821 includes subcarriers allocated to 26-RU1 811 and 26-RU2 812; (2) 52-RU2 822 includes subcarriers allocated to 26-RU3 813 and 26-RU4 824. (3) 52-RU3 823 includes subcarriers allocated to 26-RU6 816 and 26-RU7 817; and (4) 52-RU4 824 includes subcarriers allocated to 26-RU8 818 and 26-RU9 819. 106-RU 830 may include two 106-RUs, including 106-RU1 831 and 106-RU2 832, such that (1) 106-RU1 831 includes subcarriers allocated to 26-RU1 811 to 26-RU4 814; and (2) 106-RU2 832 includes subcarriers allocated to 26-RU6 816 to 26-RU9 819.

[0083] III. Multiple bitrates across resource units

[0084] On the one hand, there may be differences or gaps in signal quality between frequency bandwidth blocks or RUs (see...). Figure 8Signal quality differences can be caused by the presence of noise, other wireless devices (e.g., overlapping Basic Service Sets (OBSS)), other wireless signals (e.g., signal interference due to jammers), or other interference (e.g., electromagnetic interference (EMI), inter-carrier interference (ICI), etc.). Signal quality refers to signal-to-noise ratio (SNR), error vector magnitude (EVM), other signal strength measures (e.g., Received Signal Strength Indicator (RSSI), Reference Signal Received Quality (RSRQ), Reference Signal Received Power (RSRP), Signal-to-Interference-plus-Noise Ratio (SINR), etc.), or any quality related to the strength, clarity, or reliability of the electronic signal. In cases where such unequal conditions exist in different RUs, a fixed FEC scheme (e.g., LDPC code with a fixed code rate) for multiple streams may not be effectively utilized. For example, if there are a strongest RU (e.g., the RU with the highest signal quality) and a weakest RU (e.g., the RU with the lowest signal quality), the same fixed code rate may be too low to be used to transmit coded data with the strongest RU, or too high to be used to transmit coded data with the weakest RU.

[0085] On the one hand, LDPC codes can have certain code rates that can be used as target code rates in various designs / implementations in communication standards (e.g., IEEE 802.11bn UHR chips). An LDPC encoder can acquire a block of k bits (e.g., k = 1458) of information bits and produce n encoded bits with a code rate of R = k / n (e.g., R = 3 / 4, n = 1944). An LDPC code refers to a systematic LDPC code, a quasi-cyclic (QC) LDPC code, or any error-correcting code using a parity check matrix, which is defined as a set of equations satisfied by any valid codeword. The code rate R of an LDPC code is the ratio of the number of information bits (represented by k) to the block size (represented by n). An LDPC decoder can operate on n received bits (the noisy version) and (ideally) recover k information bits. However, for a fixed number of information bits k, a conventional LDPC code may have a fixed code rate R, and it may not be easy to construct (or generate, configure, design, implement) LDPC codes with different code rates.

[0086] To address this issue, systems and methods according to some embodiments of this disclosure can implement different modulation and coding schemes (MCS) across different resource units (RUs) or different bandwidth segments (e.g., primary and secondary bandwidths in wireless LANs or cellular communications) to mitigate interference caused by noise, other wireless devices (e.g., OBSS), other wireless signals (e.g., signal interference due to jammers), or other interference (e.g., EMI, ICI, etc.). In some embodiments, the communication system can implement unequal modulation and coding methods across different frequency bands (e.g., different RUs) without using separate FEC block codes, wherein a single master code (e.g., a single native LDPC code) and multiple derived rates can be used through appropriate bit processing. In some embodiments, the FEC encoder (and decoder) can be multiplexed serially or in parallel.

[0087] In some implementations, the communication system may perform unequal MCS (e.g., different modulation schemes and / or coding schemes) across different bandwidth segments (e.g., OFDMA RUs). In some implementations, the system may perform different MCS on two different bandwidth segments or RUs (e.g., the lower 80MHz segment and the upper 80MHz segment in a 160MHz PHY bandwidth). For example, when the upper portion / segment of the bandwidth experiences interference or is interfered with, the system may use potentially stronger FEC (e.g., LDPC codes with lower code rates) and / or lower-order modulation (e.g., M-QAM with lower M values) for the upper portion of the bandwidth, while the cleaner channel segment (e.g., the lower portion / segment of the bandwidth) may use potentially weaker FEC (e.g., LDPC codes with higher code rates) and / or higher-order QAM (e.g., M-QAM with higher M values).

[0088] In some implementations, the OFDMA system can use different modulation and coding sets (or configurations) for different RUs, thereby achieving better diversity gain and optimal overall throughput. On the other hand, when RUs across different bandwidth segments or with different SNR limits use the same modulation and coding sets (or configurations), the overall performance may favor the worst-case segment or the performance of the weakest RU.

[0089] In some implementations, the communication system (e.g., an OFDMA system) may perform unequal coding (e.g., different code rates for different streams / RUs) and unequal modulation (e.g., different QAM schemes for different streams / RUs). In some implementations, the communication system may detect or identify unequal frequency bandwidth segments or RUs (e.g., RUs with different SNR values, different EVM values, different signal qualities, or different interference) and perform unequal LDPC coding (e.g., different code rates) on the different streams corresponding to the detected or identified unequal segments or RUs. For example, a stream transmitted using a stronger RU (referred to as a "stronger stream") may potentially carry more information bits than a stream transmitted using a weaker RU (referred to as a "weaker stream") and transmit data to the receiver more reliably. Higher-order QAM (e.g., 4096-QAM) can encapsulate more information bits than lower-order QAM (e.g., 16-QAM) because the number of information bits that can be encapsulated in M-QAM is scaled as log2(M). Similarly, a higher code rate can reflect a larger number of information bits. For example, coding and modulation systems can assign higher bit rates to stronger streams and lower bit rates to weaker streams.

[0090] In some implementations, the coding and modulation system may combine the order of a modulation scheme (e.g., QAM) with a code rate (e.g., the code rate of an LDPC code) to encapsulate a wider range of discrete information bits. In some implementations, the coding and modulation system may determine a modulation and coding scheme (MCS) and select a pair of modulation / QAM sizes (M) and code rates R corresponding to the determined MCS.

[0091] In some implementations, the encoding and modulation system may include an encoding system and a modulation system. The encoding and modulation system may be implemented in hardware (e.g., a circuit system or processor), firmware, software, or a combination thereof. The encoding system may include m scramblers (e.g., m is the number of data streams and is an integer greater than 1), m pre-FEC padding, m LDPC encoders, and / or m post-FEC padding. Here, a data stream refers to the transmission of a sequence of data segments, the transmission of a series of packets, the transmission of a sequence of digitally coded signals used to convey information, or any continuous data stream generated from various sources. The modulation system may include m modulations (e.g., QAM), m RUs (e.g., RU1, RU2, ..., RU...). m m-number of inverse Fourier transforms (e.g., inverse discrete Fourier transform (IDFT) or inverse fast Fourier transform (IFFT)), m-number of cyclic prefixes, m-number of windowings, and / or m-number of analog front-ends (AFE).

[0092] In some implementations, the encoding and modulation system can divide or segment the input data stream into m data streams. This division or segmentation can be performed by the Media Access Control (MAC) layer or the Physical (PHY) layer. m scramblers can randomize the corresponding m data streams before encoding. m pre-FEC padding can add or pad one or more bits to the corresponding m data streams (or the data output from the corresponding m scramblers) to generate padded data to be provided to the corresponding m LDPC encoders. The m LDPC encoders can encode the corresponding input data (or the corresponding padded data output from the m pre-FEC padding) using corresponding LDPC codes (which may have different bit rates from each other). m post-FEC padding can add or pad one or more bits to the data output from the corresponding m LDPC encoders to generate the corresponding encoded data.

[0093] In some implementations, each of the m number of QAMs can determine the number M of different symbols (or different modulation orders) and perform M-QAM (e.g., M = 2, 4, 8, 16, 64, 256, ...) on the corresponding stream to generate the corresponding modulated signal. In some implementations, each QAM (or coding and modulation system) can determine M based on the signal quality difference (e.g., SNR difference or EVN difference) between the corresponding RU and another RU. In some implementations, the system can determine that a 3 dB SNR difference between two RUs corresponds to a 1-bit information bit difference between the two RUs. In other words, if the SNR difference between two RUs is n times 3 dB (n is a positive integer), then the system can determine that there is an n-bit information bit difference between the two RUs. For example, if the SNR difference between the stronger RU and the weaker RU is 4 x 3 dB = 12 dB, then the system can use 12 information bits for the stronger RU, which is 4 more than the 8 information bits used for the weaker RU. Therefore, the system can use 4096-QAM (12-bit) for stronger RUs and 256-QAM (8-bit) for weaker RUs. Typically, the main difference in practice in this case is interference. A segment or RU may be severely affected by signals from another station compared to different RUs. Sometimes, interference or point interference can cause an outage in a portion of the bandwidth.

[0094] For example, in an uncoded system, a 12dB SNR gap can occur when there is a 4-bit difference in the uncoded bit depth between two RUs. In some implementations, a 1-bit difference between two streams can be roughly translated into a 3dB SNR gap. One scenario might involve using 4096-QAM (12 bits) on stream 1 and 256-QAM (8 bits) on stream 2, resulting in a 12dB SNR gap (3dB per bit and a 4-bit difference across the streams). This relationship extends to coded systems, where each additional bit of information requires an additional 3dB of SNR. Here, the information rate equals the uncoded rate multiplied by the code rate.

[0095] In some implementations, such as in OFDM systems, m inverse Fourier transforms (e.g., IDFT or IFFT) can transform the corresponding m signals from the frequency domain to the time domain. For the corresponding m signals, m cyclic prefixes can be added to the last part of the OFDM symbol and appended to the beginning of the same symbol. m windowings can apply window functions (e.g., rectangular windows, Hamming windows, Blackman windows, raised cosine windows, Kaiser windows) to the corresponding m signals. m AFEs can perform various functions on the corresponding m signals (e.g., signal amplification, frequency conversion, filtering, analog-to-digital conversion).

[0096] In some implementations, the system can perform unequal modulation and coding across streams without having to use separate FEC block codes for each stream. In some implementations, the system can perform unequal coding across streams using multiple code rates derived or generated from a single master code (e.g., a single LDPC code with a single basic / master code rate) by appropriate bit processing. In some implementations, multiple FEC encoders (and / or decoders) can be multiplexed serially or in parallel. For example, multiple input streams can be serially encoded using a common single FEC encoder (e.g., an LDPC encoder) that can provide multiple code rates based on a single master code rate. Alternatively, multiple input streams can be encoded in parallel using multiple FEC encoders (e.g., LDPC encoders) corresponding to multiple input streams.

[0097] In some implementations, the system may use an appropriate MCS or coding parameters (e.g., code rate R, information bit length k, block size, or block length n) to determine which bits or bit ranges (e.g., SNR gap or difference) to load based on the signal quality difference (e.g., SNR gap or difference) between adjusted RUs (e.g., stronger RUs and weaker RUs). In some implementations, the system may perform the selection of MCS or coding parameters (e.g., code rate R, information bit length or number k, block size, or block length n) to optimally load the number of information bits to reap the benefits of the SNR gap / difference, thereby achieving maximum overall throughput. For example, a system with a first SNR gap (between stronger and weaker RUs) that is larger than a second SNR gap may (for stronger RUs) select more information bits than a system with a second SNR gap would select. Similarly, a system with a first SNR gap (between stronger and weaker RUs) that is larger than a second SNR gap may (for stronger RUs) select a higher code rate than a system with a second SNR gap would select. In this way, the system can perform unequal modulation and coding (UE-MCS) by executing different MCS schemes across streams (e.g., multiple LDPC coding with different code rates, multiple QAM with different M values).

[0098] In some implementations, the system can reduce the bit rate R i The MCS parameters for the i-th stream (e.g., data stream) are determined, and the parameters corresponding to the code rate R are determined based on (1) the code rate R, (2) the code block length n, and (3) the information bit size k of the mother / basic LDPC code. i Size of information bits in the i-th stream In some implementation schemes, the system can be determined as follows: Value:

[0099]

[0100] In some implementations, the system can reduce the bit rate R i The MCS parameters for the i-th stream (e.g., data stream) are determined, and the corresponding code rate R is determined based on (1) the code rate R and (2) the code block length n of the mother / basic LDPC code. i Length of the code block of the i-th stream (Or code block size or codeword size). In some implementations, the system may determine the following as follows: Value:

[0101]

[0102] In some implementations, the system may determine an indication of the freeze block length (or the size / length of the freeze bits) or a reference to the bit rate R. i Add to The parameter of the size of one or more information bits In some implementation schemes, the system can determine the parameters as follows:

[0103]

[0104] In some implementations, the system can use equations 14 to 16 to calculate / compute possible combinations of parameters (e.g., (make) (The parameter should be an integer value), the resulting parameter combination is stored in memory (e.g., in the form of a lookup table (LUT), and the parameter is determined by selecting a parameter combination from the LUT. Table 1 shows an example LUT containing possible parameter combinations.

[0105]

[0106] Table 1. Possible parameter combinations for multi-rate LDPC codes

[0107] Using Table 1, the system can first determine the bit rate R. i And then based on the bit rate R i Confirm / Select / Select one or more parameters

[0108] In some implementations, the system may use multi-rate LDPC codes to perform unequal modulation and coding (UE-MCS), which can provide multiple code rates (e.g., code rate R). i This allows for the encoding of different streams using a single mother code (or a single basic code). In some implementations, the single mother code may be a single LDPC code with a basic code rate (e.g., a basic code rate or mother code rate R = k / n). The basic code rate of an FEC code (e.g., an LDPC code) refers to a fixed or unique code rate achieved by using an FEC code. In some implementations, the system can determine the different code rates R for each stream. i In some implementations, the system can determine different orders (or different numbers of different symbols) of QAM modulation for each stream.

[0109] In some implementations, the system can achieve, implement, or provide different bitrates for each stream by performing appropriate preprocessing. In some implementations, for m streams (or data streams; m is an integer greater than 1), preprocessing may include selecting bitrates R1, R2, ..., R3 based on conditions (e.g., signal quality, interference, SNR difference between RUs, EVM difference between RUs) corresponding to the m streams. mThis allows for the selection of higher bitrates for stronger RUs (or the assignment of higher bitrates to stronger RUs). In some implementations, for example for m streams, preprocessing may involve using Equation 14 to select the bitrates corresponding to R1, R2, ..., R... m Block coding parameters In some implementations, for example for m streams, preprocessing may include selecting the corresponding bit rates R1, R2, ..., R using Equation 15. m Block coding parameters For example, when m = 2, the system can determine the speeds R1 and R2. and / or determine for rates R1, R2

[0110] In some implementations, multiple input streams can be serially encoded using a common single master (or basic) LDPC code, which can provide multiple code rates corresponding to the multiple input streams based on a single master code rate. Alternatively, multiple input streams can be encoded in parallel using a common single master (or basic) LDPC code, which can provide multiple code rates corresponding to the multiple input streams based on a single master code rate.

[0111] In some implementations, the system may segment or divide data (e.g., a single data stream) into multiple different types of data (e.g., type 1, type 2, ..., type m; where m is an integer greater than 1). In some implementations, different types of data may indicate different service types (e.g., video, text, audio). In some implementations, the system may segment or divide data into multiple different types of data at the MAC layer or at the MAC level. In some implementations, the multiple different types of data may have different Quality of Service (QoS) levels or grades. In some implementations, the multiple different types of data may have different (or unequal) priority levels (e.g., different data protection levels). In some implementations, the multiple different types of data may correspond to multiple streams (e.g., m streams).

[0112] In some implementations, the system can determine the size of the information bits for type i data. (For example, i is an integer greater than or equal to 1), and padding is performed on data of type i to increase the size of data of type i to equal to Or the closest bit size. In some implementations, the system may perform padding by: (1) determining the size of the padded data, (2) generating random data with the padded data of the determined size, and / or (3) adding the generated data (as padded data) to the type i data. In some implementations, the system may perform padding by: (1) determining the size of the padded data and (2) generating data with the same bit values ​​(e.g., 0) as the padded data of the determined size, and / or (3) adding the generated data (as padded data) to the type i data.

[0113] For example, for two types of segmented data (e.g., type 1 data and type 2 data), the system can determine the size or length of type 1 data (e.g., the payload length of type 1 data) and the size or length of type 2 data (e.g., the payload length of type 2 data). The system can (1) determine the information bit size of type 1 data. (2) Divide the type 1 data into portions of size equal to the number of information bits. The data portion that is a multiple of the data size and whose size is less than the information bit size The remaining portion Δ1, and / or (3) will be filled with data (size 1). Add or append to the remaining portion Δ1 to increase the size of the remaining portion to the information bit size. The system can (1) determine the size of the information bits of type 2 data. (2) Divide the type 2 data into portions of size equal to the number of information bits. The data portion that is a multiple of the data size and whose size is less than the information bit size The remaining portion Δ2, and / or (3) will be filled with data (size 1). Add or append to the remaining portion Δ2 to increase the size of the remaining portion to the information bit size.

[0114] In some implementations, the system may segment or divide data into multiple distinct data streams (PHY segmentation) at the PHY layer or at a PHY level. In some implementations, in response to data arriving at the PHY layer as a single stream (or being received at the PHY layer), the system may segment or divide a single stream into multiple data streams at the PHY layer or at a PHY level. In some implementations, for m (segmented) data streams, the system may determine the information bit size. And based on the determined information bit size A single stream can be split or divided into multiple data streams. In some implementations, the system can perform PHY splitting by limiting pre-FEC padding to one of the (split) data streams (depending on the payload length of the individual stream before PHY splitting).

[0115] In one instance of PHY segmentation, for a single data stream, the system can determine the size or length of the single data stream at the PHY layer (e.g., the payload length of the single data stream) and the number of segmented data streams (e.g., 2). The system can (1) determine the bit size of data stream 1. and the size of information bits in data stream 2 (2) Divide or divide a single data stream into its own segments of equal size. Multiple first data parts and their respective sizes equal to Multiple second data portions, such that the number of first data portions equals the number of second data portions, (3) determine the remaining portion Δ1 at the end of a single data stream (whose size is less than ), and / or (4) the filled data (size is Add or append to the remaining portion Δ1 to increase the size of the remaining portion to the information bit size.

[0116] In another instance of PHY segmentation, for a single data stream, the system can determine the size or length of the single data stream (e.g., the payload length of the single data stream) and the number of segmented data streams (e.g., 2). The system can (1) determine the bit size of data stream 1. and the size of information bits in data stream 2 (2) Divide or divide a single data stream into its own segments of equal size. Multiple first data parts and their respective sizes equal to (3) Determine the remaining portion at the end of a single data stream (whose size is greater than the number of second data portions) such that the number of first data portions equals the number of second data portions. (4) Divide the remaining part into parts of equal size The first remaining part Δ1 and its size is less than The second remaining portion Δ2, and / or (5) will be filled with data (size 1). Add or append to the second remainder Δ2 to increase the size of the second remainder to the information bit size.

[0117] In some implementations, the system can encode multiple types of data (or multiple data streams) at a fixed block length (e.g., n) using multiple code rates generated by a single LDPC encoder (or a single LDPC code). For example, the system can segment or divide the input data into Type 1 data and Type 2 data at the MAC layer. The system can determine code rates R1 and R2 for Type 1 data and Type 2 data based on RU conditions (e.g., SNR difference / variance between RUs). Based on code rates R1 and R2, the system can determine or pre-compute encoding parameters for Type 1 data and Type 2 data (e.g., ...) using Equations 14 and / or 15. The system can (1) add or append first padded data (e.g., using pre-FEC padding) to the end of the Type 1 data to increase the size of the Type 1 data. And (2) add or append a second padded data (e.g., using pre-FEC padding) to the end of the Type 2 data to increase the size of the Type 2 data. In order to encode type 1 data using a single LDPC code with a basic rate R (e.g., R = k / n), the system can use Equation 16 to determine the size. And each will have a determined size Multiple first-freeze blocks are added to the type 1 data (e.g., using pre-FEC padding). To encode the type 2 data using the same single LDPC code, the system can determine the size using Equation 16. And each will have a determined size Multiple second-freeze blocks are added to type 2 data (e.g., using pre-FEC filling).

[0118] In some implementations, the system may use a single LDPC code to perform LDPC encoding on type 1 data to generate a first codeword of size n. The system may also use a single LDPC code to perform LDPC encoding on type 2 data to generate a second codeword of size n. In some implementations, the system may perform or run a (single) LDPC encoder on type 1 and type 2 data in a time-division multiplexing manner. In some implementations, the system may perform or run two LDPC encoders (with the same master code) on type 1 and type 2 data in parallel. In some implementations, the system may shorten the process by: (1) removing or discarding multiple first freeze blocks from the first codeword to generate first encoded data corresponding to type 1 data (at code rate R1), and / or (2) removing or discarding multiple second freeze blocks from the second codeword to generate second encoded data corresponding to type 2 data (at code rate R2). In this way, for example, code rate R1 = 3 / 4、R2= 2 / 3 can be obtained from R= 5 / 6 Export. In some implementations, when discarding the first and second frozen blocks, the system may provide or send the first encoded data and the second encoded data to the QAM (e.g., a QAM with different M values).

[0119] In some implementations, the system can encode multiple types of data (or multiple data streams) using multiple native code rates provided by multiple LDPC encoders (or multiple LDPC codes) at multiple code block lengths (e.g., n1, n2, ...). For example, the system can segment or divide the input data into data stream 1 and data stream 2 at the MAC layer or PHY layer. The system can determine the native code rates R1 (=k1 / n1) and R2 (=k2 / n2) for data stream 1 and data stream 2 respectively based on RU conditions (e.g., SNR difference / discrepancy between RUs). The system can determine encoding parameters for data stream 1 and data stream 2 (e.g., ...) based on RU conditions. Encoding is performed. The system can (1) divide the data stream 1 into segments of size 1. (2) Divide the data stream 2 into multiple information blocks, each of which is of size 1. (3) Add each of the multiple information blocks with a size of Multiple first-filled or frozen blocks (e.g., using pre-FEC filling) are used to increase the size of each information block to [amount missing]. and / or (4) add their respective sizes as Multiple second-filled or frozen blocks (e.g., using pre-FEC filling) are used to increase the size of each information block to [amount missing].

[0120] In some implementations, the system may perform LDPC encoding on data stream 1 using LDPC codes with a native code rate R1 (=k1 / n1) to generate a first codeword of size n1. The system may also perform LDPC encoding on data stream 2 using LDPC codes with a native code rate R2 (=k2 / n2) to generate a second codeword of size n2. In some implementations, the system may perform or run two LDPC encoders (with code rates R1 and R2 respectively) on data streams 1 and 2 in a time-division multiplexing manner. In some implementations, the system may perform or run two LDPC encoders (with code rates R1 and R2 respectively) on data streams 1 and 2 in parallel. In some implementations, the system may shorten the process by: (1) removing or discarding multiple first freeze blocks from the first codeword to generate first encoded data corresponding to data stream 1 (at code rate R1), and / or (2) removing or discarding multiple second freeze blocks from the second codeword to generate second encoded data corresponding to data stream 2 (at code rate R2). In some implementations, when discarding the first and second frozen blocks, the system may provide or send the first encoded data and the second encoded data to the QAM (e.g., a QAM with different M values).

[0121] In some implementations, the system can encode multiple types of data (or multiple data streams) using multiple native code rates provided by multiple LDPC encoders (or multiple LDPC codes) at multiple block lengths (e.g., n1, n2, ...). For example, the system can segment or divide the input data into data stream 1 and data stream 2 at the MAC layer or PHY layer. The system can determine the native code rates R1 (=k1 / n1) and R2 (=k2 / n2) for data stream 1 and data stream 2 respectively based on RU conditions (e.g., SNR difference / discrepancy between RUs). The system can (1) divide data stream 1 into multiple information blocks of size k1, and (2) divide data stream 2 into multiple information blocks of size k2. In some implementations, the system can perform LDPC encoding on data stream 1 using LDPC codes with a native code rate R1 (=k1 / n1) to generate a first codeword of size n1 (as the first encoded data). The system can also perform LDPC encoding on data stream 2 using an LDPC code with a native code rate R2 (=k2 / n2) to generate a second codeword of size n2 (as the second encoded data). In some embodiments, the system can perform or run two LDPC encoders (with code rates R1 and R2 respectively) on data streams 1 and 2 in a time-division multiplexing manner. In some embodiments, the system can perform or run two LDPC encoders (with code rates R1 and R2 respectively) on data streams 1 and 2 in parallel. In some embodiments, after completing the encoding of data streams 1 and 2, the system can provide or send the first encoded data and the second encoded data to a QAM (e.g., a QAM with different M values).

[0122] For example, the system may use 1024-QAM with a code rate R1 = 5 / 6 for data stream 1 and 256-QAM with a code rate R2 = 2 / 3 for data stream 2. In a first embodiment, the system may (1) perform LDPC encoding with a native code rate R = 5 / 6 (e.g., n = 1944, k = 1620) on data stream 1 to generate first encoded data, (2) perform LDPC encoding with a native code rate R = 2 / 3 (e.g., n = 1944, k = 1296) on data stream 2 to generate second encoded data, and / or (3) map the first encoded data and the second encoded data to 1024-QAM and 256-QAM, respectively.

[0123] In the second embodiment, the system can (1) determine the encoding parameters. and Encode data stream 1 and data stream 2 separately (e.g., based on RU conditions), (2) divide or partition data stream 1 into multiple first blocks of size k1′=k=1620, and (3) divide or partition data stream 2 into multiple first blocks of size k1′=k=1620. (4) Add or append a frozen block of size θ = k - k2′ = 1620 - 648 = 972 bits to each of the second blocks, (5) Perform LDPC encoding with native code rate R = k / n = 1620 / 1944 = 5 / 6 on data stream 1 and (padded) data stream 2 to generate first codeword and second codeword respectively, (6) Discard the frozen blocks (each with 972 bits) from system location (e.g., the part other than parity bit) to generate first encoded data and second encoded data, and / or (7) Multiplex the first encoded data and second encoded data to perform stream-by-stream QAM modulation (with different M values).

[0124] In the third embodiment, the system may (1) perform LDPC encoding with a native code rate R = 5 / 6 on data stream 1 in a time-division multiplexing manner to generate first encoded data and perform LDPC encoding with a native code rate R = 2 / 3 on data stream 2 to generate second encoded data, and / or (2) map the first encoded data and the second encoded data to 1024-QAM and 256-QAM respectively.

[0125] The embodiments of this disclosure have at least the following advantages and benefits. First, the embodiments of this disclosure provide useful techniques for constructing / generating / configuring / designing / implementing multi-rate LDPC codes to perform unequal coding for different data streams transmitted using different RUs to mitigate interference caused by the presence of noise, other wireless devices (e.g., OBSS), other wireless signals (e.g., signal interference due to jammers), or other interference (e.g., EMI, ICI, etc.). In this way, even when unequal conditions exist in different RUs (e.g., large SNR differences between RUs), multi-rate LDPC codes can be used to encode multiple streams at different code rates determined based on the unequal conditions of the RUs. For example, if there are a strongest RU and a weakest RU, then a higher code rate and a larger information bit size can be used to encode the data stream corresponding to the strongest RU, while a lower code rate and a smaller information bit size can be used to encode the data stream corresponding to the weakest RU.

[0126] Second, the embodiments in this disclosure provide useful techniques for mapping different modulation schemes (e.g., QAMs with different M values) to data streams corresponding to different RUs with unequal conditions (e.g., large SNR differences between RUs) to mitigate interference. For example, if there are a strongest RU and a weakest RU, then a QAM with a larger M value (e.g., 4096-QAM) can be used to modulate the data stream corresponding to the strongest RU, while a QAM with a smaller M value (e.g., 16-QAM) can be used to modulate the data stream corresponding to the weakest RU.

[0127] refer to Figures 9 to 17This describes and illustrates embodiments of the systems and methods used to provide unequal coding and modulation solutions.

[0128] Figure 9 This is a diagram depicting different modulation and coding configurations across different RUs according to one or more embodiments. In some embodiments, the communication system may perform unequal MCSs (e.g., different modulation schemes and / or coding schemes) across different bandwidth segments (e.g., OFDMA RUs). Reference Figure 9 The system can apply different MCS to RU1 801 and RU2 802 (e.g., the lower 80MHz segment and the upper 80MHz segment in a 160MHz PHY bandwidth). For example, when the upper portion / segment of the bandwidth (e.g., RU2 802) experiences interference or is interfered with, the system can use potentially stronger FEC (e.g., LDPC code with a lower code rate R2) and / or lower-order modulation (e.g., M-QAM2 with a lower M=M1 value) for RU2 802, while cleaner channel segments (e.g., the lower portion / segment of the bandwidth or RU1 801) can use potentially weaker FEC (e.g., LDPC code with a higher code rate R2 such that R2>R1) and / or higher-order QAM (e.g., M-QAM1 with a higher M=M2 value such that M2>M1).

[0129] Figure 10 This is a diagram depicting an example encoding and modulation system 1000 spanning different RUs according to one or more embodiments. The encoding and modulation system 1000 may include an encoding system and a modulation system. The encoding and modulation system 1000 may be implemented in hardware (e.g., a circuit system or processor), firmware, software, or a combination thereof. The encoding system may include m scramblers 1002-1, ..., 1002-m (e.g., m is the number of data streams and is an integer greater than 1), m pre-FEC paddings 1004-1, ..., 1004-m, m LDPC encoders 1006-1, ..., 1006-m, and / or m post-FEC paddings 1008-1, ..., 1008-m. The modulation system may include m modulations (e.g., QAM) 1020-1, ..., 1020-m, m RUs 1022-1, ..., 1022-m (e.g., RU1, RU2, ..., RU...). m m inverse Fourier transforms 1040-1, ..., 1040-m (e.g., inverse discrete Fourier transform (IDFT) or inverse fast Fourier transform (IFFT)), m cyclic prefixes 1042-1, ..., 1042-m, m windowed elements 1050-1, ..., 1050m, and / or m analog front-ends (AFEs) 1052-1, ..., 1052-m.

[0130] The encoding and modulation system 1000 can divide or segment the input data stream into m data streams. This division or segmentation can be performed by the Media Access Control (MAC) layer or the Physical (PHY) layer. m scramblers 1002-1, ..., 1002-m can randomize the corresponding m data streams before encoding. m pre-FEC padding 1004-1, ..., 1004-m can add or pad one or more bits to the corresponding m data streams (or the data output from the corresponding m scramblers) to generate padded data to be provided to the corresponding m LDPC encoders 1006-1, ..., 1006-m. The m LDPC encoders 1006-1, ..., 1006-m can encode the corresponding input data (or the corresponding padded data output from the m pre-FEC padding 1004-1, ..., 1004-m) using corresponding LDPC codes (which may have different code rates from each other). The m-number of subsequent FEC padding 1008-1, ..., 1008-m can add or pad 1 or more bits to the data output from the corresponding m-number of LDPC encoders 1006-1, ..., 1006-m to generate the corresponding encoded data.

[0131] Each of the m-number QAMs 1020-1, ..., 1020-m can determine the number M of different symbols (or different modulation orders) and perform M-QAM (e.g., M = 2, 4, 8, 16, 64, 256, ...) on the corresponding stream to generate the corresponding modulated signal. In some implementations, each QAM (or coding and modulation system) can determine M based on the signal quality difference (e.g., SNR difference or EVN difference) between the corresponding RU and another RU. For example, if the SNR difference between the stronger RU and the weaker RU is 3x3 dB, then the system can use three more information bits (e.g., m = 6 bits) for the stronger RU than for the weaker RU (m = 3 bits). Because M = 2 2m Therefore, the system can use 4096-QAM for stronger RUs and 64-QAM for weaker RUs.

[0132] For example, in an OFDM system, m inverse Fourier transforms (e.g., IDFT or IFFT) 1040-1, ..., 1040-m can transform the corresponding m signals from the frequency domain to the time domain. For the corresponding m signals, m cyclic prefixes 1042-1, ..., 1042-m can add a cyclic prefix to the last part of the OFDM symbol and append said part to the beginning of the same symbol. m windowings 1050-1, ..., 1050-m can apply window functions (e.g., rectangular window, Hamming window, Blackman window, raised cosine window, Kaiser window) to the corresponding m signals. m AFEs 1052-1, ..., 1052-m can perform various functions (e.g., signal amplification, frequency conversion, filtering, analog-to-digital conversion) on the corresponding m signals.

[0133] Figure 11A and Figure 11B It is a diagram depicting instance parameters of different multi-rate LDPC codes according to one or more embodiments. Figure 11A This demonstrates how to determine the code rate R of the mother code and the expected code rate R of the i-th data stream when the code block length n = 1944. i Determine the encoding parameters (e.g., information bit length). ). refer to Figure 11A Lines 1101, 1102, 1103, and 1104 correspond to the original bitrates R = 1 / 2, 2 / 3, and 1 / 4 respectively. 3 The desired encoding parameters for / 4 and 5 / 6 (e.g., code rate R) i Information bit length Given the native bit rate R and the information bit length... It can be determined by rounding along the line corresponding to the bit rate R to the nearest natural number of information bit length (rounding up / down may cause a slight increase / decrease in the bit rate).

[0134] Figure 11B This demonstrates how to determine the code rate R of the mother code and the expected code rate R of the i-th data stream when the code block length n = 1944. i Determine the encoding parameters (e.g., code block length). ). refer to Figure 11B Lines 1151, 1152, 1153, and 1154 correspond to the original bitrates R = 1 / 2, 2 / 3, and 1 / 4 respectively. 3 The desired encoding parameters for / 4 and 5 / 6 (e.g., code rate R) i Code block length Given the native code rate R, the code block length... It can be determined by rounding along the line corresponding to the code rate R to the nearest natural number of the code block length (rounding up / down may cause a slight increase / decrease in the code rate).

[0135] Figure 12A and Figure 12B Block diagrams 1200 and 1250 are provided to illustrate example input and output parameters for multi-rate LDPC codes 1202 and 1252 according to one or more embodiments. Systems (e.g., communication system 105) can use multi-rate LDPC codes to perform unequal modulation and coding (UE-MCS), which can provide multiple code rates (e.g., code rate R0). i This allows encoding different streams using a single mother code (or a single basic code). The single mother code can be a single LDPC code with a basic code rate (e.g., a basic code rate or mother code rate R = k / n). The system can determine the different code rates R for each stream. i (For example, 1204-1, ..., 1204-m; m is the number of data streams). The system can implement, enforce, or provide different bit rates for each stream by performing appropriate preprocessing. For m streams (or data streams; m is an integer greater than 1), preprocessing may include selecting bit rates R1, R2, ..., R based on conditions (e.g., signal quality, interference, SNR difference between RUs, EVM difference between RUs) corresponding to the m streams. m (e.g., 1204-1, ..., 1204-m), allowing for the selection of higher bitrates for stronger RUs (or the assignment of higher bitrates to stronger RUs). For example, for m streams, preprocessing could involve using Equation 14 to select the bitrates corresponding to R1, R2, ..., R... m Block coding parameters (e.g., 1206-1, ..., 1206-m). For m streams, preprocessing could, for example, involve selecting the streams corresponding to R1, R2, ..., R using Equation 15. m Block coding parameters (For example, 1208-1, ..., 1208-m). Reference Figure 12B When m=2, the system can use the multi-rate LDPC code 1252 based on a basic code rate of 5 / 6, determined for rates R1=3 / 4 and R2=2 / 3. And / or determine for rates R1 = 3 / 4, R2 = 2 / 3

[0136] Figures 13A to 13C Figures 1300, 1330, and 1360 depict an instance process of data segmentation by a Media Access Control (MAC) layer or a Physical (PHY) layer according to one or more embodiments. Reference Figure 13AFor two types of segmented data (e.g., type 1 data and type 2 data), the system can determine the size or length of type 1 data (e.g., the payload length of type 1 data) and the size or length of type 2 data (e.g., the payload length of type 2 data). In process step 1310, the system can (1) determine the information bit size of type 1 data. (2) Divide the type 1 data into portions of size equal to the number of information bits. The data portion that is a multiple of 1311 and whose size is less than the information bit size The remaining part Δ1(1313), (3) determines the size of the information bits of type 2 data. (4) Divide the type 2 data into portions of size equal to the number of information bits. The data portion that is a multiple of 1312 and whose size is less than the information bit size The remaining part Δ2(1314). In process step 1320, the system can (1) fill the data 1321 (size is Add or append to the remaining portion Δ1 to increase the size of the remaining portion to the information bit size. and (2) fill the data 1322 (size is Add or append to the remaining portion Δ2 to increase the size of the remaining portion to the information bit size. Figure 13A The process shown can be executed at the MAC layer.

[0137] In some implementations, the system may segment or divide data into multiple different data streams at the PHY layer or at the PHY level (e.g., Figure 13B Data stream 1, data stream 2 (PHY segmentation). In response to data arriving at the PHY layer as a single stream (or being received at the PHY layer), the system can segment or divide the single stream into multiple data streams (e.g., data stream 1, data stream 2) at the PHY layer or at a PHY level. For m (segmented) data streams, the system can determine the information bit size. And based on the determined information size A single stream can be split or divided into multiple data streams. In some implementations, the system can perform PHY splitting by limiting pre-FEC padding to one of the (split) data streams (depending on the payload length of the individual stream before PHY splitting).

[0138] Figure 13B An example of PHY segmentation is shown, wherein for a single data stream, the system can determine the size or length of the single data stream at the PHY layer (e.g., the payload length of the single data stream) and the number of segmented data streams (e.g., 2). In process step 1340, the system can (1) determine the information bit size of data stream 1. and the size of information bits in data stream 2 (2) Divide or divide a single data stream into its own segments of equal size. Multiple first data parts 1341 and their respective sizes equal to Multiple second data portions 1342, such that the number of first data portions equals the number of second data portions, (3) determine the remaining portion Δ1(1343) at the end of a single data stream (its size is less than In process step 1350, the system can fill data 1351 (size ). Add or append to the remaining portion Δ1 to increase the size of the remaining portion to the information bit size.

[0139] Figure 13C Another example of PHY segmentation is shown, where, for a single data stream, the system can determine the size or length of the single data stream (e.g., the payload length of the single data stream) and the number of segmented data streams (e.g., 2). In process step 1370, the system can (1) determine the information bit size of data stream 1. and the size of information bits in data stream 2 (2) Divide or divide a single data stream into its own segments of equal size. Multiple first data parts 1371 and their respective sizes equal to Multiple second data portions 1372, such that the number of first data portions equals the number of second data portions, (3) determine the remaining portion at the end of a single data stream (whose size is greater than) (4) Divide the remaining part into parts of equal size The first remaining part Δ1(1373) and its size is less than The second remaining portion Δ2 (1374). In process step 1380, the system can fill the data 1381 (size 1374) with padding. Add or append to the second remainder Δ2 to increase the size of the second remainder to the information bit size.

[0140] Figure 14 Figure 1400 illustrates an example process of encoding data at two bit rates using a single LDPC encoder according to one or more embodiments. In some embodiments, the system can encode multiple types of data (or multiple data streams) at a fixed block length (e.g., n) using multiple bit rates generated by a single LDPC encoder (or a single LDPC code). Reference Figure 14In process step 1410, the system may segment or divide the input data into Type 1 data 1411 and Type 2 data 1412 at the MAC layer. The system may determine the code rates R1 and R2 of the Type 1 and Type 2 data based on RU conditions (e.g., SNR difference / discrepancy between RUs). Based on the code rates R1 and R2, the system may use Equations 14 and / or 15 to determine or pre-compute coding parameters for the Type 1 and Type 2 data (e.g., ...). Encoding is performed. In process step 1420, the system may (1) add or append first padded data 1423 (e.g., using pre-FEC padding 1004-1) to the end of the type 1 data 1421 to increase the size of the type 1 data to and (2) add or append a second padded data 1424 (e.g., using pre-FEC padded 1004-2) to the end of the type 2 data 1422 to increase the size of the type 2 data. In process step 1430, in order to encode type 1 data 1431 using a single LDPC code with a basic rate R (e.g., R = k / n), the system can determine the size using equation 16. And each will have a determined size Multiple first-freeze blocks 1433 are added to the type 1 data (e.g., using pre-FEC padding 1004-1). To encode the type 2 data 1432 using the same single LDPC code, the system can determine the size using Equation 16. And each will have a determined size Multiple second frozen blocks 1434 are added to type 2 data (e.g., 1004-2 is filled with pre-FEC).

[0141] refer to Figure 14In process step 1440, the system can perform LDPC encoding on type 1 data using a single LDPC code to generate a first codeword 1441 of size n. The system can also perform LDPC encoding on type 2 data using a single LDPC code to generate a second codeword 1442 of size n. The system can perform or run a (single) LDPC encoder on type 1 data and type 2 data in a time-division multiplexing manner. In some embodiments, the system can perform or run two LDPC encoders (with the same master code) on type 1 data and type 2 data in parallel. In process step 1450, the system can shorten the process by: (1) removing or discarding multiple first freeze blocks 1433 from the first codeword to generate first encoded data 1451 corresponding to type 1 data (at code rate R1), and / or (2) removing or discarding multiple second freeze blocks 1434 from the second codeword to generate second encoded data 1452 corresponding to type 2 data (at code rate R2). In this way, for example, code rate R1 = 3 / 4、R2= 2 / 3 can be obtained from R= 5 / 6 Export. In some implementations, when discarding the first and second frozen blocks, the system may provide or send the first encoded data 1451 and the second encoded data 1452 to the QAM (e.g., a QAM with a different M value).

[0142] Figure 15 Figure 1500 illustrates an example process of encoding data at two bitrates based on different block lengths using different LDPC encoders according to one or more embodiments. The system can encode multiple types of data (or multiple data streams) at multiple block lengths (e.g., n1, n2, ...) using multiple native bitrates provided by multiple LDPC encoders (or multiple LDPC codes). Reference Figure 15 In process step 1510, the system may segment or divide the input data into data stream 1 (1511) and data stream 2 (1512) at the MAC layer or PHY layer. The system may determine the native code rates R1 (=k1 / n1) and R2 (=k2 / n2) for data stream 1 and data stream 2 respectively based on RU conditions (e.g., SNR difference / discrepancy between RUs). The system may determine encoding parameters for data stream 1 and data stream 2 (e.g., Encoding is performed. The system can (1) divide the data stream 1 into segments of size 1. (2) Divide the data stream 2 into multiple information blocks, each of which is of size 1. (3) Add each of the multiple information blocks with a size of Multiple first-filled data or frozen blocks (e.g., using pre-FEC-filled 1004-1) are added to increase the size of each information block to k1, and / or (4) each block is added to a size of k1. Multiple second-filled data or frozen blocks (e.g., using pre-FEC-filled 1004-2) are used to increase the size of each information block to k2.

[0143] In process step 1520, the system can perform LDPC encoding on data stream 1 using an LDPC code with a native code rate R1 (=k1 / n1) to generate a first codeword 1521 of size n1. The system can also perform LDPC encoding on data stream 2 using an LDPC code with a native code rate R2 (=k2 / n2) to generate a second codeword 1522 of size n2. The system can perform or run two LDPC encoders (with code rates R1 and R2 respectively) on data stream 1 and data stream 2 in a time-division multiplexing manner. In some embodiments, the system can perform or run two LDPC encoders (with code rates R1 and R2 respectively) on data stream 1 and data stream 2 in parallel. In process step 1530, the system can shorten the process by performing the following: (1) removing or discarding multiple first freeze blocks from the first codeword (e.g., each first freeze block has a size of n1). (1) Generate first encoded data 1531 corresponding to data stream 1 at (code rate R1), and / or (2) Remove or discard multiple second frozen blocks from the second codeword (e.g., each second frozen block has a size of The system generates second encoded data 1532 corresponding to data stream 2 at a bit rate R2. When discarding the first and second frozen blocks, the system may provide or send the first encoded data 1531 and the second encoded data 1532 to the QAM (e.g., a QAM with a different M value).

[0144] Figure 16 Figure 1600 illustrates another example of a process for encoding data at two bitrates based on different block lengths using different LDPC encoders according to one or more embodiments. The system can encode multiple types of data (or multiple data streams) at multiple block lengths (e.g., n1, n2, ...) using multiple native bitrates provided by multiple LDPC encoders (or multiple LDPC codes). Reference Figure 16In process step 1610, the system may segment or divide the input data into data stream 1 (1611) and data stream 2 (1612) at the MAC layer or PHY layer. The system may determine the native code rates R1 (=k1 / n1) and R2 (=k2 / n2) for data stream 1 and data stream 2 respectively based on the conditions of RUs (e.g., SNR difference / discrepancy between RUs). The system may (1) divide data stream 1 into multiple information blocks of size k1, and (2) divide data stream 2 into multiple information blocks of size k2. In process step 1620, the system may perform LDPC encoding on data stream 1 using LDPC codes with native code rates R1 (=k1 / n1) to generate a first codeword of size n1 (as the first encoded data 1621). The system can also perform LDPC encoding on data stream 2 using an LDPC code with a native code rate R2 (=k2 / n2) to generate a second codeword of size n2 (as the second encoded data 1622). The system can perform or run two LDPC encoders (with code rates R1 and R2 respectively) on data streams 1 and 2 in a time-division multiplexing manner. In some implementations, the system can perform or run two LDPC encoders (with code rates R1 and R2 respectively) on data streams 1 and 2 in parallel. After encoding data streams 1 and 2, the system can provide or send the first encoded data 1621 and the second encoded data 1622 to a QAM (e.g., a QAM with different M values).

[0145] In some implementations, the device (e.g., communication system 105) may include a transmitter (e.g., transmitter circuitry 120) and one or more processors (e.g., processor 2010). The one or more processors may identify multiple RUs (e.g., ...) for transmitting corresponding data streams within one or more wireless channels (e.g., 20MHz channels). Figure 8 RU1 811, ..., RU9819 in the series; Figure 10 RU1, ..., RU m A wireless channel is a range of frequencies in which wireless devices can communicate, one or more frequency bands used by a wireless network, or one or more specific frequencies in the electromagnetic spectrum, or any path or frequency range through which wireless signals travel to facilitate communication between devices.

[0146] In some implementations, one or more processors may be configured to receive data streams. One or more processors may be configured to determine, via the Media Access Control (MAC) layer: (1) different service types of the data stream (e.g., Figure 13A(1) Type 1 data, Type 2 data), (2) different priority levels of the data stream or (3) different quality of service (QoS) levels of the data stream. One or more processors can be configured to be segmented by the MAC layer into corresponding data streams based at least on different data types, different priority levels or different QoS levels (e.g., Figure 13A (Type 1 data and Type 2 data).

[0147] In some implementations, one or more processors may determine the appropriate number of bits (e.g., bits per symbol corresponding to M values ​​of 16, 32, 64, ..., 4096) for the multiple RUs based at least on the signal quality differences between transmissions spanning the multiple RUs (e.g., SNR difference or EVM difference between RUs). In some implementations, the signal quality differences between the multiple RUs may be the signal-to-noise ratio (SNR) differences (e.g., SNR difference or EVM difference) between transmissions spanning the multiple RUs.

[0148] The corresponding bit lengths can be different from each other. One or more processors can use the corresponding bit lengths to modulate the corresponding data streams (e.g., performing QAM using different M values ​​= 16, 32, 64, ..., 4096) to generate the corresponding modulated data streams. The transmitter can use the corresponding RU to transmit the corresponding modulated data streams. In some embodiments, when modulating the corresponding data streams, one or more processors can be configured to perform quadrature amplitude modulation (QAM) for each RU using the corresponding bit lengths as the number of bits per symbol (e.g., corresponding to the number of bits per symbol for M values ​​= 16, 32, 64, ..., 4096).

[0149] Figure 17 This is a flowchart illustrating a process 1700 for providing multiple code rates across different RUs according to an embodiment. In some embodiments, process 1700 is executed by one or more processors of the device (e.g., processor 2010 of communication system 105). In other embodiments, process 1700 is executed by other entities (e.g., a computing system other than communication system 105). In some embodiments, process 1700 includes more than Figure 17 The steps shown may include more, fewer, or different steps.

[0150] At step 1702, one or more processors may identify multiple RUs (e.g., RUs) for transmitting corresponding data streams within one or more wireless channels (e.g., 20MHz channels). Figure 9 RU1 and RU2 in the middle; Figure 10 RU1, RU2, ..., RU m ).

[0151] In some implementations, one or more processors may receive data streams (e.g., a single data stream). The Media Access Control (MAC) layer may determine (1) different service types of the data streams (e.g., video, text, audio, etc.), (2) different priority levels of the data streams, or (3) different Quality of Service (QoS) levels of the data streams. Based at least on different data types, different priority levels, or different QoS levels, the MAC layer may segment the data streams into corresponding data streams (e.g., Type 1 data 1611, Type 2 data 1612).

[0152] In some implementations, the size of the corresponding information bits for multiple RUs can be selected based at least on the corresponding target code rate and the basic code rate. For example, it can be based at least on the corresponding target code rate (e.g., Figure 11A R1, R2) and basic bit rate (e.g., Figure 11A In R) select the appropriate information bit size (e.g., Figure 11A In At least based on the size of the corresponding information bits (e.g., Figure 13B In The physical (PHY) layer can segment the data stream into corresponding data streams (e.g., Figure 13B Data stream 1 and data stream 2 in the PHY layer. The PHY layer can select the appropriate information bit size (e.g., Figure 13B In ) will provide the corresponding data (e.g., Figure 13B In 1351) Add to the corresponding data stream (e.g., Figure 13B Data flow 1).

[0153] At step 1704, one or more processors may determine corresponding target code rates (e.g., R1, R2) for multiple RUs based at least on signal quality differences (e.g., SNR gap or EVM gap) between transmissions spanning multiple RUs. For example, a system with a first SNR gap (between a stronger RU and a weaker RU) that is larger than a second SNR gap may (for the stronger RU) select a higher code rate than the code rate selected by a system with a second SNR gap. In some embodiments, the signal quality difference between multiple RUs may be the signal-to-noise ratio (SNR) difference between transmissions spanning multiple RUs. The corresponding target code rate (e.g., Figure 11B In the code, R1 = 3 / 4 and R2 = 2 / 3 can be different from each other and are different from the basic code rate of a low-density parity-check (LDPC) code (e.g., Figure 11B The R=5 / 6 in the example is different.

[0154] In some implementations, the information rate of an RU with QAM size M and code rate R is log2(M)*R (in bits / second / Hz). Each 1-bit change in information rate may require approximately a 3dB SNR budget. Therefore, given the SNR difference ΔS and the QAM sizes M1 and M2 (for the stronger RU1 and the weaker RU2, respectively), the target code rate R1 (for RU1) and the target code rate R2 (for RU2) can be determined using the following equations:

[0155] 3(Info_rate1-Info_rate2)=3((log2M1)*R1-(log2M2)*R2)=ΔS............(Equation 17)

[0156] Where Info_rate1 and Info_rate2 are the information rates of RU1 and RU2, respectively. In other words, given the SNR difference, R1 and R2 can be determined using a two-dimensional search using Equation 17.

[0157] At step 1706, one or more processors can encode the corresponding data stream using an LDPC code with a basic code rate via an LDPC encoder to generate the corresponding encoded data stream at the corresponding target code rate. In some embodiments, when encoding the corresponding data stream, the size of the basic information bits corresponding to the basic code rate (e.g., k = 1296, R = 2 / 3 in Table 1) can be determined. The second set of information bits (e.g., the size in data block 1431 is...) Information bits can be generated from each corresponding data stream to contain a first set of information bits corresponding to a selected corresponding information bit size (e.g., a size of [size missing] in data block 1421). The first group of information bits and one or more bits (e.g., information bits) The size of the second set of information bits is increased to correspond to the size of the basic information bits (e.g., k in data block 1431). The LDPC encoder can use the basic bit rate to increase the size of the second set of information bits (e.g., k in data block 1431). The information bits are encoded to generate parity data (e.g., (nk) in data block 1441). A second set of information bits (e.g., of size 1441 in data block 1441) can be concatenated. The corresponding encoded data stream is generated by combining the information bits and parity data (e.g., (nk) in data block 1441).

[0158] In some implementations, the corresponding data streams can be encoded serially or in parallel. In some implementations, the encoded data streams can be multiplexed to perform stream-by-stream modulation. For example, see reference... Figure 14The system can use a single, shared LDPC encoder to serially encode both Type 1 and Type 2 data. This single LDPC encoder can provide multiple code rates based on a single master code rate. The system can execute or run a (single) LDPC encoder on both Type 1 and Type 2 data in a time-division multiplexing manner. The system can also execute or run two LDPC encoders (with the same master code) on both Type 1 and Type 2 data in parallel.

[0159] At step 1708, the transmitter (e.g., transmitter circuitry 120) may use the corresponding RU to transmit the corresponding encoded data stream (e.g., first encoded data 1451, second encoded data 1452).

[0160] A reference to "or" can be interpreted as inclusive, such that any term described using "or" can refer to any one, more than one, or all of the described items. A reference to at least one of a list of combined terms can be interpreted as inclusive or to refer to any one, more than one, or all of the described items. For example, a reference to "at least one of 'A' and 'B'" can include only 'A', only 'B', or both 'A' and 'B'. Such references used in conjunction with "include" or other open terms can include additional items.

[0161] It should be noted that certain paragraphs of this disclosure may refer to terms (e.g., “first” and “second”) related to subsets of transmit space streams, probe frames, responses, and devices for the purpose of identifying or distinguishing them from others. These terms are not intended merely to correlate entities (e.g., first and second devices) temporally or sequentially, although in some cases such a relationship may exist. These terms also do not limit the number of possible entities (e.g., STA, AP, beamforming initiator, and / or beamforming receiver) that may operate within the system or environment. It should be understood that the system described above may provide any or more of those components, and these components may be provided on a standalone machine or, in some embodiments, on multiple machines in a distributed system. Furthermore, the bit field positions may be changed and multiple bits may be used. Furthermore, the systems and methods described above can be provided as one or more computer-readable programs or executable instructions embodied on or therein of one or more articles of manufacture (e.g., floppy disk, hard disk, CD-ROM, flash memory card, PROM, RAM, ROM, or magnetic tape). The program can be implemented in any programming language (e.g., LISP, PERL, C, C++, C#) or in any bytecode language (e.g., JAVA). The software program or executable instructions can be stored as object code on or therein of one or more articles of manufacture.

[0162] While the foregoing written description of the methods and systems enables those skilled in the art to make and use embodiments thereof, it should be understood and appreciated that variations, combinations, and equivalents of the specific embodiments, methods, and examples exist. Therefore, the methods and systems should not be limited to the foregoing embodiments, methods, and examples, but rather to all embodiments and methods within the scope and spirit of this disclosure.

Claims

1. An apparatus comprising: The transmitter and one or more processors, wherein The one or more processors are configured to: Identify multiple resource units (RUs) used to transmit corresponding data streams in one or more wireless channels; A corresponding target code rate is determined for each of the plurality of RUs based at least on the signal quality differences between transmissions across the plurality of RUs, wherein the corresponding target code rates are different from each other and different from the basic code rate of a low-density parity-check (LDPC) code; and The corresponding data stream is encoded using the LDPC code with the stated base bitrate by an LDPC encoder to generate a corresponding encoded data stream at the stated target bitrate; and The transmitters are configured to transmit the corresponding encoded data streams using the plurality of corresponding RUs.

2. The device of claim 1, wherein the signal quality difference between the plurality of RUs is the signal-to-noise ratio (SNR) difference between the transmissions across the plurality of RUs.

3. The device of claim 1, wherein the one or more processors are further configured to: Receive data stream; The Media Access Control (MAC) layer determines (1) the different service types of the data stream, (2) the different priority levels of the data stream, or (3) the different quality of service (QoS) levels of the data stream. The data stream is segmented into the corresponding data stream by the MAC layer, based at least on the different data types, the different priority levels, or the different QoS levels.

4. The device of claim 1, wherein the one or more processors are further configured to: The corresponding information bit size is selected for the plurality of RUs based at least on the corresponding target bit rate and the basic bit rate.

5. The device of claim 4, wherein the one or more processors are configured to: At least based on the size of the corresponding information bits, the data stream is segmented into the corresponding data stream through the physical PHY layer; and The PHY layer adds the corresponding data to the corresponding data stream according to the selected corresponding information bit size.

6. The apparatus of claim 4, wherein when encoding the corresponding data stream, the one or more processors are further configured to: Determine the size of the basic information bits corresponding to the basic code rate; A second set of information bits is generated from each corresponding data stream to include a first set of information bits corresponding to the selected corresponding information bit size and one or more bits to increase the size of the second set of information bits to correspond to the basic information bit size; The second group of information bits is encoded using the basic code rate by the LDPC encoder to generate parity check data; and The corresponding encoded data stream is generated by concatenating the second set of information bits and the parity check data.

7. The apparatus of claim 1, wherein the one or more processors are further configured to serially or in parallel encode the respective data streams.

8. The apparatus of claim 1, wherein the one or more processors are further configured to multiplex the respective encoded data streams to perform stream-by-stream modulation.

9. A method comprising: Multiple resource units (RUs) are identified by one or more processors for transmitting corresponding data streams in one or more wireless channels; The one or more processors determine the respective target code rates for the plurality of RUs based at least on the signal quality differences between transmissions across the plurality of RUs, wherein the respective target code rates are different from each other and are different from the basic code rate of the low-density parity-check LDPC code; The corresponding data stream is encoded using the LDPC code having the basic bitrate by an LDPC encoder to generate the corresponding encoded data stream at the corresponding target bitrate; and The corresponding encoded data stream is transmitted via the transmitter using the corresponding RU.

10. The method of claim 9, wherein the signal quality difference between the plurality of RUs is the signal-to-noise ratio (SNR) difference between the transmissions across the plurality of RUs.

11. The method of claim 9, further comprising: Receive data stream; The Media Access Control (MAC) layer determines (1) the different service types of the data stream, (2) the different priority levels of the data stream, or (3) the different quality of service (QoS) levels of the data stream. The data stream is segmented into the corresponding data stream by the MAC layer, based at least on the different data types, the different priority levels, or the different QoS levels.

12. The method of claim 9, further comprising: The corresponding information bit size is selected for the plurality of RUs based at least on the corresponding target bit rate and the basic bit rate.

13. The method of claim 12, further comprising: At least based on the size of the corresponding information bits, the data stream is divided into the corresponding data stream through the physical PHY layer; and The PHY layer adds the corresponding data to the corresponding data stream according to the selected corresponding information bit size.

14. The method of claim 12, wherein encoding the corresponding data stream comprises: Determine the size of the basic information bits corresponding to the basic code rate; A second set of information bits is generated from each corresponding data stream to include a first set of information bits corresponding to the selected corresponding information bit size and one or more bits to increase the size of the second set of information bits to correspond to the basic information bit size; The second group of information bits is encoded using the basic code rate by the LDPC encoder to generate parity check data. and The corresponding encoded data stream is generated by concatenating the second set of information bits and the parity check data.

15. The method of claim 9, wherein encoding the corresponding data stream comprises: The corresponding data stream is encoded serially or in parallel.

16. The method of claim 9, further comprising: The corresponding encoded data streams are multiplexed to perform stream-by-stream modulation.

17. An apparatus comprising: The transmitter and one or more processors, wherein The one or more processors are configured to: Identify multiple resource units (RUs) used to transmit corresponding data streams in one or more wireless channels; The corresponding number of bits is determined for each of the plurality of RUs based at least on the signal quality differences between transmissions across the plurality of RUs, wherein the corresponding number of bits are different from each other; and The corresponding data stream is modulated using the corresponding bit depth to generate the corresponding modulated data stream. The transmitter is configured to transmit the corresponding modulated data stream using the corresponding RU.

18. The device of claim 17, wherein the signal quality difference between the plurality of RUs is a signal-to-noise ratio (SNR) difference between the transmissions across the plurality of RUs.

19. The apparatus of claim 17, wherein, when modulating the respective data stream, the one or more processors are configured to perform quadrature amplitude modulation (QAM) for each RU, using the respective bit depth as the bit depth per symbol.

20. The device of claim 17, wherein the one or more processors are configured to: Receive data stream; The Media Access Control (MAC) layer determines (1) the different service types of the data stream, (2) the different priority levels of the data stream, or (3) the different quality of service (QoS) levels of the data stream. The data stream is segmented into the corresponding data stream by the MAC layer, based at least on the different data types, the different priority levels, or the different QoS levels.

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