Cascaded clock synchronization circuit, clock synchronization circuit, chip and electronic equipment

Abstract

The invention discloses a cascade clock synchronization circuit. The cascade clock synchronization circuit comprises M stages of clock synchronization circuits in cascade connection, and each clock synchronization circuit comprises a phase detection module and a clock generation module. When the i-th count value is X + 2N-1 and X + N-1, the phase detection module outputs an i-th phase detection signal and sets the i-th phase detection signal as an effective level; and the clock generation module carries out frequency division on the ith high-frequency clock N according to the effective level of the ith phase detection signal to generate an ith Nth frequency division clock synchronous with the ith high-frequency clock N, counts the level change of the ith-level phase detection signal to obtain an ith cascade count value, and outputs the ith-level cascade signal and sets the ith-level cascade signal as the effective level when the ith cascade count value is X + 2N-1 and X. According to the invention, the problem of synchronization failure caused by clock skew accumulation of the high-speed clock and the low-speed clock in the multi-channel clock synchronization process is solved. Especially in a multi-channel data synchronous transmission scene such as a multi-BANK multi-SerDes architecture, the problem of clock synchronization failure caused by clock skew accumulation is effectively solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a cascaded clock synchronization circuit, a clock synchronization circuit, a chip and an electronic device. BACKGROUND

[0002] In high-speed communication between a programmable logic chip and an external device, a serial deserialization circuit (SerDes) realizes efficient data transmission by serializing low-frequency parallel data into high-frequency single-bit data (serialization) or inversely deserializing (deserialization). This process relies on the cooperative work of low-frequency and high-frequency clocks and needs to maintain timing synchronization to ensure that data is correctly sampled at the target time.

[0003] Traditional technical solutions generally use a global clock tree, a regional clock, and an IO clock tree for mixed transmission, so that the high-frequency clock and the low-frequency clock are still controlled within a certain clock skew after being transmitted from the source to the target circuit, thereby ensuring that the serial deserialization circuit can work normally within a certain frequency range. Although this solution can meet the basic clock synchronization requirements in a low-channel number or centralized layout scenario, its core logic is still based on the traditional clock distribution strategy. However, when facing more complex system architectures or large-scale parallel processing requirements, the traditional clock distribution strategy gradually reveals its limitations. For example, in a multi-channel data synchronization transmission scenario, the traditional method is difficult to effectively maintain the synchronization relationship between the high-frequency clock and the low-frequency clock of each channel. Especially in complex applications such as multi-BANK multi-SerDes architecture, clock skew will be significantly amplified, thereby limiting the data transmission rate and channel bit width, and further limiting the total data throughput. The multi-BANK multi-SerDes architecture refers to a scenario in which multiple SerDes channels in a programmable logic chip are divided and distributed in different I / O BANKs, and each BANK contains one or more independent SerDes channels. This architecture allows each SerDes channel to work in parallel in different BANKs to achieve higher data throughput and more flexible interface layout, and is widely used in high-performance computing, high-speed communication, and large-scale data transmission scenarios. SUMMARY

[0004] In view of the above problems, the present application provides a cascaded clock synchronization circuit, a clock synchronization circuit, a chip and an electronic device to solve the above technical problems.

[0005] In a first aspect, the present application provides a cascaded clock synchronization circuit, comprising M cascaded clock synchronization circuits, wherein each clock synchronization circuit comprises a phase detection module and a clock generation module.

[0006] The first-stage clock synchronization circuit is configured to: the phase detection module counts a level change of the first high-frequency clock to obtain a first count value, and resets the first count value to X when detecting a rising edge of the first low-frequency clock, and outputs a first phase detection signal and sets it to a valid level when the first count value is X+2N-1 and X+N-1, the first low-frequency clock is in an N frequency division relationship with the first high-frequency clock, and X is greater than or equal to 0;

[0007] The clock generation module generates a first N frequency division clock synchronized with the first high-frequency clock according to a valid level of the first phase detection signal, and counts a level change of the first phase detection signal to obtain a first cascade count value, and outputs a first-stage cascade signal and sets it to a valid level when the first cascade count value is X+2N-1 and X, and the first cascade count value is cyclically increased in a range from X to X+2N-1;

[0008] The i-th stage clock synchronization circuit is configured to: the phase detection module detects a valid level of an (i-1)-th stage cascade signal, counts a level change of an i-th high-frequency clock to obtain an i-th count value, and outputs an i-th phase detection signal and sets it to a valid level when the i-th count value is X+2N-1 and X+N-1, and the i-th count value is cyclically increased in a range from X to X+2N-1;

[0009] The clock generation module generates an i-th N frequency division clock synchronized with the i-th high-frequency clock according to a valid level of the i-th phase detection signal, and counts a level change of the i-th phase detection signal to obtain an i-th cascade count value, and outputs an i-th stage cascade signal and sets it to a valid level when the i-th cascade count value is X+2N-1 and X, and the i-th cascade count value is cyclically increased in a range from X to X+2N-1, the i-th high-frequency clock is a same-frequency synchronization signal of the first high-frequency clock, and i is equal to [2, M].

[0010] In a second aspect, the application provides a clock synchronization circuit, comprising a phase detection module and a clock generation module.

[0011] The phase detection module is configured to count a level change of a first high-frequency clock to obtain a first count value, and reset the first count value to X when detecting a rising edge of a first low-frequency clock, and output a first phase detection signal and set it to a valid level when the first count value is X+2N-1 and X+N-1, the first low-frequency clock is in an N frequency division relationship with the first high-frequency clock, and X is greater than or equal to 0.

[0012] The clock generation module is configured to generate a first N-divided clock synchronized with the first high-frequency clock according to an active level of the first phase detection signal, and count a level change of the first phase detection signal to obtain a first cascade count value, and output a first level cascade signal and set the first level cascade signal to the active level when the first cascade count value is X+2N-1 and X, and the first cascade count value is cyclically increased in a range from X to X+2N-1.

[0013] In a third aspect, the application further provides a chip comprising the cascade clock synchronization circuit of the first aspect.

[0014] In a fourth aspect, the application further provides an electronic device comprising the chip of the third aspect.

[0015] The cascade clock synchronization circuit, the clock synchronization circuit, the chip and the electronic device provided by the application, in the cascade clock synchronization circuit, the first level clock synchronization circuit generates a cascade signal through a clock generation module based on a high-low frequency clock phase relationship detected by a phase detection module, thereby forming a cascade feedback mechanism with a next level clock synchronization circuit, the next level circuit generates a next level cascade signal after adjusting the phase using the cascade signal, and finally realizes clock synchronization of each level circuit, thereby solving the technical problem of synchronization failure of high-speed clock and low-speed clock caused by clock skew accumulation in a multi-clock synchronization process, and having the technical effects of high synchronization precision, low resource consumption and reusability. Especially in the multi-channel data synchronization transmission scene such as a multi-BANK multi-SerDes architecture, the technical problem of synchronization failure of high-speed clock and low-speed clock caused by clock skew accumulation is effectively solved, thereby improving the data transmission rate and channel bit width, and finally improving the total data throughput.

[0016] These and other aspects of the application will become more fully understood from the following detailed description, given by way of example only. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0018] Figure 1 A schematic diagram of the cascade clock synchronization circuit provided by the embodiment of the application is shown.

[0019] Figure 2 A timing diagram of clock skew of a high-frequency clock and a low-frequency clock is shown.

[0020] Figure 3Another timing diagram showing clock skew of high frequency clock and low frequency clock.

[0021] Figure 4 A timing diagram of the first-stage clock synchronization circuit provided by the embodiment of the application is shown.

[0022] Figure 5 A timing diagram of the second-stage cascaded clock synchronization circuit provided by the embodiment of the application is shown.

[0023] Figure 6 A schematic diagram of the clock synchronization circuit provided by the embodiment of the application is shown.

[0024] Figure 7 Another schematic diagram of the clock synchronization circuit provided by the embodiment of the application is shown.

[0025] Figure 8 Another timing diagram of the second-stage cascaded clock synchronization circuit provided by the embodiment of the application is shown.

[0026] Figure 9 Still another schematic diagram of the clock synchronization circuit provided by the embodiment of the application is shown.

[0027] Figure 10 Another timing diagram of the first-stage clock synchronization circuit provided by the embodiment of the application is shown.

[0028] Figure 11 Still another schematic diagram of the clock synchronization circuit provided by the embodiment of the application is shown.

[0029] Figure 12 Still another schematic diagram of the clock generation module provided by the embodiment of the application is shown.

[0030] Figure 13 Still another schematic diagram of the clock generation module provided by the embodiment of the application is shown.

[0031] Figure 14 Another schematic diagram of the cascaded clock synchronization circuit provided by the embodiment of the application is shown.

[0032] Figure 15 A delay timing diagram of the cascaded clock synchronization circuit provided by the embodiment of the application is shown.

[0033] Figure 16 A schematic diagram of the clock synchronization circuit provided by the embodiment of the application is shown.

[0034] Figure 17 Another schematic diagram of the clock synchronization circuit provided by the embodiment of the application is shown.

[0035] Figure 18 A schematic diagram of the chip provided by the embodiment of the application is shown.

[0036] Figure 19 A schematic diagram of an electronic device is shown. DETAILED DESCRIPTION

[0037] In order to make the persons skilled in the art better understand the scheme of the present application, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by the person skilled in the art without creative work are within the protection scope of the present application.

[0038] In the embodiments of the present application, it should be noted that, in this document, relational terms such as first and second and the like are used solely to distinguish one entity or action from another entity or action, without necessarily requiring or implying any actual such relationship or order between or among the entities or actions.

[0039] Moreover, the terms "comprising", "comprises", "comprised of" or any other variation thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises a... " does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the a recited element.

[0040] It should be noted that, in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical elements can be direct or indirect connection between the two electrical elements. For example, A is connected with B, which can be direct connection between A and B, or indirect connection between A and B through one or more other electrical elements.

[0041] The following is a description of part of the signal labels in the drawings of the embodiments of the present application, which will not be repeated in the subsequent content.

[0042] clk_in1: first high frequency clock; clk_div_in1: first low frequency clock; inv_en1: first phase detection signal; clk_div_adj1: first N-divided clock; cascade_sync1: first stage cascade signal; clk_in2: second high frequency clock; clk_div_in2: second low frequency clock; inv_en2: second phase detection signal; clk_div_adj2: second N-divided clock; cascade_sync2: second stage cascade signal; clk_inM: Mth high frequency clock; clk_div_inM: Mth low frequency clock; inv_enM: Mth phase detection signal; clk_div_adjM: Mth N-divided clock; cascade_syncM: Mth stage cascade signal; clk_sync1: high frequency clock output by first gate unit of first stage clock synchronization circuit; clk_div_sync1: low frequency clock output by second gate unit of first stage clock synchronization circuit; wherein, 1-M represents the signal of the i-th stage clock synchronization circuit, i=[1, M]. count1_1: first count value; count1_2: first cascade count value; count2_1: second count value.

[0043] clk_in: high frequency clock; clk_div_in: low frequency clock; cascade_sync_0: cascade signal of previous stage clock synchronization circuit; inv_en: phase detection signal; clk_div_adj: N-divided clock; cascade_sync_1: cascade signal of current stage clock synchronization circuit; clk_align_ind: clock alignment indication signal; clkout_en: clock enable signal; clk_sync: high frequency clock output by first gate unit; clk_div_sync: low frequency clock output by second gate unit; wherein, the signals corresponding to these labels are not specified as belonging to which stage clock synchronization circuit, but can refer to the signals of any stage clock synchronization circuit.

[0044] sync_cmd: synchronization instruction signal; clkout_en1: first clock enable signal; clkout_en2: second clock enable signal; idel: idle signal; cascade_sync_1_bypass_n: first stage cascade signal after continuous bypassing of multi-stage clock synchronization circuit, n represents the number of circuit stages of continuous bypassing.

[0045] The embodiment of the present application provides a cascade clock synchronization circuit, Figure 1 The schematic diagram of the cascade clock synchronization circuit provided by the embodiment of the present application is shown as Figure 1As shown, the cascade clock synchronization circuit includes M-stage cascade-connected clock synchronization circuits, and each clock synchronization circuit includes a phase detection module and a clock generation module.

[0046] The first-stage clock synchronization circuit is configured to: the phase detection module counts the level change of the first high-frequency clock to obtain a first count value, and resets the first count value to X when detecting the rising edge of the first low-frequency clock, and outputs a first phase detection signal and sets it to a valid level when the first count value is X+2N-1 and X+N-1, the first low-frequency clock is in an N-division relationship with the first high-frequency clock, and X≥0.

[0047] The clock generation module generates a first N-division clock synchronized with the first high-frequency clock according to the valid level of the first phase detection signal, and counts the level change of the first phase detection signal to obtain a first cascade count value, and outputs a first-stage cascade signal and sets it to a valid level when the first cascade count value is X+2N-1 and X, and the first cascade count value is cyclically increased in the range of X to X+2N-1;

[0048] Optionally, Figure 2 A timing diagram showing the clock skew of the high-frequency clock and the low-frequency clock is shown, Figure 3 Another timing diagram showing the clock skew of the high-frequency clock and the low-frequency clock is shown, and for the phase detection module, there are two cases of the clock skew of the high-frequency clock and the low-frequency clock accepted by the phase detection module, one is that the rising edge of the low-frequency clock is located in the positive period of the high-frequency clock as shown in Figure 2 Another is that the rising edge of the low-frequency clock is located in the negative period of the low-frequency clock as shown in Figure 3 That is, in the first-stage clock synchronization circuit, the relationship between the first high-frequency clock and the first low-frequency clock has the two cases as described above, of course, the first high-frequency clock and the first low-frequency clock can also have the possibility of being in a synchronous state.

[0049] Taking the first high-frequency clock and the first low-frequency clock as an example, the phase relationship is shown in Figure 2 The timing of the first-stage clock synchronization circuit is described. Figure 4 A timing diagram of the first-stage clock synchronization circuit provided by the embodiment of the application is shown, as shown in Figure 4As shown, the phase detection module counts the level change of the first high-frequency clock to obtain a first count value, and when the first count value is 3 and 1, the first phase detection signal output is at a high level (active level), and when the first count value is 2 and 0, the first phase detection signal output is at a low level (inactive level), thereby reflecting the phase difference between the first high-frequency clock and the first low-frequency clock. When the clock generation module adjusts the phase, the transition edge of the first N-divided clock is aligned with the time when the first phase detection signal transitions from a high level to a low level, achieving phase synchronization with the high-frequency clock. At the same time, when generating the first-stage cascaded signal, the clock generation module counts the level change of the first phase detection signal to obtain a first cascaded count value, and when the first cascaded count value is 3 and 0, a high-level (active level) first-stage cascaded signal is generated, and in other cases, the first-stage cascaded signal remains at a low level (inactive level), thereby forming a cascaded signal with a specific timing relationship.

[0050] It can be understood that in the embodiments of the present application, the active level and the inactive level are relative states, that is, when the high level is set as the active level, the low level opposite to the high level is the inactive level, and vice versa.

[0051] The i-th stage clock synchronization circuit is configured such that: when the phase detection module detects the active level of the (i-1)-th stage cascaded signal, the i-th high-frequency clock is counted to obtain an i-th count value, and when the i-th count value is X+2N-1 and X+N-1, the i-th phase detection signal is output and set to an active level, and the i-th count value is cyclically incremented in the range of X to X+2N-1.

[0052] The clock generation module generates an i-th N-divided clock synchronized with the i-th high-frequency clock according to the active level of the i-th phase detection signal, and counts the level change of the i-th phase detection signal to obtain an i-th cascaded count value, and when the i-th cascaded count value is X+2N-1 and X, the i-th stage cascaded signal is output and set to an active level, the i-th cascaded count value is cyclically incremented in the range of X to X+2N-1, the i-th high-frequency clock is a same-frequency synchronization signal of the first high-frequency clock, and i=[2, M].

[0053] Alternatively, the first high-frequency clock and the first low-frequency clock are in a two-divided relationship, and their phase relationship is as shown in Figure 3 As shown, the timing of the i-th stage clock synchronization circuit when i=2 is described, Figure 5 A timing diagram of a two-stage cascaded clock synchronization circuit provided by an embodiment of the present application is shown, as shown in Figure 5As shown, after the first-stage cascade signal output by the first-stage clock synchronization circuit is high (active level), the phase detection module of the second-stage clock synchronization circuit starts to count the level change of the second high-frequency clock to obtain a second count value. When the second count value is 3 and 1, the second phase detection signal output is high (active level), and when the second count value is 2 and 0, the second phase detection signal output is low (inactive level), thereby reflecting the phase difference between the first high-frequency clock and the first low-frequency clock. The working principle and timing of the clock generation module of the i-th stage clock synchronization circuit are the same as those of the clock generation module of the first-stage clock synchronization circuit, and the working principle of the first-stage clock synchronization circuit has been described in combination with the timing in the above embodiment, and therefore the clock generation module of the i-th stage clock synchronization circuit is not repeated here.

[0054] It can be understood that the specific implementation manner of counting the signal level change is not limited in the embodiments of the present application, for example, the edge detection manner can be used for counting, that is, the counting operation is triggered by capturing the rising edge and / or falling edge of the signal; or the level sensing manner can also be used to directly count according to the high / low level state of the signal, and the specific selection can be made flexibly according to the actual application scene and circuit design requirements. In addition, in the above embodiment, X represents the starting value of counting, which can be set to any integer, and is usually set to 0.

[0055] The cascade clock synchronization circuit, the clock synchronization circuit, the chip and the electronic device provided by the embodiments of the present application, in the cascade clock synchronization circuit, the first-stage clock synchronization circuit generates a cascade signal through the clock generation module according to the high / low frequency clock phase relationship detected by the phase detection module, thereby forming a cascade feedback mechanism with the next-stage clock synchronization circuit, the next-stage circuit generates a next-stage cascade signal after adjusting the phase by using the cascade signal, and finally the clock synchronization of each stage circuit is realized. The technical problems of synchronization failure caused by clock skew accumulation of high-speed clock and low-speed clock in the multi-channel clock synchronization process are solved, and the technical effects of high synchronization precision, low resource consumption and reusability are achieved. Especially in the multi-channel data synchronization transmission scene such as multi-BANK multi-SerDes architecture, the technical problems of synchronization failure caused by clock skew accumulation of high-speed clock and low-speed clock are effectively solved, and the data transmission rate and channel bit width are improved, and finally the total data throughput is improved.

[0056] In some embodiments, Figure 6 A schematic diagram of the clock synchronization circuit provided by the embodiments of the present application is shown, as shown in Figure 6 As shown, the phase detection module includes a clock sampling unit, a first counting unit and a comparison unit.

[0057] The first-stage clock synchronization circuit is configured to:

[0058] The clock sampling unit receives the first high-frequency clock and the first low-frequency clock, samples the first low-frequency clock through double edges of the first high-frequency clock, and outputs a first reset signal when detecting a rising edge of the first low-frequency clock.

[0059] The first counting unit receives the first high-frequency clock, counts a level change of the first high-frequency clock to obtain a first counting value, and resets the first counting value to X when receiving the first reset signal.

[0060] The comparison unit receives the first counting value, compares the first counting value with preset X+2N-1 and X+N-1, outputs a first phase detection signal and makes it in an active level state when the first counting value is equal to X+2N-1 or X+N-1, and outputs the first phase detection signal and makes it in an inactive level state when the first counting value is not equal to X+2N-1 and the first counting value is not equal to X+N-1.

[0061] The i-th stage clock synchronization circuit is configured to:

[0062] The clock sampling unit receives the i-th high-frequency clock and the (i-1)-th stage cascade signal, samples the i-th stage cascade signal through a single edge of the i-th high-frequency clock, and outputs an i-th reset signal when detecting an active level of the (i-1)-th stage cascade signal;

[0063] The first counting unit is reset to X when receiving the i-th reset signal, and counts a level change of the i-th high-frequency clock to obtain an i-th counting value;

[0064] The comparison unit receives the i-th counting value, compares the i-th counting value with preset X+2N-1 and X+N-1, outputs an i-th phase detection signal and makes it in an active level state when the i-th counting value is equal to X+2N-1 or X+N-1, and outputs the i-th phase detection signal and makes it in an inactive level state when the i-th counting value is not equal to X+2N-1 and the i-th counting value is not equal to X+N-1.

[0065] Optionally, in the embodiments of the present application, the phase detection module realizes clock sampling through a clock sampling unit; the first-stage clock synchronization circuit samples the low-frequency clock in a double-edge sampling mode, and generates a reset signal of the first counting unit when recognizing the rising edge of the low-frequency clock; the first counting unit continuously counts according to the first high-frequency clock, and resets the current count value to X when receiving the first reset signal each time; the comparison unit compares the first count value with two preset values X+2N-1 and X+N-1, and outputs a corresponding first phase detection signal according to the comparison result, thereby indicating the phase difference between the first high-frequency clock and the first low-frequency clock. The i-th stage clock synchronization circuit samples the signal of the previous stage in a single-edge sampling mode, and only triggers the sampling action depending on the rising edge or the falling edge of the i-th high-frequency clock, and outputs the reset signal of the first counting unit when recognizing the valid level of the signal of the previous stage, and the first counting unit resets the count value to X after receiving the i-th reset signal, and performs cyclic counting in the range of X to X+2N-1 according to the i-th high-frequency clock, so that the count value of the i-th stage clock synchronization circuit is synchronized with the count value of the first-stage clock synchronization circuit. The comparison unit compares the i-th count value with two preset values X+2N-1 and X+N-1, and outputs a corresponding i-th phase detection signal according to the comparison result, thereby indicating the phase difference between the i-th high-frequency clock and the first low-frequency clock.

[0066] It can be understood that the embodiments of the present application aim to provide a phase detection scheme suitable for a cascaded clock synchronization circuit, so as to realize clock synchronization and phase alignment between multiple clock domains without limiting the specific circuit implementation of the clock sampling unit, the first counting unit and the comparison unit. Through the cooperative work of the above-mentioned units, the scheme can effectively improve the stability and accuracy of cross-clock-domain signal transmission, and at the same time adapt to different application scenarios.

[0067] Exemplarily, in one embodiment, the clock sampling unit can be a sampling circuit composed of flip-flops / latches and / or combinational logic, configured to sample the low-frequency clock or the cascade signal of the previous stage using the double edges or single edge of the high-frequency clock, and to generate the high / low level reset signal according to the sampling result. In another embodiment, in a programmable logic device (such as an FPGA), the clock sampling unit can also be implemented by configuring the internal register resources and lookup table (LUT), thereby having higher flexibility and reconfigurability. The core function of the first counting unit is to count the number of level changes of the high-frequency clock, and therefore it can be implemented by a simple binary counter, or a complex counter with programmable features, and according to actual needs, it can also be configured in upward counting, downward counting or bidirectional counting mode, and support dynamic adjustment of the counting range (X to X+2N-1), so as to optimize the performance in different application scenarios. Similarly, in a programmable logic device, the first counting unit can be efficiently implemented by configuring the internal logic units and carry chain structure. The main task of the comparison unit is to compare the current counting value with the preset value (X+2N-1 and X+N-1), and output the corresponding phase detection signal accordingly, which can be constructed by using basic digital logic gate circuits (such as AND gate, OR gate, etc.), or can be written by customized comparison logic with higher level hardware description language (HDL). In a programmable logic device, the comparison unit can be implemented by combinational logic or state machine, which is convenient for flexible configuration and upgrading according to different needs. Each of the above units can be flexibly selected in specific implementation form according to different design goals and technical platforms, and should fall within the protection scope of the present application.

[0068] In some embodiments, as shown in Figure 6 the clock generation module includes a frequency division unit, a second counting unit, and a cascade signal generation unit;

[0069] The first-stage clock synchronization circuit is configured to:

[0070] The frequency division unit receives the first high-frequency clock and the first phase detection signal, generates a first N-division clock based on the first high-frequency clock, and causes the first N-division clock to flip once when detecting the active level of the first phase detection signal.

[0071] The second counting unit receives the first phase detection signal, and counts the level changes of the first phase detection signal to obtain a first cascade counting value.

[0072] The cascade signal generation unit receives the first cascade counting value, outputs a first-stage cascade signal and makes it in an active level state when the first cascade counting value is equal to X+2N-1 or X, and outputs the first-stage cascade signal and makes it in an inactive level state when the first cascade counting value is not equal to X+2N-1 and the first cascade counting value is not equal to X.

[0073] The i-th stage clock synchronization circuit is configured as follows:

[0074] The frequency divider unit receives the i-th high-frequency clock and the i-th phase detection signal, generates the iN-th frequency divider clock based on the i-th high-frequency clock, and causes the iN-th frequency divider clock to undergo a level flip when the effective level of the i-th phase detection signal is detected.

[0075] The second counting unit receives the i-th phase detection signal and counts the level changes of the i-th phase detection signal to obtain the i-th cascade count value.

[0076] The cascade signal generation unit receives the i-th cascade count value. When the i-th cascade count value is equal to X+2N-1 or X, it outputs the i-th cascade signal and puts it in an active level state. When the i-th cascade count value is not equal to X+2N-1 and the i-th cascade count value is not equal to X, it outputs the i-th cascade signal and puts it in an inactive level.

[0077] Optionally, the frequency division unit receives a high-frequency clock signal (e.g., a first high-frequency clock) and a phase detection signal, and generates an N-division clock with a frequency of 1 / N of the original high-frequency clock based on the high-frequency clock and the bit detection signal. Specifically, the transition edge of the N-division clock is controlled by the phase detection signal. When the frequency division unit detects the effective level of the i-th phase detection signal, the i-th N-division clock undergoes a level flip, that is, the transition edge of the N-division clock will be aligned with the moment when the phase detection signal transitions from a high level to a low level, thus achieving phase synchronization with the high-frequency clock. The second counting unit counts the level changes of the phase detection signal. Whenever the phase detection signal undergoes a level change (e.g., from low to high or from high to low), the counting result will cyclically increase within the range of X to X+2N-1. At this time, the count value of the second counting unit is synchronized with the count value of the first counting unit. The cascade signal generation unit determines whether the corresponding cascade signal needs to be activated based on the cascade count value of the second counting unit, thereby instructing the next-stage clock synchronization circuit to perform clock synchronization.

[0078] It is understood that the purpose of this application is to provide a synchronous clock generation scheme suitable for cascaded clock synchronization circuits, so as to achieve clock synchronization and phase alignment between multiple clock domains, without limiting the specific circuit implementation of the frequency division unit, the second counting unit, and the cascaded signal generation unit. This scheme, through the coordinated operation of the above units, can effectively improve the stability and accuracy of cross-clock domain signal transmission, while adapting to different application scenarios.

[0079] For example, the frequency divider unit can achieve the N-frequency division function by periodically counting the high-frequency clock and triggering a flip-flop based on the phase detection signal. It can be constructed using asynchronous or synchronous counters in conjunction with trigger logic, or flexibly implemented in a programmable logic device using a state machine or hardware description language (HDL). Furthermore, the frequency divider unit can also be implemented based on a sampling structure, such as using the high-frequency clock to sample the edge of the phase detection signal, and immediately triggering the level flip-flop of the N-frequency divider clock when a valid level of the phase detection signal is detected, thereby achieving an N-frequency divider output that is synchronized with and phase-aligned with the high-frequency clock. The implementation of the second counting unit includes, but is not limited to, binary counters, cyclic counters, etc.; the cascaded signal generation unit can be implemented using combinational logic gates, comparator modules, or configurable logic resources within the FPGA. All of the above units can be flexibly implemented in specific forms according to different design goals and technology platforms, and all should fall within the protection scope of this application.

[0080] In some embodiments, Figure 7 Another schematic diagram of the clock synchronization circuit provided in an embodiment of this application is shown, such as... Figure 7 As shown, the clock synchronization circuit of the first stage is further configured as follows:

[0081] Before receiving the first cascade count value, the cascade signal generation unit receives a preset clock alignment indication signal. When the clock alignment indication signal indicates that the rising edge of the first high-frequency clock is aligned with the falling edge of the first N-division clock, the effective level and the invalid level of the first cascade signal are reversed, and the first cascade signal is output and made to be in an invalid level state.

[0082] The i-th stage clock synchronization circuit is also configured as follows:

[0083] Before receiving the i-th cascade count value, the cascade signal generation unit receives a preset clock alignment indication signal. When the clock alignment indication signal indicates that the rising edge of the i-th high-frequency clock is aligned with the falling edge of the iN-division clock, the effective level and invalid level of the i-th cascade signal are reversed, and the i-th cascade signal is output and made to be in an invalid level state.

[0084] Optionally, when the clock skew relationship between the high-frequency clock and the low-frequency clock is as follows: Figure 3 As shown, the timing sequence of the first-stage clock synchronization circuit and the second-stage clock synchronization circuit is as follows: Figure 5 As shown, at this time, the rising edge of the first low-frequency clock is aligned with the rising edge of the first N-division clock. In order to indicate the alignment relationship between the first high-frequency clock and the first low-frequency clock to the second-stage clock synchronization circuit, the phase detection module of the second-stage clock synchronization circuit is configured to sample the high level (effective level) of the first-stage cascaded signal by the rising edge of the second high-frequency clock. At this time, the first-stage cascaded signal can be sampled directly.

[0085] However, Figure 8 Another timing diagram of the two-stage cascaded clock synchronization circuit provided in this application embodiment is shown, where the clock skew relationship between the high-frequency clock and the low-frequency clock is as follows: Figure 2 When shown, then as Figure 8 As shown, at this time, the falling edge of the first low-frequency clock is aligned with the falling edge of the first N-division clock. In order to indicate the alignment relationship between the first high-frequency clock and the first low-frequency clock to the second-stage clock synchronization circuit, the embodiment of this application first inverts the effective level and the ineffective level of the first-stage cascaded signal, outputs the first-stage cascaded signal and keeps it in an ineffective level state for a period of time. This is done to avoid misjudgment when the second-stage clock synchronization circuit samples. Then, the phase detection module of the second-stage clock synchronization circuit samples the low level (effective level) of the first-stage cascaded signal through the falling edge of the second high-frequency clock.

[0086] In summary, in the embodiments of this application, when the clock skew relationship between the high-frequency clock and the low-frequency clock is as follows: Figure 3 As shown, the level sequence of the first-stage cascaded signal is 010. At this time, the second-stage clock synchronization circuit's sampling of the first-stage cascaded signal on the rising edge is stable. When the clock skew relationship between the high-frequency clock and the low-frequency clock is as follows... Figure 2 As shown, the level sequence of the first-stage cascaded signal is 101. At this time, the second-stage clock synchronization circuit's falling-edge sampling of the first-stage cascaded signal is stable. To distinguish between these two cases, the first-stage cascaded signal is set to output a relatively long consecutive 0 or 1. If it is a consecutive 0, rising-edge sampling is used; if it is a 1, falling-edge sampling is used. Specifically, the first-stage cascaded signal is set to default output 0 (invalid level). When it is necessary to indicate that the next stage uses falling-edge sampling, it will first jump to 1 and hold, that is, convert the valid level 1 to an invalid level while the first-stage cascaded signal still outputs an invalid level 1. Since it only jumps to 1 and does not generate a 010 sequence, no misjudgment occurs. After the invalid level 1 is held for a sufficient time, continuous detection of invalid level 1 switches to falling-edge sampling. Then, a 101 level sequence can be generated for synchronization.

[0087] It is understood that in this embodiment, the cascaded signal generation unit does not directly receive the cascaded signal from the previous stage, and the frequency division unit and the cascaded signal generation unit of the clock generation module are two independent units. Therefore, the cascaded signal generation unit can receive clock alignment indication signals from multiple sources and then output the corresponding cascaded signal accordingly. For example, the clock alignment indication signal can be output through an external circuit other than the cascaded clock synchronization circuit, so that the external circuit can determine the clock skew relationship between the high-frequency clock and the low-frequency clock; another example is that the clock alignment indication signal can come from the frequency division unit; yet another example is that the clock alignment indication signal can also come from the phase detection module. This embodiment does not limit the source of the signal.

[0088] In some embodiments, Figure 9 Another schematic diagram of the clock synchronization circuit is shown in FIG. 6, which is provided by the embodiments of the present application. Figure 9 As shown in FIG. 6, in the embodiments of the present application, the clock generation module further comprises a clock output control unit, a first gating unit and a second gating unit.

[0089] The first-stage clock synchronization circuit is configured to:

[0090] The clock output control unit receives the first cascade count value, and outputs the first clock enable signal and makes it in the active level state when detecting that the first cascade count value is X+2N-1.

[0091] The first gating unit receives the first high-frequency clock and the first clock enable signal, and outputs the first high-frequency clock when detecting the active level of the first clock enable signal.

[0092] The second gating unit receives the first N-divided clock and the first clock enable signal, and outputs the first N-divided clock when detecting the active level of the first clock enable signal.

[0093] The second-stage clock synchronization circuit is configured to:

[0094] The clock output unit receives the i-th cascade count value, and outputs the i-th clock enable signal and makes it in the active level state when detecting that the i-th cascade count value is 2N-1.

[0095] The first gating unit receives the i-th high-frequency clock and the i-th clock enable signal, and outputs the i-th high-frequency clock when detecting the active level of the i-th clock enable signal.

[0096] Optionally, taking the timing of the first-stage clock synchronization circuit as an example, Figure 10 Another timing diagram of the first-stage clock synchronization circuit is shown in FIG. 7, which is provided by the embodiments of the present application. Figure 10 As shown in FIG. 7, in order to make the high-frequency clock and the low-frequency clock output by the clock generation module aligned at the first rising edge, the two are controlled by gating, and the first gating unit and the second gating unit are in the closed state before the phase is aligned, and the clock enable signal output by the clock output control unit is 0 (inactive level), so as to avoid the unknown state to the circuit. When the phase is aligned, the clock enable signal will be pulled up when the count value of the second counting unit reaches the maximum value, i.e., 2N-1, and the first gating unit and the second gating unit start to output the high-frequency clock and the low-frequency clock aligned at the rising edge after the clock enable signal is active.

[0097] It can be understood that the embodiments of the present application aim to realize phase alignment by automatically gating the high-frequency clock and the low-frequency clock, and the structure of the first gating unit, the second gating unit and the clock output control unit is not limited. For example, the clock output control unit can be designed as a logic unit receiving a count value, outputting a high level as a clock enable signal when detecting that the count value is equal to a preset threshold (such as 2N-1), and keeping low level at other times. The gating can be realized by using a logic gate structure, for example, by using an AND gate. In addition, the first gating unit, the second gating unit and the clock output control unit described above can all be realized by using an FPGA device.

[0098] In some embodiments, Figure 11 Another schematic diagram of the clock synchronization circuit provided by the embodiments of the present application is shown in FIG. 6. As shown in FIG. 6, the clock synchronization circuit provided by the embodiments of the present application further includes: Figure 11

[0099] a clock output control circuit, configured to output a first enable signal and a second enable signal in response to a synchronization instruction signal.

[0100] The clock generation module further includes a first gating unit and a second gating unit.

[0101] The first-stage clock synchronization circuit is configured to.

[0102] The first gating unit receives the first high-frequency clock and the first clock enable signal, and outputs the first high-frequency clock.

[0103] The second gating unit receives the first N-divided clock and the first clock enable signal, and outputs the first N-divided clock.

[0104] The second-stage clock synchronization circuit is configured to:

[0105] The first gating unit receives the i-th high-frequency clock and the i-th clock enable signal, and outputs the i-th high-frequency clock.

[0106] The second gating unit receives the i-th N-divided clock and the clock enable signal, and outputs the i-th N-divided clock.

[0107] Optionally, the cascaded clock synchronization circuit provided by the embodiments of the present application, in addition to setting a gating unit at each stage of the clock synchronization circuit to automatically synchronize the clock, can also manually control the clock synchronization of each stage of the clock synchronization circuit by setting a clock output control circuit.

[0108] ​It can be understood that the embodiments of the present application aim to realize phase alignment by manually gating the high-frequency clock and the low-frequency clock, and the specific structure of the clock output control circuit is not limited, and the circuit structure for receiving external instructions and generating corresponding enable signals is easy to understand and conventionally designed for those skilled in the art.

[0109] In some embodiments, Figure 12 Another schematic diagram of the clock generation module provided by the embodiments of the present application is shown, as shown in Figure 12 The cascade clock synchronization circuit provided by the embodiments of the present application further includes a period control unit, an input end of the period control unit is connected with an output end of the second counting unit, and an output end of the period control unit is connected with an input end of the cascade signal generation unit.

[0110] The first-stage clock synchronization circuit is configured to:

[0111] The period control unit is configured to receive the first cascade counting value and output the first cascade counting value every Y counting periods.

[0112] The i-th stage clock synchronization circuit is configured to:

[0113] The period control unit is configured to receive the i-th cascade counting value and output the i-th cascade counting value every Y counting periods.

[0114] In some embodiments, Figure 13 Another schematic diagram of the clock generation module provided by the embodiments of the present application is shown, as shown in Figure 13 The cascade clock synchronization circuit provided by the embodiments of the present application further includes a period control unit, an input end of the period control unit is connected with an output end of the second counting unit, and an output end of the period control unit is connected with an input end of the cascade signal generation unit.

[0115] The first-stage clock synchronization circuit is configured to:

[0116] The period control unit is configured to receive the first cascade signal and output the i-th cascade signal L divided by L, L>1.

[0117] The i-th stage clock synchronization circuit is configured to.

[0118] The period control unit is configured to receive the i-th cascade signal and output the i-th cascade signal L divided by L.

[0119] The period control unit provided by the embodiments of the present application makes the cascade signal output once in multiple counting periods, thereby reducing the overall power consumption of the circuit.

[0120] It can be understood that the purpose of the embodiment of the present application is to set the period control unit, so that the cascade signal is not output every counting period, but is triggered once every several counting periods, thereby effectively reducing the overall power consumption of the circuit. The specific implementation structure of the period control unit is not limited in the embodiment of the present application. For example, the period control unit can be designed as a frequency division module, which receives the cascade signal or the counting value as input and outputs the cascade signal once every L counting periods (L > 1). For another example, the period control unit can be realized by a logic circuit in the FPGA; for another example, the period control unit can also realize the same function in a state machine control mode. The above structures can be flexibly selected according to the actual application scene, as long as they realize the basic function of "periodic control of cascade signal output", which should fall within the protection scope of the present application.

[0121] In some embodiments, Figure 14 Another schematic diagram of the cascade clock synchronization circuit provided by the embodiment of the present application is shown, as shown in Figure 14 The cascade clock synchronization circuit provided by the embodiment of the present application further comprises:

[0122] Further comprising a first selection unit and a second selection unit.

[0123] The first-stage clock synchronization circuit is configured to:

[0124] The first selection unit receives the first low-frequency clock and the preset idle signal, and selects the first low-frequency clock to output.

[0125] The second selection unit receives the idle signal and the first-stage cascade signal, and selects the first-stage cascade signal to output.

[0126] The i-stage clock synchronization circuit is configured to:

[0127] The first selection unit receives the i low-frequency clock and the (i-1)-stage cascade signal, and selects the i low-frequency clock or the (i-1)-stage cascade signal to output.

[0128] When the phase detection module detects the active level of the i low-frequency clock or the (i-1)-stage cascade signal, the i counting value is obtained by counting the level change of the i high-frequency clock, and when the i counting value is X+2N-1 and X+N-1, the i phase detection signal is output and set to the active level.

[0129] The clock generation module generates the i N-divided clock synchronized with the i high-frequency clock according to the active level of the i phase detection signal, and obtains the i cascade counting value by counting the level change of the i-stage phase detection signal, and when the i cascade counting value is X+2N-1 and X, the i-stage cascade signal is output and set to the active level.

[0130] The second selection unit receives the (i-1)th cascade signal and the ith cascade signal, and selects the (i-1)th cascade signal or the ith cascade signal to output.

[0131] Optionally, the first selection unit and the second selection unit are used to provide a synchronization selection for each stage of the clock synchronization circuit, when the clock synchronization of the clock synchronization circuit of the current stage is not needed, the first selection unit and the second selection unit are set to make the cascade signal of the previous stage directly transmitted to the clock synchronization circuit of the next stage through the selection unit, so as to realize the clock bypass of the clock synchronization circuit of the current stage. Figure 15 A delay timing diagram of the cascade clock synchronization circuit provided by the embodiment of the application is shown in FIG. 3. Figure 15 As shown in FIG. 3, if the first cascade signal is not used for clock synchronization of the continuous n stages of the clock synchronization circuit, the first cascade signal will generate an additional delay difference, and the delay difference will be accumulated with the number of the continuous bypass circuits, and the accumulated delay of the first cascade signal can still be synchronized successfully in a certain range, so that the number of the continuous bypass stages can be controlled. When the clock synchronization of the clock synchronization circuit of a certain stage is performed after the continuous bypass, the accumulated delay difference will be eliminated in this stage of the circuit, and the delay difference is calculated again in the next stage of the clock synchronization circuit.

[0132] The embodiment of the application further provides a clock synchronization circuit, Figure 16 A schematic diagram of the clock synchronization circuit provided by the embodiment of the application is shown in FIG. 4. Figure 16 As shown in FIG. 4, the clock synchronization circuit comprises a phase detection module and a clock generation module.

[0133] The phase detection module is used to count the level change of the first high-frequency clock to obtain a first count value, and reset the first count value to X when the rising edge of the first low-frequency clock is detected, and output a first phase detection signal and set to an effective level when the first count value is X+2N-1 and X+N-1, the first low-frequency clock and the first high-frequency clock are in an N frequency division relationship, and X≥0.

[0134] The clock generation module is used to generate a first N frequency division clock synchronized with the first high-frequency clock according to the effective level of the first phase detection signal, and count the level change of the first phase detection signal to obtain a first cascade count value, and output a first stage cascade signal and set to an effective level when the first cascade count value is X+2N-1 and X, and the first cascade count value is cyclically increased in the range of X to X+2N-1.

[0135] For other details of the above technical solutions realized in the clock synchronization circuit, refer to the description of the first clock synchronization circuit of the cascade clock synchronization circuit provided in the above embodiment, which will not be repeated here.

[0136] In some embodiments, Figure 17Another schematic diagram of the clock synchronization circuit provided by the embodiments of the present application is shown in FIG. 3, which is similar to the schematic diagram shown in FIG. 2. As shown in FIG. 3, the phase detection module includes: Figure 17

[0137] The clock sampling unit is configured to receive the first high-frequency clock and the first low-frequency clock, sample the first low-frequency clock through double edges of the first high-frequency clock, and output a first reset signal when detecting a rising edge of the first low-frequency clock.

[0138] The first counting unit is configured to receive the first high-frequency clock, count a level change of the first high-frequency clock to obtain a first counting value, and reset the first counting value to X when receiving the first reset signal.

[0139] The comparison unit is configured to receive the first counting value, compare the first counting value with preset X+2N-1 and X+N-1, output a first phase detection signal and make the first phase detection signal in a valid level state when the first counting value is equal to X+2N-1 or X+N-1, and output the first phase detection signal and make the first phase detection signal in an invalid level state when the first counting value is not equal to X+2N-1 and the first counting value is not equal to X+N-1.

[0140] The clock generation module is configured to receive the first phase detection signal and the first high-frequency clock, divide the first high-frequency clock by N according to a valid level of the first phase detection signal to generate a first N-divided clock synchronized with the first high-frequency clock.

[0141] For other details of implementing the above technical solutions in the phase detection module of the clock synchronization circuit, refer to the description of the first clock synchronization circuit of the cascaded clock synchronization circuit provided in the above embodiments, which will not be repeated here.

[0142] In some embodiments, as shown in FIG. 4, in some embodiments, the clock synchronization circuit provided by the embodiments of the present application includes: Figure 17

[0143] The frequency division unit is configured to receive the first high-frequency clock and the first phase detection signal, generate the first N-divided clock based on the first high-frequency clock, and make the first N-divided clock flip once when detecting a valid level of the first phase detection signal.

[0144] The second counting unit is configured to receive the first phase detection signal, and count a level change of the first phase detection signal to obtain a first cascaded counting value.

[0145] ​​a cascade signal generation unit, configured to receive the first cascade count value, output the first cascade signal and make it in a valid level state when the first cascade count value is equal to X+2N-1 or X, output the first cascade signal and make it in an invalid level state when the first cascade count value is not equal to X+2N-1 and the first cascade count value is not equal to X.

[0146] a clock output control unit, configured to receive the first cascade count value, output a first clock enable signal and make it in a valid level state when detecting that the first cascade count value is X+2N-1.

[0147] a first gate unit, configured to receive the first high frequency clock and the first clock enable signal, output the first high frequency clock when detecting that the first clock enable signal is in a valid level.

[0148] a second gate unit, configured to receive the first N-divided clock and the first clock enable signal, output the first N-divided clock when detecting that the first clock enable signal is in a valid level.

[0149] For other details of implementing the above technical solutions in the clock generation module of the clock synchronization circuit, refer to the description of the first clock synchronization circuit of the cascade clock synchronization circuit provided in the above embodiments, which will not be repeated here.

[0150] It can be understood that the clock synchronization circuit provided by the embodiments of the present application can be used for clock synchronization of multiple clocks through cascade connection, and thus can be applied to a multi-BANK multi-path SerDes architecture. In this case, the clock synchronization circuit of the embodiments of the present application needs to be provided with a cascade signal generation unit to generate the cascade signal required for cascade. However, the clock synchronization circuit provided by the embodiments of the present application can also be used for clock synchronization of a single high frequency clock and a low frequency clock. When it is not used for synchronization of multiple clocks, the clock synchronization circuit does not need to be provided with a cascade signal generation unit.

[0151] In specific implementations, each module / unit contained in each device / product described in the above embodiments can be a software module / unit, a hardware module / unit, or part of a software module / unit and part of a hardware module / unit.

[0152] For example, for each device, product applied to or integrated in a chip or a chip module, each module / unit contained therein can be implemented in the form of hardware such as a circuit, or at least part of the modules / units can be implemented in the form of a software program running on a processor integrated in the chip or the chip module, and the remaining (if any) modules / units can be implemented in the form of hardware such as a circuit. For each device, product applied to or integrated in a terminal, each module / unit contained therein can be implemented in the form of hardware such as a circuit, or at least part of the modules / units can be implemented in the form of a software program running on a processor integrated in the terminal, and the remaining (if any) modules / units can be implemented in the form of hardware such as a circuit.

[0153] The embodiment of the present application further provides a chip 180, Figure 18 A schematic diagram of the chip provided by the embodiment of the present application is shown, the chip 180 includes the cascade clock synchronization circuit described above. The chip (IC) also referred to as an integrated circuit, and the chip includes but is not limited to a SOC (System on Chip), a SIP (System in Package), and a FPGA (Field-Programmable Gate Array), and the like. The FPGA is a programmable logic device, and can realize user customized logic functions through a hardware description language, and has wide application in the fields of communication, industry, data center, and the like.

[0154] The embodiment of the present application further provides an electronic device, Figure 19A schematic diagram of an electronic device provided by an embodiment of the present application is shown, which includes a device main body 190 and a chip 180 as described above arranged in the device main body. The electronic device can be, but is not limited to, a body weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a human body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a vehicle charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a touch pen, a true wireless earphone, a car central control screen, a car, a smart wearable device, a mobile terminal, a smart home device. The smart wearable device includes, but is not limited to, a smart watch, a smart bracelet, a cervical vertebra massage instrument. The mobile terminal includes, but is not limited to, a smart phone, a notebook computer, a tablet computer, a POS (point of sales terminal) machine. The smart home device includes, but is not limited to, a smart socket, a smart rice cooker, a smart sweeper, a smart lamp.

[0155] The above is a further detailed description of the present application in combination with specific embodiments, and the specific implementation of the present application cannot be limited to these descriptions. For ordinary skilled persons in the technical field to which the present application belongs, some simple deductions or replacements can be made without departing from the concept of the present application, and all of them should be regarded as the protection scope of the present application.

Claims

1. A cascaded clock synchronization circuit, characterized in that, The clock synchronization circuit includes an M-level cascaded connection, wherein the clock synchronization circuit includes a phase detection module and a clock generation module; The first-level clock synchronization circuit is configured such that: the phase detection module counts the level changes of the first high-frequency clock to obtain a first count value, and resets the first count value to X when the rising edge of the first low-frequency clock is detected; when the first count value is X+2N-1 and X+N-1, the first phase detection signal is output and set to an effective level; the first low-frequency clock and the first high-frequency clock are in an N-division relationship, and X≥0; The clock generation module divides the first high-frequency clock by N to generate a first N-division clock that is synchronized with it, based on the effective level of the first phase detection signal, and counts the level changes of the first phase detection signal to obtain a first cascade count value. When the first cascade count value is X+2N-1 and X, the first cascade signal is output and set to an effective level. The first cascade count value increases cyclically in the range of X to X+2N-1. The clock synchronization circuit of the i-th stage is configured such that when the phase detection module detects the effective level of the cascaded signal of the (i-1)-th stage, it counts the level changes of the i-th high-frequency clock to obtain the i-th count value. When the i-th count value is X+2N-1 and X+N-1, it outputs the i-th phase detection signal and sets it to the effective level. The i-th count value increases cyclically in the range of X to X+2N-1. The clock generation module divides the i-th high-frequency clock by N based on the effective level of the i-th phase detection signal to generate an i-th N-division clock that is synchronized with it, and counts the level changes of the i-th stage phase detection signal to obtain the i-th cascade count value. When the i-th cascade count value is X+2N-1 and X, the i-th stage cascade signal is output and set to an effective level. The i-th cascade count value increases cyclically in the range of X to X+2N-1. The i-th high-frequency clock is the same frequency synchronization signal of the first high-frequency clock, i = [2, M].

2. The cascaded clock synchronization circuit as described in claim 1, characterized in that, The phase detection module includes a clock sampling unit, a first counting unit, and a comparison unit; The clock synchronization circuit described in the first stage is configured as follows: The clock sampling unit receives the first high-frequency clock and the first low-frequency clock, samples the first low-frequency clock through both sides of the first high-frequency clock, and outputs a first reset signal when the rising edge of the first low-frequency clock is detected. The first counting unit receives the first high-frequency clock, counts the level changes of the first high-frequency clock to obtain a first count value, and resets the first count value to X when it receives the first reset signal; The comparison unit receives the first count value and compares the first count value with preset values ​​X+2N-1 and X+N-1. When the first count value is equal to X+2N-1 or X+N-1, the first phase detection signal is output and made to be in an active level state. When the first count value is not equal to X+2N-1 and the first count value is not equal to X+N-1, the first phase detection signal is output and made to be in an inactive level state. The clock synchronization circuit described in stage i is configured as follows: The clock sampling unit receives the i-th high-frequency clock and the (i-1)-th stage cascaded signal, samples the i-th stage cascaded signal through a single edge of the i-th high-frequency clock, and outputs the i-th reset signal when an effective level of the (i-1)-th stage cascaded signal is detected. When the first counting unit receives the i-th reset signal, it is reset to X, and the level change of the i-th high-frequency clock is counted to obtain the i-th count value; The comparison unit receives the i-th count value and compares the i-th count value with preset values ​​X+2N-1 and X+N-1. When the i-th count value is equal to X+2N-1 or X+N-1, the i-th phase detection signal is output and made to be in an active level state. When the i-th count value is not equal to X+2N-1 and the i-th count value is not equal to X+N-1, the i-th phase detection signal is output and made to be in an inactive level state.

3. The cascaded clock synchronization circuit as described in claim 1, characterized in that, The clock generation module includes a frequency division unit, a second counting unit, and a cascaded signal generation unit; The clock synchronization circuit described in the first stage is configured as follows: The frequency division unit receives the first high-frequency clock and the first phase detection signal, generates the first N-division clock based on the first high-frequency clock, and causes the first N-division clock to undergo a level flip when the effective level of the first phase detection signal is detected. The second counting unit receives the first phase detection signal and counts the level changes of the first phase detection signal to obtain a first cascaded count value; The cascaded signal generation unit receives a first cascaded count value. When the first cascaded count value is equal to X+2N-1 or X, it outputs the first cascaded signal and puts it in an active level state. When the first cascaded count value is not equal to X+2N-1 and the first cascaded count value is not equal to X, it outputs the first cascaded signal and puts it in an inactive level state. The clock synchronization circuit described in stage i is configured as follows: The frequency division unit receives the i-th high-frequency clock and the i-th phase detection signal, generates the i-N-th frequency division clock based on the i-th high-frequency clock, and causes the i-N-th frequency division clock to undergo a level flip when the effective level of the i-th phase detection signal is detected. The second counting unit receives the i-th phase detection signal and counts the level changes of the i-th phase detection signal to obtain the i-th cascade count value; The cascaded signal generation unit receives the i-th cascaded count value. When the i-th cascaded count value is equal to X+2N-1 or X, it outputs the i-th cascaded signal and puts it in an active level state. When the i-th cascaded count value is not equal to X+2N-1 and the i-th cascaded count value is not equal to X, it outputs the i-th cascaded signal and puts it in an inactive level.

4. The cascaded clock synchronization circuit as described in claim 3, characterized in that, The clock synchronization circuit described in the first stage is also configured as follows: Before receiving the first cascade count value, the cascade signal generation unit receives a preset clock alignment indication signal. When the clock alignment indication signal indicates that the rising edge of the first high-frequency clock is aligned with the falling edge of the first N-division clock, the effective level and the ineffective level of the first cascade signal are reversed, and the first cascade signal is output and made to be in an ineffective level state. The clock synchronization circuit described in stage i is further configured as follows: Before receiving the i-th cascade count value, the cascade signal generation unit receives a preset clock alignment indication signal. When the clock alignment indication signal indicates that the rising edge of the i-th high-frequency clock is aligned with the falling edge of the iN-th frequency division clock, the effective level and invalid level of the i-th cascade signal are reversed, and the i-th cascade signal is output and made to be in an invalid level state.

5. The cascaded clock synchronization circuit as described in claim 3, characterized in that, The clock generation module also includes a clock output control unit, a first gating unit, and a second gating unit; The clock synchronization circuit described in the first stage is configured as follows: The clock output control unit receives the first cascaded count value. When the first cascaded count value is detected to be X+2N-1, it outputs a first clock enable signal and puts it in an effective level state. The first gating unit receives the first high-frequency clock and the first clock enable signal. When the effective level of the first clock enable signal is detected, the first high-frequency clock is output. The second gate control unit receives the first N-division clock and the first clock enable signal. When the effective level of the first clock enable signal is detected, the first N-division clock is output. The second-stage clock synchronization circuit is configured as follows: The clock output unit receives the i-th cascade count value. When the i-th cascade count value is detected to be 2N-1, it outputs the i-th clock enable signal and puts it in an active level state. The first gating unit receives the i-th high-frequency clock and the i-th clock enable signal, and outputs the i-th high-frequency clock when the effective level of the i-th clock enable signal is detected. The second gating unit receives the iNth frequency division clock and the clock enable signal, and outputs the iNth frequency division clock when the effective level of the ith clock enable signal is detected.

6. The cascaded clock synchronization circuit as described in claim 3, characterized in that, The cascaded clock synchronization circuit also includes: The clock output control circuit is used to output a first enable signal and a second enable signal in response to the synchronization command signal; The clock generation module further includes a first gating unit and a second gating unit; The clock synchronization circuit described in the first stage is configured as follows: The first gating unit receives the first high-frequency clock and the first clock enable signal, and outputs the first high-frequency clock; The second gating unit receives the first N-division clock and the first clock enable signal, and outputs the first N-division clock; The second-stage clock synchronization circuit is configured as follows: The first gating unit receives the i-th high-frequency clock and the i-th clock enable signal, and outputs the i-th high-frequency clock; The second gating unit receives the iNth frequency divider clock and the clock enable signal, and outputs the iNth frequency divider clock.

7. The cascaded clock synchronization circuit as described in claim 3, characterized in that, The clock generation module further includes a period control unit, the input terminal of which is connected to the output terminal of the second counting unit, and the output terminal of which is connected to the input terminal of the cascaded signal generation unit. The first-stage clock synchronization circuit is configured as follows: The period control unit is used to receive the first cascaded count value and output the first cascaded count value every Y counting cycles; The i-th stage clock synchronization circuit is configured as follows: The period control unit is used to receive the i-th cascade count value and output the i-th cascade count value every Y counting cycles.

8. The cascaded clock synchronization circuit as described in claim 3, characterized in that, The clock generation module further includes a period control unit, the input of which is connected to the output of the cascaded signal generation unit; The first-stage clock synchronization circuit is configured as follows: The periodic control unit is used to receive the first-stage cascaded signal and output the i-th-stage cascaded signal L by frequency division, where L>1; The i-th stage clock synchronization circuit is configured as follows: The period control unit is used to receive the i-th cascaded signal and output the i-th cascaded signal by frequency division L.

9. The cascaded clock synchronization circuit as described in claim 1, characterized in that, It also includes a first selection unit and a second selection unit; The clock synchronization circuit described in the first stage is configured as follows: The first selection unit receives the first low-frequency clock and a preset idle signal, and selects the first low-frequency clock for output; The second selection unit receives the idle signal and the first-stage cascade signal, and selects the first-stage cascade signal for output; The i-th stage clock synchronization circuit is configured as follows: The first selection unit receives the i-th low-frequency clock and the (i-1)-th stage cascaded signal, and selects the i-th low-frequency clock or the (i-1)-th stage cascaded signal for output; When the phase detection module detects the effective level of the i-th low-frequency clock or the (i-1)-th stage cascaded signal, it counts the level changes of the i-th high-frequency clock to obtain the i-th count value. When the i-th count value is X+2N-1 and X+N-1, it outputs the i-th phase detection signal and sets it to the effective level. The clock generation module divides the i-th high-frequency clock by N based on the effective level of the i-th phase detection signal to generate an i-th N-division clock that is synchronized with it, and counts the level changes of the i-th stage phase detection signal to obtain the i-th cascade count value. When the i-th cascade count value is X+2N-1 and X, the i-th stage cascade signal is output and set to an effective level. The second selection unit receives the (i-1)th stage cascade signal and the i-th stage cascade signal, and selects either the (i-1)th stage cascade signal or the i-th stage cascade signal for output.

10. A clock synchronization circuit, characterized in that, Includes a phase detection module and a clock generation module; The phase detection module is used to count the level changes of the first high-frequency clock to obtain a first count value, and reset the first count value to X when the rising edge of the first low-frequency clock is detected. When the first count value is X+2N-1 and X+N-1, the first phase detection signal is output and set to an effective level. The first low-frequency clock and the first high-frequency clock are in an N-division relationship, and X≥0. The clock generation module is used to divide the first high-frequency clock by N to generate a first N-division clock that is synchronized with it, based on the effective level of the first phase detection signal, and to count the level changes of the first phase detection signal to obtain a first cascade count value. When the first cascade count value is X+2N-1 and X, the first cascade signal is output and set to an effective level. The first cascade count value is cyclically increased in the range of X to X+2N-1.

11. The clock synchronization circuit as described in claim 10, characterized in that, The phase detection module includes: The clock sampling unit is used to receive a first high-frequency clock and a first low-frequency clock, sample the first low-frequency clock through the dual edges of the first high-frequency clock, and output a first reset signal when the rising edge of the first low-frequency clock is detected. The first counting unit is configured to receive the first high-frequency clock, count the level changes of the first high-frequency clock to obtain a first count value, and reset the first count value to X when the first reset signal is received. The comparison unit is used to receive the first count value, compare the first count value with preset values ​​X+2N-1 and X+N-1, and when the first count value is equal to X+2N-1 or X+N-1, output the first phase detection signal and make it in an active level state; when the first count value is not equal to X+2N-1 and the first count value is not equal to X+N-1, output the first phase detection signal and make it in an inactive level state. The clock generation module is used to receive the first phase detection signal and the first high-frequency clock, and generate a first N-division clock that is synchronized with the first high-frequency clock by dividing the first high-frequency clock by N according to the effective level of the first phase detection signal.

12. The clock synchronization circuit as described in claim 10, characterized in that, The clock generation module includes: The frequency division unit is used to receive the first high-frequency clock and the first phase detection signal, generate the first N-division clock based on the first high-frequency clock, and cause the first N-division clock to undergo a level flip when the effective level of the first phase detection signal is detected. The second counting unit is used to receive the first phase detection signal and count the level changes of the first phase detection signal to obtain a first cascaded count value. The clock output control unit is used to receive the first cascaded count value, and when the first cascaded count value is detected to be X+2N-1, it outputs a first clock enable signal and puts it in an effective level state. The first gating unit receives the first high-frequency clock and the first clock enable signal, and outputs the first high-frequency clock when the effective level of the first clock enable signal is detected. The second gating unit receives the first N-division clock and the first clock enable signal. When the effective level of the first clock enable signal is detected, it outputs the first N-division clock.

13. A chip, characterized in that, Includes the cascaded clock synchronization circuit described in any one of claims 1 to 9.

14. An electronic device, characterized in that, It includes a device body and a chip as described in claim 13 disposed on the device body.

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