Wafer defect measuring method and related equipment

Abstract

The invention provides a wafer defect measuring method and related equipment. The wafer defect measuring method comprises the following steps: acquiring wafer images of a wafer at a plurality of positions; identifying a graph in each wafer image through a graph identification model, and obtaining a corresponding positioning graph from the graph of each wafer image; positioning the wafer based on each positioning graph, and obtaining a defect image of the wafer; recognizing a graph in the defect image through a graph recognition model, and obtaining a target graph from the graph of the defect image; and measuring the wafer defect in the defect image based on the target graph. According to the wafer defect measurement method, the accuracy of pattern recognition and the accuracy of defect positioning can be improved, missing detection and false detection are further prevented, and the detection speed and the detection precision can be both considered. In addition, when the pattern recognition model is trained, only the pattern needs to be used for training, the data acquisition cost can be reduced, the data balance is improved, and the interpretability and generalization ability of the model are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor defect detection technology, and in particular to a wafer defect measurement method, a computer-readable storage medium, a computer program product, and a computer device. Background Technology

[0002] Wafer defect measurement is a crucial step in ensuring chip quality. The first step in wafer defect measurement is to perform nanometer-level precise positioning and calibration using image recognition technology. Due to the complex features of the wafer surface and the extremely high accuracy requirements, this process often employs sub-pixel positioning algorithms and template matching techniques, such as industry-standard normalized correlation matching and phase correlation matching. When identifying specific markings on the wafer, sub-pixel positioning algorithms can improve positioning accuracy to the nanometer level, ensuring the wafer's precise position within the equipment. After positioning and calibration, specialized equipment such as high-resolution cameras and scanning electron microscopes are used to capture wafer images. These devices operate on different principles: high-resolution cameras acquire macroscopic images of the wafer surface through optical imaging, while scanning electron microscopes generate high-resolution microscopic images through the interaction of electron beams with matter, providing a detailed data foundation for subsequent defect analysis.

[0003] Subsequently, the defect measurement stage begins, where various image processing, defect recognition, and localization methods are applied. Common image processing algorithms, such as grayscale transformation and filtering denoising, are used to improve image quality and highlight potential defect features. For example, median filtering can effectively remove salt-and-pepper noise from the image, making defect edges clearer and facilitating subsequent analysis. In defect recognition, methods such as threshold segmentation and morphological processing are widely used. By setting an appropriate threshold, defects are separated from the background, and morphological operations are then used to optimize the segmentation results, accurately outlining the defect contours. Defect localization often utilizes techniques such as coordinate transformation and feature point matching to determine the precise location of the defect on the wafer, providing crucial information for subsequent repair or process improvement.

[0004] However, semiconductor manufacturing processes are complex and diverse, encompassing multiple stages such as photolithography, etching, and deposition. The surface state of wafers varies significantly after different processes, with vastly different defect types and characteristics. Photolithography-etched wafers may exhibit pattern deviations and abnormal linewidths; etching processes are prone to over-etching and under-etching, resulting in rough edges and voids; deposition processes may introduce imperfections such as particles and uneven film thickness. This necessitates image recognition technology with strong adaptability, capable of accurately identifying and locating complex defects in various scenarios. Furthermore, with continuous breakthroughs in semiconductor technology nodes, chip integration density is constantly increasing, and feature sizes are becoming increasingly smaller, placing near-stringent demands on the accuracy and sensitivity of wafer defect measurement. In advanced process technologies, defect sizes have shrunk to the nanometer level, making it highly susceptible to missed or false detections when faced with such minute defects. Simultaneously, the imaging quality of tiny features is more significantly affected by factors such as device resolution and noise, further increasing the difficulty of defect identification.

[0005] In other words, the traditional technologies currently used in the industry are ill-suited for complex pattern recognition and accurate defect localization in various scenarios, especially for advanced manufacturing processes. To ensure production efficiency, measurement speed also needs to be improved simultaneously. Maintaining high accuracy while performing high-speed inspection has become a major challenge for traditional measurement methods. Therefore, exploring more advanced, efficient, and accurate wafer defect measurement solutions has become an urgent need to drive the semiconductor industry towards higher manufacturing processes. Specifically, the traditional technologies currently used in the industry suffer from insufficient adaptability; for nanometer-level defects in advanced processes, these traditional processes are prone to missed detections and false detections, making it difficult to balance detection speed and accuracy. Summary of the Invention

[0006] In view of the above problems, the present invention proposes a wafer defect measurement method that overcomes or at least partially solves the above problems.

[0007] One objective of this invention is to address the problem that traditional processes are difficult to adapt to complex image recognition and accurate defect localization in different scenarios, thereby improving the accuracy of image recognition and defect localization, preventing missed detections and false detections, and balancing detection speed and accuracy.

[0008] Another objective of this invention is to reduce data acquisition costs, improve data balance, and enhance the interpretability and generalization ability of the model.

[0009] Specifically, according to one aspect of the present invention, a wafer defect measurement method is provided, comprising:

[0010] Acquire wafer images at multiple locations;

[0011] The graphic recognition model identifies the graphics in each of the wafer images and obtains the corresponding localized graphics from the graphics in each of the wafer images; wherein, the graphic recognition model is a deep learning model for recognizing graphics;

[0012] The wafer is positioned based on the positioning patterns described above, and defect images of the wafer are obtained.

[0013] The graphic recognition model identifies the graphic in the defect image and obtains the target graphic from the graphic in the defect image.

[0014] Based on the target pattern, wafer defects in the defect image are measured.

[0015] Optionally, the image recognition model is configured to be trained using a preset dataset, which includes images from the process data, layer feature data, optical image data, electron beam image data, and / or design layout data of the wafer and / or other wafers.

[0016] Optionally, positioning the wafer based on each of the positioning patterns and obtaining a defect image of the wafer includes:

[0017] Based on each of the positioning graphics, locate the wafer position corresponding to each of the wafer images;

[0018] Based on the wafer position corresponding to each wafer image, the target position of the wafer is determined; wherein the target position is used to place the defect position of the wafer at or near the center of the field of view;

[0019] The defect image is acquired when the wafer is in the target position.

[0020] Optionally, determining the target location of the wafer based on the wafer location corresponding to each wafer image includes:

[0021] Obtain the first theoretical position corresponding to each of the wafer images, and the mapping relationship between each wafer position and the corresponding first theoretical position;

[0022] Obtain a second theoretical position for placing the defect location of the wafer at or near the center of the field of view;

[0023] The second theoretical position is transformed using the mapping relationship to obtain the target position.

[0024] Optionally, obtaining the mapping relationship between each of the wafer locations and the corresponding first theoretical locations includes:

[0025] The mapping relationship based on perspective transformation is calculated based on each wafer position and the corresponding first theoretical position.

[0026] Optionally, based on the target image, the wafer defects in the defect image are measured, including:

[0027] Based on the target image, local image processing is performed on the corresponding position in the defect image to obtain the test image corresponding to the defect image;

[0028] The wafer defects in the image to be tested are measured.

[0029] Optionally, the local image processing includes image noise reduction processing, graphic edge signal enhancement processing, and / or image resolution enhancement processing.

[0030] Optionally, obtaining the corresponding positioning pattern from the graphics of each of the wafer images includes:

[0031] Obtain a pattern from the patterns of each of the aforementioned wafer images;

[0032] Determine whether the graphic obtained from the graphics of each wafer image is a preset positioning graphic;

[0033] If so, the graphic obtained from the graphics of each of the wafer images is determined to be the positioning graphic.

[0034] Optionally, obtaining the target image from the image of the defect includes:

[0035] Obtain a graphic from the graphic of the defect image;

[0036] Determine whether the graphic obtained from the graphic of the defect image is a preset target graphic;

[0037] If so, the graphic obtained from the graphic of the defect image is determined to be the target graphic.

[0038] According to another aspect of the present invention, a computer-readable storage medium is also provided, on which a computer program is stored, wherein the computer program, when executed by a processor, implements the steps of any of the above-described wafer defect measurement methods.

[0039] According to another aspect of the present invention, a computer program product is also provided, comprising a computer program that, when executed by a processor, implements the steps of any of the above-described wafer defect measurement methods.

[0040] According to another aspect of the present invention, a computer device is also provided, which includes a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of any wafer defect measurement method.

[0041] In the wafer defect measurement method of this invention, wafer images at multiple locations are first acquired. The target location of the wafer is determined using the positional information of the positioning patterns in the wafer images, ensuring that the defect image is acquired at the target location. This solves the problem that traditional processes struggle to accurately locate defects in different scenarios, guaranteeing the accuracy of defect image acquisition and thus ensuring the accuracy and efficiency of defect measurement. Furthermore, the target pattern is identified, and then wafer defects at the target pattern are measured, rather than processing and measuring all locations, further improving the accuracy and efficiency of defect measurement.

[0042] Furthermore, in the wafer defect measurement method of the present invention, a pattern recognition model is used for pattern recognition. The pattern recognition model identifies patterns in wafer layouts, images, etc., and is primarily obtained through training with pattern data. For example, during training, the entire image does not need to be considered; training can be performed using a single pattern, multiple patterns, or all patterns in the image. Data sources are simple to obtain, and data acquisition costs are low. During training, the relationships between patterns in the entire image do not need to be considered; only the patterns themselves are needed. This results in high accuracy in identifying patterns, particularly complex ones, with high precision. In other words, the wafer defect measurement method of the present invention can solve the problem that traditional processes struggle to adapt to complex pattern recognition in different scenarios, thereby improving the accuracy of pattern recognition and defect localization, preventing missed and false detections, and balancing detection speed and accuracy. Moreover, since the pattern recognition model can be trained using only patterns, data acquisition costs are reduced, data balance is improved, and the model's interpretability and generalization ability are enhanced.

[0043] The above and other objects, advantages and features of the present invention will become more apparent to those skilled in the art from the following detailed description of specific embodiments of the invention in conjunction with the accompanying drawings. Attached Figure Description

[0044] The following sections will describe some specific embodiments of the invention in detail by way of example and not limitation, with reference to the accompanying drawings. The same reference numerals in the drawings denote the same or similar parts or portions. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:

[0045] Figure 1 A schematic flowchart of a wafer defect measurement method according to an embodiment of the present invention;

[0046] Figure 2 This is a schematic partial flowchart of a wafer defect measurement method according to an embodiment of the present invention;

[0047] Figure 3 A schematic flowchart of a wafer defect measurement method according to an embodiment of the present invention;

[0048] Figure 4 A schematic flowchart illustrating the process of obtaining a positioning pattern from the graphics of each wafer image in a wafer defect measurement method according to an embodiment of the present invention;

[0049] Figure 5 A schematic flowchart illustrating the process of obtaining a target pattern from a defect image in a wafer defect measurement method according to an embodiment of the present invention;

[0050] Figure 6 A schematic flowchart of a wafer defect measurement method according to an embodiment of the present invention;

[0051] Figure 7 This is a schematic diagram of a computer program product according to an embodiment of the present invention;

[0052] Figure 8 This is a schematic diagram of a computer-readable storage medium according to an embodiment of the present invention; and

[0053] Figure 9 This is a schematic diagram of a computer device according to an embodiment of the present invention. Detailed Implementation

[0054] This embodiment provides a method and related equipment for measuring wafer defects.

[0055] Figure 1 This is a schematic flowchart of a wafer defect measurement method according to an embodiment of the present invention, as shown below. Figure 1 As shown, this embodiment of the invention provides a wafer defect measurement method, which includes:

[0056] Step S100: Obtain wafer images at multiple locations. Wafer images can be acquired using a scanning electron microscope.

[0057] Step S200: The graphics in each wafer image are identified using a graphic recognition model, and the corresponding localized graphics are obtained from the graphics in each wafer image. The graphic recognition model is a deep learning model used for graphic recognition.

[0058] Step S300: Position the wafer based on each positioning pattern and acquire a defect image of the wafer. The defect image of the wafer can be acquired using a scanning electron microscope.

[0059] Step S400: Identify the graphics in the defect image using the graphics recognition model, and obtain the target graphics from the graphics in the defect image.

[0060] Step S500: Based on the target image, measure the wafer defects in the defect image.

[0061] In this embodiment of the invention, wafer images at multiple locations are first acquired. The target location of the wafer is determined using the positional information of the positioning patterns in the wafer images. This ensures that defect images of the wafer are acquired at the target location, solving the problem that traditional processes struggle to accurately locate defects in different scenarios. This guarantees the accuracy of defect image acquisition, thereby ensuring the accuracy and efficiency of defect measurement. Furthermore, the target pattern is identified, and then wafer defects at the target pattern are measured, rather than processing and measuring all locations, further improving the accuracy and efficiency of defect measurement.

[0062] Furthermore, in this embodiment of the invention, a pattern recognition model is used for pattern recognition. The pattern recognition model identifies patterns in wafer layouts, images, etc., and is primarily obtained through training with pattern data. For example, during training, the entire image does not need to be considered; training can be performed using a single pattern, multiple patterns, or all patterns in the image. Data sources are simple to obtain, and data acquisition costs are low. During training, the relationships between patterns in the entire image do not need to be considered; only the patterns themselves are needed. The accuracy of pattern recognition is high, especially when performing defect measurement on complex patterns, where it can also identify complex patterns with high precision. In other words, the wafer defect measurement method of this invention can solve the problem that traditional processes are difficult to adapt to complex pattern recognition in different scenarios, thereby improving the accuracy of pattern recognition and defect location, and preventing missed and false detections, balancing detection speed and accuracy. Moreover, since the pattern recognition model can be trained using only patterns, data acquisition costs are reduced, data balance is improved, and the interpretability and generalization ability of the model are enhanced, enabling its application on production lines.

[0063] Moreover, in this embodiment of the invention, the image recognition model used is a single model that extracts the common problems in the two steps and replaces them with a deep learning model. This reduces the model's requirements for image data, lowers the difficulty of defect measurement using traditional algorithms, and improves the accuracy and generalization ability of defect measurement, especially for defect measurement of wafers using advanced processes (such as 3nm and below).

[0064] In some embodiments of the present invention, the pattern recognition model is configured to be trained using a preset dataset, which includes patterns in wafer and / or other wafer process data, layer feature data, optical image data, electron beam image data, and / or design layout data.

[0065] The image data sources for the image recognition model in this embodiment of the invention can cover multiple stages such as photolithography, etching, and deposition. Therefore, the image recognition model has strong adaptability and can accurately recognize complex images in different scenarios. Moreover, the establishment of the dataset for the image recognition model in this embodiment of the invention does not entirely depend on wafer defect images. Since training is based on images, 90% of the image data can use non-defect data, reducing the difficulty of dataset creation. The dataset can be created separately according to wafer process, layer features, and other information, and multiple image recognition models can be used for distributed image recognition, reducing the difficulty of model training. Of course, all data can also be created uniformly.

[0066] In some embodiments of the present invention, such as Figure 2 As shown, the wafer is positioned based on each positioning pattern, and defect images of the wafer are obtained, including:

[0067] Step S310: Based on each positioning pattern, locate the wafer position corresponding to each wafer image.

[0068] Step S320: Determine the target position of the wafer based on the wafer position corresponding to each wafer image; wherein the target position is used to place the defect position of the wafer at or near the center of the field of view.

[0069] Step S330: With the wafer in the target position, acquire a defect image.

[0070] Specifically, the target location of the wafer is determined based on the wafer location corresponding to each wafer image, including:

[0071] Obtain the first theoretical position corresponding to each wafer image, and the mapping relationship between each wafer position and the corresponding first theoretical position;

[0072] Obtain a second theoretical position for placing the defect location on or near the center of the field of view of the wafer;

[0073] The target position is obtained by performing a perspective transformation on the second theoretical position according to the mapping relationship.

[0074] In this embodiment of the invention, the accuracy of the coordinate system of the stage used to mount the wafers can be determined by the various wafer positions and the first theoretical position. Then, based on the second theoretical position, the target position for acquiring defect images can be determined. Based on this target position, the stage is controlled to move the wafer to the target position, and then the wafer is photographed to obtain a defect image. This setting ensures that after the user inputs the theoretical coordinate value corresponding to the second theoretical position, the stage moves the wafer to the target position, avoiding the phenomenon of target position discrepancies caused by defects in the stage itself.

[0075] In some alternative embodiments of the present invention, it can also be said that determining the target position of the wafer based on the wafer position corresponding to each wafer image includes:

[0076] Obtain the first theoretical position corresponding to each wafer image, and the mapping relationship between each wafer position and the corresponding first theoretical position;

[0077] The coordinate system of the stage used to load the wafer is calibrated according to the mapping relationship;

[0078] Obtain a second theoretical position for placing the defect location of the wafer at or near the center of the field of view, and use the second theoretical position as the target position.

[0079] In some embodiments of the present invention, obtaining the mapping relationship between each wafer position and the corresponding first theoretical position includes:

[0080] The mapping relationship based on perspective transformation is calculated based on the position of each wafer and the corresponding first theoretical position.

[0081] Perspective transformation can calculate the transformation mapping relationship between actual coordinates and ideal coordinates, thereby calibrating the equipment coordinate system or determining the target position.

[0082] In some embodiments of the present invention, such as Figure 3 As shown, based on the target image, wafer defects in the defect image are measured, including:

[0083] Step S510: Based on the target image, perform local image processing on the corresponding position in the defect image to obtain the test image corresponding to the defect image.

[0084] Step S520: Measure the wafer defects in the image to be tested.

[0085] In this embodiment of the invention, the defect image is processed locally and in a distributed manner using the image after image recognition, rather than processing the entire defect image. This results in less data processing, higher processing efficiency, and better processing effect, thereby ensuring the accuracy of subsequent measurements.

[0086] In some embodiments of the present invention, local image processing includes image denoising, edge signal enhancement, and / or resolution enhancement. Image quality enhancement includes image denoising, edge signal enhancement, resolution enhancement, and image sharpness enhancement, with the aim of improving the accuracy of defect image measurement and detection. During defect image measurement and detection, the clearer the edge signal, the higher the signal-to-noise ratio, the higher the resolution, and the higher the measurement accuracy. Specific denoising methods, signal enhancement methods, resolution enhancement methods, and sharpness enhancement methods are not specifically limited.

[0087] In some embodiments of the present invention, such as Figure 4 As shown, the corresponding positioning patterns are obtained from the graphics of each wafer image, including:

[0088] Step S210: Obtain a pattern from the patterns of each wafer image.

[0089] Step S220: Determine whether the pattern obtained from the pattern of each wafer image is a preset positioning pattern.

[0090] If so, proceed to step S230 to determine that the graphic obtained from the graphics of each wafer image is the positioning graphic.

[0091] If not, return to step S210.

[0092] The preset positioning graphic can be a distinctive graphic, such as a cross mark, or other graphics, such as a square.

[0093] In some embodiments of the present invention, such as Figure 5 As shown, the target graphic is obtained from the graphic of the defect image, including:

[0094] Step S410: Obtain a graphic from the graphic of the defect image.

[0095] Step S420: Determine whether the graphic obtained from the graphic of the defect image is the preset target graphic.

[0096] If so, proceed to step S430 to determine that the graphic obtained from the graphic of the fracture defect image is the target graphic.

[0097] If not, return to step S410.

[0098] The preset target graphic is the graphic that the user wants to measure. Because there is a preset target graphic, there is no need to process and measure the image area corresponding to the graphic that the user does not need to measure, which can ensure the accuracy of the defect measurement object and improve the measurement efficiency.

[0099] In some embodiments of the present invention, such as Figure 6 As shown, this embodiment of the invention provides a wafer defect measurement method, which includes:

[0100] Step S610: Acquire wafer images at multiple locations. When capturing wafer images, the wafer is placed on a corresponding stage. The position and shooting angle of the scanning electron microscope remain unchanged, while the stage moves the wafer, and the worktable moves to multiple locations according to the first theoretical position corresponding to the positioning pattern, thus acquiring multiple wafer images.

[0101] Step S620: Obtain the localized pattern in the wafer image. Based on the wafer image captured in the previous step, a deep learning-based pattern recognition model is used to obtain the localized pattern in the wafer image. This step is crucial, as the success rate of subsequent processes depends on the accuracy of pattern recognition in this step. The pattern recognition model in this embodiment of the invention is trained based on various patterns and has high accuracy.

[0102] Step S630: Obtain the theoretical and actual coordinate values ​​of each wafer image. In other words, by using the graphics obtained in the previous step and formulating simple and definite registration rules, accurate registration of the wafer images can be achieved, thereby obtaining the theoretical and actual coordinate values ​​of each wafer image. This means that based on each positioning graphic, the wafer position corresponding to each wafer image can be located, and the first theoretical position corresponding to each wafer image can be obtained.

[0103] Step S640 involves calibrating the wafer coordinate system, moving the wafer to the target position, and acquiring a defect image of the wafer. Using the theoretical and actual coordinate values ​​of multiple positions obtained in the previous step, the wafer coordinate system is calibrated using the principle of perspective transformation. The wafer is then moved to the target position using the calibrated coordinate system, and defect image capture is performed. This ensures accurate wafer positioning, with defect images close to the center of the Field of View (FOV). In other words, improved wafer positioning calibration accuracy significantly enhances wafer image quality (e.g., improved signal-to-noise ratio and resolution), thereby greatly improving the accuracy and stability of wafer defect measurement.

[0104] Step S650: Obtain the target pattern from the defect image of the wafer. Based on the defect image captured in the previous step, the target pattern in the defect image is also obtained using a deep learning-based pattern recognition model.

[0105] Step S660: Perform local image quality enhancement processing. Based on the target image detected in the previous step, perform local image noise reduction, enhance the image edge signal, and simultaneously utilize super-resolution technology to improve image resolution.

[0106] Step S670: Measure the wafer defects in the defect image. Based on the wafer image processed in the previous step, execute the defect measurement process. Due to the improved image quality, the accuracy and stability of defect measurement can be significantly improved.

[0107] This invention proposes a wafer defect measurement method based on an image recognition model. This method enables wafer positioning and calibration. During calibration, a deep learning-based image recognition model identifies the positioning image. The position of this image determines the target location of the wafer, i.e., the location of the captured defect image. Wafer positioning and calibration can be achieved through simple perspective transformation. Furthermore, based on accurately capturing the wafer defect image, the deep learning-based image recognition model is used to obtain the target image to be measured. For this target image, image noise reduction and edge signal enhancement can be implemented for each corresponding region. Finally, wafer defect measurement is performed. By accurately capturing high-quality defect images and performing defect measurement based on these images, the accuracy and stability of defect measurement can be greatly improved.

[0108] The flowchart provided in this embodiment is not intended to indicate that the operations of the method will be performed in any particular order, or that all operations of the method are included in every case. Furthermore, the method may include additional operations. Within the scope of the technical concept provided by the method in this embodiment, additional variations can be made to the above method.

[0109] It should be understood that in some embodiments, the components may be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods may be implemented using software or firmware stored in memory and executed by a suitable instruction execution system.

[0110] This embodiment also provides a computer program product 10, a computer-readable storage medium 20, and a computer device 30. Figure 7 This is a schematic diagram of a computer program product 10 according to an embodiment of the present invention. Figure 8 This is a schematic diagram of a computer-readable storage medium 20 according to an embodiment of the present invention. Figure 9 This is a schematic diagram of a computer device 30 according to an embodiment of the present invention. The computer program product 10 includes a computer program 11, which, when executed by the processor 32, implements the steps of the wafer defect measurement method of any of the above embodiments. A computer-readable storage medium 20 stores the computer program 11 thereon, which, when executed by the processor 32, implements the steps of the wafer defect measurement method of any of the above embodiments. The computer device 30 may include a memory 31, a processor 32, and the computer program 11 stored in the memory 31 and running on the processor 32.

[0111] The computer program 11 used to perform the operations of this invention may be assembly instructions, Instruction Set Architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages ​​and procedural programming languages. The computer program 11 may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer. In some embodiments, to perform aspects of this invention, electronic circuits, including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), may execute computer-readable program instructions using status information from computer-readable program instructions to personalize the electronic circuits.

[0112] For the purposes of this embodiment, computer program product 10 is a related product that includes computer program 11.

[0113] For the purposes of this embodiment, the computer-readable storage medium 20 is a tangible device capable of holding and storing a computer program 11. It can be any device capable of containing, storing, communicating, propagating, or transmitting the program 11 for use by or in conjunction with an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable storage medium 20 include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable optical disc read-only memory (CD-ROM), digital versatile disc (DVD), memory stick, floppy disk, mechanical encoding device, and any suitable combination thereof.

[0114] Computer device 30 can be, for example, a server, desktop computer, laptop computer, tablet computer, or smartphone. In some examples, computer device 30 can be a cloud computing node. Computer device 30 can be described in the general context of computer system executable instructions (such as program modules) executed by a computer system. Typically, program modules can include routines, programs, object programs, components, logic, data structures, etc., that perform specific tasks or implement specific abstract data types. Computer device 30 can be implemented in a distributed cloud computing environment where tasks are performed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules can reside on local or remote computing system storage media, including storage devices.

[0115] Computer device 30 may include a processor 32 adapted to execute stored instructions and a memory 31 that provides temporary storage space for the operation of said instructions during operation. The processor 32 may be a single-core processor, a multi-core processor, a computing cluster, or any other configuration. The memory 31 may include random access memory (RAM), read-only memory, flash memory, or any other suitable storage system.

[0116] Computer device 30 may also include a network adapter / interface and an input / output (I / O) interface. The I / O interface allows external devices that can be connected to the computer device to input and output data. The network adapter / interface provides communication between the computer device and a network, typically represented as a communication network.

[0117] Therefore, those skilled in the art should recognize that although numerous exemplary embodiments of the present invention have been shown and described in detail herein, many other variations or modifications conforming to the principles of the present invention can be directly determined or derived from the disclosure of the present invention without departing from the spirit and scope of the invention. Thus, the scope of the present invention should be understood and construed as covering all such other variations or modifications.

Claims

1. A method for measuring wafer defects, characterized in that, include: Acquire wafer images at multiple locations; The graphic recognition model identifies the graphics in each wafer image and obtains the corresponding localized graphics from the graphics in each wafer image; wherein, the graphic recognition model is a deep learning model for recognizing graphics; The wafer is positioned based on the positioning patterns described above, and defect images of the wafer are obtained. The graphic recognition model identifies the graphic in the defect image and obtains the target graphic from the graphic in the defect image. Based on the target pattern, wafer defects in the defect image are measured.

2. The wafer defect measurement method according to claim 1, characterized in that, The image recognition model is configured to be trained using a preset dataset, which includes images from the process data, layer feature data, optical image data, electron beam image data, and / or design layout data of the wafer and / or other wafers.

3. The wafer defect measurement method according to claim 1, characterized in that, Positioning the wafer based on the positioning patterns and obtaining defect images of the wafer includes: Based on each of the positioning graphics, locate the wafer position corresponding to each of the wafer images; Based on the wafer position corresponding to each wafer image, the target position of the wafer is determined; wherein the target position is used to place the defect position of the wafer at or near the center of the field of view; The defect image is acquired when the wafer is in the target position.

4. The wafer defect measurement method according to claim 3, characterized in that, Determining the target location of the wafer based on the wafer location corresponding to each wafer image includes: Obtain the first theoretical position corresponding to each of the wafer images, and the mapping relationship between each wafer position and the corresponding first theoretical position; Obtain a second theoretical position for placing the defect location of the wafer at or near the center of the field of view; The second theoretical position is transformed using the mapping relationship to obtain the target position.

5. The wafer defect measurement method according to claim 4, characterized in that, Obtaining the mapping relationship between each of the wafer locations and the corresponding first theoretical locations includes: The mapping relationship based on perspective transformation is calculated based on each wafer position and the corresponding first theoretical position.

6. The wafer defect measurement method according to claim 1, characterized in that, Based on the target image, the wafer defects in the defect image are measured, including: Based on the target image, local image processing is performed on the corresponding position in the defect image to obtain the test image corresponding to the defect image; The wafer defects in the image to be tested are measured.

7. The wafer defect measurement method according to claim 6, characterized in that, The local image processing includes image noise reduction processing, graphic edge signal enhancement processing, and / or image resolution enhancement processing; Obtaining the corresponding positioning pattern from the graphics of each of the wafer images includes: Obtain a pattern from the patterns of each of the aforementioned wafer images; Determine whether the graphic obtained from the graphics of each wafer image is a preset positioning graphic; If so, the graphic obtained from the graphics of each of the wafer images is determined to be the positioning graphic; Obtaining the target image from the image of the defect includes: Obtain a graphic from the graphic of the defect image; Determine whether the graphic obtained from the graphic of the defect image is a preset target graphic; If so, the graphic obtained from the graphic of the defect image is determined to be the target graphic.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the wafer defect measurement method according to any one of claims 1 to 7.

9. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the wafer defect measurement method according to any one of claims 1 to 7.

10. A computer device, characterized in that, The method includes a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the wafer defect measurement method according to any one of claims 1 to 7.

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