Broken line repairing circuit and method thereof, display panel and display equipment

Abstract

The invention discloses a broken line repairing circuit and method, a display panel and display equipment, and relates to the technical field of display, and the circuit comprises a gate line array, a gate driving module, a broken line detection module and a compensation module, when the gate driving modules arranged on the left side and the right side of the gate line array respectively output gate signals to the gate signal lines in the corresponding rows line by line according to a preset row scanning sequence; the method comprises the following steps: monitoring an input current signal of each gate signal line when a gate driving module outputs a gate signal line by line through a disconnection detection module, and generating a disconnection data signal comprising a rising edge detection current and a disconnection gate line according to the input current signal; through a compensation module, a broken line data signal sent by a broken line detection module is received, a gate compensation digital signal is generated according to a rising edge detection current, and a broken gate line is repaired according to the gate compensation digital signal, so that the broken gate signal line is repaired to improve the product yield of a display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a broken wire repair circuit and method thereof, a display panel, and a display device. Background Technology

[0002] With the continuous development of display technology, display devices (such as LCD screens) have made continuous breakthroughs in resolution, refresh rate and size, which has put forward higher requirements for manufacturing processes and product yield.

[0003] In the manufacturing process of LCD screens, process defects often lead to various display defects. Among them, GDL (Gate Driver Logic, also known as gate driver module) related defects are particularly prominent. They are mainly manifested as short circuits or open circuits in the Gate signal line, which prevent the TFT (Thin-Film Transistor) of the corresponding scan line from turning on normally, thus forming significant display abnormalities such as horizontal dark lines on the panel, seriously affecting the product yield of the display panel.

[0004] Therefore, how to repair broken gate signal lines to improve the product yield of display panels is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] The main objective of this application is to provide a circuit and method for repairing broken lines, a display panel, and a display device, which aim to repair broken lines in GDL to improve the product yield of the display panel.

[0006] To achieve the above objectives, this application provides a broken wire repair circuit, the broken wire repair circuit comprising: A gate line array, the gate line array comprising a plurality of parallel gate signal lines; A gate driving module is disposed on the left and right sides of the gate line array. The gate driving module is configured to output gate signals to the gate signal lines of the corresponding rows in a preset row scanning order. A disconnection detection module is provided, wherein the input terminal of the disconnection detection module is electrically connected to the output terminal of the gate driving module. The disconnection detection module is configured to monitor the input current signal of each gate signal line line by line when the gate driving module outputs the gate signal, and generate a disconnection data signal based on the input current signal. The disconnection data signal includes rising edge detection current and disconnected gate line. The compensation module has its input terminal electrically connected to the output terminal of the disconnection detection module. The compensation module is configured to receive the disconnection data signal sent by the disconnection detection module, generate a gate compensation digital signal based on the rising edge detection current, and repair the disconnected gate line based on the gate compensation digital signal.

[0007] In one embodiment, the compensation module includes a left edge detection element, a right edge detection element, a logic enable unit, and a level conversion unit; The input terminal of the left edge detector is electrically connected to the output terminal of the left gate driver through the left disconnection detector in the disconnection detection module. The output terminal of the left edge detector is electrically connected to the first signal terminal of the logic enable unit. The left gate driver is a gate driver module disposed on the left side of the gate line array. The input terminal of the right edge detector is electrically connected to the output terminal of the right gate driver through the right disconnection detector in the disconnection detection module. The output terminal of the right edge detector is electrically connected to the first signal terminal of the logic enable unit. The right gate driver is a gate driver module disposed on the right side of the gate line array. The output of the logic enable unit is electrically connected to the level conversion unit.

[0008] In one embodiment, the left edge detection element includes a first resistor, a first NOT gate, and a first edge trigger; The first terminal of the first resistor constitutes the input terminal of the left edge detection element and is electrically connected to the input terminal of the first NOT gate and the output terminal of the left gate driver. The output terminal of the first NOT gate is electrically connected to the data input terminal of the first edge flip-flop. The clock terminal of the first edge flip-flop is electrically connected to the scan clock signal terminal. The state output terminal of the first edge flip-flop constitutes the output terminal of the left edge detection element and is electrically connected to the first signal terminal of the logic enable unit. The second terminal of the first resistor is grounded; and / or, The right edge detection element includes a second resistor, a second NOT gate, and a second edge trigger. The first end of the second resistor forms the input terminal of the right edge detection device and is electrically connected to the input terminal of the second NOT gate and the output terminal of the right gate driver. The output terminal of the second NOT gate is electrically connected to the data input terminal of the second edge flip-flop. The clock terminal of the second edge flip-flop is electrically connected to the scan clock signal terminal. The state output terminal of the second edge flip-flop forms the output terminal of the right edge detection device and is electrically connected to the second signal terminal of the logic enable unit. The second end of the second resistor is grounded.

[0009] In one embodiment, the logic enable unit includes an OR gate and an AND gate; The first input terminal of the OR gate constitutes the first signal terminal of the logic enable unit and is electrically connected to the output terminal of the left edge detector; the second input terminal of the OR gate constitutes the second signal terminal of the logic enable unit and is electrically connected to the output terminal of the right edge detector. The output of the OR gate is electrically connected to the first input of the AND gate, the second input of the AND gate is electrically connected to the reference pulse terminal, and the output of the AND gate is electrically connected to the level conversion unit.

[0010] Furthermore, to achieve the above objectives, this application also provides a method for repairing a broken wire in a broken wire repair circuit. This method is applied to the broken wire repair circuit described in any of the preceding claims, and includes: When the gate driving module outputs gate signals to the corresponding gate signal lines line by line according to the preset row scanning order, the disconnection detection module is enabled to monitor the input current signal of each gate signal line line by line when the gate driving module outputs the gate signal, and generates a disconnection data signal based on the input current signal. The disconnection data signal includes rising edge detection current and disconnected gate line. The control compensation module generates a gate compensation digital signal based on the rising edge detected current, and repairs the broken gate line according to the gate compensation digital signal.

[0011] In one embodiment, the step of generating a disconnection data signal based on the input current signal includes: The rising edge phase of the input current signal is extracted by the disconnection detection module, and the rising edge phase is compared with the reference edge phase of the disconnection detection module to obtain the phase comparison result. If the phase comparison result indicates that there is a phase difference between the rising edge phase and the reference edge phase, then the gate signal line that outputs the input current signal is determined to be a disconnected gate line, and the input current signal is determined to be a rising edge detection current. The rising edge detection current and the disconnected gate line are used as disconnected data signals.

[0012] In one embodiment, the step of generating a gate compensation digital signal based on the rising edge detection current includes: By connecting a sampling resistor in parallel to the signal output path of the disconnection data signal, the rising edge detection current is converted into a digital voltage signal; The enable compensation module responds to the target timing signal corresponding to the disconnected gate line and generates a gate compensation digital signal that is an inverted digital voltage signal.

[0013] In one embodiment, the step of repairing the broken gate line based on the gate compensation digital signal includes: A logical AND operation is performed based on the gate compensation digital signal and a preset reference pulse signal to generate a repair data signal with a duty cycle matching the reference pulse signal. The duty cycle of the reference pulse signal is the same as the duty cycle of the target timing signal. The repair data signal level is converted into a repair level signal, and when the gate drive module electrically connected to both ends of the broken gate line is disconnected, the repair level signal is synchronously input to both ends of the broken gate line.

[0014] In addition, to achieve the above objectives, this application also provides a display panel, wherein the display panel is provided with the broken line repair circuit described in any of the above claims, the display panel includes a display area and a non-display area, the non-display area is disposed around the periphery of the display area, a gate line array is disposed in the display area, and gate driving modules are disposed on the left and right sides of the gate line array in the non-display area, and the compensation module is integrated on the circuit board on which the display panel is soldered and fixed.

[0015] Furthermore, to achieve the above objectives, this application also provides a display device, which includes the aforementioned display panel; or, The display device includes a processor, a memory, and a driver program stored in the memory that can be executed by the processor, wherein when the driver program is executed by the processor, the steps of the above-described disconnection repair method are implemented.

[0016] This application provides a broken-line repair circuit integrating a gate line array, a gate driving module, a broken-line detection module, and a compensation module. When the gate driving modules located on the left and right sides of the gate line array output gate signals to the corresponding gate signal lines line by line according to a preset row scanning sequence, the broken-line detection module monitors the input current signal of each gate signal line under the gate signal driving line line by line. When an abnormal input current signal of a certain gate signal line is detected, a broken-line data signal including the rising edge detection current and the broken gate line is generated, realizing real-time monitoring of the broken gate signal line fault. At this time, after receiving the broken-line data signal, the compensation module generates an accurate and reliable gate compensation digital signal based on the rising edge detection current, and effectively repairs the broken gate line based on the gate compensation digital signal, thereby restoring the signal transmission function of the broken gate signal line, avoiding the horizontal dark line display defect caused by the inability of the TFT to turn on in the scanning line where the broken gate line is located, and effectively improving the product yield of the display panel. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a structural block diagram of the first embodiment of the wire breakage repair circuit of this application; Figure 2 This is a schematic diagram of the broken wire repair circuit involved in the embodiment of this application; Figure 3 This is a schematic diagram of the rising edge waveform involved in the embodiments of this application; Figure 4 This is a waveform diagram illustrating the normal and abnormal output of the gate signal line in the embodiments of this application; Figure 5 This is a schematic diagram of the output waveform of the D flip-flop involved in the embodiment of this application; Figure 6 This is a schematic diagram of the structure of the display panel involved in the embodiments of this application; Figure 7 This is a schematic diagram of the structure of the display device involved in the embodiments of this application.

[0020] The reference numerals in the attached diagram are as follows: 10, Gate line array; 20, Gate drive module; 30, Disconnection detection module; 31, Left disconnection detector; 32, Right disconnection detector; 40, Compensation module; 41, Left edge detector; 42, Right edge detector; 43, Logic enable unit; 44, Level conversion unit; R1, First resistor; F1, First NOT gate; U1, First edge-triggered flip-flop; R2, Second resistor; F2, Second NOT gate; U2, Second edge-triggered flip-flop.

[0021] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0023] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0024] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0025] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0026] During the manufacturing process of LCD screens, various display defects such as bright spots, dark spots, and flashing spots can occur due to process defects. Among these defects, GDL (Gate Driver Logic, also known as gate driver module) related defects account for as much as 30%. Short circuits or open circuits in the gate signal line will prevent the current row TFT (Thin-Film Transistor) from turning on properly, resulting in horizontal dark lines. Due to the abnormal display of the LCD screen, it cannot be sold normally, which will cause considerable economic losses.

[0027] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art.

[0028] To address the lateral dark line display defect caused by broken gate signal lines and improve the product yield of display panels, this application provides a broken line repair circuit and method, a display panel, and a display device.

[0029] This application provides a broken wire repair circuit, referring to... Figure 1 As shown, Figure 1 This is a structural block diagram of the first embodiment of the wire breakage repair circuit of this application. The wire breakage repair circuit includes: Gate line array 10, which includes a plurality of parallel gate signal lines.

[0030] In this embodiment, refer to Figure 1 The gate line array 10 consists of multiple parallel gate signal lines. The gate line array 10 ensures that the gate signals output by the gate driving module 20 row by row can be efficiently and orderly transmitted to the corresponding gate signal lines through the parallel gate line structure, thereby controlling the opening and closing of the pixel unit TFT electrically connected to the gate signal line and realizing the row-by-row scanning of the display screen.

[0031] Gate driving module 20 is disposed on the left and right sides of the gate line array 10. The gate driving module 20 is configured to output gate signals to the gate signal lines of the corresponding rows in a preset row scanning order.

[0032] In this embodiment, refer to Figure 1 The gate driving module 20 adopts a dual-end driving architecture and is located on the left and right sides of the gate line array 10. The gate driving module 20 synchronously outputs gate signals to both ends of the gate signal line of the corresponding row according to the preset row scanning order. This can effectively shorten the signal transmission distance of the gate signal and eliminate the signal delay and attenuation phenomenon caused by long-distance transmission of the gate signal output by the single-side driving architecture, ensuring the normal display of high-resolution or large-size display panels.

[0033] A disconnection detection module 30 is provided, the input terminal of which is electrically connected to the output terminal of the gate driving module 20. The disconnection detection module 30 is configured to monitor the input current signal of each gate signal line when the gate driving module 20 outputs the gate signal, and generate a disconnection data signal based on the input current signal. The disconnection data signal includes the rising edge detection current and the disconnected gate line.

[0034] In this embodiment, refer to Figure 1 In this application, the input terminal of the disconnection detection module 30 is electrically connected to the output terminal of the gate driving module 20. The disconnection detection module 30 uses frequency tracking technology to track the current change value of each gate signal line when it is connected to the gate signal output by the gate driving module 20. It can accurately detect the input current signal of each row of gate signal lines. The disconnection detection module 30 records the rising edge phase of each input current signal and can accurately identify the gate signal line with abnormal input current signal based on the rising edge phase. It generates a disconnection data signal containing the rising edge detection current and the disconnected gate line, thereby realizing the effective detection of the disconnection fault of the gate signal line.

[0035] The compensation module has its input terminal electrically connected to the output terminal of the disconnection detection module 30. The compensation module is configured to receive the disconnection data signal sent by the disconnection detection module 30, generate a gate compensation digital signal based on the rising edge detection current, and repair the disconnected gate line based on the gate compensation digital signal.

[0036] In this embodiment, the input terminal of the compensation module is electrically connected to the output terminal of the disconnection detection module 30. After receiving the disconnection data signal sent by the disconnection detection module 30, which includes the rising edge detection current and the disconnection gate line, the compensation module generates an accurate and reliable gate compensation digital signal based on the rising edge detection current, and effectively repairs the disconnected gate line based on the gate compensation digital signal, thereby restoring the signal transmission function of the broken gate signal line, avoiding the horizontal dark line display defect caused by the TFT of the scan line where the disconnected gate line is located not being able to turn on, and effectively improving the product yield of the display panel.

[0037] Furthermore, in some other feasible embodiments, reference is made to... Figure 2 The compensation module includes a left edge detection element 41, a right edge detection element 42, a logic enable unit 43, and a level conversion unit 44. The input terminal of the left edge detection element 41 is electrically connected to the output terminal of the left gate driver through the left disconnection detection element 31 in the disconnection detection module 30, and the output terminal of the left edge detection element 41 is electrically connected to the first signal terminal of the logic enable unit 43. The left gate driver is a gate driver module 20 disposed on the left side of the gate line array 10. The input terminal of the right edge detection element 42 is electrically connected to the output terminal of the right gate driver through the right disconnection detection element 32 in the disconnection detection module 30, and the output terminal of the right edge detection element 42 is electrically connected to the first signal terminal of the logic enable unit 43. The right gate driver is a gate driver module 20 disposed on the right side of the gate line array 10. The output terminal of the logic enable unit 43 is electrically connected to the level conversion unit 44.

[0038] In this embodiment, due to Figure 1The gate drive module 20 adopts a dual-ended drive architecture. When a gate signal line in a certain row is disconnected, an output abnormality will occur. This abnormality is mainly manifested in the voltage and current when the gate signal line is connected to the gate drive module 20 to output the gate signal. The disconnection detection module 30 provided in this application detects the input current signal when the gate signal line is connected to the gate drive module 20 to output the gate signal, thereby achieving accurate detection of the gate disconnection. For example, since there are broken gate signal lines on both the left and right sides of the display panel of the dual-end driving architecture, the disconnection detection module 30 is provided with a left disconnection detection element 31 electrically connected to the gate driving module 20 (i.e., the left gate driving element) located on the left side of the gate line array 10, and a right disconnection detection element 32 electrically connected to the gate driving module 20 (i.e., the right gate driving element) located on the right side of the gate line array 10. This allows the disconnection detection module 30 to quickly distinguish whether the disconnection of the gate signal line occurs on the side electrically connected to the left gate driving element or the side electrically connected to the right gate driving element, or whether the disconnection fault occurs on both sides simultaneously, based on the input current on the left and right sides of the gate signal line.

[0039] Next, refer to Figure 2 The left disconnection detection unit 31 detects the input current signal Ii_L on the left side of each row of gate signal lines according to the preset row scanning order, and records the rising edge phase of the input current signal Ii_L. The normal input current signal Ii_L is output. Figure 3 The rising edge waveform of the current signal is shown in (a). Subsequently, the left disconnection detection unit 31 compares the rising edge phase of the input current signal Ii_L with the preset reference edge phase. If there is a phase difference between the rising edge phase and the reference edge phase, it indicates that the rising edge current of the input current signal Ii_L has disappeared. The input current signal Ii_L with the disappearing rising edge current is taken as the rising edge detection current Ii_L_rise. Based on the gate line number carried by the rising edge detection current Ii_L_rise, the gate signal line corresponding to the input current signal Ii_L can be quickly located to be disconnected on the side near the left gate driver (i.e., the disconnected gate line). Next, the left disconnection detection unit 31 sends the disconnection data signal signal_L carrying the rising edge detection current Ii_L_rise and the disconnected gate line to the compensation module to trigger the disconnection repair mechanism of the compensation module.

[0040] The right disconnection detector 32, which operates synchronously with the left disconnection detector 31, uses the same disconnection detection logic and timing control. It detects the input current signal Ii_R on the right side of each row of gate signal lines, records the rising edge phase of the input current signal Ii_R, and compares it with a preset reference edge phase. When a phase difference is detected between the rising edge phase of the input current signal Ii_R and the reference edge phase, it indicates that the rising edge current of the input current signal Ii_R has disappeared. The input current signal Ii_R with the disappeared rising edge current is marked as the rising edge detection current Ii. The rising edge detection current Ii_L_rise is used to quickly locate the gate signal line corresponding to the input current signal Ii_R that is broken on the side near the right gate driver (i.e., the broken gate line). Similarly, the rising edge detection current Ii_L_rise and the broken gate line data signal signal_R are sent to the compensation module to ensure that the broken data signal signal_R can be received by the compensation module on the same time axis as the broken data signal signal_L.

[0041] After receiving the disconnection data signals signal_L and signal_R, the compensation module synchronously calls the left edge detector 41 and the right edge detector 42 to perform voltage conversion on the rising edge detection currents Ii_L_rise and Ii_R_rise, respectively, to obtain digital voltage signals Vdata_L and Vdata_R. Then, it enables the left edge detector 41 and the right edge detector 42 to simultaneously respond to the target timing signal corresponding to the disconnected gate line, generating gate compensation digital signals V'data_L and V'data_R, respectively, which are then transmitted to the logic enable unit 43. This allows the logic enable unit 43 to determine the gate compensation digital signal... After at least one of the signals V'data_L and the gate compensation digital signal V'data_R is at a high level, this high level voltage is logically ANDed with a preset reference pulse signal to generate a repair data signal with a duty cycle matching the reference pulse signal. The duty cycle of the reference pulse signal is the same as the duty cycle of the target timing signal. Next, the repair data signal is input to the level conversion unit 44 to be converted into a repair level signal. Simultaneously, the repair level signal is input to both ends of the broken gate line by disconnecting the gate drive module 20 which is electrically connected to both ends of the broken gate line, thereby restoring the signal transmission function of the broken gate signal line, avoiding the horizontal dark line display defect caused by the TFT of the scan line where the broken gate line is located being unable to turn on, and effectively improving the product yield of the display panel.

[0042] It should be noted that, referring to Figure 4 , Figure 4Waveform 1 in the image represents the normal output voltage waveform from gate signal lines G107 to G112. Figure 4 Waveforms 2 and 3 in the diagram represent voltage output waveforms indicating an abnormal voltage output on gate signal line G108. For example, if the gate line number carried by the rising edge detection current is identified as G108, then the disconnected gate line can be determined to be gate signal line G108.

[0043] Furthermore, in some feasible embodiments, reference is made to Figure 2 The left edge detection element 41 includes a first resistor R1, a first NOT gate F1, and a first edge trigger U1. The first end of the first resistor R1 forms the input terminal of the left edge detection element 41 and is electrically connected to the input terminal of the first NOT gate F1 and the output terminal of the left gate driver. The output terminal of the first NOT gate F1 is electrically connected to the data input terminal of the first edge trigger U1. The clock terminal of the first edge trigger U1 is electrically connected to the scan clock signal terminal. The state output terminal of the first edge trigger U1 forms the output terminal of the left edge detection element 41 and is electrically connected to the first signal terminal of the logic enable unit 43. The second end of the first resistor R1 is grounded.

[0044] In this embodiment, refer to Figure 2 In this application, a first resistor R1 is connected in parallel to the output terminal of the left edge detection element 41, thereby converting the rising edge detection current Ii_L_rise voltage in the input current signal Ii_L transmitted via the left edge detection element 41 into a digital voltage signal Vdata_L. Since the rising edge detection current Ii_L_rise refers to the input current signal Ii_L where the rising edge current disappears, that is, the rising edge detection current Ii_L_rise is 0, in other words, the digital voltage signal Vdata_L is... Figure 5 The waveform (a) shows the 0V corresponding to the broken gate signal line G108; subsequently, the digital voltage signal Vdata_L is 0 and is inverted by the first NOT gate F1. This digital voltage signal Vdata_L then... Figure 5 The waveform (c) shows a jump from 0V to 3.3V, outputting the digital voltage signal Vdata_L to... Figure 2 The first edge-triggered flip-flop U1 is used as the data input terminal (i.e., the D terminal); subsequently, the clock signal Clk_i is used as the trigger signal of the first edge-triggered flip-flop U1, and a counter is used to calculate the clock signal Clk_i. Figure 4The location of the break point in waveform 2 is determined by identifying the gate line number G108 based on the rising edge detection current, thus identifying the broken gate line as gate signal line G108. Furthermore, the row switching clock control of the gate drive module 20 switches to the next row for scanning every 8 clock cycles. Therefore, based on 108 / 8 = 13 remainder 4, the clock signal Clk_i is calculated as the target timing signal CLK4 representing the 4th clock signal. At this time, the first edge-triggered trigger U1... Figure 5 As shown in waveform (b), when the target timing signal CLK4 is triggered, the digital voltage signal Vdata_L output by the first NOT gate F1 jumps from 0V to 3.3V as the gate compensation digital signal V'data_L for output.

[0045] The right edge detection element 42 includes a second resistor R2, a second NOT gate F2, and a second edge trigger U2. The first end of the second resistor R2 forms the input terminal of the right edge detection element 42 and is electrically connected to the input terminal of the second NOT gate F2 and the output terminal of the right gate driver. The output terminal of the second NOT gate F2 is electrically connected to the data input terminal of the second edge trigger U2. The clock terminal of the second edge trigger U2 is electrically connected to the scan clock signal terminal. The state output terminal of the second edge trigger U2 forms the output terminal of the right edge detection element 42 and is electrically connected to the second signal terminal of the logic enable unit 43. The second end of the second resistor R2 is grounded.

[0046] In this embodiment, refer to Figure 2 In this application, a second resistor R2 is connected in parallel to the output terminal of the right edge detection element 42, thereby converting the rising edge detection current Ii_R_rise voltage in the input current signal Ii_R transmitted via the right edge detection element 42 into a digital voltage signal Vdata_R. Since the rising edge detection current Ii_R_rise refers to the input current signal Ii_R where the rising edge current disappears, i.e., the rising edge detection current Ii_R_rise is 0, that is, the digital voltage signal Vdata_R is... Figure 5 The waveform (a) shows the 0V corresponding to the broken gate signal line G108; subsequently, the digital voltage signal Vdata_R is 0 and is inverted by the second NOT gate F2. This digital voltage signal Vdata_R then... Figure 5 The waveform (c) shows a jump from 0V to 3.3V, outputting the digital voltage signal Vdata_R to... Figure 2 The second edge-triggered flip-flop U2 is used as the data input terminal (i.e., the D terminal); subsequently, the clock signal Clk_i is used as the trigger signal for the second edge-triggered flip-flop U2, and a counter is used to calculate the clock signal Clk_i. Figure 4The location of the break point in waveform 2 is determined by identifying the broken gate line as gate signal line G108 based on the gate line number carried by the rising edge detection current. Since the row switching clock control of the gate drive module 20 switches to the next row for scanning every 8 clock cycles, the clock signal Clk_i is calculated as the target timing signal CLK4 representing the 4th clock signal, based on 108 / 8 = 13 remainder 4. At this time, the second edge-triggered trigger U2... Figure 5 As shown in waveform (b), when the target timing signal CLK4 is triggered, the digital voltage signal Vdata_R output by the second NOT gate F2 jumps from 0V to 3.3V as the gate compensation digital signal V'data_R and is output.

[0047] It should be noted that 0V can be understood as a low-level voltage, and 3.3V can be understood as a high-level voltage. The first edge-triggered flip-flop U1 and the second edge-triggered flip-flop U2 can be understood as D flip-flops.

[0048] Furthermore, in some other feasible embodiments, reference is made to... Figure 2 The logic enable unit 43 includes an OR gate and an AND gate; the first input terminal of the OR gate constitutes the first signal terminal of the logic enable unit 43 and is electrically connected to the output terminal of the left edge detection element 41; the second input terminal of the OR gate constitutes the second signal terminal of the logic enable unit 43 and is electrically connected to the output terminal of the right edge detection element 42; the output terminal of the OR gate is electrically connected to the first input terminal of the AND gate; the second input terminal of the AND gate is electrically connected to the reference pulse terminal; and the output terminal of the AND gate is electrically connected to the level conversion unit 44.

[0049] In this embodiment, when the gate compensation digital signal V'data_L and the gate compensation digital signal V'data_R are input to the OR gate, the logical OR operation of the OR gate outputs a high-level voltage if either of the gate compensation digital signals V'data_L or V'data_R is a high-level voltage (3.3V). The waveform of this high-level voltage is as follows: Figure 5 The waveform (c) is shown in the figure; then the high-level voltage output by the OR gate is logically ANDed with the preset reference pulse signal to output a repair data signal with the same high-level duty cycle as the reference pulse signal.

[0050] Next, since the repair data signal output by the AND gate is a digital voltage signal that continuously outputs a high-level voltage during the high-level period of the reference pulse signal output, and the normal operation of the TFT connected to the gate signal line requires the alternating conduction of the high-level signal Vgh and the high-level signal Vgl, this application sets the level conversion module to be implemented using an operational amplifier, setting the reference voltage Vref between 0 and 3.3V, with a high-level voltage input at the positive power supply terminal and a low-level voltage input at the negative power supply terminal. This enables the operational amplifier to output signal Vgh when the input voltage is a high-level voltage of 3.3V and output signal Vgl when the input voltage is a low-level voltage of 0V, thereby generating the repair level signal corresponding to the repair data signal. Next, the repair data signal is input to the level conversion unit 44 to be converted into a repair level signal, and the gate drive module 20, which is disconnected from the two ends of the broken gate line, synchronously inputs the repair level signal to both ends of the broken gate line, thereby effectively repairing the broken gate line.

[0051] In summary, this application provides a broken-line repair circuit integrating a gate line array 10, a gate driving module 20, a broken-line detection module 30, and a compensation module. When the gate driving modules 20, located on the left and right sides of the gate line array 10, output gate signals to the corresponding gate signal lines line by line according to a preset row scanning sequence, the broken-line detection module 30 monitors the input current signal of each gate signal line under the gate signal drive line by line. When an abnormal input current signal of a certain gate signal line is detected, a broken-line data signal containing the rising edge detection current and the broken gate line is generated, realizing real-time monitoring of the broken gate signal line fault. At this time, after receiving the broken-line data signal, the compensation module generates an accurate and reliable gate compensation digital signal based on the rising edge detection current, and effectively repairs the broken gate line based on the gate compensation digital signal, thereby restoring the signal transmission function of the broken gate signal line, avoiding the horizontal dark line display defect caused by the inability of the TFT to turn on in the scanning line where the broken gate line is located, and effectively improving the product yield of the display panel.

[0052] Furthermore, based on the first embodiment of the disconnection repair circuit of this application, a second embodiment of the disconnection repair method of this application is proposed.

[0053] The disconnection repair method of this application is applied to the disconnection repair circuit of any of the above claims. The disconnection repair method of this application is executed by a terminal device that drives and controls the disconnection repair circuit. The disconnection repair method of this application includes the following implementation steps S10 to S20.

[0054] Step S10: When the gate driving module 20 outputs gate signals to the corresponding gate signal lines line by line according to the preset row scanning order, the disconnection detection module 30 is enabled to monitor the input current signal of each gate signal line line by line when the gate driving module 20 outputs the gate signal, and generates a disconnection data signal based on the input current signal. The disconnection data signal includes rising edge detection current and disconnected gate line.

[0055] In this embodiment, refer to Figure 1 In this application, the input terminal of the disconnection detection module 30 is electrically connected to the output terminal of the gate driving module 20. The disconnection detection module 30 uses frequency tracking technology to track the current change value of each gate signal line when it is connected to the gate signal output by the gate driving module 20. It can accurately detect the input current signal of each row of gate signal lines. The disconnection detection module 30 records the rising edge phase of each input current signal and can accurately identify the gate signal line with abnormal input current signal based on the rising edge phase. It generates a disconnection data signal containing the rising edge detection current and the disconnected gate line, thereby realizing the effective detection of the disconnection fault of the gate signal line.

[0056] Step S20: Control the compensation module to generate a gate compensation digital signal based on the rising edge detected current, and repair the broken gate line according to the gate compensation digital signal.

[0057] In this embodiment, the input terminal of the compensation module is electrically connected to the output terminal of the disconnection detection module 30. After receiving the disconnection data signal sent by the disconnection detection module 30, which includes the rising edge detection current and the disconnection gate line, the compensation module generates an accurate and reliable gate compensation digital signal based on the rising edge detection current, and effectively repairs the disconnected gate line based on the gate compensation digital signal, thereby restoring the signal transmission function of the broken gate signal line, avoiding the horizontal dark line display defect caused by the TFT of the scan line where the disconnected gate line is located not being able to turn on, and effectively improving the product yield of the display panel.

[0058] Furthermore, in some other feasible embodiments, the above step S10: generating a disconnection data signal based on the input current signal, further includes the following implementation steps S101 to S102.

[0059] Step S101: Extract the rising edge phase of the input current signal through the disconnection detection module 30, and compare the rising edge phase with the reference edge phase of the disconnection detection module 30 to obtain the phase comparison result.

[0060] In this embodiment, the disconnection detection module 30 detects the input current signal of each row of gate signal lines line by line and records the rising edge phase of the input current signal. A normal input current signal is output. Figure 3The rising edge waveform of the current signal shown in (a) is shown below, and... Figure 3 The rising edge waveform of the current signal shown in (a) is used as the preset reference edge phase. Subsequently, the disconnection detection module 30 compares the rising edge phase of the input current signal with the reference edge phase to accurately obtain the phase comparison result. Based on the phase comparison result, the phase shift caused by the breakage of the gate signal line can be quickly identified, providing accurate and reliable phase difference data for subsequent disconnection fault identification.

[0061] Step S102: If the phase comparison result shows that there is a phase difference between the rising edge phase and the reference edge phase, then the gate signal line that outputs the input current signal is determined to be a disconnected gate line, and the input current signal is determined to be a rising edge detection current. The rising edge detection current and the disconnected gate line are used as disconnected data signals.

[0062] In this embodiment, if the phase comparison result shows a phase difference between the rising edge phase and the reference edge phase, it indicates that the rising edge current of the input current signal has disappeared. The input current signal with the disappeared rising edge current is used as the rising edge detection current, and the broken gate line is determined according to the signal line row number identifier carried by the input current signal. The broken position of the broken gate line is on the side electrically connected to the left gate driver. Next, the left broken detection unit 31 sends the broken data signal carrying the rising edge detection current and the broken gate line to the compensation module. The compensation module converts the rising edge detection current voltage into... Figure 3 The digital voltage signal of the voltage signal waveform shown in (b) is used to make the same output gate compensation digital signal as the target timing signal corresponding to the disconnected gate line, and the inverted digital voltage signal is sent to the logic enable unit 43.

[0063] In another embodiment, if the phase comparison result shows that there is no phase difference between the rising edge phase and the reference edge phase, it indicates that the gate signal line that outputs the input current signal is a normal gate signal line.

[0064] Furthermore, in some feasible embodiments, the above step S20: generating a gate compensation digital signal based on the rising edge detection current may also include the following implementation steps S201 to S202.

[0065] Step S201: Convert the rising edge detection current into a digital voltage signal by connecting a sampling resistor in parallel to the signal output path of the disconnection data signal.

[0066] In this embodiment, a sampling resistor is connected in parallel to the signal output path of the disconnection data signal so that the weak rising edge detection current can be efficiently converted into a measurable digital voltage signal, providing a stable and reliable voltage data input for disconnection detection.

[0067] In a specific embodiment, if the disconnection data signal is output by the left disconnection detection unit 31, the sampling resistor is the first resistor R1; if the disconnection data signal is output by the right disconnection detection unit 32, the sampling resistor is the second resistor R2.

[0068] Step S202: Enable the compensation module to generate an inverted digital voltage signal as a gate compensation digital signal in response to the target timing signal corresponding to the disconnected gate line.

[0069] In this embodiment, after inverting the digital voltage signal (0V) according to the logical NOT operation, the digital voltage signal from... Figure 5 The waveform (c) shows a jump from 0V to 3.3V, outputting a digital voltage signal to... Figure 2 The first edge-triggered flip-flop U1 is used as the data input terminal (i.e., the D terminal); subsequently, the clock signal Clk_i is used as the trigger signal for the D flip-flop in the first edge-triggered flip-flop U1, and a counter is used to calculate the clock signal Clk_i. Figure 4 The location of the break point in waveform 2 is determined by identifying the gate line number G108 based on the rising edge detection current, thus identifying the broken gate line as gate signal line G108. Furthermore, the row switching clock control of the gate drive module 20 switches to the next row for scanning every 8 clock cycles. Therefore, based on 108 / 8 = 13 remainder 4, the clock signal Clk_i is calculated as the target timing signal CLK4 representing the 4th clock signal. At this time, the D flip-flop... Figure 5 As shown in waveform (b), when triggered by the target timing signal CLK4, the inverted digital voltage signal Vdata_L jumps from 0V to 3.3V as the gate compensation digital signal for output.

[0070] Furthermore, in some other feasible embodiments, the above step S20: repairing the broken gate line according to the gate compensation digital signal may also include the following implementation steps A10 to A20.

[0071] Step A10: Perform a logical AND operation based on the gate compensation digital signal and the preset reference pulse signal to generate a repair data signal with a duty cycle matching the reference pulse signal. The duty cycle of the reference pulse signal is the same as the duty cycle of the target timing signal.

[0072] In this embodiment, when the gate compensation digital signal V'data_L and the gate compensation digital signal V'data_R are input to the OR gate, the logical OR operation of the OR gate outputs a high-level voltage if either of the gate compensation digital signals V'data_L or V'data_R is a high-level voltage (3.3V). The waveform of this high-level voltage is as follows: Figure 5The waveform (c) is shown in the figure; then the high-level voltage output by the OR gate is logically ANDed with the preset reference pulse signal to output a repair data signal with the same high-level duty cycle as the reference pulse signal.

[0073] Step A20: Convert the repair data signal level into a repair level signal, and simultaneously input the repair level signal to both ends of the broken gate line when disconnecting the gate drive module 20 electrically connected to both ends of the broken gate line.

[0074] In this embodiment, the repair data signal output by the AND gate is a digital voltage signal that continuously outputs a high-level voltage during the high-level period of the reference pulse signal output. However, the normal operation of the TFT connected to the gate signal line requires the alternating conduction of the high-level signal Vgh and the high-level signal Vgl. This application sets the level conversion module to be implemented using an operational amplifier, setting the reference voltage Vref between 0 and 3.3V, with a high-level voltage input at the positive power supply terminal and a low-level voltage input at the negative power supply terminal. This enables the operational amplifier to output signal Vgh when the input voltage is a high-level voltage of 3.3V and to output signal Vgl when the input voltage is a low-level voltage of 0V, thereby generating the repair level signal corresponding to the repair data signal. Next, the repair data signal is input to the level conversion unit 44 to be converted into a repair level signal, and the gate driving module 20, which is disconnected from the two ends of the broken gate line, synchronously inputs the repair level signal to both ends of the broken gate line, thereby effectively repairing the broken gate line.

[0075] In summary, this application provides a broken-line repair circuit integrating a gate line array 10, a gate driving module 20, a broken-line detection module 30, and a compensation module. When the gate driving modules 20, located on the left and right sides of the gate line array 10, output gate signals to the corresponding gate signal lines line by line according to a preset row scanning sequence, the broken-line detection module 30 monitors the input current signal of each gate signal line under the gate signal drive line by line. When an abnormal input current signal of a certain gate signal line is detected, a broken-line data signal containing the rising edge detection current and the broken gate line is generated, realizing real-time monitoring of the broken gate signal line fault. At this time, after receiving the broken-line data signal, the compensation module generates an accurate and reliable gate compensation digital signal based on the rising edge detection current, and effectively repairs the broken gate line based on the gate compensation digital signal, thereby restoring the signal transmission function of the broken gate signal line, avoiding the horizontal dark line display defect caused by the inability of the TFT to turn on in the scanning line where the broken gate line is located, and effectively improving the product yield of the display panel.

[0076] In addition, to achieve the above objectives, refer to Figure 6 , Figure 6This is a schematic diagram of the structure of a display panel according to an embodiment of this application. This application also provides a display panel, which is provided with the broken line repair circuit described in any of the above claims. The display panel includes a display area and a non-display area, the non-display area surrounding the periphery of the display area. A gate line array is disposed within the display area, and gate driving modules are disposed on the left and right sides of the gate line array in the non-display area. The compensation module is integrated on a circuit board that is soldered and fixed to the display panel.

[0077] It should be noted that, Figure 6 The shaded area in the image represents the non-display area. Figure 6 The blank rectangular area is the display area.

[0078] In addition, this application also provides a display device. Please refer to... Figure 7 , Figure 7 This is a schematic diagram of the display device involved in the embodiments of this application. Specifically, the display device in the embodiments of this application may be a device for locally running a disconnection repair method.

[0079] like Figure 7 As shown, the display device in this embodiment may include: the aforementioned disconnection repair circuit; or, a processor 1001, such as a CPU, a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. The communication bus 1002 is used to enable communication between these components. The user interface 1003 may include a display screen and an input unit such as a keyboard; optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface).

[0080] The memory 1005 is disposed on the main body of the display device. The memory 1005 stores a program that performs corresponding operations when executed by the processor 1001. The memory 1005 is also used to store parameters used by the display device. The memory 1005 can be a high-speed RAM or a stable, non-volatile memory, such as a disk drive. Optionally, the memory 1005 can also be a storage device independent of the aforementioned processor 1001.

[0081] Those skilled in the art will understand that Figure 7 The display device structure shown does not constitute a limitation on the display device and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0082] like Figure 7As shown, the memory 1005, which serves as a storage medium, may include an operating system, a network communication module, a user interface module, and a driver for a display device.

[0083] exist Figure 7 In the display device shown, the processor 1001 can be used to call the display device driver stored in the memory 1005 and execute the steps of the disconnection repair method described above.

[0084] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0085] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0086] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a display device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0087] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A circuit for repairing broken wires, characterized in that, The broken wire repair circuit includes: A gate line array, the gate line array comprising a plurality of parallel gate signal lines; A gate driving module is disposed on the left and right sides of the gate line array. The gate driving module is configured to output gate signals to the gate signal lines of the corresponding rows in a preset row scanning order. A disconnection detection module is provided, wherein the input terminal of the disconnection detection module is electrically connected to the output terminal of the gate driving module. The disconnection detection module is configured to monitor the input current signal of each gate signal line line by line when the gate driving module outputs the gate signal, and generate a disconnection data signal based on the input current signal. The disconnection data signal includes rising edge detection current and disconnected gate line. The compensation module has its input terminal electrically connected to the output terminal of the disconnection detection module. The compensation module is configured to receive the disconnection data signal sent by the disconnection detection module, generate a gate compensation digital signal based on the rising edge detection current, and repair the disconnected gate line based on the gate compensation digital signal.

2. The broken wire repair circuit as described in claim 1, characterized in that, The compensation module includes a left edge detection element, a right edge detection element, a logic enable unit, and a level conversion unit. The input terminal of the left edge detector is electrically connected to the output terminal of the left gate driver through the left disconnection detector in the disconnection detection module. The output terminal of the left edge detector is electrically connected to the first signal terminal of the logic enable unit. The left gate driver is a gate driver module disposed on the left side of the gate line array. The input terminal of the right edge detector is electrically connected to the output terminal of the right gate driver through the right disconnection detector in the disconnection detection module. The output terminal of the right edge detector is electrically connected to the first signal terminal of the logic enable unit. The right gate driver is a gate driver module disposed on the right side of the gate line array. The output of the logic enable unit is electrically connected to the level conversion unit.

3. The broken wire repair circuit as described in claim 2, characterized in that, The left edge detection element includes a first resistor, a first NOT gate, and a first edge trigger. The first terminal of the first resistor constitutes the input terminal of the left edge detection element and is electrically connected to the input terminal of the first NOT gate and the output terminal of the left gate driver. The output terminal of the first NOT gate is electrically connected to the data input terminal of the first edge flip-flop. The clock terminal of the first edge flip-flop is electrically connected to the scan clock signal terminal. The state output terminal of the first edge flip-flop constitutes the output terminal of the left edge detection element and is electrically connected to the first signal terminal of the logic enable unit. The second terminal of the first resistor is grounded; and / or, The right edge detection element includes a second resistor, a second NOT gate, and a second edge trigger. The first end of the second resistor forms the input terminal of the right edge detection device and is electrically connected to the input terminal of the second NOT gate and the output terminal of the right gate driver. The output terminal of the second NOT gate is electrically connected to the data input terminal of the second edge flip-flop. The clock terminal of the second edge flip-flop is electrically connected to the scan clock signal terminal. The state output terminal of the second edge flip-flop forms the output terminal of the right edge detection device and is electrically connected to the second signal terminal of the logic enable unit. The second end of the second resistor is grounded.

4. The broken wire repair circuit as described in claim 2, characterized in that, The logic enable unit includes an OR gate and an AND gate; The first input terminal of the OR gate constitutes the first signal terminal of the logic enable unit and is electrically connected to the output terminal of the left edge detector; the second input terminal of the OR gate constitutes the second signal terminal of the logic enable unit and is electrically connected to the output terminal of the right edge detector. The output of the OR gate is electrically connected to the first input of the AND gate, the second input of the AND gate is electrically connected to the reference pulse terminal, and the output of the AND gate is electrically connected to the level conversion unit.

5. A method for repairing broken wires, characterized in that, The broken wire repair method is applied to the broken wire repair circuit as described in any one of claims 1 to 4, and the broken wire repair method includes: When the gate driving module outputs gate signals to the corresponding gate signal lines line by line according to the preset row scanning order, the disconnection detection module is enabled to monitor the input current signal of each gate signal line line by line when the gate driving module outputs the gate signal, and generates a disconnection data signal based on the input current signal. The disconnection data signal includes rising edge detection current and disconnected gate line. The control compensation module generates a gate compensation digital signal based on the rising edge detected current, and repairs the broken gate line according to the gate compensation digital signal.

6. The wire breakage repair method as described in claim 5, characterized in that, The step of generating a disconnection data signal based on the input current signal includes: The rising edge phase of the input current signal is extracted by the disconnection detection module, and the rising edge phase is compared with the reference edge phase of the disconnection detection module to obtain the phase comparison result. If the phase comparison result indicates that there is a phase difference between the rising edge phase and the reference edge phase, then the gate signal line that outputs the input current signal is determined to be a disconnected gate line, and the input current signal is determined to be a rising edge detection current. The rising edge detection current and the disconnected gate line are used as disconnected data signals.

7. The wire breakage repair method as described in claim 5, characterized in that, The step of generating a gate compensation digital signal based on the rising edge detected current includes: By connecting a sampling resistor in parallel to the signal output path of the disconnection data signal, the rising edge detection current is converted into a digital voltage signal; The enable compensation module responds to the target timing signal corresponding to the disconnected gate line and generates a gate compensation digital signal that is an inverted digital voltage signal.

8. The wire breakage repair method as described in claim 7, characterized in that, The step of repairing the broken gate line based on the gate compensation digital signal includes: A logical AND operation is performed based on the gate compensation digital signal and a preset reference pulse signal to generate a repair data signal with a duty cycle matching the reference pulse signal. The duty cycle of the reference pulse signal is the same as the duty cycle of the target timing signal. The repair data signal level is converted into a repair level signal, and when the gate drive module electrically connected to both ends of the broken gate line is disconnected, the repair level signal is synchronously input to both ends of the broken gate line.

9. A display panel, characterized in that, The display panel is provided with a broken line repair circuit as described in any one of claims 1 to 4. The display panel includes a display area and a non-display area. The non-display area is arranged around the periphery of the display area. A gate line array is arranged in the display area. A gate driving module is arranged on the left and right sides of the gate line array in the non-display area. The compensation module is integrated on the circuit board that is soldered and fixed to the display panel.

10. A display device, characterized in that, The display device includes the display panel as described in claim 9; or... The display device includes a processor, a memory, and a driver program stored in the memory that can be executed by the processor, wherein when the driver program is executed by the processor, it implements the steps of the disconnection repair method as described in any one of claims 5 to 8.

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