A method and system for monitoring the status of optical storage devices based on FPGA

Abstract

This invention relates to the field of condition monitoring technology, and in particular to a method and system for condition monitoring of photovoltaic energy storage devices based on FPGA. The method includes the following steps: acquiring FPGA structure data; deploying a ring oscillator unit in the idle logic resource area of ​​the FPGA based on the FPGA structure data, and configuring a leakage current measurement channel on the FPGA programmable I / O pins to obtain leakage current measurement channel configuration data; collecting RO oscillation frequency data and gate leakage current data according to the leakage current measurement channel configuration data; and mapping and calculating the RO oscillation frequency data and gate leakage current data based on preset temperature calibration curves and voltage calibration curves, respectively. This invention, through high-precision real-time monitoring and multivariate regression modeling based on FPGA, effectively improves the diagnostic accuracy and intelligent early warning capability of temperature and stress in key areas of photovoltaic energy storage devices, solving the problems of insufficient accuracy, real-time performance, and specificity of traditional monitoring systems.

Description

Technical Field

[0001] This invention relates to the field of status monitoring technology, and in particular to a method and system for status monitoring of optical storage devices based on FPGA. Background Technology

[0002] Traditional condition monitoring relies heavily on analog circuits or dedicated sensors, which suffer from low sensitivity, poor anti-interference capabilities, and insufficient integration. In recent years, Field-Programmable Gate Array (FPGA) technology has gradually become the core platform for intelligent monitoring systems due to its high parallel processing capabilities, flexible hardware reconfiguration features, and excellent real-time performance. Early FPGAs were mainly used in digital signal processing and communication, but with continuous advancements in technology, their resource abundance and power consumption have significantly improved, making their application in the condition monitoring of photovoltaic (PV) and energy storage devices possible. Currently, using FPGAs for high-precision acquisition and analysis of key parameters such as current, voltage waveforms, and leakage current in PV and energy storage devices has become a research hotspot. Simultaneously, FPGAs support the implementation of various embedded algorithms, enabling complex data processing and anomaly detection. However, traditional PV and energy storage device condition monitoring often relies on data from single sensors, lacks precise quantification of temperature and gate stress, and often ignores internal structural differences, making it difficult to effectively diagnose critical areas. Summary of the Invention

[0003] Therefore, it is necessary to provide a method and system for monitoring the status of optical storage devices based on FPGA to solve at least one of the above-mentioned technical problems.

[0004] To achieve the above objectives, an FPGA-based optical storage device status monitoring method is provided, the method comprising the following steps:

[0005] Step S1: Obtain FPGA structure data; Based on the FPGA structure data, deploy a ring oscillator unit in the FPGA's idle logic resource area, and configure a leakage current measurement channel on the FPGA's programmable I / O pins to obtain leakage current measurement channel configuration data;

[0006] Step S2: Collect RO oscillation frequency data and gate leakage current data according to the leakage current measurement channel configuration data; map and calculate the RO oscillation frequency data and gate leakage current data based on the preset temperature calibration curve and voltage calibration curve respectively to obtain the local temperature and gate oxide stress index.

[0007] Step S3: Obtain structural data of the photovoltaic storage device; analyze the structural topology of the photovoltaic storage device structural data and select the driving board area of ​​the photovoltaic storage device; construct a multivariate regression model for the driving board area of ​​the photovoltaic storage device through local temperature and gate oxidation stress index to generate a detection model for the driving board of the photovoltaic storage device.

[0008] Step S4: Use the detection model of the photovoltaic storage device driver board to monitor the RO oscillation frequency data and gate leakage current data to monitor the driver board temperature and gate stress indicators, and generate driver board temperature monitoring data and gate stress monitoring data; compare the driver board temperature monitoring data and gate stress monitoring data with preset thresholds respectively, thereby generating a hardware health alarm signal for the photovoltaic storage device and triggering the device soft shutdown or load reduction protection.

[0009] This invention fully leverages the reconfigurability of the FPGA structure by dynamically deploying Ring Oscillator (RO) units and configuring leakage current measurement channels with programmable I / O pins in the idle logic resource area of ​​the FPGA. This avoids the introduction of additional sensors, saves hardware resources, and improves system integration. By simultaneously acquiring RO oscillation frequency data and gate leakage current data, and combining temperature and voltage calibration curves for dual-channel mapping calculation, high-resolution sensing of local temperature and gate oxide stress is achieved, resulting in higher accuracy and robustness compared to single-parameter monitoring schemes. The invention introduces topology analysis technology for photovoltaic storage devices, extracting the driver board area as the key monitoring object. A multivariate regression model is constructed using local physical indicators, enabling the detection model to possess structural matching and region specificity, significantly improving model adaptability and prediction accuracy. The detection model can perform real-time calculations on the acquired data, generating driver board temperature monitoring data and gate stress monitoring data, achieving continuous tracking and trend warning of hardware operating status, forming a hardware-software coupled intelligent diagnostic link. By dynamically comparing monitoring data with preset health thresholds, a health alarm signal is quickly output. Based on the health status, a soft shutdown or load reduction protection mechanism can be autonomously triggered, achieving a dynamic balance between equipment safety and power performance. During the long-term operation of photovoltaic storage equipment, the risks of localized overheating and stress concentration are easily overlooked. The microscale dynamic monitoring scheme provided by this invention can detect potential aging or breakdown hazards in advance, thereby effectively reducing the system's sudden failure rate and extending the overall service life of the equipment. Therefore, this invention, through high-precision real-time monitoring based on FPGA and multivariate regression modeling, effectively improves the diagnostic accuracy and intelligent early warning capabilities of temperature and stress in key areas of photovoltaic storage equipment, solving the problems of insufficient accuracy, real-time performance, and specificity of traditional monitoring systems.

[0010] Preferably, step S1 includes the following steps:

[0011] Step S11: Obtain FPGA structure data;

[0012] Step S12: Identify idle logic cells in the FPGA structure data and generate idle logic resource distribution map data; perform local temperature sensitive area screening processing based on the idle logic resource distribution map data to generate candidate area data for ring oscillator deployment;

[0013] Step S13: Based on the candidate region data for ring oscillator deployment, perform ring oscillator topology binding processing to generate ring oscillator cell deployment data; perform pin electrical configuration parsing on the I / O resources in the FPGA structure data to generate programmable I / O pin configuration table data;

[0014] Step S14: Select pin groups with leakage current acquisition capability according to the programmable I / O pin configuration table data to generate leakage current channel candidate pin data; perform pin multiplexing conflict detection and sampling channel binding on the leakage current channel candidate pin data to generate leakage current measurement channel configuration data.

[0015] This invention analyzes FPGA structure data to construct a distribution map of idle logic resources, enabling spatial mapping of the usage of internal logic units and providing a foundation for refined resource scheduling for subsequent functional deployment. A temperature-sensitive region-priority screening strategy is employed to extract the most suitable region for deploying a ring oscillator from idle logic resources, improving thermal response sensitivity and ensuring high thermal-frequency coupling at the deployment location, thereby enhancing local temperature monitoring accuracy. An optimized ring oscillator topology is constructed in the candidate regions to ensure topological consistency, frequency adjustability, and thermal stability of the deployed oscillators, improving detection consistency and measurement effectiveness under large-scale deployment. By deeply analyzing the configuration capabilities and physical and electrical attributes of FPGA I / O resources, pin groups with leakage current acquisition capabilities are effectively distinguished, avoiding invalid calls to non-functional pins and improving resource utilization. Electrical attribute and functional reuse detection is performed on programmable I / O pins to screen pins that meet current sampling requirements, ensuring the electrical stability and data reliability of subsequent current channel measurements. Pin reuse conflicts are detected to prevent resource contention or functional abnormalities between data acquisition and other functions, improving the security of measurement channel configuration and system stability. Channel binding is performed on candidate pin data to ensure the continuity of sampling paths and timing stability, thereby improving the real-time performance and completeness of overall current data acquisition.

[0016] Preferably, step S14, which involves pin multiplexing conflict detection and sampling channel binding for candidate pin data of the leakage current channel, includes:

[0017] The candidate pin data of the leakage current channel is retrieved from the function multiplexing table to generate pin multiplexing conflict mapping data.

[0018] Priority conflict elimination is performed on the pin multiplexing conflict mapping data to generate conflict-free pin candidate data;

[0019] Based on the candidate data of conflict-free pins, the internal sampling logic structure of the FPGA is evaluated for resource adaptation, and sampling channel mapping matching data is generated.

[0020] The sampling bandwidth is filtered and the frequency response is verified on the sampling channel mapping matching data to generate the binding pin data that meets the bandwidth requirements;

[0021] Based on the bandwidth-compliant bound pin data, the sampling channel address index is encoded to generate leakage current measurement channel configuration data.

[0022] This invention constructs a function multiplexing table and generates pin multiplexing conflict mapping data. The system can comprehensively identify potential conflicts between pins used in various applications, effectively avoiding resource contention or data anomalies caused by multiplexing mismatch, and improving the stability and security of system configuration. A priority elimination strategy is introduced, prioritizing the retention of conflict-free pin resources crucial to the sampling channel while ensuring functional integrity, thereby optimizing the deployment success rate and robustness of the sampling channel. Conflict-free pin data is matched and evaluated with the FPGA's internal sampling logic structure to ensure that each bound pin has structural reachability and resource compatibility, enhancing sampling path coherence and deployment success rate. During the sampling channel binding process, bandwidth screening and frequency response verification are performed on matching pins to ensure that the selected pins have sufficient electrical transmission capabilities and dynamic response characteristics, greatly improving the authenticity, stability, and bandwidth reliability of the sampled signal. Address indexing encoding technology is introduced to generate a unique identifier for each valid sampling pin bound to the channel, facilitating efficient calling and accurate identification in subsequent FPGA control logic or data acquisition scheduling, achieving automated address mapping and management. Channel binding based on structure matching and bandwidth verification can effectively avoid data misalignment or information delay caused by channel blockage, sampling conflict and other problems, and improve system-level acquisition accuracy and scheduling real-time performance.

[0023] Preferably, step S2 includes the following steps:

[0024] Step S21: Bind the sampling task to the leakage current measurement channel configuration data to generate RO oscillation frequency sampling configuration data; perform data acquisition operation on the RO oscillation frequency sampling configuration data to generate RO oscillation frequency data;

[0025] Step S22: Perform leakage current channel activation and voltage scan control on the leakage current measurement channel configuration data to generate raw gate leakage current acquisition data;

[0026] Step S23: Perform frequency matching calculation on the preset temperature calibration curve based on the RO oscillation frequency data to generate local temperature data;

[0027] Step S24: Perform multi-segment conduction fitting on the preset voltage calibration curve based on the original gate leakage current acquisition data to generate gate oxide stress index data.

[0028] This invention generates dedicated RO oscillation frequency sampling configuration data by binding sampling tasks to the leakage current measurement channel configuration data. This achieves accurate mapping between sampling tasks and physical channels, improving the standardization and automation of task scheduling and avoiding multi-channel acquisition conflicts. The automated data acquisition process triggered after sampling configuration can quickly generate high-time-resolution RO oscillation frequency data, enhancing the ability to capture local dynamic thermal responses and meeting the need for precise perception of microscale time-varying temperature fields. In gate leakage current acquisition, by actively activating the sampling channel and executing a voltage scan control process, current response data can be acquired under different operating voltages, effectively restoring the true electrical characteristic curve and improving the integrity and controllability of the leakage current testing process. The multi-voltage segment current scan mechanism can obtain the variation characteristics of the current response in the conduction region, subthreshold region, and breakdown region, providing a more physically representative data foundation for subsequent stress modeling and reliability assessment. Frequency matching calculation of the RO oscillation frequency data and temperature calibration curve avoids the problem of delayed response and physical inconsistency of traditional external temperature sensors, achieving high-resolution modeling of the local thermal field inside the chip and effectively supporting thermal behavior tracking and thermal fatigue prediction. By fitting multiple conduction regions using raw gate leakage current data, the rate of change of current response under different conduction states can be extracted, and approximate indices of stress factors such as gate oxide electric field strength, mobility degradation, and interface state density can be constructed, thereby quantifying the process aging state.

[0029] Preferably, step S24 includes the following steps:

[0030] Step S241: Divide the raw gate leakage current data into voltage segments to generate multiple voltage region data, including subthreshold region division, linear region division and saturation region division.

[0031] Step S242: Based on the data of multiple voltage regions, perform linear and exponential regression fitting on the leakage current response in each region to generate region conduction slope fitting data.

[0032] Step S243: Calculate the slope offset of the region conduction slope fitting data to obtain conduction characteristic offset data;

[0033] Step S244: Weight the weights of different voltage segments according to the conduction characteristic offset data to generate the gate oxide stress factor; normalize the gate oxide stress factor and add temperature sensitivity correction parameters to generate the final gate oxide stress index data.

[0034] This invention divides leakage current acquisition data into subthreshold, linear, and saturation voltage segments, giving the fitting process physically distinct regional response characteristics. This effectively avoids local distortion caused by overall curve fitting and enhances the ability to identify subtle aging or process fluctuations. Adaptive linear and exponential regression methods are used for different voltage segments to correspond to weak conduction, strong conduction, and breakdown trend stages, respectively, improving the inclusiveness and accuracy of the fitting model for different conduction behaviors and supporting adaptive analysis of transistor behavior under various process conditions. The slope offset calculated based on the conduction characteristic slope fitting data reveals non-ideal conduction characteristics caused by microscale physical effects such as transistor aging, changes in interface state density, and carrier mobility degradation, providing sensitive physical indicators under process changes, thermal stress, or time degradation. By introducing a weighting strategy for different voltage regions, the conduction characteristic offset is weighted and accumulated into a comprehensive stress factor, which comprehensively considers the total stress load borne by the transistor in different operating ranges, improving the coverage and overall effectiveness of stress expression. After normalizing the stress factor, the resulting stress index is free from dimension dependence, exhibiting good versatility and cross-device comparability. It is suitable for unified health status assessment of different FPGA models, package types, and electrical environments. Adding a temperature sensitivity correction parameter during index generation compensates for the distortion of the stress index caused by leakage current gain under the influence of thermally excited carriers, further improving the final index's ability to accurately reflect real oxidation stress and enhancing its physical reliability and engineering guidance value.

[0035] Preferably, step S3 includes the following steps:

[0036] Step S31: Obtain structural data of the photovoltaic storage device;

[0037] Step S32: Extract the topology of the photovoltaic storage device structure data to identify the connection relationship and logical distribution between components and generate structural topology map data; filter the spatial location area of ​​the photovoltaic storage device driver board based on the structural topology map data to obtain driver board area identification data;

[0038] Step S33: Map the local temperature and gate oxide stress index to the driver board area identification data to generate driver board local stress response data; perform multivariate feature correlation screening on the driver board local stress response data using the mutual information method to generate the model training input dataset;

[0039] Step S34: Use the input dataset for model training to train a multivariate regression model and generate a detection model for the optical storage device driver board.

[0040] This invention analyzes the structural data of photovoltaic storage devices and generates a structural topology map, which systematically identifies the spatial layout and logical connections between various hardware components, providing structural support for subsequent location and feature mapping of key areas (such as the driver board). Region filtering based on the structural topology map accurately locates the physical position and boundary markers of the driver board, avoiding misassociation of data from non-critical areas and improving the targeting and detection efficiency of subsequent models. By mapping local temperature and gate oxidation stress indices to the driver board region marker data, local stress response data with spatial context can be formed, helping to characterize the true distribution characteristics of thermal and electrical stress in key areas. By fusing temperature information derived from RO frequency and stress indices obtained from leakage current modeling, a high-value multidimensional feature dataset can be constructed for behavior prediction, performance drift analysis, and lifetime modeling. Using mutual information to perform multivariate correlation analysis on the local stress response data of the driver board quantifies the information contribution between each feature and the target output, effectively identifying redundant and key features, and improving model training efficiency and generalization ability. The feature selection process ensures that the most representative and predictive input variables are retained, improving data quality from the source. This helps reduce overfitting, accelerates convergence, and enhances the model's robustness in real-world deployments. Based on the selected input dataset, multivariate regression modeling training outputs a highly interpretable, parameter-transparent, and lightweight driver board health detection model, enabling real-time perception of equipment micro-aging trends or abnormal behavior. The driver board detection model integrates spatial structure perception and stress data prediction capabilities, allowing for early detection of various stress accumulation states, such as thermal, electrical, and aging stresses, before critical failures occur, significantly improving the granularity of system health management.

[0041] Preferably, step S34 includes the following steps:

[0042] Step S341: Obtain the regression prediction model framework, wherein the mathematical formula of the regression prediction model framework is as follows:

[0043] ;

[0044] In the formula, These are the model's predicted values. This is the constant offset of the model's output when all input variables are 0. The number of input variables involved in the modeling. For the first The regression coefficients of each input feature. For the first The actual values ​​of each input feature;

[0045] Step S342: Perform feature multicollinearity detection on the model training input dataset, filter out highly collinear features, and generate redundant training data; evaluate linear separability based on the redundant training data, and generate a model regression applicability analysis report;

[0046] Step S343: Perform multivariate regression modeling calculations on the redundant training data to generate an initial regression coefficient matrix; perform regularization processing on the initial regression coefficient matrix to suppress model overfitting and generate regularized regression parameter data;

[0047] Step S344: Input the regularized regression parameter data into the regression prediction model framework for validation set performance evaluation, and generate training error analysis data; judge the fitting quality of the training error analysis data, and when the error threshold requirement is met, output the optical storage device driver board detection model.

[0048] This invention introduces a mathematically clear regression prediction model expression. This ensures the model has good interpretability and formal consistency, facilitating deployment on different platforms and subsequent maintenance. Each regression coefficient... Rather than input variables One-to-one correspondence allows for the quantification of the impact of each stress or temperature index on the output prediction results, providing quantitative analytical support for subsequent equipment health diagnosis. Multicollinearity detection and removal eliminates highly linearly correlated variables, preventing issues such as unstable regression coefficients, abnormal amplification, or interference term shifts during model training, thus enhancing model training reliability. Linear separability assessment before modeling effectively determines whether the current data structure is suitable for linear regression methods, providing a theoretical basis for selecting regression strategies and preventing model misuse or failure. Joint modeling of multiple physical input features using multiple linear regression forms a systematic prediction model, simultaneously capturing the impact of multiple stress / temperature change trends on equipment status, achieving multi-factor collaborative prediction. Regularized regression (such as L2 regularization) retains the contribution of key features while suppressing excessive weights of individual variables, significantly reducing the model's dependence on the training set, enhancing its adaptability to unknown data, and improving model generalization performance. A validation set performance evaluation process is introduced, comparing the fitting error between training results and actual values ​​to ensure the model's performance on unseen data has engineering applicability and prediction accuracy, preventing the "overfitting trap." By comparing the training error with a preset error threshold, an output admission mechanism is established to ensure that the final output detection model has high predictive reliability and practicality, supporting its deployment and operation in actual optical storage equipment systems.

[0049] Preferably, step S4 includes the following steps:

[0050] Step S41: Calculate the thermal characteristics of RO oscillation frequency data using the photovoltaic storage device drive board detection model, extract the nonlinear drift of the oscillation frequency over time, and generate drive board temperature monitoring data.

[0051] Step S42: Use the detection model of the photovoltaic storage device driver board to perform temperature and pressure coupling subdivision calculation on the gate leakage current data, identify the leakage rate step point in the high bias period, and generate gate stress monitoring data.

[0052] Step S43: Compare the difference between the driver board temperature monitoring data and the preset driver board temperature tolerance value to generate temperature anomaly judgment result data; compare the gate stress monitoring data with the preset stress tolerance curve by segment mapping to generate gate voltage degradation degree judgment data.

[0053] Step S44: Logically fuse the temperature anomaly judgment data and the gate voltage degradation degree judgment data to generate a hardware health alarm signal; when the hardware health alarm signal is activated, determine the current system power status; if the system is running under high load, trigger load reduction protection control; if the system is in a critical abnormal section, trigger soft shutdown control and generate equipment protection execution instructions.

[0054] This invention effectively captures the nonlinear drift of the oscillation frequency over time by calculating the thermal characteristics based on the RO oscillation frequency, meticulously reflecting the dynamic changes in local temperature of the driver board, overcoming the problems of slow response and low spatial resolution of traditional temperature sensors. Temperature and voltage coupling analysis is performed on the gate leakage current data to accurately identify the leakage rate step point during high bias periods, revealing hidden gate electrical stress mutations and effectively monitoring potential local breakdown risks and aging trends. Sensitive identification of temperature anomalies is achieved by comparing the difference between the driver board temperature monitoring data and the preset temperature tolerance value; simultaneously, gate stress monitoring data is combined with stress tolerance curves for segmented mapping to accurately assess the degree of gate voltage degradation, ensuring the scientific rigor and detail of anomaly judgment. The combined results of temperature anomaly judgment and gate voltage degradation assessment form a multi-parameter fused health alarm signal, significantly improving the robustness of fault detection, reducing the risk of false alarms and missed alarms, and ensuring safe system operation. Based on the system power status when the hardware health alarm is activated, the current load condition is intelligently determined, and a hierarchical control strategy is implemented, balancing system performance and safety, rationally allocating resources, and extending equipment lifespan. During high-load operation, load descent protection is triggered to reduce thermal and electrical stress and prevent equipment damage. In critical abnormal sections, soft shutdown control is implemented to quickly cut off potential fault chains and minimize hardware damage and system crashes. This achieves a closed-loop process from data acquisition, feature extraction, anomaly detection to alarms and protection, enhancing the safety early warning and risk control capabilities during equipment operation and improving the overall system reliability and stability.

[0055] Preferably, step S41 includes the following steps:

[0056] Step S411: Obtain the thermal response coefficient of the driver board; perform time window slicing on the RO oscillation frequency data to generate oscillation frequency time-series slice data;

[0057] Step S412: Calculate the rate of change of oscillation frequency per unit time based on the oscillation frequency time-series slice data, and extract the slope data of the frequency change curve;

[0058] Step S413: Perform multi-segment fitting on the slope data of the frequency change curve, identify the abrupt change region of the fitting residual, and generate nonlinear drift interval data; use the nonlinear drift interval data to compare and analyze with the preset thermal characteristic drift reference template, and extract the thermal drift amount of the drift segment.

[0059] Step S414: Calculate the estimated temperature rise based on the thermal drift and the thermal response coefficient of the drive board, and generate the drive board temperature monitoring data.

[0060] This invention generates fine-grained time-series slice data by slicing RO oscillation frequency data into time windows, effectively capturing the dynamic changes in the driver board's oscillation frequency and achieving a sensitive response to short-term thermal fluctuations. It calculates the rate of change of oscillation frequency per unit time, quantifying the instantaneous trend of frequency change, providing a more representative dynamic indicator for subsequent thermal characteristic fitting and abnormal drift detection. A multi-segment fitting method is used to segment and model the slope data of the frequency change curve, meticulously distinguishing different thermal response stages, effectively identifying nonlinear drift phenomena in temperature changes, and avoiding the accumulation of errors from single-model fitting. By identifying abrupt change regions in the fitting residuals, the nonlinear stage of thermal drift is accurately located, enabling sensitive detection of potential thermal anomalies or rapid temperature rise intervals, improving fault early warning capabilities. Using a preset thermal characteristic drift reference template and comparing it with the nonlinear drift interval ensures that temperature estimation is based on a validated physical model, enhancing the accuracy and reproducibility of the estimation. Combined with the specific thermal response coefficient of the driver board, the thermal drift is converted into an estimated temperature rise value, achieving a quantitative mapping from frequency drift to actual temperature, facilitating subsequent health monitoring and thermal management decisions. This method can reflect the thermal status of the drive board in real time, support dynamic thermal management and early overheat warning, and ensure the safe and stable operation of photovoltaic energy storage equipment under high load and complex operating conditions.

[0061] This specification provides an FPGA-based optical storage device status monitoring system for executing the aforementioned FPGA-based optical storage device status monitoring method. The FPGA-based optical storage device status monitoring system includes:

[0062] The measurement configuration module is used to acquire FPGA structure data; based on the FPGA structure data, a ring oscillator unit is deployed in the FPGA's idle logic resource area, and a leakage current measurement channel is configured on the FPGA's programmable I / O pins to obtain leakage current measurement channel configuration data;

[0063] The gate calculation module is used to collect RO oscillation frequency data and gate leakage current data according to the leakage current measurement channel configuration data; based on the preset temperature calibration curve and voltage calibration curve, the RO oscillation frequency data and gate leakage current data are mapped and calculated to obtain local temperature and gate oxide stress indicators.

[0064] The equipment detection module is used to acquire structural data of photovoltaic and energy storage equipment; analyze the structural topology of the structural data of photovoltaic and energy storage equipment, and select the driving board area of ​​photovoltaic and energy storage equipment; construct a multivariate regression model of the driving board area of ​​photovoltaic and energy storage equipment through local temperature and gate oxidation stress index, and generate a detection model of driving board of photovoltaic and energy storage equipment.

[0065] The equipment control module is used to monitor the RO oscillation frequency data and gate leakage current data using the photovoltaic storage equipment driver board detection model to monitor the driver board temperature and gate stress indicators, and generate driver board temperature monitoring data and gate stress monitoring data. The driver board temperature monitoring data and gate stress monitoring data are compared with preset thresholds to generate a photovoltaic storage equipment hardware health alarm signal and trigger the equipment soft shutdown or load reduction protection.

[0066] The beneficial effects of this invention lie in the fact that the measurement configuration module scientifically utilizes idle logic resources of the FPGA to deploy the ring oscillator unit and intelligently configures the leakage current measurement channel, achieving efficient real-time acquisition of internal chip temperature and leakage current, thus improving the accuracy and completeness of data acquisition. The gate calculation module, based on preset temperature and voltage calibration curves, accurately maps and calculates the acquired RO oscillation frequency and leakage current data to obtain local temperature and gate oxide stress indices, providing a physical quantitative basis for equipment health assessment. The equipment detection module analyzes the structural data and topology of the photovoltaic storage device to accurately locate the driver board area, and constructs a multivariate regression model based on temperature and stress indices to achieve intelligent identification of the status of key components and early fault prediction. The equipment control module uses the driver board detection model to dynamically monitor hardware temperature and stress status, and triggers health alarms based on preset thresholds to achieve soft shutdown or load reduction protection, ensuring safe operation of the equipment under abnormal conditions and extending its service life. This achieves a closed-loop end-to-end system from internal chip physical signal acquisition to equipment-level status assessment, significantly improving the sensitivity to temperature changes and electrical stress accumulation. The multivariate physical feature fusion and model-driven method effectively reduce the false alarm rate and improve the accuracy and reliability of fault prediction. The system possesses real-time data acquisition, dynamic calculation, and intelligent judgment capabilities, enabling it to respond promptly to abnormal equipment conditions and automatically adjust operating parameters or execute protection strategies. Therefore, this invention, through FPGA-based high-precision real-time monitoring and multivariate regression modeling, effectively improves the diagnostic accuracy and intelligent early warning capabilities for temperature and stress in key areas of photovoltaic energy storage equipment, solving the problems of insufficient accuracy, real-time performance, and specificity in traditional monitoring systems. Attached Figure Description

[0067] Figure 1 This is a flowchart illustrating the steps of a FPGA-based optical storage device status monitoring method.

[0068] Figure 2 for Figure 1 A detailed flowchart illustrating the implementation steps of step S2.

[0069] Figure 3 for Figure 1 A detailed flowchart illustrating the implementation steps of step S3.

[0070] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0071] The technical method of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0072] Furthermore, the accompanying drawings are merely illustrative of the invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor methods and / or microcontroller methods.

[0073] It should be understood that although the terms "first," "second," etc., may be used herein to describe various units, these units should not be limited by these terms. These terms are used merely to distinguish one unit from another. For example, without departing from the scope of the exemplary embodiments, a first unit may be referred to as a second unit, and similarly, a second unit may be referred to as a first unit. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0074] To achieve the above objectives, please refer to Figures 1 to 3 A method for monitoring the status of optical storage devices based on FPGA, the method comprising the following steps:

[0075] Step S1: Obtain FPGA structure data; Based on the FPGA structure data, deploy a ring oscillator unit in the FPGA's idle logic resource area, and configure a leakage current measurement channel on the FPGA's programmable I / O pins to obtain leakage current measurement channel configuration data;

[0076] Step S2: Collect RO oscillation frequency data and gate leakage current data according to the leakage current measurement channel configuration data; map and calculate the RO oscillation frequency data and gate leakage current data based on the preset temperature calibration curve and voltage calibration curve respectively to obtain the local temperature and gate oxide stress index.

[0077] Step S3: Obtain structural data of the photovoltaic storage device; analyze the structural topology of the photovoltaic storage device structural data and select the driving board area of ​​the photovoltaic storage device; construct a multivariate regression model for the driving board area of ​​the photovoltaic storage device through local temperature and gate oxidation stress index to generate a detection model for the driving board of the photovoltaic storage device.

[0078] Step S4: Use the detection model of the photovoltaic storage device driver board to monitor the RO oscillation frequency data and gate leakage current data to monitor the driver board temperature and gate stress indicators, and generate driver board temperature monitoring data and gate stress monitoring data; compare the driver board temperature monitoring data and gate stress monitoring data with preset thresholds respectively, thereby generating a hardware health alarm signal for the photovoltaic storage device and triggering the device soft shutdown or load reduction protection.

[0079] This invention fully leverages the reconfigurability of the FPGA structure by dynamically deploying Ring Oscillator (RO) units and configuring leakage current measurement channels with programmable I / O pins in the idle logic resource area of ​​the FPGA. This avoids the introduction of additional sensors, saves hardware resources, and improves system integration. By simultaneously acquiring RO oscillation frequency data and gate leakage current data, and combining temperature and voltage calibration curves for dual-channel mapping calculation, high-resolution sensing of local temperature and gate oxide stress is achieved, resulting in higher accuracy and robustness compared to single-parameter monitoring schemes. The invention introduces topology analysis technology for photovoltaic storage devices, extracting the driver board area as the key monitoring object. A multivariate regression model is constructed using local physical indicators, enabling the detection model to possess structural matching and region specificity, significantly improving model adaptability and prediction accuracy. The detection model can perform real-time calculations on the acquired data, generating driver board temperature monitoring data and gate stress monitoring data, achieving continuous tracking and trend warning of hardware operating status, forming a hardware-software coupled intelligent diagnostic link. By dynamically comparing monitoring data with preset health thresholds, a health alarm signal is quickly output. Based on the health status, a soft shutdown or load reduction protection mechanism can be autonomously triggered, achieving a dynamic balance between equipment safety and power performance. During the long-term operation of photovoltaic storage equipment, the risks of localized overheating and stress concentration are easily overlooked. The microscale dynamic monitoring scheme provided by this invention can detect potential aging or breakdown hazards in advance, thereby effectively reducing the system's sudden failure rate and extending the overall service life of the equipment. Therefore, this invention, through high-precision real-time monitoring based on FPGA and multivariate regression modeling, effectively improves the diagnostic accuracy and intelligent early warning capabilities of temperature and stress in key areas of photovoltaic storage equipment, solving the problems of insufficient accuracy, real-time performance, and specificity of traditional monitoring systems.

[0080] In this embodiment of the invention, reference is made to Figure 1 The diagram shown is a flowchart illustrating the steps of an FPGA-based optical storage device status monitoring method according to the present invention. In this example, the FPGA-based optical storage device status monitoring method includes the following steps:

[0081] Step S1: Obtain FPGA structure data; Based on the FPGA structure data, deploy a ring oscillator unit in the FPGA's idle logic resource area, and configure a leakage current measurement channel on the FPGA's programmable I / O pins to obtain leakage current measurement channel configuration data;

[0082] Step S2: Collect RO oscillation frequency data and gate leakage current data according to the leakage current measurement channel configuration data; map and calculate the RO oscillation frequency data and gate leakage current data based on the preset temperature calibration curve and voltage calibration curve respectively to obtain the local temperature and gate oxide stress index.

[0083] Step S3: Obtain structural data of the photovoltaic storage device; analyze the structural topology of the photovoltaic storage device structural data and select the driving board area of ​​the photovoltaic storage device; construct a multivariate regression model for the driving board area of ​​the photovoltaic storage device through local temperature and gate oxidation stress index to generate a detection model for the driving board of the photovoltaic storage device.

[0084] Step S4: Use the detection model of the photovoltaic storage device driver board to monitor the RO oscillation frequency data and gate leakage current data to monitor the driver board temperature and gate stress indicators, and generate driver board temperature monitoring data and gate stress monitoring data; compare the driver board temperature monitoring data and gate stress monitoring data with preset thresholds respectively, thereby generating a hardware health alarm signal for the photovoltaic storage device and triggering the device soft shutdown or load reduction protection.

[0085] In this embodiment of the invention, detailed structural data of the target FPGA is acquired, including its logic cell layout, available free logic resource areas, and programmable input / output (I / O) pin distribution information. A logic resource utilization report is exported using FPGA design tools (such as Xilinx Vivado or Intel Quartus) to accurately locate unoccupied logic cell areas. Based on this, ring oscillator (RO) units are deployed within the free logic resource areas. The number and distribution of RO units should ensure coverage of the entire target detection area, typically with no fewer than 16 units to achieve sufficient spatial resolution. Simultaneously, leakage current measurement channels are configured on the FPGA's programmable I / O pins, specifically including connections to leakage current detection circuits (such as high-precision current sensors or integrated current mirror circuits). The channels must support microamp-level current acquisition with a sampling rate of no less than 1kHz to ensure real-time monitoring. After this step, leakage current measurement channel configuration data is generated, including the location and number of RO units and the corresponding I / O leakage current measurement channel mapping. The oscillation frequency of each RO unit and the gate leakage current of the corresponding leakage current measurement channel are acquired in real time using a high-speed data acquisition system. Oscillation frequency acquisition utilizes a frequency meter or an FPGA-based counter module with a resolution of 1kHz or higher. Leakage current signals are amplified by a low-noise amplifier and then sampled via an analog-to-digital converter (ADC) with a resolution of at least 16 bits. After acquisition, the RO oscillation frequency data and gate leakage current data are mapped and calculated using pre-established temperature calibration curves (RO oscillation frequency versus temperature, typically obtained through standard ambient temperature calibration, covering a range of -40℃ to 125℃ with an error within ±1℃) and voltage calibration curves (leakage current versus gate voltage, measured voltage range 0~5V with an error within ±5mV). The corresponding local temperature values ​​and gate oxide stress indices are calculated. The gate oxide stress index is derived based on the leakage current increase law, and its value reflects the aging degree of the gate oxide layer. Overall structural data of the photovoltaic storage device is acquired, including the layout of each functional module, the driver board, and its interface locations. Structural topology analysis methods (e.g., graph theory analysis based on node connection matrices) are used to identify the area where the driver board is located and its logically related areas. Based on the calculated local temperature and gate oxide stress data, corresponding sampling points within the driver board area are selected, and statistical modeling techniques such as multiple linear regression or support vector regression (SVR) are used to construct a temperature and stress detection model for the photovoltaic and energy storage device driver board. The model inputs are RO oscillation frequency and leakage current data, and the outputs are estimated driver board temperature and predicted gate oxide stress values. Historical datasets are used for model training, and the training error is controlled within 5% to ensure detection accuracy. The constructed driver board detection model is then applied to real-time monitoring. The collected RO oscillation frequency and gate leakage current data are input into the model to obtain driver board temperature monitoring data and gate stress monitoring data.The monitoring data is compared with preset safety thresholds (e.g., temperature not exceeding 85℃, stress index not exceeding 0.8). If any index exceeds the threshold, a hardware health alarm signal is immediately generated. This alarm signal triggers the photovoltaic energy storage device control system to execute safety strategies, including soft shutdown or power load reduction protection, to avoid equipment damage and safety accidents. Alarm triggering and device control are completed through standard communication protocols (such as Modbus and CAN bus), ensuring a response latency of less than 100ms, achieving efficient hardware health management.

[0086] Preferably, step S1 includes the following steps:

[0087] Step S11: Obtain FPGA structure data;

[0088] Step S12: Identify idle logic cells in the FPGA structure data and generate idle logic resource distribution map data; perform local temperature sensitive area screening processing based on the idle logic resource distribution map data to generate candidate area data for ring oscillator deployment;

[0089] Step S13: Based on the candidate region data for ring oscillator deployment, perform ring oscillator topology binding processing to generate ring oscillator cell deployment data; perform pin electrical configuration parsing on the I / O resources in the FPGA structure data to generate programmable I / O pin configuration table data;

[0090] Step S14: Select pin groups with leakage current acquisition capability according to the programmable I / O pin configuration table data to generate leakage current channel candidate pin data; perform pin multiplexing conflict detection and sampling channel binding on the leakage current channel candidate pin data to generate leakage current measurement channel configuration data.

[0091] In this embodiment of the invention, complete structural data of the target FPGA is obtained through FPGA design tools or Hardware Description Language (HDL) code parsing, covering logic cell layout, clock domain distribution, power consumption areas, and input / output pin resources. This structural data serves as the basis for subsequent deployment of ring oscillator units and leakage current measurement channels. Based on the FPGA structural data, a resource utilization analysis algorithm is used to identify all idle and unoccupied logic cells, forming an idle logic resource distribution map. Subsequently, combined with a local temperature sensitivity assessment model (e.g., based on historical thermal maps or simulated thermal models), temperature-sensitive areas are screened in the idle logic resource regions to extract candidate regions suitable for deploying ring oscillators. These regions must ensure good temperature response characteristics and balanced spatial distribution to avoid monitoring errors caused by thermal coupling. Based on the candidate region data, ring oscillator topology binding processing is performed, i.e., multiple ring oscillator units are deployed in the candidate regions, and their logical connections and timing relationships are determined to ensure stable and independent oscillation signals. This process generates detailed ring oscillator unit deployment data, including the specific logic location and topology of each oscillator. Simultaneously, the electrical characteristics of the input / output resources (I / O) in the FPGA structure data are analyzed to obtain the electrical parameters, supported functions, and maximum carrying capacity of the pins, generating comprehensive programmable I / O pin configuration table data. Based on the I / O pin configuration table data, pin combinations with leakage current acquisition capabilities are selected, considering signal integrity, sampling accuracy, and the physical layout of the pins, generating candidate pin data for leakage current channels. Subsequently, pin reuse conflict detection is performed on these candidate pins to avoid sampling interference caused by resource contention. At the same time, the candidate pins are bound to the leakage current sampling channels, finally generating leakage current measurement channel configuration data for real-time leakage current sampling.

[0092] Preferably, step S14, which involves pin multiplexing conflict detection and sampling channel binding for candidate pin data of the leakage current channel, includes:

[0093] The candidate pin data of the leakage current channel is retrieved from the function multiplexing table to generate pin multiplexing conflict mapping data.

[0094] Priority conflict elimination is performed on the pin multiplexing conflict mapping data to generate conflict-free pin candidate data;

[0095] Based on the candidate data of conflict-free pins, the internal sampling logic structure of the FPGA is evaluated for resource adaptation, and sampling channel mapping matching data is generated.

[0096] The sampling bandwidth is filtered and the frequency response is verified on the sampling channel mapping matching data to generate the binding pin data that meets the bandwidth requirements;

[0097] Based on the bandwidth-compliant bound pin data, the sampling channel address index is encoded to generate leakage current measurement channel configuration data.

[0098] In this embodiment of the invention, the candidate pin data for leakage current channels is retrieved using a function multiplexing table. This function multiplexing table records the various functions performed by all pins of the FPGA (such as general-purpose I / O, analog input, clock input, etc.). By querying the function multiplexing table, pin multiplexing conflict mapping data is generated to determine whether each candidate pin has multiplexing conflicts with other functions or modules. Next, priority conflict elimination processing is performed on the pin multiplexing conflict mapping data. This processing is based on preset priority rules, such as real-time sampling functions having higher priority than non-critical communication functions, eliminating all pins that cause resource contention and signal interference, and filtering out conflict-free pin candidate data without multiplexing conflicts. Subsequently, based on the conflict-free pin candidate data, resource adaptation evaluation is performed on the internal sampling logic structure of the FPGA. Specifically, this includes the available resources of the sampling control unit, the number of sampling channels, the internal bus bandwidth, and the sampling triggering mechanism, evaluating the compatibility between pins and sampling logic, generating sampling channel mapping matching data, and determining the sampling channel number and resource allocation corresponding to each pin. Furthermore, sampling bandwidth filtering and frequency response verification are performed on the sampling channel mapping matching data. By simulating and verifying the sampling frequency range, bandwidth limitations, and timing characteristics of the sampling channels, binding relationships that do not meet the sampling bandwidth or response frequency requirements are eliminated, ultimately determining the binding pin data that meets the bandwidth and frequency response requirements. Finally, based on the binding pin data that meets the bandwidth requirements, sampling channel address index encoding is performed. The sampling channel address, pin number, and configuration parameters corresponding to each binding pin are uniformly encoded into a standardized configuration format to generate complete leakage current measurement channel configuration data for use by the sampling controller and data acquisition system.

[0099] As an example of the present invention, reference is made to Figure 2 As shown, step S2 in this example includes:

[0100] Step S21: Bind the sampling task to the leakage current measurement channel configuration data to generate RO oscillation frequency sampling configuration data; perform data acquisition operation on the RO oscillation frequency sampling configuration data to generate RO oscillation frequency data;

[0101] Step S22: Perform leakage current channel activation and voltage scan control on the leakage current measurement channel configuration data to generate raw gate leakage current acquisition data;

[0102] Step S23: Perform frequency matching calculation on the preset temperature calibration curve based on the RO oscillation frequency data to generate local temperature data;

[0103] Step S24: Perform multi-segment conduction fitting on the preset voltage calibration curve based on the original gate leakage current acquisition data to generate gate oxide stress index data.

[0104] In this embodiment of the invention, based on the leakage current measurement channel configuration data established in the previous steps, sampling tasks are assigned and sampling frequencies are set for each channel. Specifically, this includes binding the RO oscillator output signal to the counter module inside the FPGA, setting a sampling period (e.g., 1ms) and a data recording window (no less than 10 sampling points) for each oscillator. The sampling task is implemented through the FPGA on-chip resource scheduling logic. The task scheduling table should clearly define the sampling channel address and buffer index corresponding to each RO unit, generating RO oscillation frequency sampling configuration data. Subsequently, parallel sampling operations are performed on this configuration data, periodically reading the number of oscillations (in Hz) per unit time of each oscillator and outputting it to the main control processing unit to form complete RO oscillation frequency data. This data has timestamp and location index information, facilitating subsequent spatial temperature reconstruction. Initialization and control processes are performed on the leakage current channel configuration data, including channel power-on, bias voltage setting, and leakage current activation window selection. The configuration process involves the main control logic controlling the voltage source module to sequentially apply different voltage scan values ​​to the I / O pins (e.g., increasing in multiple segments from 0.5V to 3.3V). At each voltage step, the leakage current response on the current I / O channel is acquired. The current signal is sampled and converted into a digital quantity via an analog-to-digital converter. The sampling accuracy must meet nanoampere-level resolution. To suppress noise, the raw acquisition data should include the average and variance statistics of multiple samples, forming complete raw gate leakage current acquisition data. The data format includes a sequence of current values ​​for each channel at each voltage step. The obtained RO oscillation frequency data is mapped and solved using a preset temperature calibration curve. This calibration curve, based on experimental results, typically consists of RO frequency response curves under multiple temperature conditions and can be expressed as: ,in This represents the inverse function mapping from frequency to temperature. Mapping methods can employ table lookup, linear interpolation, or high-order polynomial fitting. The corresponding temperature value is found based on the frequency data of each oscillator, generating local temperature data with an accuracy of ±1℃. Simultaneously, frequency drift trends are considered, and temperature change rate indices are superimposed to predict the evolution trend of hot spots in key areas. Based on the raw gate leakage current data, a multi-segment conduction model is fitted to the preset voltage-current calibration curve to extract oxidation stress behavior. The calibration model can employ an exponential breakdown model or a subthreshold leakage current fitting model: I_leak = A·exp(B·V_gate). By fitting the leakage current change rate under different voltages, the slope and inflection point of current growth are extracted, thereby defining gate oxidation stress indices, including stress aggravation factors and degradation slope factors. If the leakage current slope of a certain channel significantly exceeds the calibration reference value (e.g., higher than the 3σ standard range), it can be identified as a potential oxidation aging region.

[0105] Preferably, step S24 includes the following steps:

[0106] Step S241: Divide the raw gate leakage current data into voltage segments to generate multiple voltage region data, including subthreshold region division, linear region division and saturation region division.

[0107] Step S242: Based on the data of multiple voltage regions, perform linear and exponential regression fitting on the leakage current response in each region to generate region conduction slope fitting data.

[0108] Step S243: Calculate the slope offset of the region conduction slope fitting data to obtain conduction characteristic offset data;

[0109] Step S244: Weight the weights of different voltage segments according to the conduction characteristic offset data to generate the gate oxide stress factor; normalize the gate oxide stress factor and add temperature sensitivity correction parameters to generate the final gate oxide stress index data.

[0110] In this embodiment of the invention, the raw gate leakage current data is processed by voltage segmentation. Specifically, the applied voltage is divided into three regions according to the typical conduction range of a MOSFET: subthreshold region (typically less than 0.7V), linear region (between the threshold and saturation critical voltage, approximately 0.7V to 1.5V), and saturation region (greater than 1.5V). During segmentation, the sampling points corresponding to each voltage segment are labeled to generate multi-segment voltage region data, which serves as the basic input for subsequent fitting and feature extraction. Based on the multi-segment voltage region data, mathematical modeling and fitting are performed on the leakage current response data within each voltage segment. For the subthreshold region, an exponential fitting model is used (a typical model is shown in Figure 1). The breakdown trend of subthreshold current is captured; in the linear and saturation regions, a linear regression model is used to fit the leakage current-voltage relationship and extract the current growth slope. The fitting results for each voltage segment are expressed as slope, fitting coefficient (R²), and deviation error, ultimately generating regional conduction slope fitting data. Based on the deviation between the fitted slope and the system calibration reference slope (usually derived from the initial factory or standard operating condition curve), the conduction characteristic deviation data for each voltage segment is calculated. This data is expressed as "slope deviation" or "percentage change rate," for example: ;in For the first Offset factor of voltage segment region The measured slope The standard slope is used. Based on the conduction offset factor of each voltage segment, combined with preset segment sensitivity weights (e.g., the subthreshold region has a higher weight because it is more sensitive to aging and oxidation stress), a weighted accumulation is performed to form a comprehensive stress intensity factor, namely the gate oxide stress factor. The weights can be set to W1:W2:W3=0.5:0.3:0.2, corresponding to the subthreshold region, linear region, and saturation region, respectively. Then, the obtained factor is normalized (mapped to the range of 0~1), and a sensitivity correction coefficient based on local temperature data is added (e.g., the stress factor increases exponentially with increasing temperature) to form the final gate oxide stress index data. This index comprehensively reflects the degree of oxidation degradation of the device under the current operating environment, providing key input for subsequent health status judgment and protection mechanism triggering.

[0111] As an example of the present invention, reference is made to Figure 3 As shown, step S3 in this example includes:

[0112] Step S31: Obtain structural data of the photovoltaic storage device;

[0113] Step S32: Extract the topology of the photovoltaic storage device structure data to identify the connection relationship and logical distribution between components and generate structural topology map data; filter the spatial location area of ​​the photovoltaic storage device driver board based on the structural topology map data to obtain driver board area identification data;

[0114] Step S33: Map the local temperature and gate oxide stress index to the driver board area identification data to generate driver board local stress response data; perform multivariate feature correlation screening on the driver board local stress response data using the mutual information method to generate the model training input dataset;

[0115] Step S34: Use the input dataset for model training to train a multivariate regression model and generate a detection model for the optical storage device driver board.

[0116] In this embodiment of the invention, structural data of the photovoltaic storage device is acquired. This structural data can originate from CAD drawings during the design phase, the equipment manufacturing BOM system, or be extracted using 3D structural scanning technology. This data should include spatial layout information, material parameters, and interface connection methods of the internal components (such as inverters, inductors, capacitors, driver boards, control modules, etc.), providing a foundation for subsequent structural topology extraction and region positioning. Based on the structural data extracted in step S31, structural topology analysis is performed. Specifically, a graph model is established for the structural components, where nodes represent component units and edges represent their physical or electrical connections, generating structural topology graph data. Graph theory algorithms (such as adjacency matrix analysis and DFS depth search) are used to identify the logical connection paths and spatial hierarchy relationships of the target components. The region where the driver board is located is locked in the topology graph. The location region of the driver board is filtered out by combining spatial location information and electrical connection paths, generating driver board region identification data, which will be used for subsequent stress index mapping. Local temperature data and gate oxide stress index data (e.g., based on the results calculated in step S24) from the FPGA analysis stage are mapped to the driver board region. Mapping can be based on component number, location coordinates (e.g., 2D / 3D point cloud matching), timestamp alignment, etc. Local stress response data of the drive board is generated through mapping operations, including spatiotemporal characteristics such as temperature evolution, stress intensity, and fluctuation frequency at each measuring point within a specific time period. Subsequently, mutual information analysis is used to select features from this response data, i.e., calculating the information gain value between each feature and the target health state, and selecting the most representative multivariate features (e.g., abrupt change slope, temperature rise slope, stress accumulation intensity, etc.), ultimately constructing the model training input dataset. A multivariate regression model is trained using the generated dataset. Training methods can include support ridge regression, Lasso regression, partial least squares regression (PLSR), etc., to construct a drive board detection model that can effectively map "local temperature + oxidative stress → drive board health state". Cross-validation strategies can be added during training to improve the model's generalization ability. The final output detection model can not only predict the current state of the drive board but also has a certain trend prediction capability.

[0117] Preferably, step S34 includes the following steps:

[0118] Step S341: Obtain the regression prediction model framework, wherein the mathematical formula of the regression prediction model framework is as follows:

[0119] ;

[0120] In the formula, These are the model's predicted values. This is the constant offset of the model's output when all input variables are 0. The number of input variables involved in the modeling. For the first The regression coefficients of each input feature. For the first The actual values ​​of each input feature;

[0121] Step S342: Perform feature multicollinearity detection on the model training input dataset, filter out highly collinear features, and generate redundant training data; evaluate linear separability based on the redundant training data, and generate a model regression applicability analysis report;

[0122] Step S343: Perform multivariate regression modeling calculations on the redundant training data to generate an initial regression coefficient matrix; perform regularization processing on the initial regression coefficient matrix to suppress model overfitting and generate regularized regression parameter data;

[0123] Step S344: Input the regularized regression parameter data into the regression prediction model framework for validation set performance evaluation, and generate training error analysis data; judge the fitting quality of the training error analysis data, and when the error threshold requirement is met, output the optical storage device driver board detection model.

[0124] In this embodiment of the invention, a regression prediction model framework is selected as the basic form for constructing the detection model of the photovoltaic storage device driver board. This framework adopts a classic multiple linear regression structure, and its mathematical expression is: In the formula, These are the model's predicted values. This is the constant offset of the model's output when all input variables are 0. The number of input variables involved in the modeling. For the first The regression coefficients of each input feature. For the first The actual values ​​of each input feature are considered. This regression framework has good interpretability and is suitable for engineering modeling needs with physical traceability. The linear dependencies between features are analyzed using methods such as variance inflation factor (VIF) and feature correlation matrices (e.g., Pearson correlation coefficient matrix). If strong collinearity exists between certain features (e.g., VIF > 10), it will interfere with the stability and generalization ability of the model. Such features are removed or dimensionality reduced to form redundant training data. Principal component analysis (PCA) or linear discriminant analysis (LDA) are used to examine the linear structure and projection discrimination of the training data, and a model regression suitability analysis report is generated to confirm whether the linear model can effectively fit the data distribution. The initial regression coefficient matrix (i.e., β0, β1, ..., βn) is calculated using algorithms such as least squares. To avoid overfitting under small sample or high-dimensional data conditions, L1 (Lasso) or L2 (Ridge) regularization methods are introduced to penalize the regression coefficients, generating regularized regression parameter data with stronger generalization ability. Regularization can further compress the coefficients of unimportant features to near zero, achieving implicit feature selection. The regularized model parameters are then fed into the regression model framework to perform predictions on the validation set samples. These predictions are compared with the actual output values, and metrics such as the residual sum of squares (RSS), mean squared error (MSE), and coefficient of determination (R²) are calculated to generate training error analysis data. If this error data meets the preset quality indicators (e.g., MSE < 5%, R² > 0.85), the training is considered successful, and the final output is a detection model for the optical storage device driver board capable of engineering deployment. Otherwise, the process returns to step S343 for adjustment and iterative optimization until convergence.

[0125] Preferably, step S4 includes the following steps:

[0126] Step S41: Calculate the thermal characteristics of RO oscillation frequency data using the photovoltaic storage device drive board detection model, extract the nonlinear drift of the oscillation frequency over time, and generate drive board temperature monitoring data.

[0127] Step S42: Use the detection model of the photovoltaic storage device driver board to perform temperature and pressure coupling subdivision calculation on the gate leakage current data, identify the leakage rate step point in the high bias period, and generate gate stress monitoring data.

[0128] Step S43: Compare the difference between the driver board temperature monitoring data and the preset driver board temperature tolerance value to generate temperature anomaly judgment result data; compare the gate stress monitoring data with the preset stress tolerance curve by segment mapping to generate gate voltage degradation degree judgment data.

[0129] Step S44: Logically fuse the temperature anomaly judgment data and the gate voltage degradation degree judgment data to generate a hardware health alarm signal; when the hardware health alarm signal is activated, determine the current system power status; if the system is running under high load, trigger load reduction protection control; if the system is in a critical abnormal section, trigger soft shutdown control and generate equipment protection execution instructions.

[0130] In this embodiment of the invention, the real-time acquired RO oscillation frequency data is processed using the aforementioned trained detection model for the photovoltaic storage device driver board. The following operations are performed: the RO oscillation frequency data is fitted and mapped to the thermal characteristic coefficients in the model; minute fluctuations in frequency over time are extracted using a sliding time window and nonlinear interpolation techniques; the oscillation frequency drift trend caused by localized heating of the driver board is identified based on the frequency conversion characteristics, and representative nodes in the temperature change curve are output; finally, driver board temperature monitoring data is generated, and its variation amplitude and response sensitivity are recorded in a time series. The same detection model is used to perform multi-dimensional analysis of the gate leakage current data, specifically including: cross-analyzing leakage current with voltage and temperature data to construct a temperature-pressure coupling mapping surface; focusing on the data in the high-bias operating range to identify phenomena such as sudden increases and jumps in gate leakage current; extracting these characteristic abrupt changes and quantifying them as leakage rate step values, representing the degree of stress degradation of the gate dielectric; finally, gate stress monitoring data is generated as an important reference for early warning signals of hardware degradation. Perform dual tolerance comparison and judgment: Analyze the difference between the driver board temperature monitoring data and the preset driver board temperature tolerance value (e.g., 85°C); when the actual temperature exceeds the tolerance threshold, it is marked as "abnormal," generating temperature abnormality judgment result data. Map the gate stress monitoring data to the preset stress tolerance curve; segment the data according to the curve, such as mild degradation, moderate degradation, high risk, etc.; output the corresponding gate voltage degradation degree judgment data and assign a health status level. Logically fuse the above two types of judgment results: if the temperature abnormality judgment result is "abnormal" or the gate voltage degradation degree is "moderate or above," the system generates a hardware health alarm signal; after the alarm signal is activated, the system enters the protection mode judgment stage: if the equipment is in a high-load operation state at this time (e.g., the DC bus current exceeds 80% of the rated value), the system triggers load reduction protection control, automatically reducing the load output to mitigate thermal / stress shocks; if the equipment operating parameters fall into the preset critical abnormal section (e.g., the temperature rise curve continues to rise and the load fluctuates violently), soft shutdown control is triggered to gently stop the operation process and prevent the hard fault from escalating. Finally, the device protection execution command is generated, which will be sent to the microgrid or upper control system to activate the protection mechanism, record alarm logs, and implement recovery strategies.

[0131] This specification provides an FPGA-based optical storage device status monitoring system for executing the aforementioned FPGA-based optical storage device status monitoring method. The FPGA-based optical storage device status monitoring system includes:

[0132] The measurement configuration module is used to acquire FPGA structure data; based on the FPGA structure data, a ring oscillator unit is deployed in the FPGA's idle logic resource area, and a leakage current measurement channel is configured on the FPGA's programmable I / O pins to obtain leakage current measurement channel configuration data;

[0133] The gate calculation module is used to collect RO oscillation frequency data and gate leakage current data according to the leakage current measurement channel configuration data; based on the preset temperature calibration curve and voltage calibration curve, the RO oscillation frequency data and gate leakage current data are mapped and calculated to obtain local temperature and gate oxide stress indicators.

[0134] The equipment detection module is used to acquire structural data of photovoltaic and energy storage equipment; analyze the structural topology of the structural data of photovoltaic and energy storage equipment, and select the driving board area of ​​photovoltaic and energy storage equipment; construct a multivariate regression model of the driving board area of ​​photovoltaic and energy storage equipment through local temperature and gate oxidation stress index, and generate a detection model of driving board of photovoltaic and energy storage equipment.

[0135] The equipment control module is used to monitor the RO oscillation frequency data and gate leakage current data using the photovoltaic storage equipment driver board detection model to monitor the driver board temperature and gate stress indicators, and generate driver board temperature monitoring data and gate stress monitoring data. The driver board temperature monitoring data and gate stress monitoring data are compared with preset thresholds to generate a photovoltaic storage equipment hardware health alarm signal and trigger the equipment soft shutdown or load reduction protection.

[0136] The beneficial effects of this invention lie in the fact that the measurement configuration module scientifically utilizes idle logic resources of the FPGA to deploy the ring oscillator unit and intelligently configures the leakage current measurement channel, achieving efficient real-time acquisition of internal chip temperature and leakage current, thus improving the accuracy and completeness of data acquisition. The gate calculation module, based on preset temperature and voltage calibration curves, accurately maps and calculates the acquired RO oscillation frequency and leakage current data to obtain local temperature and gate oxide stress indices, providing a physical quantitative basis for equipment health assessment. The equipment detection module analyzes the structural data and topology of the photovoltaic storage device to accurately locate the driver board area, and constructs a multivariate regression model based on temperature and stress indices to achieve intelligent identification of the status of key components and early fault prediction. The equipment control module uses the driver board detection model to dynamically monitor hardware temperature and stress status, and triggers health alarms based on preset thresholds to achieve soft shutdown or load reduction protection, ensuring safe operation of the equipment under abnormal conditions and extending its service life. This achieves a closed-loop end-to-end system from internal chip physical signal acquisition to equipment-level status assessment, significantly improving the sensitivity to temperature changes and electrical stress accumulation. The multivariate physical feature fusion and model-driven method effectively reduce the false alarm rate and improve the accuracy and reliability of fault prediction. The system possesses real-time data acquisition, dynamic calculation, and intelligent judgment capabilities, enabling it to respond promptly to abnormal equipment conditions and automatically adjust operating parameters or execute protection strategies. Therefore, this invention, through FPGA-based high-precision real-time monitoring and multivariate regression modeling, effectively improves the diagnostic accuracy and intelligent early warning capabilities for temperature and stress in key areas of photovoltaic energy storage equipment, solving the problems of insufficient accuracy, real-time performance, and specificity in traditional monitoring systems.

[0137] Therefore, the embodiments should be considered as exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of the equivalents of the application are intended to be included within the invention.

[0138] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features of the invention herein.

Claims

1. A method for monitoring the status of optical storage devices based on FPGA, characterized in that, Includes the following steps: Step S1: Obtain FPGA structure data; Based on the FPGA structure data, a ring oscillator unit is deployed in the idle logic resource area of ​​the FPGA, and a leakage current measurement channel is configured on the FPGA programmable I / O pin to obtain the leakage current measurement channel configuration data. Step S2: Collect RO oscillation frequency data and gate leakage current data according to the leakage current measurement channel configuration; map and calculate the RO oscillation frequency data and gate leakage current data based on the preset temperature calibration curve and voltage calibration curve respectively to obtain the local temperature and gate oxide stress index; wherein, step S2 includes the following steps: Step S21: Bind the sampling task to the leakage current measurement channel configuration data to generate RO oscillation frequency sampling configuration data; perform data acquisition operation on the RO oscillation frequency sampling configuration data to generate RO oscillation frequency data; Step S22: Perform leakage current channel activation and voltage scan control on the leakage current measurement channel configuration data to generate raw gate leakage current acquisition data; Step S23: Perform frequency matching calculation on the preset temperature calibration curve based on the RO oscillation frequency data to generate local temperature data; Step S24: Perform multi-segment conduction fitting on the preset voltage calibration curve based on the original gate leakage current acquisition data to generate gate oxide stress index data; Step S3: Obtain structural data of the photovoltaic-storage device; analyze the structural topology of the photovoltaic-storage device structural data and select the driving board area of ​​the photovoltaic-storage device; construct a multivariate regression model for the driving board area of ​​the photovoltaic-storage device using local temperature and gate oxidation stress indices to generate a detection model for the driving board of the photovoltaic-storage device; wherein, step S3 includes the following steps: Step S31: Obtain structural data of the photovoltaic storage device; Step S32: Extract the topology of the photovoltaic storage device structure data to identify the connection relationship and logical distribution between components and generate structural topology map data; filter the spatial location area of ​​the photovoltaic storage device driver board based on the structural topology map data to obtain driver board area identification data; Step S33: Map the local temperature and gate oxide stress index to the driver board area identification data to generate driver board local stress response data; perform multivariate feature correlation screening on the driver board local stress response data using the mutual information method to generate the model training input dataset; Step S34: Use the input dataset for model training to train a multivariate regression model and generate a detection model for the optical storage device driver board; Step S4: Use the detection model of the photovoltaic storage device driver board to monitor the RO oscillation frequency data and gate leakage current data to monitor the driver board temperature and gate stress indicators, and generate driver board temperature monitoring data and gate stress monitoring data; compare the driver board temperature monitoring data and gate stress monitoring data with preset thresholds respectively, thereby generating a hardware health alarm signal for the photovoltaic storage device and triggering the device soft shutdown or load reduction protection.

2. The FPGA-based optical storage device status monitoring method according to claim 1, characterized in that, Step S1 includes the following steps: Step S11: Obtain FPGA structure data; Step S12: Identify idle logic cells in the FPGA structure data and generate idle logic resource distribution map data; perform local temperature sensitive area screening processing based on the idle logic resource distribution map data to generate candidate area data for ring oscillator deployment; Step S13: Based on the candidate region data for ring oscillator deployment, perform ring oscillator topology binding processing to generate ring oscillator cell deployment data; perform pin electrical configuration parsing on the I / O resources in the FPGA structure data to generate programmable I / O pin configuration table data; Step S14: Select pin groups with leakage current acquisition capability based on the programmable I / O pin configuration table data to generate candidate pin data for leakage current channels; perform pin reuse conflict detection and sampling channel binding on the candidate pin data for leakage current channels to generate leakage current measurement channel configuration data.

3. The FPGA-based optical storage device status monitoring method according to claim 2, characterized in that, Step S14, which involves pin multiplexing conflict detection and sampling channel binding for candidate pin data of the leakage current channel, includes: The candidate pin data of the leakage current channel is retrieved from the function multiplexing table to generate pin multiplexing conflict mapping data. Priority conflict elimination is performed on the pin multiplexing conflict mapping data to generate conflict-free pin candidate data; Based on the candidate data of conflict-free pins, the internal sampling logic structure of the FPGA is evaluated for resource adaptation, and sampling channel mapping matching data is generated. The sampling bandwidth is filtered and the frequency response is verified on the sampling channel mapping matching data to generate the binding pin data that meets the bandwidth requirements; Based on the bandwidth-compliant bound pin data, the sampling channel address index is encoded to generate leakage current measurement channel configuration data.

4. The FPGA-based optical storage device status monitoring method according to claim 1, characterized in that, Step S24 includes the following steps: Step S241: Divide the raw gate leakage current data into voltage segments to generate multiple voltage region data, including subthreshold region division, linear region division and saturation region division. Step S242: Based on the data of multiple voltage regions, perform linear and exponential regression fitting on the leakage current response in each region to generate region conduction slope fitting data. Step S243: Calculate the slope offset of the region conduction slope fitting data to obtain conduction characteristic offset data; Step S244: Weight the weights of different voltage segments according to the conduction characteristic offset data to generate the gate oxide stress factor; normalize the gate oxide stress factor and add temperature sensitivity correction parameters to generate the final gate oxide stress index data.

5. The FPGA-based optical storage device status monitoring method according to claim 1, characterized in that, Step S34 includes the following steps: Step S341: Obtain the regression prediction model framework, wherein the mathematical formula of the regression prediction model framework is as follows: ； In the formula, These are the model's predicted values. This is the constant offset of the model's output when all input variables are 0. The number of input variables involved in the modeling. For the first The regression coefficients of each input feature. For the first The actual values ​​of each input feature; Step S342: Perform feature multicollinearity detection on the model training input dataset, filter out highly collinear features, and generate redundant training data; evaluate linear separability based on the redundant training data, and generate a model regression applicability analysis report; Step S343: Perform multivariate regression modeling calculations on the redundant training data to generate an initial regression coefficient matrix; perform regularization processing on the initial regression coefficient matrix to suppress model overfitting and generate regularized regression parameter data; Step S344: Input the regularized regression parameter data into the regression prediction model framework for validation set performance evaluation, and generate training error analysis data; judge the fitting quality of the training error analysis data, and when the error threshold requirement is met, output the optical storage device driver board detection model.

6. The FPGA-based optical storage device status monitoring method according to claim 1, characterized in that, Step S4 includes the following steps: Step S41: Calculate the thermal characteristics of RO oscillation frequency data using the photovoltaic storage device drive board detection model, extract the nonlinear drift of the oscillation frequency over time, and generate drive board temperature monitoring data. Step S42: Use the detection model of the photovoltaic storage device driver board to perform temperature and pressure coupling subdivision calculation on the gate leakage current data, identify the leakage rate step point in the high bias period, and generate gate stress monitoring data. Step S43: Compare the difference between the driver board temperature monitoring data and the preset driver board temperature tolerance value to generate temperature anomaly judgment result data; compare the gate stress monitoring data with the preset stress tolerance curve by segment mapping to generate gate voltage degradation degree judgment data. Step S44: Logically fuse the temperature anomaly judgment data and the gate voltage degradation degree judgment data to generate a hardware health alarm signal; when the hardware health alarm signal is activated, determine the current system power status; if the system is running under high load, trigger load reduction protection control; if the system is in a critical abnormal section, trigger soft shutdown control and generate equipment protection execution instructions.

7. The FPGA-based optical storage device status monitoring method according to claim 6, characterized in that, Step S41 includes the following steps: Step S411: Obtain the thermal response coefficient of the driver board; perform time window slicing on the RO oscillation frequency data to generate oscillation frequency time-series slice data; Step S412: Calculate the rate of change of oscillation frequency per unit time based on the oscillation frequency time-series slice data, and extract the slope data of the frequency change curve; Step S413: Perform multi-segment fitting on the slope data of the frequency change curve, identify the abrupt change region of the fitting residual, and generate nonlinear drift interval data; use the nonlinear drift interval data to compare and analyze with the preset thermal characteristic drift reference template, and extract the thermal drift amount of the drift segment. Step S414: Calculate the estimated temperature rise based on the thermal drift and the thermal response coefficient of the drive board, and generate the drive board temperature monitoring data.

8. A status monitoring system for optical storage devices based on FPGA, characterized in that, For executing the FPGA-based optical storage device status monitoring method as described in claim 1, the FPGA-based optical storage device status monitoring system includes: The measurement configuration module is used to acquire FPGA structure data; based on the FPGA structure data, a ring oscillator unit is deployed in the FPGA's idle logic resource area, and a leakage current measurement channel is configured on the FPGA's programmable I / O pins to obtain leakage current measurement channel configuration data; The gate calculation module is used to collect RO oscillation frequency data and gate leakage current data according to the leakage current measurement channel configuration data; based on the preset temperature calibration curve and voltage calibration curve, the RO oscillation frequency data and gate leakage current data are mapped and calculated to obtain local temperature and gate oxide stress indicators. The equipment detection module is used to acquire structural data of photovoltaic and energy storage equipment; analyze the structural topology of the structural data of photovoltaic and energy storage equipment, and select the driving board area of ​​photovoltaic and energy storage equipment; construct a multivariate regression model of the driving board area of ​​photovoltaic and energy storage equipment through local temperature and gate oxidation stress index, and generate a detection model of driving board of photovoltaic and energy storage equipment. The equipment control module is used to monitor the RO oscillation frequency data and gate leakage current data using the photovoltaic storage equipment driver board detection model to monitor the driver board temperature and gate stress indicators, and generate driver board temperature monitoring data and gate stress monitoring data. The driver board temperature monitoring data and gate stress monitoring data are compared with preset thresholds to generate a photovoltaic storage equipment hardware health alarm signal and trigger the equipment soft shutdown or load reduction protection.

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