Field effect transistor, device and manufacturing method thereof

Abstract

The invention discloses a field effect transistor, equipment and a manufacturing method of the field effect transistor, and relates to the technical field of transistors, the field effect transistor comprises a substrate, an oxide layer, a polycrystalline silicon layer, a source electrode and a drain electrode, the substrate is provided with a first groove and a second groove, the oxide layer and the polycrystalline silicon layer are sequentially stacked on the top surface of the substrate, and the source electrode and the drain electrode are arranged in the first groove. The area, located between the first groove and the second groove, of the polycrystalline silicon layer is configured to be a grid electrode, the bottom of the first groove and the bottom of the second groove are provided with a source electrode and a drain electrode respectively, the protruding portion of the substrate is arranged between the first groove and the second groove, a protruding portion is formed in the portion, between the first groove and the second groove, of the substrate, and the grid electrode is located above the protruding portion. A channel communicated with the source electrode and the drain electrode is formed in the convex part; according to the technical scheme provided by the invention, the current capacity of the channel region is improved, so that the overall performance and reliability of the transistor are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of transistor technology, particularly to a field effect transistor, device and manufacturing method and application thereof. BACKGROUND

[0002] A field effect transistor (FET) is a semiconductor device that uses the electric field effect to control the conductivity of a semiconductor material. It realizes the switching and amplification function of current by applying voltage at the gate to adjust the channel conductivity between the source and the drain. FET has high input impedance, low power consumption, fast switching speed and other advantages, and is widely used in digital circuits, analog circuits, power electronics and sensors. Common FET types include MOSFET (metal-oxide-semiconductor field effect transistor), JFET (junction field effect transistor) and MESFET (metal-semiconductor field effect transistor), which have different characteristics in structure and performance to meet the needs of different application scenarios.

[0003] Taking MOSFET as an example, in the related technology of manufacturing MOSFET devices, an oxide is usually deposited on the substrate, and etched on the oxide layer to form a trench for ion implantation to form the source and the drain, which results in a shorter path between the source and the drain, which will cause the current driving capability of the MOSFET device to be insufficient, limiting its performance in high power and high current applications. SUMMARY

[0004] The main purpose of the present application is to propose a field effect transistor, device and manufacturing method, aiming to improve the current capacity of the channel region between the source and the drain, thereby improving the overall performance and reliability of the transistor.

[0005] To achieve the above purpose, the field effect transistor proposed by the present application comprises: a substrate, the top surface of the substrate forms first and second trenches arranged at intervals; an oxide layer covering the top surface and having openings corresponding to the first and second trenches; a polysilicon layer provided on the side of the oxide layer away from the substrate, the part of the polysilicon layer between the first and second trenches constitutes a gate; a source provided on the substrate and located at the bottom of the first trench, the source metal layer is at least partially exposed outside the first trench; a drain provided on the substrate and located at the bottom of the second trench, the drain metal layer is at least partially exposed outside the second trench; The substrate forms a convex portion between the first trench and the second trench, the gate is located above the convex portion, and a channel is formed in the convex portion and connects the source and the drain.

[0006] In another embodiment, the convex portion comprises a first surface, a second surface and a third surface connected in sequence, the first surface is located in the first trench, and the third surface is located in the second trench. The channel is arranged at least partially along the side of the first surface, the second surface and the third surface away from the oxide layer.

[0007] In another embodiment, the channel is arranged along the side of the first surface, the second surface and the third surface away from the oxide layer; or The channel fills the entire area of the convex portion.

[0008] In another embodiment, the source comprises a first source doped region and a second source doped region, the drain comprises a first drain doped region and a second drain doped region, the first source doped region and the first drain doped region are filled with first doped ions, and the second source doped region and the second drain doped region are filled with second doped ions. The concentration of the second doped ions is greater than the concentration of the first doped ions. The first doped ions are P-type doped ions or N-type doped ions, and the second doped ions are P-type doped ions or N-type doped ions.

[0009] In another embodiment, the distance between the bottom of the first source doped region and the bottom of the trench is less than the distance between the bottom of the second source doped region and the bottom of the trench; and / or The distance between the bottom of the first drain doped region and the bottom of the trench is less than the distance between the bottom of the second drain doped region and the bottom of the trench.

[0010] In another embodiment, a source metal layer is arranged on the side of the source away from the substrate, a drain metal layer is arranged on the side of the drain away from the substrate, and a gate metal layer is arranged on the side of the gate away from the substrate.

[0011] In another embodiment, the polysilicon layer forms an insulating layer towards the first trench and the second trench respectively, and the insulating layer is used to electrically isolate the source, the drain and the gate. The source metal layer and the drain metal layer are both deposited on the two insulating layers.

[0012] In another embodiment, the thickness of the oxide layer is 8nm to 12nm.

[0013] The application also provides a device comprising a digital circuit or an analog circuit, wherein the digital circuit or the analog circuit comprises the field effect transistor.

[0014] The application also provides a manufacturing method of a field effect transistor, which is used for manufacturing the field effect transistor. coating photoresist on the top surface of the substrate to form a photoresist layer; etching the photoresist layer to form a first groove and a second groove, and forming a convex part between the first groove and the second groove; removing the photoresist, and depositing an oxide layer on the top surface of the substrate, in the first groove and in the second groove; opening two openings in the oxide layer respectively corresponding to the first groove and the second groove, and implanting ions into the substrate through the two openings to form a source and a drain respectively; performing secondary ion implantation on the substrate exposed in the opening area; depositing a polysilicon layer on the side of the oxide layer away from the substrate to form a gate; removing the polysilicon layer on the source and the drain; depositing an insulating layer between the sidewalls of the first groove and the second groove; depositing a metal layer on the side of the polysilicon layer away from the oxide layer; performing patterning on the metal layer to form a source metal layer, a drain metal layer and a gate metal layer.

[0015] The technical scheme of the application provides a field effect transistor, a device and a manufacturing method thereof, wherein the field effect transistor comprises a substrate, an oxide layer, a polysilicon layer, a source, a drain and a gate, the top surface of the substrate forms a first groove and a second groove arranged in an interval, the oxide layer and the polysilicon layer are arranged in sequence on the top surface of the substrate, the bottom of the first groove is provided with the source, the bottom of the second groove is provided with the drain, and the polysilicon layer between the first groove and the second groove forms the gate. Since the first groove and the second groove are directly opened in the substrate, the substrate forms a convex part protruding upward between the first groove and the second groove, the gate is arranged on the convex part, the gate applies a voltage to form a channel, when the voltage of the gate reaches a certain threshold value, the carriers (electrons or holes) on the surface of the substrate are attracted to the area below the gate to form a conductive channel, the channel is connected to the source and the drain, so that the electrons can flow from the source to the drain, and since the convex part is formed, the channel is bent, the current capacity of the channel is expanded, and the overall performance and reliability of the transistor are improved. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1Structure diagram of a first embodiment of a field effect transistor provided by the present application; Figure 2 Structure diagram of a channel in the first embodiment; Figure 3 Structure diagram of a second embodiment of a field effect transistor provided by the present application; Figure 4 Structure diagram of a channel in the first embodiment; Figure 5 Flow chart of the first step to the third step of a method for manufacturing a field effect transistor provided by the present application; Figure 6 Flow chart of the fourth step to the sixth step of a method for manufacturing a field effect transistor provided by the present application; Figure 7 Flow chart of the seventh step to the ninth step of a method for manufacturing a field effect transistor provided by the present application; Figure 8 Flow chart of the tenth step to the eleventh step of a method for manufacturing a field effect transistor provided by the present application; Figure 9 Production flow chart of the first step to the eleventh step of a method for manufacturing a field effect transistor; Figure 10 Step flow chart of a method for manufacturing a field effect transistor.

[0017] Explanation of reference numerals: 100, field effect transistor; 1, substrate; 11, protrusion; 111, first face; 112, second face; 113, third face; 12, channel; 121, first accommodating section; 122, second accommodating section; 123, third accommodating section; 1a, top face; 1a1, first groove; 1a2, second groove; 2, oxide layer; 2a, opening; 3, polysilicon layer; 31, gate; 4, source; 41, first source doped region; 42, second source doped region; 5, drain; 51, first drain doped region; 52, second drain doped region; 6, source metal layer; 7, drain metal layer; 8, gate metal layer; 9, insulating layer.

[0018] 200, photoresist; 300, oxide protection film; 400, metallization layer.

[0019] The implementation, functional features and advantages of the present application will be further explained with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0020] It should be noted that if the application embodiments involve directionality indications (such as up, down, left, right, front, back, etc.), the directionality indications are only used to explain the relative position relationship, movement, etc. between components in a certain posture, and if the certain posture changes, the directionality indications will also change accordingly.

[0021] In addition, if the application embodiments involve descriptions such as "first", "second", etc., the descriptions of "first", "second", etc. are only for description purposes and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of technical features indicated. Therefore, the features limited by "first", "second" can explicitly or implicitly include at least one of the features. In addition, "and / or" or "and / or" appearing throughout the text means that the three parallel solutions are included, for example, "A and / or B" includes A solution, or B solution, or A and B solution. In addition, the technical solutions of each embodiment can be combined with each other, but it must be based on the realization of ordinary skilled in the art, when the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, nor within the scope of protection claimed by the present application.

[0022] In the conventional MOSFET manufacturing process, a layer of oxide is first deposited on the substrate 1, and then a trench for ion implantation is etched on the oxide layer to build the source 4 and the drain 5. This process limits the path length between the source 4 and the drain 5, resulting in a too small channel 12 region. Since the channel 12 region is the key area for current flow, its small size increases the on-resistance, thereby reducing the current driving capability. This not only limits the performance of MOSFET in high power and high current applications, but also may cause the device to overheat under high load, affecting its stability and service life. In addition, the small channel 12 region also limits the voltage withstand capability of the device, making it more prone to breakdown in high voltage applications, further limiting its application range. Therefore, optimizing the design of the channel 12 region is crucial to improving the overall performance of the MOSFET.

[0023] To solve the above problems, the application provides a field effect transistor 100, which aims to improve the current capacity of the channel 12 region between the source 4 and the drain 5, thereby improving the overall performance and reliability of the transistor, Figures 1 to 9 The structural schematic diagram of an embodiment of the field effect transistor 100 provided by the application.

[0024] Please refer to Figures 1 to 9The application provides a field effect transistor 100, which comprises a substrate 1, an oxide layer 2, a polysilicon layer 3, a source electrode 4 and a drain electrode 5. The top surface 1a of the substrate 1 is provided with a first groove 1a1 and a second groove 1a2 which are arranged at intervals. The oxide layer 2 covers the top surface 1a and forms an opening 2a in the first groove 1a1 and the second groove 1a2. The polysilicon layer 3 is arranged on the side of the oxide layer 2 which is away from the substrate 1. The polysilicon layer 3 is arranged in the region between the first groove 1a1 and the second groove 1a2 and is configured as a gate electrode 31. The side of the gate electrode 31 which is away from the substrate 1 is provided with a gate metal layer 8. The source electrode 4 is arranged on the substrate 1 and is located at the bottom of the first groove 1a1. The side of the source electrode 4 which is away from the substrate 1 is provided with a source metal layer 6. The source metal layer 6 is at least partially exposed outside the first groove 1a1. The drain electrode 5 is arranged on the substrate 1 and is located at the bottom of the second groove 1a2. The side of the drain electrode 5 which is away from the substrate 1 is provided with a drain metal layer 7. The drain metal layer 7 is at least partially exposed outside the second groove 1a2. The substrate 1 comprises a convex part 11 which is located between the first groove 1a1 and the second groove 1a2. The gate electrode 31 is arranged on the convex part 11. The convex part 11 is internally provided with a channel 12 which is connected with the source electrode 4 and the drain electrode 5. The channel 12 is located below the gate electrode 31.

[0025] The application provides a field effect transistor 100, a manufacturing method and application thereof. The field effect transistor 100 comprises a substrate 1, an oxide layer 2, a polysilicon layer 3, a source electrode 4, a drain electrode 5 and a gate electrode 31. The top surface 1a of the substrate 1 is provided with a first groove 1a1 and a second groove 1a2 which are arranged at intervals. The oxide layer 2 and the polysilicon layer 3 are sequentially arranged on the top surface 1a of the substrate 1. The bottom of the first groove 1a1 is provided with the source electrode 4. The bottom of the second groove 1a2 is provided with the drain electrode 5. The polysilicon layer 3 arranged between the first groove 1a1 and the second groove 1a2 forms the gate electrode 31. The first groove 1a1 and the second groove 1a2 are directly formed on the substrate 1, so that the substrate 1 is formed with a convex part 11 which protrudes upward between the first groove 1a1 and the second groove 1a2. The gate electrode 31 is arranged on the convex part 11. When the gate electrode 31 is applied with a voltage, a channel 12 is formed. When the voltage of the gate electrode 31 reaches a certain threshold value, the carriers (electrons or holes) on the surface of the substrate 1 are attracted to the region below the gate electrode 31, so as to form a conductive channel 12. The channel 12 is connected with the source electrode 4 and the drain electrode 5, so as to ensure that the electrons can flow from the source electrode 4 to the drain electrode 5. Due to the formation of the convex part 11, the channel 12 is bent, so as to expand the current capacity of the channel 12, thereby improving the overall performance and reliability of the transistor.

[0026] It can be understood that, since the top surface 1a of the substrate 1 is etched with the first groove 1a1 and the second groove 1a2 which are arranged at intervals, the convex part 11 which is higher than the bottom of the first groove 1a1 and the second groove 1a2 is naturally formed between the first groove 1a1 and the second groove 1a2. Specifically, please refer to the following drawings. Figure 2, the convex part 11 as a whole presents a trapezoidal structure with a wide bottom and a narrow top, and the width thereof along the direction of the connecting line of the first groove 1a1 and the second groove 1a2 gradually decreases from the end close to the substrate 1 to the end away from the substrate 1. The convex part 11 is located between the first groove 1a1 and the second groove 1a2, and forms a first face 111 toward the first groove 1a1 and a third face 113 toward the second groove 1a2, and the first face 111 and the third face 113 are connected by a second face 112. It should be noted that the first face 111, the second face 112 and the third face 113 can be straight faces, inclined faces or curved faces, and the present application does not limit the same. In an embodiment of the present application, the first face 111 and the third face 113 are inclined faces, and the second face 112 is a straight face. As can be seen from the cross-sectional view of the field effect transistor 100, the cross-sectional shape of the convex part 11 as a whole presents an isosceles trapezoid, the first face 111 and the third face 113 are two sides of the isosceles trapezoid, i.e., are arranged in the form of inclined faces and are arranged at an angle with the top face 1a of the substrate 1, and the second face 112 is the upper top face 1a of the isosceles trapezoid. The side of the convex part 11 connected to the body of the substrate 1 is the lower bottom face of the isosceles trapezoid.

[0027] The present application proposes two structures of field effect transistors 100, namely NMOS tubes (N-type metal-oxide-semiconductor field effect transistors 100) and PMOS tubes (P-type metal-oxide-semiconductor field effect transistors 100). The main difference between the NMOS tube and the PMOS tube lies in their conduction type, conduction condition, current direction and application occasion. The NMOS tube is an N-type channel 12, uses a P-type substrate 1, the main carrier is an electron, is turned on by applying a positive gate 31 voltage, and the current flows from the drain 5 to the source 4. The PMOS tube is a P-type channel 12, uses an N-type substrate 1, the main carrier is a hole, is turned on by applying a negative gate 31 voltage, and the current flows from the source 4 to the drain 5.

[0028] The NMOS tube and the PMOS tube are often used in different application scenarios due to their different conduction characteristics and working principles. The NMOS tube is usually used for low-end driving, for example, in switching power supplies, motor control and reverse connection protection circuits, because it is turned on when a high level is applied to the gate 31, and is suitable for controlling the conduction between the ground. In addition, the NMOS tube is also often used in the design of logic gates in digital circuits, such as AND gates, OR gates, NOT gates, etc. The PMOS tube is more suitable for high-end driving, for example, as a pull-up load device in power management circuits, for power switching or the pull-up part in inverters. In lithium battery charging circuits, the PMOS tube is often used to control the connection between the battery and the charging power supply, to ensure the safety and stability of the charging process. In addition, the PMOS tube is also widely used in digital circuits and analog circuits, such as logic gates, memory cells, amplifiers and filters, etc.

[0029] Further, in the first embodiment proposed in the present application, the PMOS tube, that is, the P-type metal-oxide-semiconductor field effect transistor. The channel 12 is formed in the protrusion 11, and the channel 12 forms a conductive path between the source 4 and the drain 5 for electrons to pass through, since the channel 12 is generated by the voltage applied by the gate 31 to attract electrons or holes in the substrate 1, the channel 12 is arranged along the side of the protrusion 11 close to the gate 31, and is sequentially formed along the first surface 111, the second surface 112 and the third surface 113 from the source 4 to the drain 5, please further refer to Figure 2 , the channel 12 sequentially includes the first accommodation section 121, the second accommodation section 122 and the third accommodation section 123 along the direction of electron flow, the first accommodation section 121 and the third accommodation section 123 are arranged along the first surface 111 and the third surface 113 of the protrusion 11 respectively, and the second accommodation section is arranged along the second surface 112 of the protrusion 11, the multi-section channel 12 can significantly increase the length and current capacity of the channel 12. This design forms a curved channel 12 path in the protrusion 11 of the substrate 1, not only expands the transmission path of electrons or holes, thereby reducing the on-resistance and improving the current driving capability, but also enhances the voltage withstand performance of the device, making it more suitable for high-power and high-current application scenarios. In addition, the multi-section channel 12 design can also optimize the electric field distribution, reduce the electric field concentration phenomenon, and improve the stability and reliability of the device. The innovation of this structure effectively improves the overall performance of the MOSFET without increasing the device area.

[0030] In the second embodiment proposed in the present application, the NMOS tube, that is, the N-type metal-oxide-semiconductor field effect transistor 100. The channel 12 is formed in the protrusion 11, and the channel 12 forms a conductive path between the source 4 and the drain 5 for electrons to pass through, please further refer to Figure 4 , the channel 12 exists in the entire protrusion 11 region, and the channel 12 of the NMOS tube is designed to be larger than that of the PMOS tube, mainly to optimize the current driving capability and voltage withstand performance of the device. The carrier of the NMOS tube is electron, and its mobility is usually higher than that of the hole in the PMOS tube, so under the same channel 12 size, the NMOS tube can achieve higher current density. However, in order to meet the needs of high-power and high-current applications, or to achieve higher voltage withstand capability under certain process conditions, the channel 12 of the NMOS tube may be designed to be longer or wider. This design can increase the current path, reduce the on-resistance, and at the same time disperse the electric field by increasing the length of the channel 12 to improve the voltage withstand capability of the device.

[0031] In the technical solution of the present application, the formation of the source electrode 4 and the drain electrode 5 is achieved by doping in the substrate 1, usually by ion implantation process to form doping in the substrate 1. Specifically, ion implantation is performed at the bottom of the first trench 1a1 to form a doped region of the source electrode 4; ion implantation is performed at the bottom of the second trench 1a2 to form a doped region of the drain electrode 5. Annealing treatment is usually required after ion implantation. During ion implantation, high-energy ions will bombard the substrate 1, causing damage to the lattice structure of the substrate 1, and the doping ions may also be in an inactive state. Annealing treatment by high-temperature heating, on the one hand, repairs lattice damage and restores the crystal structure of the substrate 1; on the other hand, it activates the doping ions, making them enter the interstitial sites or replace the lattice positions, thereby achieving the expected electrical properties. The activated ions can enter the lattice positions of the silicon lattice and form covalent bonds with silicon atoms, thereby becoming electrically active dopant atoms. This process enables the doping ions to effectively change the conductivity of silicon and achieve the desired N-type or P-type conductivity characteristics.

[0032] It should be noted that the doping ions can be P-type doping ions or N-type doping ions, which are not limited by the present application. The selection of P-type doping ions or N-type doping ions mainly depends on the type of device and the expected conductivity characteristics. For NMOS devices, N-type doping ions (such as nitrogen ions, phosphorus ions, arsenic ions, etc.) are usually selected because these ions provide additional free electrons in the substrate 1, thereby forming an N-type conductive region suitable for applications requiring high electron mobility and fast switching speed. For PMOS devices, P-type doping ions (such as boron ions, aluminum ions, indium ions, germanium ions, etc.) are usually selected because these ions capture electrons in the substrate 1 to form holes, thereby forming a P-type conductive region suitable for applications requiring high voltage capacity and high current driving capacity. Therefore, the selection of the type of doping ions is based on the design requirements and application scenarios of the device to ensure that the device can achieve the best performance and reliability.

[0033] Further, for NMOS devices, when the substrate 1 is made of silicon carbide material (SiC), phosphorus (P) ions are selected for N-type doping because the solubility of phosphorus ions in SiC is relatively high and the doping efficiency is good. The diffusion coefficient of phosphorus ions in SiC is relatively large, which can achieve a high electrical activation rate in a short annealing time. In addition, the high solubility limit of phosphorus ions allows for lower sheet resistance at high concentration doping, which has a significant advantage in improving the conductivity of the device and reducing power consumption. Therefore, phosphorus ions are widely used in N-type doping of SiC devices to achieve high performance and high reliability of the device characteristics.

[0034] For PMOS devices, when the substrate 1 is made of silicon carbide (SiC), the P-type doping of the PMOS device usually selects aluminum (Al) as the doping ion. The main reason is that aluminum has a lower ionization energy (about 0.2 eV), compared with 0.37 eV of boron, which is more likely to produce active holes at room temperature, thereby improving the P-type doping effect. In addition, the diffusion coefficient of aluminum in SiC is low, and the diffusion range is small during high-temperature annealing, which can accurately control the distribution of the doped region and avoid abnormal diffusion problems. Aluminum can also achieve high-concentration doping, reduce resistance, and improve the conductivity of the device. At the same time, aluminum doping can significantly improve the temperature characteristics and stability of SiC devices in high-temperature environments, which is particularly important for SiC devices that require high reliability. Therefore, aluminum as a P-type doping ion has many advantages in SiC devices, which can significantly improve the performance and reliability of the device.

[0035] In another embodiment of the present application, the source 4 includes a first source doping region 41 and a second source doping region 42, and the drain 5 includes a first drain doping region 51 and a second drain doping region 52. Specifically, please further refer to Figure 1 or Figure 3 That is, the source 4 and the drain 5 each contain two doping regions, wherein the first source doping region 41 and the first drain doping region 51 are filled with a first doping ion, and the second source doping region 42 and the second drain doping region 52 are filled with a second doping ion. The design of two-time doping can optimize the electrical performance and reliability of the device. Taking the source 4 as an example, the shallow doping region (first source doping region 41) formed by the first doping can provide lower resistance, thereby reducing the contact resistance of the source 4 and the drain 5 and improving the conductivity of the device. The deep doping region (second source doping region 42) formed by the second doping can increase the doping concentration, further improve the current driving capability of the device, and also help to improve the voltage withstand performance of the device. Similarly, the drain 5 is consistent with the above principle.

[0036] In this embodiment, the design of two-time ion implantation with low concentration and high concentration is adopted, and the concentration of the second doping ion is greater than that of the first doping ion, which can optimize the performance and reliability of the device. The low-concentration first doping (shallow doping region) can form a shallower doping layer, reduce the contact resistance of the source 4 and the drain 5, and improve the conductivity of the device. The high-concentration second doping (deep doping region) provides higher doping concentration, increases the current driving capability, and also helps to improve the voltage withstand performance of the device. This design is particularly important in high-power and high-current applications, because it can not only reduce the on-resistance and power consumption, but also improve the stability and service life of the device, thereby achieving better overall performance.

[0037] To achieve electrical isolation between the source 4, drain 5 and gate 31, prevent the direct leakage of current between these areas. Polysilicon layer 3 towards the first trench 1a1 and the second trench 1a2 respectively form an insulating layer 9, the insulating layer 9 to form the source 4, drain 5 and gate 31 electrical isolation. Both sides of the first trench 1a1 sidewall is provided with an insulating layer 9, the corresponding, the second trench 1a2 both sidewalls are also provided with an insulating layer 9, the source metal layer 6 and drain metal layer 7 is set on the two insulating layer 9, with the gate 31 form insulating isolation, the bottom of the source metal layer 6 and the source 4 are connected, the bottom of the drain metal layer 7 and the drain 5 are connected, part of the structure of the source metal layer 6 and the drain metal layer 7 is exposed to the outside, so as to access the external circuit. The insulating layer 9 is usually composed of oxide (such as silicon dioxide), these materials have good insulating properties, can effectively prevent the flow of current. By forming an insulating layer 9 between the polysilicon layer 3 and the source 4, drain 5, can ensure that the gate 31 voltage can accurately control the conductivity of the channel 12, and will not be affected by the source 4 and drain 5 potential interference. In addition, the insulating layer 9 can also protect the device from the external environment, such as moisture and impurities, so as to improve the stability and reliability of the device. Can prevent short circuit between the source 4 and the drain 5, ensure the safe operation of the device.

[0038] In this application, the oxide layer 2 is generally made of silicon dioxide material, the thickness of the oxide layer 2 is mainly selected according to the performance requirements of the device and the application scene, in this embodiment, the thickness of the oxide layer 2 is greater than or equal to 8 nm and less than or equal to 12 nm. When the thickness of the oxide layer 2 is 8 nm, it is suitable for application scenarios that require higher switching speed and lower power consumption. Thinner oxide layer 2 can reduce the threshold voltage, allowing the device to be turned on at a lower gate 31 voltage, thereby improving the switching speed and saving power consumption. However, thin oxide layer 2 may increase the gate 31 leakage current, resulting in increased static power consumption. When the thickness of the oxide layer 2 is 12 nm, it is suitable for applications that require higher reliability and voltage resistance. Thicker oxide layer 2 can provide better thermodynamic stability and higher voltage resistance, reduce the electric field concentration phenomenon, improve the long-term reliability and life of the device. In addition, thick oxide layer 2 can effectively suppress the formation of interface traps, reduce defect accumulation, thereby improving the stability and reliability of the device.

[0039] The present application also proposes a device, the device includes a digital circuit or an analog circuit, the digital circuit or the analog circuit includes the field effect transistor 100 as described above, the specific structure of the field effect transistor 100 is referred to the above embodiment, since the device adopts all the technical solutions of the above-mentioned embodiments, at least has all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here.

[0040] The field effect transistor 100 can be suitable for a variety of different application scenarios, as follows: in power transmission and distribution systems, it can be used for low-voltage direct-current power supply of industrial equipment, such as small photovoltaic energy storage systems; in communication equipment and information technology systems, it can provide high-quality power supply for 5G base stations and the like; in industrial automation and control systems, it can meet the stable low-voltage direct-current power supply needs of automated production line equipment; in medical equipment and medical systems, it can provide low-noise power supply for high-precision medical equipment; in industrial robots and automation equipment, it can be used for low-voltage servo drivers of collaborative robots; in the field of consumer electronics, it can be applied to power management of smartphones and laptops to ensure long-lasting and stable power supply; in the field of automotive electronics, with the transformation of the automotive industry towards electrification and intelligentization, MOSFET devices can be used for charging and battery management systems of electric vehicles to meet the needs of high-performance and high-reliability power management.

[0041] The present application also proposes a manufacturing method of the field effect transistor 100 for manufacturing the field effect transistor 100 device as described above, which includes the following specific steps: S1: coating photoresist 200 on the top surface 1a of the substrate 1 to form a photoresist layer: in this step, first obtain the substrate 1, which can be an N-type substrate 1 or a P-type substrate 1, and the specific selection can be made according to the actual needs of the device, then coat photoresist 200 on the top surface 1a of the substrate 1, which is to prepare for the subsequent pattern transfer and etching process. Specifically, the substrate 1 is usually a semiconductor material (such as silicon) used to build the basic structure of the device. The purpose of coating photoresist 200 is to form a layer of photosensitive material on the surface of the substrate 1, which will be exposed and developed according to the pattern of the mask in the subsequent photolithography process, thereby forming the required pattern trench on the substrate 1. The coating of photoresist 200 usually adopts the spin coating method, which can ensure that the photoresist 200 is uniformly distributed on the surface of the substrate 1, forming a thin and uniform photoresist 200 film. The thickness and uniformity of the photoresist 200 are crucial to the precision and quality of the subsequent process, so the parameters in the coating process, such as the rotation speed and the viscosity of the photoresist 200, need to be strictly controlled.

[0042] S2: etching the photoresist layer to form a first trench 1a1 and a second trench 1a2, and a convex part 11 between the first trench 1a1 and the second trench 1a2: in this step, first, the pattern on the mask plate is projected onto the photoresist 200 by the photoetching machine, so that the photoresist 200 in the exposed area undergoes a chemical reaction. Next, after developing, the unexposed photoresist 200 is removed, exposing the surface of the substrate 1 in a certain area. Finally, by dry etching or wet etching, the substrate 1 material in these exposed areas is removed, forming a first trench 1a1 and a second trench 1a2 on the substrate 1. After etching is completed, the photoresist 200 is removed, exposing the area to be formed into the source electrode 4 and the drain electrode 5, preparing for the subsequent deposition of the polysilicon layer 3 and the metal layer.

[0043] Dry etching is a process that removes material in a vacuum environment using plasma or reactive gas. The specific implementation process is as follows: first, introduce the reaction gas (such as SF6, CF4, Cl2, etc.) into the vacuum chamber, and under the action of radio frequency or microwave energy, the gas is ionized into plasma. The high-energy ions and free electrons in the plasma bombard the substrate surface, causing the substrate 1 material to undergo a chemical reaction and be physically sputtered and removed. This method has high selectivity and high anisotropy, and can achieve high-precision pattern transfer, suitable for etching of complex structures such as deep trench isolation and polysilicon gate. Wet etching is a process that uses chemical solutions (such as hydrofluoric acid, nitric acid, etc.) to react with the substrate 1 material, thereby dissolving and removing the material. The specific implementation process includes: first, select the appropriate chemical solution according to the material to be etched, for example, hydrofluoric acid (HF) is commonly used to etch silicon dioxide (SiO2), while the mixed solution of nitric acid (HNO3) and phosphoric acid (H3PO4) is commonly used to etch silicon (Si). These solutions react with the substrate material to form soluble compounds, thereby removing the material. Next, immerse the substrate in the chemical solution, and control the etching rate and depth by controlling the concentration, temperature and immersion time of the solution. Wet etching generally has high isotropy, i.e. the etching rate is the same in all directions, suitable for large-area and shallow etching requirements, such as photoresist removal and shallow trench etching.

[0044] S3: removing photoresist 200, and depositing oxide layer 2 on the top surface la of substrate 1, in the first trench la1 and the second trench la2: In this step, techniques such as chemical vapor deposition (CVD) or physical vapor deposition (PVD) are usually used to achieve the deposition of oxide layer 2. The main role of oxide layer 2 is to insulate and isolate the subsequently formed polysilicon gate 31 from the substrate 1, to prevent current leakage, and to protect the substrate 1 from contamination and damage in subsequent process steps. In addition, oxide layer 2 can also improve the electrical performance of the device, for example, by controlling its thickness to adjust the capacitance characteristics between the gate 31 and the substrate 1. During deposition, the thickness and uniformity of the oxide layer 2 need to be precisely controlled to ensure the performance and reliability of the device.

[0045] S4: forming two openings 2a in the oxide layer 2 corresponding to the first trench la1 and the second trench la2 respectively, and implanting ions into the substrate 1 through the two openings 2a to form source 4 and drain 5 respectively: In this step, two openings 2a corresponding to the first trench la1 and the second trench la2 are first formed in the oxide layer 2. Through these openings 2a, ion implantation is performed on the exposed substrate 1 area to form source 4 and drain 5. During ion implantation, high-current, low-energy ion implantation equipment is usually used to ensure that the doping ions can be accurately implanted into the predetermined area. This high-concentration ion implantation helps to reduce the resistance of the source 4 and drain 5, thereby improving the conductivity of the device. In addition, the depth and concentration of ion implantation can be precisely controlled according to the design requirements of the device to optimize the performance of the device. After implantation is completed, high-temperature annealing treatment is usually required to activate the doping ions and repair the lattice damage that may occur during implantation. This process is crucial to ensure the electrical characteristics of the source 4 and drain 5, and also guarantees the overall performance and reliability of the device.

[0046] Further, during ion implantation, the window area (i.e. opening 2a) can completely remove the oxide, or retain a certain thickness of oxide (5nm to 100nm). Completely removing the oxide can allow the ions to be directly implanted into the substrate, ensuring that the concentration and distribution of the doping ions are more uniform, which is very advantageous for applications that require high doping concentration and precise control of the doping area. However, this method may cause the substrate surface to be damaged to some extent during ion implantation. In contrast, retaining a certain thickness of oxide can act as a buffer layer to reduce damage to the substrate during ion implantation, protecting the crystal structure of the substrate and thus improving the stability and reliability of the device. In addition, the retained oxide can also be used as a mask or insulating layer in subsequent processes, further optimizing the performance of the device. The choice of the above two processing methods needs to be adapted according to the actual needs of the device.

[0047] S5: Polysilicon layer 3 is deposited on the side of oxide layer 2 facing away from substrate 1 to form gate 31: In this step, polysilicon layer 3 is deposited on the side of oxide layer 2 facing away from substrate 1, i.e. the upper surface of oxide layer 2. This process is usually achieved by chemical vapor deposition (CVD) technology, in which silicon source gas is decomposed at high temperature and in a specific atmosphere and deposited on the surface of oxide layer 2 to form a uniform polysilicon film. Polysilicon layer 3 serves as gate 31 material, which mainly controls the conductivity of channel 12 between source 4 and drain 5 by applying voltage. Polysilicon has good electrical conductivity and thermal stability, can withstand high temperature process, and its conductivity can be further adjusted by doping. After deposition, polysilicon layer 3 usually needs to be patterned by photolithography and etching process to form precise gate 31 structure. Moreover, in the present manufacturing method, polysilicon is avoided as a mask for doping of source 4 and drain 5, so that the requirement of polysilicon pattern sidewall angle is not needed to be met, and the two steps of forming polysilicon as gate 31 and doping in source 4 and drain 5 regions are decoupled in process, thereby reducing the process requirement and etching difficulty.

[0048] S6: Remove polysilicon layer 3 on source 4 and drain 5: In this step, the purpose is to ensure that the source 4 and drain 5 regions are completely exposed so that a good ohmic contact can be formed on them subsequently. The specific operation usually adopts photolithography and etching technology, first defines the gate 31 region that needs to be retained on the polysilicon layer 3 by photolithography process, and then removes the polysilicon material above the source 4 and drain 5 by dry or wet etching technology. This process needs to be controlled with high precision to avoid damaging the doped region of source 4 and drain 5, while ensuring the integrity of gate 31 structure. Through this step, source 4 and drain 5 can form a low-resistance electrical connection with the metal layer deposited subsequently, thereby improving the conductivity and overall performance of the device.

[0049] S7: Deposit a metal layer on the side of polysilicon layer 3 facing away from oxide layer 2: In this step, a metal film, i.e. metallization layer 400, is deposited on the side of polysilicon layer 3 facing away from oxide layer 2. Physical vapor deposition or chemical vapor deposition technology is usually used to complete this step. Physical vapor deposition techniques, such as sputtering deposition, use physical methods to transfer metal materials from solid or liquid sources to the silicon wafer. Chemical vapor deposition technology deposits thin films on the surface of the silicon wafer through chemical reaction. The deposited metal layer is usually used to form the metal contact of source 4, drain 5 and gate 31, to ensure efficient flow of current in the device.

[0050] S8: Patterning the metal layer to form the source metal layer 6, the drain metal layer 7 and the gate metal layer 8: In this step, photoresist 200 is coated on the metal layer by photolithography technology, and the patterns of the source 4, the drain 5 and the gate 31 are transferred to the photoresist 200 by exposure and development process. Next, the metal parts not protected by the photoresist 200 are removed by dry etching or wet etching technology, so as to form the accurate source 4, the drain 5 and the gate metal layer 8. Finally, the remaining photoresist 200 is removed, and the patterning of the metal layer is completed. This process needs to be accurately controlled to ensure that the pattern of the metal layer is consistent with the design, so as to achieve high performance and reliability of the device.

[0051] The above eight steps are necessary manufacturing processes for manufacturing the field effect transistor 100 proposed in the present application, which covers the complete process from the preparation of the substrate 1 to the patterning of the metal layer. First, the photoresist 200 is coated on the top surface 1a of the substrate 1 and the first and second trenches 1a2 are formed by etching with a photolithography machine; then, the oxide layer 2 is deposited on the substrate 1 and in the trenches, and the source 4 and the drain 5 are formed at the bottom of the trenches by ion implantation. Subsequently, the polysilicon layer 3 is deposited on the oxide layer 2 to build the gate 31, and the polysilicon layer 3 above the source 4 and the drain 5 is removed to expose these areas. Finally, the metal layer is deposited on the polysilicon layer 3 and is subjected to patterning process to form the metal contacts of the source 4, the drain 5 and the gate 31. This series of steps ensures high performance and reliability of the device, which is suitable for various application scenarios.

[0052] In another embodiment of the present application, the formation of the source 4 and the drain 5 requires two ion implantations respectively, specifically, after the step S4, it further includes: performing secondary ion implantation on the substrate 1 exposed in the area of the opening 2a. First, the first ion implantation is performed to form shallow low-doped regions, which have lower doping concentration and help to reduce the resistance of the source 4 and the drain 5, while reducing the short channel 12 effect. Subsequently, a certain thickness of oxide protection film 300 is reserved at the bottom of the first trench 1a1 and the second trench 1a2, and then the second ion implantation is performed to prevent the damage of the substrate 1 caused by the second ion implantation. The second ion implantation will form deep high-doped regions, which have higher doping concentration and can further improve the conductivity of the source 4 and the drain 5. This two-time ion implantation design can optimize the doping concentration distribution, reduce the resistance of the source 4 and the drain 5, and at the same time improve the voltage resistance and reliability of the device.

[0053] In the technical solution of the present application, in order to ensure the insulation performance between the source electrode 4, the drain electrode 5 and the gate electrode 31, before the step S7, an insulation layer 9 is further formed between the source electrode 4 and the gate electrode 31, and between the drain electrode 5 and the gate electrode 31. The main advantage of such design is to prevent current leakage between the source electrode 4, the drain electrode 5 and the gate electrode 31, thereby improving the reliability and performance of the device. The insulation layer 9 can effectively isolate the electric field interference between different electrodes, and ensure that the gate electrode 31 voltage can accurately control the conductivity of the channel 12, without being disturbed by the source electrode 4 and the drain electrode 5 potential. In addition, the insulation layer 9 can also protect the device from the influence of the external environment, such as the erosion of moisture and impurities, thereby improving the stability and service life of the device.

[0054] The above description is only an exemplary embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structural transformation, direct / indirect application in other related technical fields, or direct / indirect application in other related technical fields within the technical concept of the present application, using the content of the present application specification and drawings, are all included in the patent protection scope of the present application.

Claims

1. A field effect transistor, characterized by The application relates to a substrate (1), a top surface (1a) of the substrate (1) forming first and second grooves (1a1, 1a2) arranged at intervals, an oxide layer (2) covering the top surface (1a) and having openings (2a) corresponding to the first and second grooves (1a1, 1a2), a polysilicon layer (3) arranged on the side of the oxide layer (2) away from the substrate (1), the polysilicon layer (3) being located between the first and second grooves (1a1, 1a2) and constituting a gate electrode (31), a source electrode (4) arranged on the substrate (1) and located at the bottom of the first groove (1a1), one side of the source electrode (4) being provided with a source metal layer (6), the source metal layer (6) being at least partially exposed outside the first groove (1a1), and a drain electrode (5) arranged on the substrate (1) and located at the bottom of the second groove (1a2), one side of the drain electrode (5) being provided with a drain metal layer (7), the drain metal layer (7) being at least partially exposed outside the second groove (1a2). The substrate (1) forms a convex portion (11) between the first and second grooves (1a1, 1a2), the gate electrode (31) is located above the convex portion (11), and a channel (12) is formed in the convex portion (11) and communicates with the source electrode (4) and the drain electrode (5). The convex portion (11) comprises a first surface (111), a second surface (112) and a third surface (113) connected in sequence, the first surface (111) is located in the first groove (1a1), and the third surface (113) is located in the second groove (1a2). The channel (12) is arranged at least partially on the side of the first surface (111), the second surface (112) and the third surface (113) away from the oxide layer (2). The channel (12) is arranged on the side of the first surface (111), the second surface (112) and the third surface (113) away from the oxide layer (2), or the channel (12) fills all the areas of the convex portion (11). The source electrode (4) comprises a first source doped region (41) and a second source doped region (42), the drain electrode (5) comprises a first drain doped region (51) and a second drain doped region (52), the first source doped region (41) and the first drain doped region (51) are filled with first doping ions, and the second source doped region (42) and the second drain doped region (52) are filled with second doping ions. The concentration of the second doping ions is greater than that of the first doping ions.

2. The field effect transistor of claim 1, wherein The first doping ions are P-type doping ions or N-type doping ions, and the second doping ions are P-type doping ions or N-type doping ions. The distance between the bottom of the first source doped region (41) and the bottom of the groove is smaller than the distance between the bottom of the second source doped region (42) and the bottom of the groove, and / or the distance between the bottom of the first drain doped region (51) and the bottom of the groove is smaller than the distance between the bottom of the second drain doped region (52) and the bottom of the groove.

3. The field-effect transistor as described in claim 2, characterized in that, ​ 4. The field effect transistor according to any one of claims 1 to 3, wherein ​ ​ ​ 5. The field-effect transistor as described in claim 4, characterized in that, ​ The distance between the bottom of the first drain doped region (51) and the bottom of the trench is less than the distance between the bottom of the second drain doped region (52) and the bottom of the trench.

6. The field-effect transistor as described in any one of claims 1 to 3, characterized in that, The side of the source (4) facing away from the substrate (1) is provided with a source metal layer (6), the side of the drain (5) facing away from the substrate (1) is provided with a drain metal layer (7), and the side of the gate (31) facing away from the substrate (1) is provided with a gate metal layer (8).

7. The field-effect transistor as described in any one of claims 1 to 3, characterized in that, The polysilicon layer (3) forms an insulating layer (9) towards the first trench (1a1) and the second trench (1a2) respectively, which is used to electrically isolate the source (4), the drain (5) and the gate (31); The source metal layer (6) and the drain metal layer (7) are both deposited on the two insulating layers (9).

8. The field-effect transistor as described in any one of claims 1 to 3, characterized in that, The thickness of the oxide layer (2) is 8-12 nm.

9. An apparatus, comprising: The field effect transistor according to any one of claims 1-8.

10. A method of manufacturing a field effect transistor for manufacturing a field effect transistor according to any one of claims 1 to 8, characterized in that The field effect transistor comprises: A photoresist (200) is coated on the top surface (1a) of the substrate (1) to form a photoresist layer; The photoresist layer is etched to form a first trench (1a1) and a second trench (1a2), and a convex part (11) is formed between the first trench (1a1) and the second trench (1a2); The photoresist (200) is removed, and an oxide layer (2) is deposited on the top surface (1a) of the substrate (1), in the first trench (1a1) and in the second trench (1a2); Two openings (2a) corresponding to the first trench (1a1) and the second trench (1a2) respectively are formed in the oxide layer (2), and ions are injected into the substrate (1) through the two openings (2a) to form a source (4) and a drain (5) respectively; Secondary ion implantation is performed on the substrate (1) exposed in the opening (2a) region; A polysilicon layer (3) is deposited on the side of the oxide layer (2) facing away from the substrate (1) to form a gate (31); The polysilicon layer (3) on the source (4) and the drain (5) is removed; An insulating layer (9) is deposited between the sidewalls of the first trench (1a1) and the second trench (1a2); A metal layer is deposited on the side of the polysilicon layer (3) facing away from the oxide layer (2); The metal layer is patterned to form a source metal layer (6), a drain metal layer (7) and a gate metal layer (8).

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