Storage and calculation integrated method and equipment for matrix exponentiation

Abstract

The invention discloses a storage and calculation integrated method and device for matrix exponentiation, and the method comprises the steps: inputting a to-be-exponentiated matrix A and a power k into a storage and calculation integrated circuit; an optimal operation sequence for calculating the k-th power of a matrix A to be exponentiated is determined through a dynamic programming algorithm, the optimal operation sequence is combined with a linear method and a flat method to minimize the total calculation time, and corresponding matrix multiplication operations are sequentially executed in a storage and calculation integrated circuit according to the optimal operation sequence, completing the calculation of the k-th power of the matrix A to be exponentiated to obtain a calculation result; and outputting a calculation result.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory computing, and particularly relates to a memory computing method and device for matrix power calculation. BACKGROUND

[0002] Matrix power calculation is a core operation in scientific computing and engineering applications, widely used in differential equation solving, graph neural network reasoning, quantum system simulation, and Markov chain prediction scenarios. Matrix power calculation needs to be realized through multiple matrix multiplication operations. In traditional computing architecture, large-scale matrix data needs to be moved from memory to computing units for each iteration. This process causes frequent data migration under the Von Neumann architecture, resulting in high latency and energy consumption overhead, especially for high-order matrices or high-precision scenarios, the performance bottleneck is significant.

[0003] As a new computing paradigm, memory computing (CIM) significantly reduces the data movement overhead by integrating computing functions directly into storage media, thereby improving computing efficiency and energy utilization. Memory computing technology has wide application prospects in high-performance computing, large-scale data processing, and machine learning, especially in scenarios that require frequent matrix operations.

[0004] Currently, memory computing technology mainly focuses on accelerating matrix-vector multiplication, especially in the field of neural networks and deep learning. Matrix-vector multiplication is a core operation in many machine learning algorithms, such as convolutional neural networks (CNN), where convolution operations can be decomposed into multiple matrix-vector multiplications. Memory computing significantly improves computing efficiency by directly performing these operations in storage units. However, there are relatively few acceleration schemes for matrix power calculation. Matrix power calculation has important applications in linear algebra, cryptography, and scientific computing, but existing memory computing methods do not fully support this operation, especially in scenarios that require high precision and large-scale computation.

[0005] Therefore, the existing technology lacks a method that can effectively balance computing efficiency, storage demand, and data movement cost when performing matrix power calculation in a memory computing scheme. There is an urgent need for an optimized matrix power calculation method that can fully utilize the advantages of memory computing, reduce the number of read and write operations, and reduce the total calculation time.

[0006] The above information disclosed in the background section is only intended to enhance the understanding of the background of the present application, and therefore can contain information that is not prior art known to those of ordinary skill in the art. SUMMARY

[0007] The present application provides a memory computing method and device for matrix power calculation, which uses a memory computing scheme to complete fast matrix power calculation.

[0008] The storage-computation integrated method for matrix power calculation comprises,

[0009] Input a matrix A to be powered and a power k in the storage-computation integrated circuit;

[0010] Determine the optimal operation sequence for calculating the k-th power of the matrix A to be powered by a dynamic programming algorithm, wherein the optimal operation sequence combines a linear method and a square method to minimize the total calculation time, wherein the linear method writes the matrix A to be powered into the storage-computation integrated circuit, calculates the product of the matrix A to be powered and an input matrix, and repeats the process until the required power is reached; the square method writes the matrix A to be powered into the storage-computation integrated circuit, calculates the product of the matrix A to be powered and the matrix A to be powered to obtain A², writes A² into the storage-computation integrated circuit and calculates the product of A² and A², and repeats the process until the required power is reached;

[0011] According to the optimal operation sequence, sequentially perform the corresponding matrix multiplication operations in the storage-computation integrated circuit to complete the calculation of the k-th power of the matrix A to be powered and obtain the calculation result;

[0012] Output the calculation result.

[0013] In the storage-computation integrated method for matrix power calculation, the determination of the optimal operation sequence for calculating the k-th power of the matrix A to be powered by a dynamic programming algorithm comprises,

[0014] Set the calculation time t compute and the write time t write ;

[0015] Initialize the dynamic programming array to record the minimum time cost of reaching each power;

[0016] For each power i from 2 to k, calculate the minimum time of reaching the power i by the linear method and the square method, and record the predecessor information;

[0017] When i is k, select the operation sequence corresponding to the minimum time cost.

[0018] In the storage-computation integrated method for matrix power calculation, according to the optimal operation sequence, sequentially perform the corresponding matrix multiplication operations in the storage-computation integrated circuit to complete the calculation of the k-th power of the matrix A to be powered and obtain the calculation result;

[0019] Split the matrix to be multiplied into multiple row vectors;

[0020] Calculate the multiplication of each row vector and the matrix using the storage-computation integrated circuit;

[0021] Combine the calculation results into the complete matrix multiplication result.

[0022] The method for matrix power calculation in the memory-compute integrated circuit comprises the following steps:

[0023] The matrix is stored in the memory-compute integrated circuit, the row vector is input, and the matrix-vector multiplication operation is performed.

[0024] The method for matrix power calculation in the memory-compute integrated circuit comprises the following steps:

[0025] The state dp0[i] represents the minimum time cost of the linear method when reaching the power i;

[0026] The state dp1[i] represents the minimum time cost of the linear method when reaching the power i;

[0027] For each power i, from 2 to k, the candidate time of reaching the power i by the linear method or the linear method is calculated, and the corresponding state is updated;

[0028] Finally, dp0[k] and dp1[k] are compared, the minimum one is selected as the total time cost, and the optimal operation sequence is obtained by backtracking.

[0029] The method for matrix power calculation in the memory-compute integrated circuit comprises the following steps:

[0030] An electronic device for performing a memory-compute integrated method for matrix power calculation comprises,

[0031] The memory-compute integrated circuit module is used for performing matrix multiplication operation;

[0032] The processor is connected with the memory-compute integrated circuit module, and is used for performing a dynamic programming algorithm to determine an optimal operation sequence, and controlling the memory-compute integrated circuit module to perform matrix power calculation operation according to the operation sequence.

[0033] The electronic device further comprises,

[0034] The input buffer is used for buffering the matrix row vector data to be processed;

[0035] The output buffer is used for temporarily storing the intermediate results of matrix multiplication, and merging and outputting the final results after all row vector operations are completed.

[0036] In the electronic device, the processor is further used for dynamically adjusting the optimal operation sequence according to the single matrix multiplication time consumption and the single write time consumption, so as to adapt to different application scenarios.

[0037] In the electronic device, the processor comprises a central processing unit.

[0038] Compared with the prior art, the application has the following advantages: the mixed path of the linear method and the flat method is intelligently selected by the dynamic programming algorithm, the calculation time and the write overhead are balanced, and the total time consumption and energy consumption are significantly reduced. Through row vector splitting and merging, the data transfer is reduced by using the compute-in-memory circuit, and the matrix multiplication efficiency is improved. The logic is clear, compatible with various compute-in-memory circuit architectures, and the design complexity and research and development cost are reduced. BRIEF DESCRIPTION OF DRAWINGS

[0039] Various other advantages and benefits of the present application will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are intended to only illustrate preferred embodiments of the application and are not to be considered as limiting thereof. Obviously, the drawings described below are only some embodiments of the present application, and other drawings can be obtained from these drawings without creative labor for those of ordinary skill in the art. Moreover, the same reference numerals are used to represent the same components throughout the drawings.

[0040] In the drawings:

[0041] Figure 1 A flowchart of a preferred method of compute-in-memory matrix power calculation provided for an embodiment of the present disclosure;

[0042] Figure 2 A process diagram of linear matrix power calculation based on compute-in-memory circuit provided for an embodiment of the present disclosure;

[0043] Figure 3 A process diagram of square matrix power calculation based on compute-in-memory circuit provided for an embodiment of the present disclosure;

[0044] Figure 4 A flowchart of calculating the optimal power sequence by dynamic programming algorithm provided for an embodiment of the present disclosure;

[0045] Figure 5 A result display diagram of calculating the optimal power sequence by dynamic programming algorithm provided for an embodiment of the present disclosure;

[0046] Figure 6 A flowchart of compute-in-memory matrix operation processing provided for an embodiment of the present disclosure;

[0047] Figure 7 A schematic diagram of a compute-in-memory matrix power electronic device provided for an embodiment of the present disclosure.

[0048] The present application will be further explained in conjunction with the drawings and embodiments. DETAILED DESCRIPTION

[0049] Specific embodiments of the present application will now be described in greater detail with reference to the figures. Although specific embodiments of the application are shown in the drawings, it should be understood that the application can be practiced with various forms and should not be limited to the embodiments set forth in the description. Rather, the description is meant to provide a complete disclosure of the application and to cover all modifications and alternatives of the application that come within the scope of the description.

[0050] It should be noted that certain terms have been used throughout the description and the claims to refer to particular components. As one skilled in the art will appreciate, components can be referred to by different names and can be used in accordance with a variety of protocols. The description and claims should not be limited to the specific components described herein, but should be understood as covering all components that fall within the scope of the claims. As used throughout the description and the claims, the term "comprising" is used in the sense of "including", and thus should be interpreted to cover a non-exclusive inclusion. The description and the claims should not be limited to the specific embodiments described herein, but should be understood as covering all embodiments that fall within the scope of the claims. The scope of the present application is defined by the appended claims.

[0051] In order to facilitate the understanding of the embodiments of the present application, the following will be further explained with specific examples in conjunction with the drawings, and each drawing does not constitute a limitation to the embodiments of the present application.

[0052] As shown in the figure, the storage-computation integrated method for matrix power calculation includes the following steps: Figures 1 to 7

[0053] Input the matrix A to be powered and the power k in the storage-computation integrated circuit;

[0054] Determine the optimal operation sequence for calculating the k-th power of the matrix A to be powered by a dynamic programming algorithm, wherein the optimal operation sequence combines a linear method and a square method to minimize the total calculation time. The linear method writes the matrix A to be powered into the storage-computation integrated circuit, calculates the product of the matrix A to be powered and the input matrix, and repeats the process until the desired power is reached. The square method writes the matrix A to be powered into the storage-computation integrated circuit, calculates the product of the matrix A to be powered and the matrix A to be powered to obtain A², writes A² into the storage-computation integrated circuit and calculates the product of A² and A², and repeats the process until the desired power is reached.

[0055] According to the optimal operation sequence, perform the corresponding matrix multiplication operations in the storage-computation integrated circuit in sequence to complete the calculation of the k-th power of the matrix A to be powered and obtain the calculation result.

[0056] Output the calculation result.

[0057] ​In the preferred embodiment of the storage-computation integrated method for matrix power calculation, the optimal operation sequence for calculating the k-th power of the matrix A is determined by a dynamic programming algorithm, which comprises the following steps:

[0058] Setting the calculation time t compute and the write time t write ;

[0059] Initializing a dynamic programming array to record the minimum time cost for reaching each power;

[0060] For each power i from 2 to k, calculating the minimum time for reaching the power i by the linear method and the flat method, and recording the predecessor information;

[0061] When i is k, selecting the operation sequence corresponding to the minimum time cost.

[0062] In the preferred embodiment of the storage-computation integrated method for matrix power calculation, the corresponding matrix multiplication operations are sequentially performed in the storage-computation integrated circuit according to the optimal operation sequence, which comprises the following steps:

[0063] Splitting the matrix to be multiplied into multiple row vectors;

[0064] Calculating the multiplication of each row vector and the matrix by using the storage-computation integrated circuit;

[0065] Combining the calculation results into the complete matrix multiplication result.

[0066] In the preferred embodiment of the storage-computation integrated method for matrix power calculation, the multiplication of each row vector and the matrix by using the storage-computation integrated circuit comprises the following steps:

[0067] Storing the matrix in the storage-computation integrated circuit, inputting the row vector, and performing the matrix-vector multiplication operation.

[0068] In the preferred embodiment of the storage-computation integrated method for matrix power calculation, the dynamic programming algorithm comprises the following steps:

[0069] Defining the state dp0[i] to represent the minimum time cost of the linear method for reaching the power i;

[0070] Defining the state dp1[i] to represent the minimum time cost of the flat method for reaching the power i;

[0071] For each power i from 2 to k, calculating the candidate time for reaching the power i by the linear method or the flat method, and updating the corresponding state;

[0072] Finally, comparing dp0[k] and dp1[k], selecting the minimum one as the total time cost, and backtracking to obtain the optimal operation sequence.

[0073] In the preferred embodiment of the storage-computation integrated method for matrix exponentiation, the storage-computation integrated circuit is implemented by any of the following memory units: static random access memory, dynamic random access memory, magnetic random access memory, resistive random access memory, phase change memory, or ferroelectric memory.

[0074] An electronic device 30 for performing a storage-computation integrated method for matrix exponentiation comprises,

[0075] a storage-computation integrated circuit module 10 for performing matrix multiplication operation;

[0076] a processor 20 connected to the storage-computation integrated circuit module 10 for performing a dynamic programming algorithm to determine an optimal operation sequence and controlling the storage-computation integrated circuit module to perform matrix exponentiation operation according to the operation sequence.

[0077] In the preferred embodiment of the electronic device, further comprising,

[0078] an input buffer for buffering matrix row vector data to be processed;

[0079] an output buffer for temporarily storing intermediate results of matrix multiplication and merging and outputting final results after all row vector operations are completed.

[0080] In the preferred embodiment of the electronic device, the processor is further configured to dynamically adjust the optimal operation sequence according to single matrix multiplication time consumption and single write time consumption to adapt to different application scenarios.

[0081] In the preferred embodiment of the electronic device, the processor comprises a central processing unit.

[0082] In one embodiment, as shown in Figure 1 The preferred method of storage-computation integrated matrix exponentiation is disclosed, comprising the following steps:

[0083] S100: input a matrix A to be exponentiated and an exponent k;

[0084] S200: dynamically program to calculate an optimal path, combining linear method and flat method;

[0085] S300: perform a hybrid computing strategy;

[0086] S400: output .

[0087] In this embodiment, the method combines the advantages of linear method and flat method by using dynamic programming algorithm to calculate the optimal scheme for the final exponent to be calculated, and adopts a hybrid strategy to achieve matrix high-order power calculation.

[0088] Further, Figure 2An embodiment provides a process for calculating matrix power based on a storage-computing integrated circuit linearly. The process includes:

[0089] Step 1, write matrix A;

[0090] Step 2, calculate A A, to obtain A 2 ;

[0091] Step 3, output A 2 , and write A 2 back to the storage-computing integrated circuit and continue to multiply A.

[0092] Step 4, repeat step 3, multiply the obtained result with A until the required power is obtained.

[0093] In this embodiment, the process for calculating matrix power by the linear method only needs to complete a write operation of matrix A once, but needs to complete k-1 times of calculation operations. This method is more suitable for matrix power calculation when the required power is low. The time for calculating matrix power by this method is:

[0094] t 线性法 =(k-1)t compute +t write

[0095] Wherein, t compute is the time required to complete a matrix multiplication, t write is the time required to complete a matrix write operation to the storage-computing integrated circuit, and k is the required power.

[0096] Further, Figure 3 is a process diagram for calculating matrix power based on a storage-computing integrated circuit square provided by an embodiment of the present disclosure, which includes:

[0097] Step 1. Write matrix A;

[0098] Step 2. Calculate A A, to obtain A 2 ;

[0099] Step 3. Output A², and write A² back to the storage-computing integrated circuit;

[0100] Step 4. Calculate A² A², to obtain A 4 ;

[0101] Step 5. Repeat steps 3 to 4, write the obtained result back to the storage-computing integrated circuit and multiply itself as input, until the required power is obtained.

[0102] In the present embodiment, the process of the flat method for calculating the matrix power requires multiple write operations, but significantly reduces the number of calculations compared to the linear method. The number of calculations of the method is much smaller than that of the linear method, and is more suitable for the case where the power to be calculated is high. The time for calculating the matrix power using the method is:

[0103] t 平方法 = (t compute +t write) )

[0104] where t compute is the time required to complete one matrix multiplication, t write is the time required to complete one matrix write to the storage and calculation integrated circuit, and k is the power to be calculated.

[0105] To further illustrate the respective characteristics of the linear method and the flat method and the performance when facing different calculation tasks, let t 线性法 t 平方法 , it can be obtained that:

[0106]

[0107] It should be noted that when k = 2, the denominator is zero (the time consumption of the flat method is equal to that of the linear method). When k = 1, it is meaningless (the power is at least 2). depends on the performance of the storage and calculation integrated circuit, and depends on the calculation task.

[0108] The inequality shows that the lower the write time consumption (t write is smaller), the greater the advantage of the flat method; the greater the power k, the more significant the advantage of the flat method.

[0109] In one embodiment, as shown in Figure 4 , the present disclosure provides a flowchart for calculating the optimal power sequence using a dynamic programming algorithm. Dynamic programming is an important algorithmic idea for solving optimization problems. It solves the original problem by decomposing it into multiple sub-problems, solving the sub-problems step by step, and finally combining the solutions of the sub-problems to solve the original problem.

[0110] As mentioned before, there are two basic methods for matrix power: linear method and flat method. The method of calculating the matrix power using a combination of linear method and flat method can combine the advantages of both.

[0111] The problem of solving the optimal calculation sequence of the matrix power is transformed into solving the method of the last step to reach the matrix power A i .

[0112] For example, if A i is to be obtained, the following method is considered:

[0113] Method 1 (Linear Method): Calculate A by the memory-computing integrated circuit A i-1 , where A exists in the memory-computing integrated circuit, A i-1 is input from outside. Assuming that the previous step also adopts the linear method and A is stored in the circuit, this step only needs calculation time.

[0114] Method 2 (Linear Method): Calculate A by the memory-computing integrated circuit A i-1 , where A exists in the memory-computing integrated circuit, A i-1 is input from outside. But assuming that the previous step adopts the flat method and A is stored in the circuit , the operation performed is At this time, A A i-1 needs to be rewritten, and the time required for this step is the time for writing the matrix A A i-1 plus the time for calculating A ;

[0115] Method 3 (Flat Method, i is even): Calculate A by the memory-computing integrated circuit , the time required is the time for writing the matrix A k plus the time for calculating A .

[0116] By considering these three methods step by step and recording the minimum time cost of each step, the shortest time for the final A k can be obtained. And through path backtracking, the optimal operation sequence can be obtained.

[0117] The specific steps include:

[0118] 1. Set the cost parameters: each matrix multiplication takes time , and the write operation takes time ; define state 0 as: the previous operation of the current power is obtained by the linear method; define state 1: the previous operation of the current power is obtained by the flat method.

[0119] 2. Construct the optimal path based on dynamic programming:

[0120] Initialization: let (1) = 0, (1) = ∞; (P represents the dynamic programming array of state 0, recording the minimum time cost when reaching each power; (This represents a dynamic programming array representing state 1, recording the minimum time cost to reach each power.)

[0121] Perform the following steps sequentially for i = 2…k:

[0122] Linear transfer:

[0123]

[0124]

[0125] in, This indicates that the linear method is used to obtain information from A. i-1 Arrive at A i Furthermore, the predecessor is a candidate time for state 0. This indicates that the linear method is used to obtain information from A. i-1 Arrive at A i However, the predecessor is a candidate time for state 1.

[0126] Square transition (when i is even, j= hour):

[0127] candidate = min( (j), (j))+ + , (i) = candidate;

[0128] Where, candidate represents the method of obtaining from A. j Arrive at A i The candidate time.

[0129] Meanwhile, the optimal predecessor power and state are recorded in pre_node0(i), pre_state0(i), pre_node1(i), and pre_state1(i), respectively (pre_node0(i) represents A in state 0). i The predecessor exponent index; pre_state0(i) represents A in state 0. i The predecessor state; pre_node1(i) represents A in state 1. i The predecessor power index; pre_state1(i) represents A in state 1. i (precursor state);

[0130] 3. Termination Decision: When i=k, compare... (k) and (k), take the smaller one as total_time, and determine the final state final_state;

[0131] 4. Path backtracking:

[0132] From current=k and state=final_state, backtracking in pre_nodeX, pre_stateX in reverse order to 1, obtaining node sequence path_nodes and corresponding operation type (linear method, flat method) and each step time in turn;

[0133] Figure 5 The result display diagram of calculating the optimal power sequence by using the dynamic programming algorithm is provided for an embodiment of the present disclosure. In this embodiment, t compute The time for calculating a matrix multiplication by the memory-compute integrated circuit (70ns), t write The time for writing a matrix by the memory-compute integrated circuit (490ns). The power of the matrix to be calculated is 66 (i.e., the demand A 66 ).

[0134] The optimal power sequence for calculating A 66 by using the dynamic programming algorithm is 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 32, 33, 66. In the whole process, 16 linear methods and 2 flat methods are executed, and the total time required is 2730ns. Figure 5 Meanwhile, the shortest time required for calculating all powers between A 2 and A 66 by using the dynamic programming algorithm is displayed, indicating the effectiveness of the algorithm in finding the optimal sequence for calculating the matrix power.

[0135] It should be noted that the above is only exemplary, and the specific values of t compute and may be adjusted according to the actual performance of the memory-compute integrated circuit to achieve the optimal solution of the power path.

[0136] Figure 6 A memory-compute integrated matrix operation processing flowchart is provided for an embodiment of the present disclosure. The matrix operation includes the following steps:

[0137] Matrix row vector splitting: split the matrix to be subjected to matrix multiplication into the form of multiple row vectors, and perform matrix vector multiplication step by step in multiple clock cycles.

[0138] Matrix vector multiplication by the memory-compute integrated circuit: complete the multiplication calculation of the row vector and the matrix by using the memory-compute integrated circuit.

[0139] Row vector merging: the result of the matrix vector multiplication calculated by the memory-compute integrated chip each time is used as the row vector of the matrix multiplication result. After multiple times of the above operation, the calculation of a matrix multiplication is completed.

[0140] In addition, Figure 6 Two buffers (Buffer) shown in the middle are used to optimize data flow and computational efficiency. The input buffer is responsible for storing the matrix row vector data to be processed (such as a 11 , a 12 ,..., a nn ) and sequentially transmitting the data to the compute-in-memory circuit within the appropriate clock cycle to ensure the continuity of the calculation process. The output buffer is used to temporarily store the matrix multiplication results calculated by the compute-in-memory circuit (such as a 2 11 , a 2 12 ,..., a 2 nn ) and merge the output after all row vector multiplications are completed, thereby reducing data transmission delay and improving overall operation efficiency.

[0141] The compute-in-memory circuit, as the core computing unit, integrates storage and computing functions. By working with the input buffer and the output buffer, the compute-in-memory circuit realizes efficient data reading, calculation, and result output, avoiding the additional overhead of data migration in traditional architectures, thereby significantly improving the performance and energy efficiency of matrix operations.

[0142] In this embodiment, the basic storage unit of the compute-in-memory circuit includes but is not limited to any of the following: static random access memory, dynamic random access memory, magnetic random access memory, resistive random access memory, phase change memory, and ferroelectric memory.

[0143] Figure 7 A schematic diagram of an electronic device for compute-in-memory matrix exponentiation according to an embodiment of the present disclosure is provided. The electronic device includes a compute-in-memory circuit module and a processor.

[0144] In this embodiment, the compute-in-memory circuit is connected to the processor. The compute-in-memory circuit module is used to complete the calculation of the matrix power, and the processor is used to execute the dynamic programming algorithm to calculate the optimal path (operation sequence) in the entire power calculation process according to the target power, so that the compute-in-memory circuit executes the linear method and the flat method according to the operation sequence to complete the efficient and fast matrix power calculation.

[0145] In one embodiment, a preferred method for compute-in-memory matrix exponentiation is applied to a compute-in-memory circuit. The method includes the following steps:

[0146] Input the matrix A to be exponentiated and the power k;

[0147] Calculate the optimal path using dynamic programming, and combine the linear method and the flat method;

[0148] Performing a hybrid computing strategy;

[0149] Output .

[0150] Further, the linear method comprises: writing matrix A into the storage-computing integrated circuit, and then computing A A, obtaining A 2 After that, A 2 is multiplied as input with A existing in the storage-computing integrated circuit, that is, A is written only once, and the result of each matrix multiplication is multiplied as new input with A.

[0151] The flat method comprises: writing matrix A into the storage-computing integrated circuit, and then computing A A, obtaining A 2 After that, A 2 is written into the storage-computing integrated circuit and A 2 is multiplied as input with A existing in the storage-computing integrated circuit 2 , that is, the calculation result of each matrix multiplication is written into the storage-computing integrated circuit and multiplied as new input to calculate the next round of matrix multiplication. This method needs to erase and write the storage-computing integrated circuit multiple times, but can significantly reduce the number of calculations compared with the linear method.

[0152] Further, the optimal operation sequence determined by the dynamic programming algorithm comprises:

[0153] Setting the calculation time t compute and the writing time t write ;

[0154] Initializing the dynamic programming array to record the minimum time cost of reaching each power exponent;

[0155] For each power exponent i from 2 to k, the minimum time of reaching i by the linear method and the flat method is calculated, and the predecessor information is recorded;

[0156] When i is k, the operation sequence corresponding to the minimum time cost is selected.

[0157] In addition, the present disclosure also provides a preferred computing method for completing matrix multiplication by using the storage-computing integrated technology, which comprises:

[0158] Matrix row vector splitting;

[0159] The storage-computing integrated circuit calculates the matrix vector multiplication;

[0160] Row vector merging.

[0161] Optionally, the matrix row vector splitting is to split the matrix to be subjected to matrix multiplication into the form of multiple row vectors.

[0162] Optionally, the storage-computing integrated circuit calculates the matrix vector multiplication by using the storage-computing integrated circuit to complete multiplication calculation of a row vector and a matrix.

[0163] The row vector merging, i.e., the result of the matrix vector multiplication calculated by the storage-computing integrated circuit each time, can be used as a row vector of the matrix multiplication result. Through multiple operations, the matrix multiplication calculation can be completed.

[0164] The dynamic programming algorithm determines the optimal operation path, mixes the linear method and the flat method, balances the calculation times and the write times in the matrix power calculation, reduces the total time consumption and the energy consumption, and finds the minimum time cost path from A to A k under the given power k by using the dynamic programming algorithm. According to the t compute and t write parameters, the strategy selection is dynamically adjusted, different hardware performances are adapted, unnecessary data reading and writing and repeated calculation are reduced, the overall efficiency is improved, the linear method is continuously multiplied by the original matrix A, is suitable for a low power scenario, reduces the write operation times, only needs to write A once to complete all subsequent operations, is suitable for a low power and small k situation, avoids the overhead caused by frequent erasing and writing, and the calculation process is simple and easy to control. The square operation of the flat method quickly increases the power and is suitable for a high power scenario, significantly reduces the calculation times, quickly approaches the target power by using the power doubling mechanism, although the write times are increased, the multiplication times are greatly reduced, is particularly suitable for efficiently processing large-scale matrix operations in the storage-computing integrated architecture, the matrix row vector splitting and merging mechanism improves the execution efficiency of the matrix multiplication in the storage-computing integrated circuit, splits the matrix into multiple vectors according to rows, sends the vectors into the CIM module one by one, multiplies each vector with the complete matrix, and uses the result as an output row vector to avoid the whole matrix carrying, fully utilizes the data locality advantage of the CIM, uses the storage-computing integrated circuit to perform the matrix multiplication, breaks through the Von Neumann architecture bottleneck, reduces the data carrying delay and the power consumption, directly performs the calculation in the storage unit, eliminates frequent data transmission, supports various memory types such as SRAM, MRAM, RRAM, and the like, is suitable for high-performance and low-power matrix intensive tasks, the input buffer and the output buffer are designed to optimize the data flow scheduling, improve the throughput and the calculation continuity, the input Buffer temporarily stores the row vectors to be processed, sends the row vectors to the CIM module in sequence, the output Buffer buffers the intermediate results, and outputs the results after uniform merging, effectively alleviates the data dependence and the pipeline blocking problem, the processor controls the optimal path execution to realize intelligent scheduling and path selection, improves the overall system efficiency, the processor runs the dynamic programming algorithm to generate an optimal operation sequence, controls the CIM module to perform the matrix multiplication in the specified order, and the strategy can be adjusted according to different application scenarios.

[0165] Although the embodiments of the present application have been described above with reference to the accompanying drawings, the present application is not limited to the above-described specific embodiments and areas of application, and the above-described specific embodiments are merely illustrative and instructive, but are not restrictive. Many modifications can be made by those skilled in the art under the teachings of the present specification and without departing from the scope of the present application as defined by the claims.

Claims

1. A storage-based computation method for matrix exponentiation, characterized in that, The method includes the following steps: Input the power matrix A and the power k to be calculated into the in-memory computing circuit; The optimal sequence of operations for calculating the kth power of the power matrix A is determined using a dynamic programming algorithm. This optimal sequence of operations combines a linear method and a squaring method to minimize the total computation time. The linear method involves writing the power matrix A into an in-memory computing circuit, calculating the product of the power matrix A and the input matrix, and repeating this process until the desired power is reached. The squaring method involves writing the power matrix A into an in-memory computing circuit, calculating the product of the power matrix A and the input matrix A², writing A² into the in-memory computing circuit, and calculating the product of A² and A², repeating this process until the desired power is reached. According to the optimal operation sequence, the corresponding matrix multiplication operations are executed sequentially in the in-memory computing circuit to complete the calculation of the kth power of the power matrix A to be calculated and obtain the calculation result. Output the calculation results.

2. The in-memory computation method for matrix exponentiation as described in claim 1, characterized in that, Preferably, the optimal sequence of operations for calculating the kth power of the matrix A to be raised to the power of the desired power, determined using a dynamic programming algorithm, includes: Set calculation time t compute and write time t write ; Initialize a dynamic programming array and record the minimum time cost to reach each power of 1. For each power i from 2 to k, calculate the minimum time to reach power i using the linear method and the flat method, and record the predecessor information; When i is k, select the operation sequence corresponding to the minimum time cost.

3. The in-memory computation method for matrix exponentiation as described in claim 1, characterized in that, According to the optimal operation sequence, the corresponding matrix multiplication operations are sequentially performed in the in-memory computing circuit, including... The matrix to be multiplied is split into multiple row vectors; Calculate the multiplication of each row vector with a matrix using in-memory computing circuits; The calculation results are combined into a complete matrix multiplication result.

4. The in-memory computation method for matrix exponentiation as described in claim 3, characterized in that, Calculating the multiplication of each row vector and matrix using in-memory computing circuits includes: The matrix is ​​stored in an in-memory computing circuit, and a row vector is input to perform matrix-vector multiplication.

5. The in-memory computation method for matrix exponentiation as described in claim 1, characterized in that, The dynamic programming algorithm includes the following steps: Define state dp0[i] as the minimum time cost of the previous step using the linear method when reaching power i; Define state dp1[i] as the minimum time cost of the previous step being the flat method when reaching power i; For each power i, from 2 to k, calculate the candidate time to reach power i using either the linear method or the squaring method, and update the corresponding state. Finally, dp0[k] and dp1[k] are compared, and the one with the smaller value is selected as the total time cost. The optimal operation sequence is then obtained by backtracking.

6. The in-memory computation method for matrix exponentiation as described in claim 1, characterized in that, The in-memory computing circuit is implemented using any of the following storage units: static random access memory, dynamic random access memory, magnetic random access memory, resistive random access memory, phase change memory, or ferroelectric memory.

7. An electronic device that performs the in-memory computation method for matrix exponentiation as described in any one of claims 1-6, characterized in that, It includes, In-memory computing module for performing matrix multiplication operations; The processor, connected to the in-memory computing module, is used to execute a dynamic programming algorithm to determine the optimal operation sequence and control the in-memory computing module to perform matrix exponentiation operations according to the operation sequence.

8. The electronic device as claimed in claim 7, characterized in that, It also includes, The input buffer is used to cache the matrix row vector data to be processed; The output buffer is used to temporarily store intermediate results of matrix multiplication and to merge and output the final result after all row vector operations are completed.

9. The electronic device as claimed in claim 7, characterized in that, The processor is also used to dynamically adjust the optimal operation sequence based on the time consumed by a single matrix multiplication and the time consumed by a single write operation, in order to adapt to different application scenarios.

10. The electronic device as claimed in claim 7, characterized in that, The processor includes a central processing unit.

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