Domestic PSOC mirror image partition storage and upgrading method based on secondary guidance

Abstract

The invention discloses a domestic PSOC mirror image partition storage and upgrading method based on secondary guidance, and belongs to the technical field of embedded software, the method comprises monitoring software and main control software, the monitoring software realizes online upgrading of ARM application software and FPGA application software through an ARM loading program; the main control software realizes the normal function of a product and the response of an online upgrading command, and a primary bootstrap program in the main control software is driven by bottom hardware to complete the initialization of basic hardware and the moving execution of a secondary bootstrap program; the second-level bootstrap program completes bootstrap starting of the ARM application software and the FPGA application software from different FLASH partitions, and the ARM application software and the FPGA application software complete product normal functions and response to online upgrading commands. According to the method, the workload of software development and maintenance is reduced, the reliability and safety of the system are improved, and the risks of mistaken updating and updating missing in software configuration item management are solved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of embedded software, and particularly relates to a domestic PSOC image partition storage and upgrading method based on secondary booting. BACKGROUND

[0002] The domestic PSOC full programmable chip represented by Shanghai Fudan Microelectronics integrates a high-performance processor system SOC with rich functions and FPGA programmable logic. Compared with the traditional CPU plus FPGA two-chip solution, the full programmable PSOC integrates CPU and FPGA programmable logic on one chip, greatly improves system performance and IO bandwidth, shortens development cycle, and saves production cost. For example, patent CN118132123B discloses an application software online upgrading and secure booting method. The chip's image.bin file is generated by a boot program (FSBL), ARM application software and FPGA application software in a three-in-one manner. The ARM application software and the FPGA application software belong to different configuration items, which are synthesized into one image file and fixed in the CPU. However, there are the following problems: 1) The ARM application software and the FPGA application software are coupled together, which leads to the fact that any change in the configuration item must re-synthesize a new image file. When the software of an external factory is upgraded, all configuration items must be updated once. Even if the configuration item is not changed, there is a certain risk in technical state management, and there is a problem of mis-update or missed-update of the configuration item; 2) Due to the FPGA hardware characteristics and the compilation process, the FPGA generated image file is usually large, which leads to a large final synthesized image file. Due to the limitation of the baud rate and load capacity of the online upgrading bus, the online upgrading time of the ARM application software is too long. Patent CN118276907A discloses a software online upgrading system based on a Zynq chip, which realizes online upgrading of FPGA software and ARM software respectively. However, when the FPGA software is upgraded by using this method, additional FPGA monitoring software needs to be designed, and the upgrading command needs to be interacted with the ARM software, which increases the software development and maintenance workload and the software design complexity, and reduces the system reliability and security. SUMMARY

[0003] In view of the above deficiencies in the prior art, the application provides a domestic PSOC image partition storage and upgrading method based on secondary boot, which realizes partition storage and independent online upgrading of ARM application software and FPGA application software through ARM loading software, and has simple monitoring software, reduced software development and maintenance workload, improved system reliability and safety, solved the risk of false updating and missed updating in software configuration item management, improved online upgrading efficiency of the ARM application software, and added image file identification, image integrity detection and post-updating software verification functions in the online software upgrading process, thereby preventing products from becoming bricks due to abnormal upgrading, and having high reliability and robustness.

[0004] To achieve the above-mentioned application purposes, the application adopts the technical scheme of a domestic PSOC image partition storage and upgrading method based on secondary boot, which comprises monitoring software and main control software, the monitoring software comprises a boot program and an ARM loading program, the main control software comprises a primary boot program, a secondary boot program, ARM application software and FPGA application software, and specifically comprises the following steps: S1: after the product is powered on, the boot program of the monitoring software is executed, the boot program obtains the software online upgrading identifier from the product off-chip FLASH, and judges whether the synchronization header and the checksum of the obtained data are correct, if yes, step S2 is executed, otherwise, step S9 is executed; S2: it is judged whether the online upgrading identifier is AA55AA55H, if yes, step S3 is executed, otherwise, step S9 is executed; S3: the ARM loading program in the monitoring software is executed, the ARM loading program receives the execution upgrading command and the image file information sent by the test equipment through the RS-422A bus, if the execution upgrading command is valid, step S4 is entered, otherwise, step S3 is repeatedly executed; S4: the image file data receiving operation is executed, when the first frame of image file information is received, it is judged whether the software image ID and the software image name in the first 16 bytes of the frame information are consistent with the ARM application software, if yes, the FLASH erasing base address FLASH_BASE_ADDR is updated to FLASH_ADDR1, and step S6 is executed, otherwise, step S5 is executed; S5: it is judged whether the software image ID and the software image name in the first 16 bytes of the first frame of image file information are consistent with the FPGA application software, if yes, the FLASH erasing base address FLASH_BASE_ADDR is updated to FLASH_ADDR2, and step S6 is executed, otherwise, the image file error is reported, and step S3 is re-executed; S6: Continue to receive mirror file information of subsequent frames, and perform verification calculation on the received complete mirror file information. If the mirror file passes the verification, proceed to step S7; otherwise, report the transmission failure and re-execute step S3. S7: Calculate the number of FLASH sectors to be erased based on the length information of the received image file, and start the FLASH sector erasure operation from the base address FLASH_BASE_ADDR. At the same time, set the image erasure flag to 1. After the FLASH sector erasure is completed, write the received image data into the corresponding FLASH partition, then read back the image data from the FLASH partition and compare it with the image data received through the RS-422A bus. If the two are consistent, the image verification is determined to be successful and step S8 is executed. Otherwise, the image verification is reported as failed and step S3 is re-executed. S8: Set the image erase flag to 0, perform CPU software reset operation, and the program jumps to the first-level boot program of the main control software; S9: Execute the first-level boot program in the main control software. The first-level boot program completes the initialization of basic hardware information and the transfer and execution of the second-level boot program, and then executes step S10. S10: Execute the secondary boot program in the main control software, obtain the FPGA application software image data in the main control software from the FLASH base address FLASH_ADDR2, run the FPGA application program, and continue to execute step S11; S11: Execute the secondary boot program in the main control software, obtain the ARM application software image data in the main control software from the FLASH base address FLASH_ADDR1, run the ARM application, and continue to execute S12; S12: Execute the ARM application to perform normal mode tasks. In the ARM application, determine in real time whether a valid online upgrade command has been received. If a valid online upgrade command has been received, set the online upgrade flag to AA55AA55H and execute step S13; otherwise, execute step S14. S13: Package the online upgrade identifier, add a synchronization header and checksum during the packaging process, write the packaged online upgrade identifier into the FLASH partition, and perform a CPU software reset operation. The program then jumps to the monitoring software's boot program and runs. S14: The ARM application software determines in real time whether a valid clear upgrade flag command has been received and whether the image erase flag is 0. If both the valid clear upgrade flag command and the image erase flag are 0, the online upgrade flag stored in the FLASH partition is cleared, realizing the storage and upgrade of the domestic PSOC image partition based on secondary boot. Otherwise, step S12 is repeated.

[0005] Furthermore, the method for determining the validity of the upgrade command is as follows: the upgrade command changes from invalid 0 to valid 1, and the valid 1 lasts for at least 45ms; The first 16 bytes of the image file information contain the software image ID and the software image name. The image ID for the ARM application software is 50035H and the image name is ARM.bin. The image ID for the FPGA application software is 40032H and the image name is FPGA.bin.

[0006] Furthermore, the verification calculation method is CRC cyclic redundancy check.

[0007] Furthermore, the method for determining the validity of the online upgrade command is as follows: if the received online upgrade command changes from invalid 0 to valid 1, and the valid 1 lasts for at least 45ms, then the online upgrade command is considered to have been received; otherwise, the online upgrade command is considered not to have been received.

[0008] Furthermore, the method for determining the validity of the clear upgrade flag command is as follows: if the received clear upgrade flag command changes from invalid 0 to valid 1 and the valid 1 lasts for at least 45ms, then it is considered that a valid clear upgrade flag command has been received; otherwise, it is considered that a valid clear upgrade flag command has not been received.

[0009] The beneficial effects of this invention are: (1) This invention achieves partitioned storage and independent online upgrade of ARM application software and FPGA application software by designing ARM loading software and combining secondary boot program, which reduces the workload of software development and maintenance, improves the reliability and security of the system, and decouples ARM application software image and FPGA application software image, solves the risk of erroneous update and missed update in software configuration item management, improves the online upgrade efficiency of ARM application software, and has strong engineering application value.

[0010] (2) The present invention has the functions of image ID, image name and image integrity detection, which prevents the product from becoming "bricked" due to abnormal online upgrades, and has strong reliability and robustness.

[0011] (3) After the image upgrade verification is successful, the present invention executes the updated application through a jump instruction and clears the online upgrade mark in the application. This ensures that the updated application runs normally and prevents the updated image from being "bricked" due to errors, thus preventing the product from starting normally. It has the advantages of high reliability and strong robustness. Attached Figure Description

[0012] Figure 1 This is a flowchart of the domestic PSOC image partitioning storage and upgrade method based on secondary booting according to the present invention.

[0013] Figure 2 This is a schematic diagram of the program storage partition of the present invention. Detailed Implementation

[0014] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0015] like Figure 1 and Figure 2 As shown, a method for partitioning and upgrading a domestically produced PSOC image based on secondary booting is disclosed. The method includes monitoring software and main control software. The monitoring software includes a bootloader and an ARM loader. The main control software includes a primary bootloader, a secondary bootloader, ARM application software, and FPGA application software. Specifically, the method includes the following steps: S1: After the product is powered on, the monitoring software boot program is executed. The boot program obtains the software online upgrade identifier from the product's external FLASH and determines whether the synchronization header and checksum of the obtained data are correct. If correct, step S2 is executed; otherwise, step S9 is executed. S2: Determine if the online upgrade identifier is AA55AA55H. If it is, proceed to step S3; otherwise, proceed to step S9. S3: Execute the ARM loader in the monitoring software. The ARM loader receives the upgrade command and image file information sent by the test device through the RS-422A bus. If the upgrade command is valid, proceed to step S4; otherwise, repeat step S3. The validity of the upgrade command is determined as follows: the upgrade command changes from invalid 0 to valid 1, and the valid 1 lasts for at least 45ms. The first 16 bytes of the image file information contain the software image ID and the software image name. The image ID for the ARM application software is 50035H and the image name is ARM.bin. The image ID for the FPGA application software is 40032H and the image name is FPGA.bin.

[0016] S4: Perform image file data receiving operation. When receiving the first frame of image file information, determine whether the software image ID and software image name in the first 16 bytes of the frame information are consistent with the ARM application software. If they are consistent, update the FLASH erase base address FLASH_BASE_ADDR to FLASH_ADDR1 and execute step S6; otherwise, execute step S5. S5: Determine whether the software image ID and software image name in the first 16 bytes of the first frame image file information are consistent with the FPGA application software. If they are consistent, update the FLASH erase base address FLASH_BASE_ADDR to FLASH_ADDR2 and execute step S6; otherwise, report an image file error and re-execute step S3. S6: Continue to receive mirror file information of subsequent frames, and perform verification calculation on the received complete mirror file information. If the mirror file passes the verification, proceed to step S7; otherwise, report the transmission failure and re-execute step S3. The verification calculation method is CRC cyclic redundancy check.

[0017] S7: Calculate the number of FLASH sectors to be erased based on the length information of the received image file, and start the FLASH sector erasure operation from the base address FLASH_BASE_ADDR. At the same time, set the image erasure flag to 1. After the FLASH sector erasure is completed, write the received image data into the corresponding FLASH partition, then read back the image data from the FLASH partition and compare it with the image data received through the RS-422A bus. If the two are consistent, the image verification is determined to be successful and step S8 is executed. Otherwise, the image verification is reported as failed and step S3 is re-executed. S8: Set the image erase flag to 0, perform CPU software reset operation, and the program jumps to the first-level boot program of the main control software; S9: Execute the first-level boot program in the main control software. The first-level boot program completes the initialization of basic hardware information and the transfer and execution of the second-level boot program, and then executes step S10. S10: Execute the secondary boot program in the main control software, obtain the FPGA application software image data in the main control software from the FLASH base address FLASH_ADDR2, run the FPGA application program, and continue to execute step S11; S11: Execute the secondary boot program in the main control software, obtain the ARM application software image data in the main control software from the FLASH base address FLASH_ADDR1, run the ARM application, and continue to execute S12; S12: Execute the ARM application to perform normal mode tasks. In the ARM application, determine in real time whether a valid online upgrade command has been received. If a valid online upgrade command has been received, set the online upgrade flag to AA55AA55H and execute step S13; otherwise, execute step S14. The validity of an online upgrade command is determined as follows: if the received online upgrade command changes from invalid 0 to valid 1 and the valid 1 lasts for at least 45ms, then the online upgrade command is considered to have been received; otherwise, the online upgrade command is considered not to have been received.

[0018] S13: Package the online upgrade identifier, add a synchronization header and checksum during the packaging process, write the packaged online upgrade identifier into the FLASH partition, and perform a CPU software reset operation. The program then jumps to the monitoring software's boot program and runs. S14: The ARM application software determines in real time whether a valid clear upgrade flag command has been received and whether the image erase flag is 0. If both the valid clear upgrade flag command and the image erase flag are 0, the online upgrade flag stored in the FLASH partition is cleared, realizing the storage and upgrade of the domestic PSOC image partition based on secondary boot. Otherwise, step S12 is repeated.

[0019] The validity of the clear upgrade flag command is determined as follows: if the received clear upgrade flag command changes from invalid 0 to valid 1 and the valid 1 lasts for at least 45ms, then the clear upgrade flag command is considered to have been received; otherwise, the clear upgrade flag command is considered not to have been received.

[0020] This invention proposes a domestic PSOC image partitioning storage and upgrade method based on secondary booting, enabling partitioned storage and independent online upgrades of ARM and FPGA application software. The method includes monitoring software and main control software. The monitoring software uses an ARM loader to implement online upgrades of the ARM and FPGA application software. The main control software implements normal product functions and responds to online upgrade commands. The primary bootloader in the main control software is a low-level hardware driver, completing basic hardware initialization and the migration and execution of the secondary bootloader. The secondary bootloaders boot and start the ARM and FPGA application software from different FLASH partitions respectively. The ARM and FPGA application software then implement normal product functions and respond to online upgrade commands. This method, through the combination of ARM loader software and secondary bootloader, achieves partitioned storage and independent online upgrades of ARM and FPGA application software, reducing software development and maintenance workload, improving system reliability and security, resolving the risks of erroneous and missed updates in software configuration item management, and improving the efficiency of online upgrades for ARM application software. Furthermore, the online upgrade process adds image recognition, image integrity detection, and post-update software verification functions to prevent the product from becoming unusable due to upgrade anomalies.

[0021] Those skilled in the art will recognize that the embodiments described herein are intended to help the reader understand the principles of the invention, and should be understood that the scope of protection of the invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations based on the technical teachings disclosed in this invention without departing from the spirit of the invention, and these modifications and combinations are still within the scope of protection of the invention.

Claims

1. A method for partitioning and upgrading a domestically produced PSOC image based on secondary booting, characterized in that, The method includes monitoring software and main control software. The monitoring software includes a bootloader and an ARM loader. The main control software includes a primary bootloader, a secondary bootloader, ARM application software, and FPGA application software. Specifically, it includes the following steps: S1: After the product is powered on, the monitoring software boot program is executed. The boot program obtains the software online upgrade identifier from the product's external FLASH and determines whether the synchronization header and checksum of the obtained data are correct. If correct, step S2 is executed; otherwise, step S9 is executed. S2: Determine if the online upgrade identifier is AA55AA55H. If it is, proceed to step S3; otherwise, proceed to step S9. S3: Execute the ARM loader in the monitoring software. The ARM loader receives the upgrade command and image file information sent by the test device through the RS-422A bus. If the upgrade command is valid, proceed to step S4; otherwise, repeat step S3. S4: Perform image file data receiving operation. When receiving the first frame of image file information, determine whether the software image ID and software image name in the first 16 bytes of the frame information are consistent with the ARM application software. If they are consistent, update the FLASH erase base address FLASH_BASE_ADDR to FLASH_ADDR1 and execute step S6; otherwise, execute step S5. S5: Determine whether the software image ID and software image name in the first 16 bytes of the first frame image file information are consistent with the FPGA application software. If they are consistent, update the FLASH erase base address FLASH_BASE_ADDR to FLASH_ADDR2 and execute step S6; otherwise, report an image file error and re-execute step S3. S6: Continue to receive mirror file information of subsequent frames, and perform verification calculation on the received complete mirror file information. If the mirror file passes the verification, proceed to step S7; otherwise, report the transmission failure and re-execute step S3. S7: Calculate the number of FLASH sectors to be erased based on the length information of the received image file, and start the FLASH sector erasure operation from the base address FLASH_BASE_ADDR. At the same time, set the image erasure flag to 1. After the FLASH sector erasure is completed, write the received image data into the corresponding FLASH partition, then read back the image data from the FLASH partition and compare it with the image data received through the RS-422A bus. If the two are consistent, the image verification is determined to be successful and step S8 is executed. Otherwise, the image verification is reported as failed and step S3 is re-executed. S8: Set the image erase flag to 0, perform CPU software reset operation, and the program jumps to the first-level boot program of the main control software; S9: Execute the first-level boot program in the main control software. The first-level boot program completes the initialization of basic hardware information and the transfer and execution of the second-level boot program, and then executes step S10. S10: Execute the secondary boot program in the main control software, obtain the FPGA application software image data in the main control software from the FLASH base address FLASH_ADDR2, run the FPGA application program, and continue to execute step S11; S11: Execute the secondary boot program in the main control software, obtain the ARM application software image data in the main control software from the FLASH base address FLASH_ADDR1, run the ARM application, and continue to execute S12; S12: Execute the ARM application to perform normal mode tasks. In the ARM application, determine in real time whether a valid online upgrade command has been received. If a valid online upgrade command has been received, set the online upgrade flag to AA55AA55H and execute step S13; otherwise, execute step S14. S13: Package the online upgrade identifier, add a synchronization header and checksum during the packaging process, write the packaged online upgrade identifier into the FLASH partition, and perform a CPU software reset operation. The program then jumps to the monitoring software's boot program and runs. S14: The ARM application software determines in real time whether a valid clear upgrade flag command has been received and whether the image erase flag is 0. If both the valid clear upgrade flag command and the image erase flag are 0, the online upgrade flag stored in the FLASH partition is cleared, realizing the storage and upgrade of the domestic PSOC image partition based on secondary boot. Otherwise, step S12 is repeated.

2. The method for partitioning and upgrading a domestically produced PSOC image based on secondary booting as described in claim 1, characterized in that, The method for determining the validity of the upgrade command is as follows: the upgrade command changes from invalid 0 to valid 1, and the valid 1 lasts for at least 45ms; The first 16 bytes of the image file information contain the software image ID and the software image name. The image ID for the ARM application software is 50035H and the image name is ARM.bin. The image ID for the FPGA application software is 40032H and the image name is FPGA.bin.

3. The method for partitioning and upgrading a domestically produced PSOC image based on secondary booting as described in claim 1, characterized in that, The verification calculation method is CRC cyclic redundancy check.

4. The method for partitioning and upgrading a domestically produced PSOC image based on secondary booting as described in claim 1, characterized in that, The method for determining the validity of the online upgrade command is as follows: if the received online upgrade command changes from invalid 0 to valid 1 and the valid 1 lasts for at least 45ms, then the online upgrade command is considered to have been received; otherwise, the online upgrade command is considered not to have been received.

5. The method for partitioning and upgrading a domestically produced PSOC image based on secondary booting as described in claim 1, characterized in that, The method for determining the validity of the clear upgrade flag command is as follows: if the received clear upgrade flag command changes from invalid 0 to valid 1 and the valid 1 lasts for at least 45ms, then it is considered that a valid clear upgrade flag command has been received; otherwise, it is considered that a valid clear upgrade flag command has not been received.

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