Heat dissipation enhancement type semiconductor packaging method

Abstract

The invention discloses a heat dissipation enhanced semiconductor packaging method, which comprises the following steps of: performing deep silicon etching to form a vertical through hole; insulation and metallization are carried out; thinning the wafer; performing hybrid bonding and stacking of multiple layers of chips; a heat dissipation design is adopted to form a vertical heat dissipation path; a three-dimensional thermal through hole network: adding pure copper thermal through holes in a non-functional area; performing microfluid cooling integration; molding and packaging; and thermal performance verification: verifying that the junction temperature can be controlled within 85 DEG C through infrared thermal imaging and finite element simulation. The TSV with the depth-to-width ratio of 10: 1 can be realized by adopting the Bosch process; a three-dimensional integrated TSV array supporting HBM and other high-speed memories is embedded into diamond or graphene heat dissipation columns, a low-heat-resistance vertical heat dissipation path is formed by combining a three-dimensional pure copper heat through hole network, and local hot spots are effectively dispersed; the high-thermal-conductivity epoxy molding compound and the embedded copper block enhance the overall mechanical strength and thermal diffusivity, so that the product can dissipate heat efficiently, and the overall area is not easy to influence.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor, and particularly relates to a heat dissipation enhanced semiconductor packaging method. BACKGROUND

[0002] With the trend of multi-function and miniaturization of electronic products, high-density microelectronic assembly technology gradually becomes mainstream on the new generation of electronic products. In order to cooperate with the development of the new generation of electronic products, especially smart phones, palm computers, super notebooks and other products, the size of the chip is developing in the direction of higher density, faster speed, smaller size and lower cost, such as the Chinese invention patent with the patent name of a high-performance chiplet packaging implementation method with the publication number CN119812105A, which discloses the following steps: making TSV in the chiplet and depositing a layer of dielectric material on the region with metal on the surface of the chiplet; pretreating the substrate, including depositing a layer of dielectric material on the side of the substrate with pads; bonding the pretreated chiplet and the pretreated substrate together; then bonding another pretreated chiplet on the bonded chiplet to form a chiplet module; wherein the chiplets bonded together rely on TSV to form information interaction, and through the installation of the heat dissipation cover, mechanical protection is provided for the chip while the heat dissipation is enhanced, thereby improving the performance of the chip. In the above patent, the top of the heat dissipation cover cavity is parallel to the substrate, and a certain slope is formed around it, which increases the heat dissipation area while the stress is more uniform under the same load, the stress concentration coefficient at the corner is smaller, and failure is less likely to occur, while the heat dissipation cover itself has a certain thickness, especially the design with a cavity, which increases the total height of the chip packaging, and the design of the side wall slope increases the occupation area of the heat dissipation cover in the XY plane, resulting in poor internal heat dissipation effect of the multi-layer chip vertical interconnection semiconductor, thereby affecting the overall mechanical strength and heat diffusion capacity. SUMMARY

[0003] To solve the above technical problems, the purpose of the present application is to disclose a heat dissipation enhanced semiconductor packaging method.

[0004] To achieve the above technical purpose, the technical means adopted by the present application is: A heat dissipation enhanced semiconductor packaging method, comprising the following steps: S1, deep silicon etching: Bosch process is used for high aspect ratio TSV etching, SF6 gas etching and C4F8 passivation are alternately performed to form a vertical through hole with a diameter of 5-10 μm and an aspect ratio of 10:1, so as to ensure that the hole wall perpendicularity error is less than 1°; S2, insulation and metallization: TiO2 insulating layer, Ta / TaN barrier layer and Cu seed layer were deposited sequentially, and copper was filled by electrochemical deposition (ECD). The surface was then smoothed by annealing and CMP polishing. S3, Wafer Thinning: The back side of the completed TSV wafer is ground to a thickness of 50-100 μm to expose the TSV copper pillars and prepare a redistribution layer; S4, hybrid bonding: A hybrid bonding technology combining direct copper bonding and dielectric layer bonding is used to stack multi-layer chips, with bonding accuracy controlled within ±0.5μm; S5, Heat dissipation design: High thermal conductivity materials, such as diamond or graphene, are embedded in the TSV array to form heat dissipation pillars that are spaced apart from the TSV copper pillars, thus creating a vertical heat dissipation path. S6, Three-dimensional thermal via network: Add pure copper thermal vias with a diameter of 20-50μm to non-functional areas to connect the copper interconnect layers of the chip and reduce interlayer thermal resistance. S7, Microfluidic Cooling Integration: Microchannels are integrated within the packaging substrate to achieve active heat dissipation by pumping coolant, working in conjunction with TSV copper pillars; S8, Molded Package: High thermal conductivity epoxy molding compound is used for encapsulation, with a thermal conductivity >3Wm·K, and copper blocks are embedded in key heat-generating areas; S9. Thermal performance verification: Infrared thermal imaging and finite element simulation were used to verify the performance at 300 W / cm². 2 At the given heat flux density, the junction temperature can be controlled below 85℃.

[0005] Preferably, in step S1, the single cycle time of SF6 gas etching and C4F8 passivation in the Bosch process is 3-5s, the total number of cycles is 200-500, and the roughness Ra of the through-hole sidewall is ≤0.1μm.

[0006] Preferably, in step S2, the Ta / TaN barrier layer is deposited using atomic layer deposition (ALD) with a thickness of 20-50 nm, the Cu seed layer has a thickness of 100-200 nm, and the resistivity of the copper pillar filled by ECD is ≤2.0 μΩ·cm.

[0007] Preferably, in step S3, the wafer thinning adopts a two-step grinding method: first, it is coarsely ground to 150μm at a rate of 200-300μm / min, and then finely ground to the target thickness at a rate of 50-100μm / min, with the TSV copper pillar protrusion controlled at 0.2-0.5μm.

[0008] Preferably, in step S4, a 5-10 nm thick nanotwinned copper layer is pre-formed on the copper-copper bonding surface, the bonding temperature is 200-250℃, the pressure is 1-3 MPa, and the interface resistance after bonding is ≤10 Ω·μm. 2 .

[0009] Preferably, in step S5, the high thermal conductivity material is a chemical vapor deposition (CVD) diamond column with a diameter of 3-8 μm and a thermal conductivity ≥1000 W / (m·K), arranged at a 1:2 interval with the copper TSV.

[0010] Preferably, in step S6, the pure copper thermal vias are arranged in a hexagonal close-packed array with a center-to-center distance of 1.5-2 times the aperture diameter, and are connected to at least 3 device layers through a silicon interposer.

[0011] Preferably, in step S7, the microchannel width is 50-100μm, the depth is 200-300μm, and it is built-in. Nanofluids with a flow rate of 0.5-2 ml / min and a center distance of ≤100 μm from the TSV copper pillars.

[0012] Preferably, in step S8, the epoxy molding compound contains 40-60 vol% boron nitride filler, has a glass transition temperature ≥180℃, and a coefficient of thermal expansion (CTE) ≤10 ppm / ℃.

[0013] Preferably, in step S9, the thermal verification uses a transient thermal test method to measure the thermal resistance, and under the conditions of pulse power 300 W / cm² and pulse width 100 μs, the junction temperature rise slope is ≤0.5℃ / μs.

[0014] Compared with the prior art, the beneficial effects achieved by the present invention are as follows: This invention utilizes Bosch technology to achieve a 10:1 aspect ratio TSV, shortening the signal transmission path by more than 85% compared to traditional wire bonding, reducing interconnect latency and increasing bandwidth by 30%. The vertical channel enables an interconnect density of up to 10 per unit area. -4 / cm² level; supports 3D integrated TSV arrays for high-speed memories such as HBM, with embedded diamond or graphene heat dissipation pillars, combined with a 3D pure copper thermal via network to form a low thermal resistance vertical heat dissipation path, effectively dispersing local hot spots. The microchannels and TSV copper pillars work together to dynamically adjust the temperature, supporting stable operation under a high heat flux density of 300W / cm²; high thermal conductivity epoxy molding compound and embedded copper blocks enhance the overall mechanical strength and heat diffusion capability, enabling the product to dissipate heat efficiently without easily affecting the overall area. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the process structure of the present invention; Figure 2 This is a top view of the chip structure of the present invention; Figure 3 This is a schematic diagram of the cross-sectional structure of the chip of the present invention; Figure 4 This is a schematic diagram of the multi-layer stacked structure of the chip of the present invention; Figure 5 This is a schematic diagram of the chip encapsulation structure of the present invention; Figure 6 This is a schematic diagram of the microchannel cooling system of the present invention. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] like Figures 1-6 As shown, a heat-enhancing semiconductor packaging method includes the following steps: S1, Deep Silicon Etching: High aspect ratio TSV etching is performed using the Bosch process. Vertical vias with a diameter of 5-10 μm and an aspect ratio of 10:1 are formed by alternating SF6 gas etching and C4F8 passivation, ensuring that the verticality error of the via wall is <1°. In the Bosch process, the single cycle time of SF6 gas etching and C4F8 passivation is 3-5 s, the total number of cycles is 200-500, and the roughness Ra of the via sidewall is ≤0.1 μm. In this step, vertical deep-hole etching is achieved through alternating cycles of SF6 gas etching and C4F8 passivation. SF6 plasma generates F radicals to perform isotropic chemical etching of silicon, while C4F8 forms a polymer passivation film on the sidewalls to protect non-target areas. C4F8 plasma also deposits CFx polymer on the sidewalls to suppress lateral etching. The bottom passivation layer is selectively removed by subsequent ion bombardment to ensure the etching direction is vertically downward. A verticality error of <1° depends on precise cycle parameters and the uniformity of the passivation layer.

[0018] S2, Insulation and Metallization: TiO2 insulating layer, Ta / TaN barrier layer and Cu seed layer are deposited sequentially. Copper is filled by electrochemical deposition (ECD). The surface is smoothed by annealing and CMP polishing. The Ta / TaN barrier layer is made by atomic layer deposition (ALD) with a thickness of 20-50 nm. The Cu seed layer has a thickness of 100-200 nm. The SiO2 insulating layer is deposited on the TSV sidewalls using PECVD or ALD processes to prevent leakage caused by copper 3 diffusion and to achieve electrical isolation between adjacent TSVs. A 20-50nm Ta / TaN bilayer structure is deposited using ALD. TaN inhibits copper atom diffusion, while Ta enhances adhesion. The two work together to improve interface stability. The ALD barrier layer reduces the copper 3 diffusion rate by more than 90%. The resistivity of the copper pillars filled by ECD is ≤2.0μΩ·cm, which is 12% lower than that of the traditional PVD process. Dynamic power consumption is reduced by 8%. The conical TSV structure combined with the stepped deposition process increases the film coverage by 40% and extends the electromigration lifetime by 5 times.

[0019] S3, Wafer Thinning: The back side of the completed TSV wafer is ground to a thickness of 50-100 μm to expose the TSV copper pillars and prepare a redistribution layer; S4, hybrid bonding: A hybrid bonding technology combining direct copper bonding and dielectric layer bonding is used to stack multiple layers of chips 4, with bonding accuracy controlled within ±0.5μm; S5, Heat dissipation design: Heat dissipation pillars 5, which are made of highly thermally conductive materials such as diamond or graphene, are embedded in the TSV array and arranged alternately with the TSV copper pillars to form a vertical heat dissipation path. S6, Three-dimensional thermal via network: Add pure copper thermal vias with a diameter of 20-50μm to non-functional areas to connect the copper interconnect layers of the chip and reduce interlayer thermal resistance. S7, Microfluidic Cooling Integration: Microchannel 2 is integrated within the packaging substrate to achieve active heat dissipation by pumping coolant, and works in conjunction with the TSV copper pillars; S8, Molded Package: High thermal conductivity epoxy molding compound is used for encapsulation, with a thermal conductivity >3Wm·K, and copper blocks are embedded in key heat-generating areas; S9. Thermal performance verification: Infrared thermal imaging and finite element simulation were used to verify that the junction temperature could be controlled below 85℃ at a heat flux density of 300W / cm².

[0020] In some implementations, in step S3, wafer thinning employs a two-step grinding method. First, it is coarsely ground to 150μm at a rate of 200-300μm / min, mainly to remove substrate material and form a preliminary flat surface. Then, it is finely ground to the target thickness at a rate of 50-100μm / min, while reducing the stress damage layer generated by coarse grinding, ensuring surface roughness and thickness uniformity. Through precise thickness control, the amount of TSV copper pillar protrusion is stabilized at 0.2-0.5μm, providing an electrical connection basis for subsequent redistribution layer fabrication. The two-step method balances efficiency and precision: coarse grinding improves throughput, fine grinding ensures surface quality, reduces the risk of microcracks and warpage, and the controlled amount of protruding copper pillars ensures reliable interconnection between RDL and TSV, reduces contact resistance, and improves the heat dissipation efficiency of the high-power chip 4.

[0021] In some embodiments, in step S4, a 5-10 nm thick nanotwinned copper layer is pre-formed on the copper-copper bonding surface, with a bonding temperature of 200-250°C and a pressure of 1-3 MPa, resulting in an interface resistance ≤10 Ω·μm² after bonding. This is achieved through direct copper bonding (without solder) to a dielectric layer (such as…). The combination of bonding and inter-layer bonding enables vertical interconnection of the chip. The nanotwinned copper layer promotes the interdiffusion of copper atoms at low temperatures (200-250℃) by reducing the grain boundary diffusion barrier, forming a low-resistance interface with an interface resistance ≤10Ω·μm², which is significantly better than traditional solder (100Ω·μm²). This reduces power consumption and improves signal integrity. The nanotwinned copper inhibits electromigration, and the dielectric layer bonding relieves thermal stress and extends device life.

[0022] In some embodiments, in step S5, the high thermal conductivity material is a chemical vapor deposition (CVD) diamond pillar with a diameter of 3-8 μm and a thermal conductivity ≥1000 W / (m·K). It is arranged at a 1:2 interval with the copper TSV to form a three-dimensional heat dissipation network. Through the ultra-high thermal conductivity of diamond 2000 W / (m·K), the heat in the active area of ​​the chip is quickly conducted to the heat sink in the vertical direction, avoiding the accumulation of lateral thermal resistance in traditional planar heat dissipation.

[0023] In some embodiments, in step S6, the pure copper thermal vias are arranged in a hexagonal close-packed array with a center-to-center distance of 1.5-2 times the aperture diameter, connecting at least three device layers through a silicon interposer. The high thermal conductivity of copper 3 (401 W / m·K) establishes a rapid heat conduction channel in the vertical direction, replacing the interlayer thermal resistance path of the original low thermal conductivity dielectric material. Thermal interconnection of the 3D stacked device layers is achieved through TSV technology, forming a continuous heat flow path from the top layer to the substrate. The thermal via array diffuses point heat sources into surface heat sources, enhancing the longitudinal heat flow component (Q=-kAΔT / Δx) through Fourier's law, thereby reducing interlayer thermal resistance by 40% to 60%.

[0024] In some implementations, in step S7, the microchannel width is 50-100 μm, the depth is 200-300 μm, and it is built-in. Nanofluids, with a flow rate of 0.5-2 ml / min and a center distance of ≤100 μm from the TSV copper pillars, achieve efficient convective heat transfer using high specific surface area. The synergy between microchannels and TSV reduces thermal resistance by more than 40%, which can handle heat flux densities of >300 W / cm² in 3D-ICs. The synergy between nanofluid flow and TSV thermal conduction reduces local hot spots, keeping the chip temperature difference within 2℃. The microchannels embedded in the substrate save external heat dissipation space, making it suitable for the compact layout requirements of advanced packaging (such as 2.5D / 3D ICs).

[0025] In some embodiments, in step S8, the epoxy molding compound contains 40-60 vol% boron nitride filler, has a glass transition temperature ≥180°C, and a coefficient of thermal expansion (CTE) ≤10 ppm / °C, forming a three-dimensional thermally conductive channel in the epoxy resin matrix. Its two-dimensional sheet structure enables rapid heat conduction through its high in-plane thermal conductivity.

[0026] In some implementations, in step S9, the thermal verification uses a transient thermal test to measure the thermal resistance, and the junction temperature rise slope is ≤0.5℃ / μs under the conditions of pulse power 300W / cm² and pulse width 100μs.

[0027] A 640×512 resolution infrared detector is used to monitor the surface temperature distribution of the chip in real time. The radiation intensity is converted into temperature data through the Stefan-Boltzmann law to capture the microscopic thermal field characteristics under the condition of 300W / cm². The system synchronously records the junction temperature change curve within 100μs after pulse power loading to verify whether the rising slope meets the design target of ≤0.5℃ / μs.

[0028] Any parts or structures not specifically described in this invention can be made using existing technologies or products, and will not be elaborated upon here.

[0029] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A heat-enhanced semiconductor packaging method, characterized in that, Includes the following steps: S1. Deep silicon etching is used to form vertical vias, ensuring that the perpendicularity error of the hole wall is less than 1°. S2, insulation and metallization; S3, wafer thinning; S4. Hybrid bonding, stacking multiple layers of chips, with bonding accuracy controlled within ±0.5μm; S5, heat dissipation design, forming a vertical heat dissipation path; S6, Three-dimensional thermal via network: Pure copper thermal vias are added to non-functional areas to connect the copper interconnect layers of the chip and reduce interlayer thermal resistance; S7, integrated microfluidic cooling; S8, molded packaging; S9. Thermal performance verification: Through infrared thermal imaging and finite element simulation, it was verified that the junction temperature can be controlled within 85℃ at a heat flux density of 300W / cm².

2. The heat-enhancing semiconductor packaging method according to claim 1, characterized in that, In step S1, the deep silicon etching process includes: High aspect ratio TSV etching was performed using the Bosch process. Vertical vias with a diameter of 5-10 μm and an aspect ratio of 10:1 were formed by alternating SF6 gas etching and C4F8 passivation. The cycle time for SF6 gas etching and C4F8 passivation was 3-5 s, and the total number of cycles was 200-500. The roughness Ra of the via sidewall was ≤0.1 μm.

3. The heat-enhancing semiconductor packaging method according to claim 1, characterized in that, In step S2, the insulation and metallization steps include: TiO2 insulating layer, Ta / TaN barrier layer and Cu seed layer are deposited sequentially, and copper is filled by electrochemical deposition. The surface is then smoothed by annealing and CMP polishing.

4. The heat-enhancing semiconductor packaging method according to claim 1, characterized in that, In step S3, the wafer thinning step includes: The back side of the TSV obtained in step S2 is ground to a thickness of 50-100 μm to expose the TSV copper pillars and prepare a redistribution layer.

5. The heat-enhancing semiconductor packaging method according to claim 1, characterized in that, In step S3, wafer thinning is performed using a two-step grinding method. First, the wafer is coarsely ground to 150μm at a rate of 200-300μm / min, and then finely ground to the target thickness at a rate of 50-100μm / min. The TSV copper pillar protrusion is controlled at 0.2-0.5μm.

6. The heat-enhancing semiconductor packaging method according to claim 1, characterized in that, In step S4, a hybrid bonding technique combining direct copper bonding and dielectric layer bonding is used to stack multiple layers of chips. A 5-10 nm thick nanotwinned copper layer is pre-generated on the copper-copper bonding surface. The bonding temperature is 200-250℃, the pressure is 1-3 MPa, and the interface resistance after bonding is ≤10 Ω·μm. 2 .

7. The heat-enhancing semiconductor packaging method according to claim 1, characterized in that, In step S5, a high thermal conductivity material is embedded in the TSV copper pillar array, and it is arranged alternately with the TSV copper pillars to form a vertical heat dissipation path.

8. The heat-enhancing semiconductor packaging method according to claim 1, characterized in that, In step S6, the pure copper thermal vias are arranged in a hexagonal close-packed array with a center-to-center distance of 1.5-2 times the aperture diameter, and are connected to at least 3 device layers through a silicon interposer.

9. The heat-enhancing semiconductor packaging method according to claim 1, characterized in that, In step S7, a microchannel is integrated within the packaging substrate. The microchannel has a width of 50-100 μm and a depth of 200-300 μm. TiO2 nanofluid is embedded within the microchannel with a flow rate of 0.5-2 ml / min. The center distance between the microchannel and the TSV copper pillar is ≤100 μm. Active heat dissipation is achieved by pumping coolant, and the microchannel works in conjunction with the TSV copper pillar.

10. A heat-enhancing semiconductor packaging method according to claim 1, characterized in that, In step S8, a high thermal conductivity epoxy molding compound is used for encapsulation, with a thermal conductivity >3Wm·K, and copper blocks are embedded in the key heat-generating areas. The epoxy molding compound contains boron nitride filler, with a glass transition temperature ≥180℃ and a coefficient of thermal expansion ≤10ppm / ℃.

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