Radio frequency millimeter wave ultra-low noise single-stage sampling phase-locked loop
By using a narrow-pulse single-stage sampling phase-locked loop structure, combined with a transformer series resonant voltage-controlled oscillator and a frequency divider, the problem of sampling clock noise was solved, realizing a low-noise, low-spurious, and small-area RF millimeter-wave phase-locked loop design, which improved the system's stability and frequency synthesis effect.
Patent Information
- Application Number
- CN202511139582.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-14
- Publication Date
- 2025-12-19
AI Technical Summary
The performance of existing RF millimeter-wave sampling phase-locked loops is limited by the phase noise propagation characteristics of the sampling clock, which leads to a deterioration of the phase noise floor in the high-frequency band, requiring compensation from ultra-low jitter reference sources or digital jitter calibration techniques.
A narrow-pulse single-stage sampling phase-locked loop structure is adopted, including a sampling phase detector, a transformer-based series resonant voltage-controlled oscillator, and a frequency divider. Instantaneous sampling and frequency adjustment are achieved through picosecond-level narrow pulse signals. Combined with a clock generation module, an ultra-narrow pulse signal is generated, reducing noise and area.
A sampling phase-locked loop with low phase noise, low reference spurious emissions, and small area was achieved, which significantly suppressed phase noise and improved the robustness and frequency synthesis performance of the system.
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Figure CN121173290A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the field of mixed analog-digital integrated circuits, and particularly relates to a radio frequency millimeter wave ultra-low noise single-stage sampling phase-locked loop. BACKGROUND
[0002] As a core control unit of modern radio frequency systems, the phase-locked loop (PLL) is a closed-loop control system based on a phase-frequency feedback mechanism. Its core function is to dynamically adjust the output frequency and phase of the internal voltage-controlled oscillator (VCO) through an external high-precision reference signal, thereby realizing precise phase synchronization and frequency locking of the output signal and the input reference signal. In key fields such as high-speed data communication, millimeter wave radar, satellite navigation, etc., the PLL undertakes core functions such as clock signal regeneration, frequency synthesis, and modulation and demodulation, and is the basic circuit module to ensure signal integrity and system stability.
[0003] The typical architecture of a phase-locked loop is shown in Figure 1 , which consists of a phase-frequency discriminator, a charge pump, a frequency divider, a loop filter, and a voltage-controlled oscillator to form a closed-loop feedback system. The specific working process is as follows: the phase discriminator receives the external reference signal and the feedback signal after the VCO output is divided by frequency, and generates an error voltage signal by detecting the phase difference between the two; after the signal is filtered to remove high-frequency noise and smoothed by the loop filter, it is converted into the control voltage of the VCO, thereby dynamically adjusting the oscillation frequency.
[0004] The closed-loop dynamic adjustment process of the phase-locked loop can be divided into two stages: lock establishment and steady-state maintenance. In the unlocked state, the high-frequency signal output by the voltage-controlled oscillator is reduced in frequency by the frequency divider and input into the phase-frequency discriminator synchronously with the reference signal, and an error pulse is generated by real-time detection of the phase / frequency difference between the two. The charge pump converts this pulse into a charge / discharge current, which is integrated by the loop filter to generate a control voltage that drives the VCO frequency to converge to the reference signal until strict synchronization is achieved and the locked state is entered. In the locked state, the system continuously monitors the frequency offset through a high-sensitivity phase error detection mechanism (with a precision of picoseconds), and dynamically corrects the control voltage through a negative feedback loop. Phase noise, as a key indicator of the phase-locked loop, reflects the random fluctuations of the output signal phase in the time domain in the locked state, and its spectral characteristics directly determine the signal integrity of the communication link.
[0005] Type I-SPLL achieves the balance between high integration and ultra-low phase noise by architecture simplification and multi-stage noise optimization technology. The core design discards redundant modules, only keeps four key units of reference oscillator, frequency divider, sampling phase detector and voltage controlled oscillator, so that the chip area is reduced by more than 30%, and the noise source of each module is targetedly suppressed. The external ultra-low noise crystal oscillator (phase noise as low as-160dBc / Hz@1MHz) directly drives the loop to avoid the thermal noise interference of the on-chip oscillator; the VCO clock domain retiming technology is adopted to block the metastable state jitter introduced by the logic flip of the frequency divider through D flip-flop synchronization; the phase detection sensitivity is improved to suppress the noise in the loop band by increasing the phase detection gain; the VCO low frequency noise is suppressed by high Q value resonant cavity and reducing the pulse sensitivity function of VCO output.
[0006] As a kind of Type I-SPLL, RS-PLL directly samples the output signal of the frequency-divided voltage controlled oscillator, uses the sampling and holding circuit to quantify the phase difference between the reference signal and the feedback signal, and replaces the analog phase detection mechanism of the traditional charge pump and frequency discriminator. This principle innovation has the following advantages: first, since the non-ideal effects such as charge pump charge and discharge current mismatch and switch timing deviation are eliminated, the reference spur of RS-PLL can be suppressed to below-70dBc, meeting the stringent requirements of millimeter wave communication on spectral purity; second, its digital architecture is naturally adapted to advanced CMOS process, without charge pump and complex analog loop filter, greatly simplifying the circuit structure and improving the integration level, especially suitable for multi-band RF SoC design. However, the performance of RS-PLL is limited by the phase noise transfer characteristics of the sampling clock-the jitter of the sampling path (such as clock skew, power noise coupling) will be directly modulated to the VCO output phase, resulting in deterioration of the high frequency phase noise floor, which needs to rely on ultra-low jitter reference source (such as high Q value crystal oscillator) or digital jitter calibration technology for compensation. SUMMARY
[0007] In order to solve the above problems existing in the prior art, the present application provides a radio frequency millimeter wave ultra-low noise single-stage sampling phase-locked loop. The technical problem to be solved by the present application is solved by the following technical scheme: The embodiment of the present application provides a radio frequency millimeter wave ultra-low noise single-stage sampling phase-locked loop, comprising: A sampling phase detector is used for instantaneous sampling of a reference signal according to a picosecond narrow pulse signal, and outputs a sampling voltage, wherein the reference signal and the picosecond narrow pulse signal have the same frequency; A transformer-based series resonant voltage controlled oscillator is connected with the sampling phase detector, and is used for adjusting the oscillation frequency according to the sampling voltage, and outputs a high frequency signal; A frequency divider is connected with the voltage-controlled oscillator and used for frequency dividing the high-frequency signal to output a clock control signal; A clock generation module is connected with the frequency divider and the sampling phase detector and used for generating the picosecond-level narrow pulse signal according to the clock control signal.
[0008] In an embodiment of the present application, the sampling phase detector comprises a first transmission gate, a second transmission gate, a third transmission gate, a fourth transmission gate, a fifth transmission gate and a sampling capacitor, wherein, The signal input end of the first transmission gate inputs a reference signal; The first transmission gate, the second transmission gate, the third transmission gate, the fourth transmission gate and the fifth transmission gate are connected in series, and the first control input end of each of the gates inputs a positive phase signal and the second control input end inputs a negative phase signal; The output end of the fifth transmission gate is connected with one end of the sampling capacitor and outputs a sampling voltage.
[0009] In an embodiment of the present application, the channel width of the first transmission gate, the second transmission gate, the third transmission gate, the fourth transmission gate and the fifth transmission gate is in binary decrease.
[0010] In an embodiment of the present application, the frequency dividing ratio of the frequency divider is the ratio of the oscillation frequency of the voltage-controlled oscillator to the reference signal.
[0011] In an embodiment of the present application, the clock generation module comprises a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, a first selector, a second selector, a third selector and an AND gate, wherein, The input end of the first inverter is connected with the first input end of the AND gate and inputs the clock control signal; The first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter and the seventh inverter are connected in series; The output end of the seventh inverter is connected with the first input end of the first selector, the output end of the fifth inverter is connected with the second input end of the first selector, the output end of the third inverter is connected with the first input end of the second selector, and the output end of the first inverter is connected with the second input end of the second selector; The output end of the first selector is connected with the first input end of the third selector, and the output end of the second selector is connected with the second input end of the third selector; The output end of the third selector is connected with the second input end of the AND gate; The output end of the AND gate outputs the picosecond-level narrow pulse signal.
[0012] In one embodiment of the present application, the pulse width of the picosecond-level narrow pulse signal is 40 ps-100 ps.
[0013] In one embodiment of the present application, the series resonant voltage-controlled oscillator comprises a first MOS tube, a second MOS tube, a first resistor, a third MOS tube, a fourth MOS tube, a second resistor, a first attenuation capacitor, a second attenuation capacitor, a parallel resonant inductor, a first series resonant inductor, a second series resonant inductor, a first adjustable capacitor, a second adjustable capacitor, a first series resonant capacitor array, and a second series resonant capacitor array, wherein, the source of the first MOS tube is connected to ground, the drain is connected to the drain of the second MOS tube and the first end of the first resistor, and the gate is connected to the gate of the second MOS tube and the second end of the first resistor; the source of the second MOS tube is connected to a power supply voltage; the first MOS tube, the second MOS tube, and the first resistor form a first transimpedance amplifier, the input end of the first transimpedance amplifier is connected to the LP_P end of the parallel resonant inductor, the first end of the first series resonant capacitor array, and the first end of the first adjustable capacitor through the first attenuation capacitor, and the output end is connected to the LS_N end of the first series resonant inductor; the LS_CAPN end of the first series resonant inductor is connected to the first end of the second series resonant capacitor array; the source of the third MOS tube is connected to ground, the drain is connected to the drain of the fourth MOS tube and the first end of the second resistor, and the gate is connected to the gate of the fourth MOS tube and the second end of the second resistor; the source of the fourth MOS tube is connected to a power supply voltage; the third MOS tube, the fourth MOS tube, and the second resistor form a second transimpedance amplifier, the input end of the second transimpedance amplifier is connected to the LP_N end of the parallel resonant inductor, the second end of the first series resonant capacitor array, and the first end of the second adjustable capacitor through the second attenuation capacitor, and the output end is connected to the LS_P end of the second series resonant inductor; the LS_CAPP end of the second series resonant inductor is connected to the second end of the second series resonant capacitor array; the second end of the first adjustable capacitor and the second end of the second adjustable capacitor are connected and input an adjustment voltage.
[0014] In one embodiment of the present application, the parallel resonant inductor, the first series resonant inductor, and the second series resonant inductor are coupled at the same end.
[0015] In one embodiment of the present application, the parallel resonant inductor, the first series resonant inductor, and the second series resonant inductor are wound in the following manner: The parallel resonant inductor is formed by a plurality of first bending segments arranged along the edges of the octagon, and is spaced apart between the LP_P end and the LP_N end; The first series resonant inductor and the second series resonant inductor are both formed by a plurality of second bending segments arranged around the outer periphery of the parallel resonant inductor, and each second bending segment is parallel to the opposite first bending segment; The LS_N end of the first series resonant inductor is coupled to the LP_N end of the parallel resonant inductor, the LS_P end of the second series resonant inductor is coupled to the LP_P end of the parallel resonant inductor, and the LS_N end of the first series resonant inductor is close to the LS_P end of the second series resonant inductor and spaced apart therebetween by a distance; The LS_CAPP end of the first series resonant inductor is close to the LS_CAPN end of the second series resonant inductor and spaced apart therebetween by a distance.
[0016] In an embodiment of the present application, the frequency coverage range of the series resonant voltage-controlled oscillator is 11-12 GHz.
[0017] Compared with the prior art, the present application has the following advantages: The sampling phase-locked loop of the present application consists of a sampling phase detector, a series resonant voltage-controlled oscillator, a frequency divider and a clock generation module, the sampling phase detector uses narrow pulse single sampling, when the sampling pulse is small enough, the instantaneous sampling characteristic of the impulse response is realized, the phase noise of the single sampling module is suppressed, and the area is reduced by more than half; the clock generation module is used to generate picosecond-level narrow pulse signals, the PVT drift rate of the pulse width is reduced, and the robustness of the system is improved; the series resonant voltage-controlled oscillator based on transformer can withstand greater current, generate greater oscillation amplitude, and achieve significant phase noise suppression, at the same frequency, the phase noise of the voltage-controlled oscillator is effectively suppressed; therefore, the sampling phase-locked loop of the present application realizes effective suppression of noise, has the advantages of low phase noise, low reference spur and small area. BRIEF DESCRIPTION OF DRAWINGS
[0018] Figure 1 It is a typical architecture of phase-locked loop; Figure 2 It is a structure schematic diagram of a radio frequency millimeter wave ultra-low noise single sampling phase-locked loop provided by an embodiment of the present application; Figure 3 It is a fitting diagram of the overall phase noise of the sampling phase-locked loop provided by an embodiment of the present application; Figure 4 It is a structure schematic diagram of the sampling phase detector provided by an embodiment of the present application; Figure 5 It is a comparison diagram of the phase noise of the sampling phase detector provided by an embodiment of the present application; Figure 6 A structure diagram of a clock generation module provided by an embodiment of the present application is shown in the figure; Figure 7 A structure diagram of a series resonant voltage-controlled oscillator provided by an embodiment of the present application is shown in the figure; Figure 8 A winding mode diagram of a single-core ultra-small-area transformer inductor provided by an embodiment of the present application is shown in the figure; Figure 9 A phase noise diagram when the frequency of the series resonant voltage-controlled oscillator provided by an embodiment of the present application is 12 GHz is shown in the figure. DETAILED DESCRIPTION
[0019] The present application will be further described in detail below with specific embodiments, but the embodiments of the present application are not limited thereto.
[0020] Embodiment one Please refer to Figure 2 , Figure 2 A structure diagram of a radio frequency millimeter wave ultra-low noise single-stage sampling phase-locked loop provided by an embodiment of the present application is shown in the figure.
[0021] The radio frequency millimeter wave ultra-low noise single-stage sampling phase-locked loop in this embodiment adopts a narrow pulse single-stage sampling architecture, and realizes high-performance frequency synthesis through a minimalist hardware design, including a sampling phase detector 1, a transformer-based series resonant voltage-controlled oscillator 2, a frequency divider 3, and a clock generation module 4. The sampling phase detector 1 is used to instantaneously sample a reference signal according to a picosecond-level narrow pulse signal and output a sampling voltage. The reference signal has the same frequency as the picosecond-level narrow pulse signal. The transformer-based series resonant voltage-controlled oscillator 2 is connected with the sampling phase detector 1 and is used to adjust the oscillation frequency according to the sampling voltage and output a high-frequency signal. The frequency divider 3 is connected with the voltage-controlled oscillator 2 and is used to divide the high-frequency signal and output a clock control signal. The clock generation module 4 is connected with the frequency divider 3 and the sampling phase detector 1 and is used to generate a picosecond-level narrow pulse signal according to the clock control signal.
[0022] In one specific embodiment, the high-frequency signal output by the transformer-based series resonant voltage-controlled oscillator 2 is divided by 120 by the frequency divider 3 to generate a 100 MHz clock signal, which drives the clock generation module 4 to generate a picosecond-level narrow pulse sequence. After receiving the picosecond-level narrow pulse sequence, the sampling phase detector 1 instantaneously samples a reference signal of the same frequency, and the sampling voltage obtained by the sampling directly regulates the VCO tuning end. When the loop is locked, the system accurately synthesizes a 12 GHz output signal through the 100 MHz reference clock. Please refer to Figure 3 , Figure 3 A fitting diagram of the overall phase noise of the sampling phase-locked loop provided by an embodiment of the present application is shown in the figure. Figure 3The jitter fitting curve shows that when the output frequency of the overall phase-locked loop is 12GHz, the jitter is 17fs.
[0023] Please refer to Figure 4 , Figure 4 The structure diagram of the sampling phase detector provided by the embodiment of the application is shown in the figure. The sampling phase detector 1 of the embodiment adopts a low-noise narrow-pulse single-stage sampling phase detector, which comprises a first transmission gate Tran1, a second transmission gate Tran2, a third transmission gate Tran3, a fourth transmission gate Tran4, a fifth transmission gate Tran5 and a sampling capacitor C1. The signal input end of the first transmission gate Tran1 inputs a reference signal REF. The first transmission gate Tran1, the second transmission gate Tran2, the third transmission gate Tran3, the fourth transmission gate Tran4 and the fifth transmission gate Tran5 are connected in series, and the first control input end of each of the gates inputs a positive-phase signal V PULS_P , and the second control input end of each of the gates inputs a negative-phase signal V PULS_N . The output end of the fifth transmission gate Tran5 is connected with one end of the sampling capacitor C1 and outputs a sampling voltage VCTRL.
[0024] The first transmission gate Tran1, the second transmission gate Tran2, the third transmission gate Tran3, the fourth transmission gate Tran4 and the fifth transmission gate Tran5 are connected in series to form a sampling switch. The multi-stage transmission gate connection mode is equivalent to increasing the channel length of the switch, which significantly reduces the phase noise and suppresses the feedthrough of the reference signal compared with directly using a long-gate-size switch.
[0025] Specifically, the channel width of the first transmission gate Tran1, the second transmission gate Tran2, the third transmission gate Tran3, the fourth transmission gate Tran4 and the fifth transmission gate Tran5 decreases in a binary manner. For example, the channel width of the first transmission gate Tran1, the second transmission gate Tran2, the third transmission gate Tran3, the fourth transmission gate Tran4 and the fifth transmission gate Tran5 is 100μm, 50μm, 25μm, 12.5μm and 6.25μm respectively, and the channel length of each of the gates is 30nm.
[0026] Specifically, when the negative-phase signal V PULS_N is 1 and the positive-phase signal V PULS_P is 0, the switch is turned on to charge the sampling capacitor C1; when the negative-phase signal V PULS_N is 0 and the positive-phase signal V PULS_P is 1, the switch is turned off, and the sampling capacitor C1 is in a holding stage.
[0027] Please refer to Figure 5 , Figure 5 The phase noise comparison diagram of the sampling phase detector provided by the embodiment of the application is shown in the figure. The phase noise of the sampling phase detector of the embodiment is 0.5dBc / Hz@1MHz, which is much lower than the phase noise of the prior art. Figure 5It can be seen that, compared with the traditional MSS-PD, the sampling phase detector of the embodiment reduces the noise at a frequency offset of 1MHz by about 9dBc under the same size.
[0028] The main in-band noise contribution of the type I sampling phase-locked loop is the sampling phase detector, and the conventional method is to improve the phase detection gain to suppress the in-band noise. The embodiment proposes a time domain pulse shaping solution for the in-band noise core contradiction of the type I sampling phase-locked loop, i.e., the phase noise dominant problem of the sampling phase detector. Unlike the linearization idea of improving the phase detection gain through cascading structure of the traditional master-slave sampling architecture MSS-PD, the embodiment uses a single-stage narrow pulse sampling mechanism to realize noise-area collaborative optimization. Specifically, when the sampling pulse is small enough, the instantaneous sampling characteristic of the impulse response is realized, compared with the traditional master-slave sampling phase detector, the device of the sampling module is more than half, the phase noise of the single sampling module can be reduced by more than 6dB in theory, and the area is reduced by more than half.
[0029] Please refer to Figure 6 , Figure 6 A structure diagram of a clock generation module provided by the embodiment of the application. The clock generation module 4 of the embodiment is used for generating picosecond-level ultra-narrow pulses, and includes a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, a first selector MUX1, a second selector MUX2, a third selector MUX3, and an AND gate. The input end of the first inverter INV1 is connected with the first input end of the AND gate and inputs a clock control signal CLK_IN. The first inverter INV1, the second inverter INV2, the third inverter INV3, the fourth inverter INV4, the fifth inverter INV5, the sixth inverter INV6, and the seventh inverter INV7 are connected in series. The output end of the seventh inverter INV7 is connected with the first input end of the first selector MUX1, the output end of the fifth inverter INV5 is connected with the second input end of the first selector MUX1, the output end of the third inverter INV3 is connected with the first input end of the second selector MUX2, and the output end of the first inverter INV1 is connected with the second input end of the second selector MUX2. The output end of the first selector MUX1 is connected with the first input end of the third selector MUX3, the output end of the second selector MUX2 is connected with the second input end of the third selector MUX3, and the output end of the third selector MUX3 is connected with the second input end of the AND gate. The output end of the AND gate outputs a picosecond-level narrow pulse signal V PULS .
[0030] Specifically, the clock signal (i.e. high frequency signal) output by the VCO is first input into the frequency divider 3, the frequency division ratio of the frequency divider 3 is the ratio of the oscillation frequency of the VCO to the reference signal, and the clock control signal CLK_IN output by the frequency divider 3 is input into the clock generation module 4. The clock control signal CLK_IN is delayed by the inverter to generate four signals with delay, and after being selected by the four-to-one selector MUX, the clock control signal CLK_IN is input into the AND gate to generate the picosecond-level ultra-narrow pulse signal required for sampling, the pulse width is 40ps-100ps, and the pulse width difference is less than 5ps under all PVTs.
[0031] The embodiment proposes an ultra-narrow pulse generator to meet the requirement of the ultra-narrow pulse required by the narrow pulse single-stage sampling technology, which can provide sampling clock with various pulse widths of 40ps-100ps, the PVT drift rate of the pulse width is reduced to within ±5%, and the system robustness is significantly improved.
[0032] Please refer to Figure 7 , Figure 7 The structure diagram of the series resonance voltage-controlled oscillator provided by the embodiment of the application is shown in FIG. 1. The series resonance voltage-controlled oscillator (SRVCO) comprises a first MOS transistor M1, a second MOS transistor M2, a first resistor R1, a third MOS transistor M3, a fourth MOS transistor M4, a second resistor R2, a first attenuation capacitor C2, a second attenuation capacitor C3, a parallel resonance inductor LP, a first series resonance inductor LS1, a second series resonance inductor LS2, a first adjustable capacitor C A1 , a second adjustable capacitor C A2 , a first series resonance capacitor array C LP , and a second series resonance capacitor array C LS .
[0033] The source of the first MOS transistor M1 is connected to the ground, the drain is connected to the drain of the second MOS transistor M2 and the first end of the first resistor R1, and the gate is connected to the gate of the second MOS transistor M2 and the second end of the first resistor R1. The source of the second MOS transistor M2 is connected to a power supply voltage. The first MOS transistor M1, the second MOS transistor M2, and the first resistor R1 form a first transimpedance amplifier, which provides a 180-degree phase shift. The input end of the first transimpedance amplifier is connected to the LP_P end of the parallel resonance inductor LP, the first end of the first series resonance capacitor array C LP , and the first end of the first adjustable capacitor C A1 through the first attenuation capacitor C2. The output end is connected to the LS_N end of the first series resonance inductor LS1. The LS_CAPN end of the first series resonance inductor LS1 is connected to the first end of the second series resonance capacitor array C LS .
[0034] The source of the third MOS transistor M3 is connected to ground, the drain is connected to the drain of the fourth MOS transistor M4 and the first end of the second resistor R2, the gate is connected to the gate of the fourth MOS transistor M4 and the second end of the second resistor R2, and the source of the fourth MOS transistor M4 is connected to a power supply voltage. The third MOS transistor M3, the fourth MOS transistor M4 and the second resistor R2 form a second trans-impedance amplifier, and the second trans-impedance amplifier provides a phase shift of 180 degrees. The input end of the second trans-impedance amplifier is connected to the LP_N end of the parallel resonant inductor LP, the second end of the first series resonant capacitor array C LP , the first end of the second adjustable capacitor C A2 , and the output end is connected to the LS_P end of the second series resonant inductor LS2; and the LS_CAPP end of the second series resonant inductor LS2 is connected to the second end of the second series resonant capacitor array C LS .
[0035] The second end of the first adjustable capacitor C A1 and the second end of the second adjustable capacitor C A2 are connected and input an adjustment voltage Vtune.
[0036] Specifically, the first series resonant capacitor array C LP adopts a capacitor array C LP <3:0>, and the second series resonant capacitor array C LS adopts a capacitor array C LS <3:0>.
[0037] Specifically, the series resonant voltage-controlled oscillator 2 can change the capacitance values of the first adjustable capacitor C A1 and the second adjustable capacitor C A2 by adjusting the voltage Vtune, so as to change the output frequency of the oscillator. The frequency of the VCO is determined by the resonant cavity composed of the parallel resonant inductor LP and the first series resonant capacitor array C LP <3:0>, and the resonant cavity composed of the first series resonant inductor LS1, the second series resonant inductor LS2 and the second series resonant capacitor array C LS <3:0>. Specifically, the frequency coverage of the series resonant VCO in the embodiment is 11-12 GHz.
[0038] In the embodiment, the resonator composed of the parallel resonant inductor LP and the first series resonant capacitor array C LP <3:0> has a voltage swing generally greater than 3V, which will cause the trans-impedance amplifier to be overvoltage breakdown, so the first attenuation capacitor C2 and the second attenuation capacitor C3 are connected at both ends thereof, and C2 and C3 divide the voltage with the gate capacitor of the trans-impedance amplifier, thereby reducing the input swing of the trans-impedance amplifier.
[0039] Since the suppression of VCO noise of the type I PLL is half of the type II PLL, the noise performance of the VCO is more stringent. Since the working frequency of other modules is near the reference frequency, the output frequency of the PLL has little effect on the module noise, and the VCO noise will decrease with the increase of the frequency, so the design of the high-frequency VCO is more difficult. The transformer-based series resonant cavity in the embodiment can withstand greater current, generate greater oscillation amplitude, and achieve significant phase noise suppression. At the same frequency, the phase noise level of the VCO is at the leading level.
[0040] Further, the parallel resonant inductor LP, the first series resonant inductor LS1 and the second series resonant inductor LS2 are coupled at the same name end with a coupling coefficient K, and no phase shift is provided, so the total phase shift of the whole loop is 360 degrees, satisfying the Barkhausen criterion of the starting circuit.
[0041] Please refer to Figure 8 , Figure 8 The winding mode schematic diagram of a single-core ultra-small-area transformer inductor provided by the embodiment of the application is shown in the figure. The single-core ultra-small-area transformer is composed of a parallel resonant inductor LP, a first series resonant inductor LS1 and a second series resonant inductor LS2. The winding mode is as follows: the parallel resonant inductor LP is arranged by a plurality of first bending segments along the edges of an octagon, and a distance is provided between the LP_P end and the LP_N end; the first series resonant inductor LS1 and the second series resonant inductor LS2 are both arranged by a plurality of second bending segments surrounding the outer periphery of the parallel resonant inductor LP, and each second bending segment is parallel to the opposite first bending segment; the LS_N end of the first series resonant inductor LS1 is close to the LP_N end of the parallel resonant inductor LP, the LS_P end of the second series resonant inductor LS2 is close to the LP_P end of the parallel resonant inductor LP, and the LS_N end of the first series resonant inductor LS1 is close to the LS_P end of the second series resonant inductor LS2 and a distance is provided between the two; the LS_CAPP end of the first series resonant inductor LS1 is close to the LS_CAPN end of the second series resonant inductor LS2 and a distance is provided between the two.
[0042] It can be understood that the parallel resonant inductor LP is bent along the edges of the octagon to form seven bending segments, and the opening formed between the LP_P end and the LP_N end is an edge of the octagon. The first series resonant inductor LS1 and the second series resonant inductor LS2 surround the outer periphery of the parallel resonant inductor LP and are coupled at the same name end with the parallel resonant inductor LP, i.e., the LS_N end is coupled with the LP_N end, and the LS_P end is coupled with the LP_P end. A distance is provided between the ports of the first series resonant inductor LS1 and the second series resonant inductor LS2.
[0043] Specifically, the coupling coefficient between the parallel resonant inductor LP and the first series resonant inductor LS1 and the second series resonant inductor LS1 is less than 0.15, which meets the demand, and the inductor area is only 200um*300um, which is more than half smaller than the area of the traditional transformer winding mode.
[0044] Please refer to Figure 9 , Figure 9 The phase noise schematic diagram of the series resonant voltage-controlled oscillator provided by the embodiment of the present application is 12GHz. As shown in Figure 9 , the entire VCO has a power consumption of 120mW, and the phase noise can reach-132dBc at 1MHz frequency offset when the frequency is 12GHz, and the noise performance is excellent.
[0045] The sampling phase-locked loop of the present application consists of a sampling phase detector, a series resonant voltage-controlled oscillator, a frequency divider and a clock generation module to form a closed loop. The sampling phase detector uses narrow pulse single sampling, and when the sampling pulse is small enough, the instantaneous sampling characteristics of the impulse response are realized, so that the phase noise of the single sampling module is suppressed, and the area is reduced by more than half. The clock generation module generates picosecond-level narrow pulse signals, which reduces the PVT drift rate of the pulse width and improves the robustness of the system. The series resonant voltage-controlled oscillator based on the transformer can withstand greater current, generate greater oscillation amplitude, and achieve significant phase noise suppression. At the same frequency, the phase noise of the voltage-controlled oscillator is effectively suppressed. Therefore, the sampling phase-locked loop of the present application realizes effective noise suppression, has the advantages of low phase noise, low reference spur and small area.
[0046] The above is a further detailed description of the present application in combination with a specific preferred embodiment, and the specific implementation of the present application cannot be limited to these descriptions. For ordinary skilled persons in the technical field to which the present application belongs, some simple deductions or substitutions can be made without departing from the concept of the present application, and all of them should be regarded as falling within the protection scope of the present application.
Claims
1. A radio frequency millimeter-wave ultra-low noise single-stage sampling phase-locked loop, characterized in that, include: A sampling phase detector (1) is used to instantaneously sample a reference signal based on a picosecond-level narrow pulse signal and output a sampling voltage, wherein the reference signal and the picosecond-level narrow pulse signal have the same frequency; A transformer-based series resonant voltage-controlled oscillator (2) is connected to a sampling phase detector (1) to adjust its oscillation frequency according to the sampling voltage and output a high-frequency signal. Frequency divider (3) is connected to the voltage-controlled oscillator (2) and is used to divide the high-frequency signal and output a clock control signal; The clock generation module (4) is connected to the frequency divider (3) and the sampling phase detector (1) and is used to generate the picosecond-level narrow pulse signal according to the clock control signal.
2. The radio frequency millimeter-wave ultra-low noise single-stage sampling phase-locked loop according to claim 1, characterized in that, The sampling phase detector (1) includes: a first transmission gate (Tran1), a second transmission gate (Tran2), a third transmission gate (Tran3), a fourth transmission gate (Tran4), a fifth transmission gate (Tran5), and a sampling capacitor (C1), wherein, The first transmission gate (Tran1) receives a reference signal (REF) at its signal input terminal; The first transmission gate (Tran1), the second transmission gate (Tran2), the third transmission gate (Tran3), the fourth transmission gate (Tran4), and the fifth transmission gate (Tran5) are connected in series, and all of them are input with a positive phase signal (V). PULS_P The second control input terminal is input with an inverted signal (V). PULS_N ); The output of the fifth transmission gate (Tran5) is connected to one end of the sampling capacitor (C1) and outputs a sampling voltage (VCTRL).
3. The radio frequency millimeter-wave ultra-low noise single-stage sampling phase-locked loop according to claim 2, characterized in that, The channel widths of the first transmission gate (Tran1), the second transmission gate (Tran2), the third transmission gate (Tran3), the fourth transmission gate (Tran4), and the fifth transmission gate (Tran5) decrease in binary order.
4. The radio frequency millimeter-wave ultra-low noise single-stage sampling phase-locked loop according to claim 1, characterized in that, The division ratio of the frequency divider (3) is the ratio of the voltage-controlled oscillator oscillation frequency to the reference signal.
5. The radio frequency millimeter-wave ultra-low noise single-stage sampling phase-locked loop according to claim 1, characterized in that, The clock generation module (4) includes a first inverter (INV1), a second inverter (INV2), a third inverter (INV3), a fourth inverter (INV4), a fifth inverter (INV5), a sixth inverter (INV6), a seventh inverter (INV7), a first selector (MUX1), a second selector (MUX2), a third selector (MUX3), and an AND gate, wherein... The input terminal of the first inverter (INV1) is connected to the first input terminal of the AND gate and receives a clock control signal (CLK_IN); The first inverter (INV1), the second inverter (INV2), the third inverter (INV3), the fourth inverter (INV4), the fifth inverter (INV5), the sixth inverter (INV6), and the seventh inverter (INV7) are connected in series; The output of the seventh inverter (INV7) is connected to the first input of the first selector (MUX1), the output of the fifth inverter (INV5) is connected to the second input of the first selector (MUX1), the output of the third inverter (INV3) is connected to the first input of the second selector (MUX2), and the output of the first inverter (INV1) is connected to the second input of the second selector (MUX2). The output of the first selector (MUX1) is connected to the first input of the third selector (MUX3); the output of the second selector (MUX2) is connected to the second input of the third selector (MUX3). The output of the third selector (MUX3) is connected to the second input of the AND gate; The output of the AND gate outputs the picosecond-level narrow pulse signal (V). PULS ).
6. The radio frequency millimeter-wave ultra-low noise single-stage sampling phase-locked loop according to claim 1 or 5, characterized in that, The picosecond-level narrow pulse signal has a pulse width of 40ps-100ps.
7. The radio frequency millimeter-wave ultra-low noise single-stage sampling phase-locked loop according to claim 1, characterized in that, The series resonant voltage-controlled oscillator (2) includes: a first MOSFET (M1), a second MOSFET (M2), a first resistor (R1), a third MOSFET (M3), a fourth MOSFET (M4), a second resistor (R2), a first attenuation capacitor (C2), a second attenuation capacitor (C3), a parallel resonant inductor (LP), a first series resonant inductor (LS1), a second series resonant inductor (LS2), and a first adjustable capacitor (C). A1 ), second adjustable capacitor (C) A2 ), first series resonant capacitor array (C) LP ) and the second series resonant capacitor array (C LS ),in, The source of the first MOSFET (M1) is grounded, its drain is connected to the drain of the second MOSFET (M2) and the first terminal of the first resistor (R1), and its gate is connected to the gate of the second MOSFET (M2) and the second terminal of the first resistor (R1). The source of the second MOSFET (M2) is connected to the power supply voltage. The first MOSFET (M1), the second MOSFET (M2), and the first resistor (R1) form a first transimpedance amplifier. The input terminal of the first transimpedance amplifier is connected to the LP_P terminal of the parallel resonant inductor (LP) and the first series resonant capacitor array (C) through the first attenuation capacitor (C2). LP The first terminal of ) and the first adjustable capacitor (C) A1 The first terminal of the first series resonant inductor (LS1) is connected to the LS_N terminal of the first series resonant inductor (LS1); the LS_CAPN terminal of the first series resonant inductor (LS1) is connected to the second series resonant capacitor array (C). LS The first end; The source of the third MOSFET (M3) is grounded, its drain is connected to the drain of the fourth MOSFET (M4) and the first terminal of the second resistor (R2), and its gate is connected to the gate of the fourth MOSFET (M4) and the second terminal of the second resistor (R2). The source of the fourth MOSFET (M4) is connected to the power supply voltage. The third MOSFET (M3), the fourth MOSFET (M4), and the second resistor (R2) form a second transimpedance amplifier. The input terminal of the second transimpedance amplifier is connected to the LP_N terminal of the parallel resonant inductor (LP) and the first series resonant capacitor array (C) through the second attenuation capacitor (C3). LP The second terminal of ) and the second adjustable capacitor (C) A2 The first terminal of the first series resonant inductor (LS2) is connected to the LS_P terminal of the second series resonant inductor (LS2); the LS_CAPP terminal of the second series resonant inductor (LS2) is connected to the second series resonant capacitor array (C LS The second end of ); The first adjustable capacitor (C) A1 The second terminal of ) and the second adjustable capacitor (C) A2 The second terminal is connected to and the input adjustment voltage (Vtune) is applied.
8. The radio frequency millimeter-wave ultra-low noise single-stage sampling phase-locked loop according to claim 7, characterized in that, The parallel resonant inductor (LP), the first series resonant inductor (LS1), and the second series resonant inductor (LS2) are coupled at the same terminals.
9. The radio frequency millimeter-wave ultra-low noise single-stage sampling phase-locked loop according to claim 7, characterized in that, The winding method of the parallel resonant inductor (LP), the first series resonant inductor (LS1), and the second series resonant inductor (LS2) is as follows: The parallel resonant inductor (LP) is formed by a number of first bent segments arranged along the sides of an octagon, and there is a distance between the LP_P terminal and the LP_N terminal. Both the first series resonant inductor (LS1) and the second series resonant inductor (LS2) are formed by a plurality of second bends arranged around the periphery of the parallel resonant inductor (LP), and each second bend is parallel to the opposite first bend. The LS_N terminal of the first series resonant inductor (LS1) is coupled to the LP_N terminal of the parallel resonant inductor (LP), and the LS_P terminal of the second series resonant inductor (LS2) is coupled to the LP_P terminal of the parallel resonant inductor (LP). The LS_N terminal of the first series resonant inductor (LS1) and the LS_P terminal of the second series resonant inductor (LS2) are close to each other but are separated by a distance. The LS_CAPP terminal of the first series resonant inductor (LS1) is close to the LS_CAPN terminal of the second series resonant inductor (LS2) and there is a distance between them.
10. The radio frequency millimeter-wave ultra-low noise single-stage sampling phase-locked loop according to claim 1, characterized in that, The frequency range of the series resonant voltage-controlled oscillator (2) is 11-12 GHz.