Solid-state vacuum triode and preparation method thereof

Abstract

A solid-state vacuum triode comprises a substrate, two sides of the top of the substrate are respectively provided with an anode and a cathode, the top of the anode is provided with an anode contact layer in ohmic contact with the anode, the top of the cathode is provided with a cathode contact layer in ohmic contact with the cathode, and a dielectric layer is arranged between the anode contact layer and the cathode contact layer. A groove body is formed in the top surface of the dielectric layer, the groove body is communicated with or not communicated with the vacuum area, and a grid is arranged in the groove body; glass packaging outside a vacuum area of a traditional vacuum triode is replaced with solid materials, the defects that the glass packaging of the traditional vacuum triode is poor in reliability and cannot be miniaturized are overcome, meanwhile, a carrier transport area of a traditional all-solid-state semiconductor triode is vacuumized, the problem that the carrier movement of a solid-state triode is scattered, and the reliability of the solid-state triode is improved is solved. According to the solid-state triode, the unlimited movement of current carriers is combined with the miniaturization of a solid-state structure, so that the conversion power and the working efficiency of a traditional solid-state triode are improved.

Description

Technical Field

[0001] This invention relates to the field of vacuum transistor technology, specifically to a solid-state vacuum transistor and its fabrication method. Background Technology

[0002] Transistors are commonly used three-terminal semiconductor devices with a wide range of applications, especially in various electronic circuits. By strategically connecting transistors with resistors, capacitors, inductors, and other components, circuits with different functions can be constructed, enabling functions such as current amplification. Conventional transistors are made of semiconductor materials such as silicon, selenium, germanium, gallium arsenide, gallium nitride, and silicon carbide. Bipolar junction transistors (BJTs) have three electrodes: emitter, base, and collector. Field-effect transistors (FETs) have a source, gate, and drain. Vacuum transistors (VJTs) have a cathode, gate, and anode. In conventional solid-state transistors, carrier transport within the solid semiconductor material is affected by the solid material's lattice structure, impurities in the solid material, and scattering of the transported carriers themselves, significantly limiting carrier mobility. Furthermore, traditional VJTs, due to their glass tube encapsulation, suffer from poor reliability and cannot be miniaturized.

[0003] In 1962, Hofstein presented "The Silicon Insulated-GateField-Effect Transistor" at the International Electron Devices Conference, discussing issues related to metal-oxide-semiconductor (MOS) structures. His main focus was replacing the reverse-biased PN junction of traditional unipolar transistors with a MOS-controlled structure, which could enhance or deplete the charge near the semiconductor surface. Simultaneously, for cases with thick oxide layers and shallow conductive channels, the paper proposed a simplified model to derive the fundamental current-voltage relationship of transistors, contrasting sharply with the Schock PN junction transistor (corresponding to a structure with extremely thin oxide layers and uniformly deep, deep channel doping). To explain experimental anomalies that the simplified model could not account for, a detailed model was proposed, abandoning the "constant current in the saturation region" approximation and studying the drain resistance characteristics in the saturation region. The relationships derived from this detailed model were highly similar to those of vacuum tubes, and experimental data showed good agreement with theoretical predictions.

[0004] Hofstein's article theoretically constructed a device analysis system, with detailed analytical expressions of the model showing good agreement with experimental data, thus improving the device theory. Devices fabricated at the experimental and application levels exhibited excellent characteristics, with an average wafer yield exceeding 95%, verifying the performance advantages of the novel structure and providing crucial evidence for its large-scale application in the integrated circuit field. However, carriers in MOS devices need to move within the channel, and their mobility is limited by both the inherent properties of the semiconductor material and the device structure: the electron mobility in silicon is only about 1450 cm⁻¹. 2 / (V·s), which is far lower than the electron mobility efficiency in a vacuum environment; at the same time, the interface traps between the MOSFET channel and the gate oxide layer will capture and release carriers, and uneven channel doping concentration and lattice defects will exacerbate carrier scattering, further reducing the actual mobility; in addition, with the miniaturization of device size, the shortening of the channel length will cause a "velocity saturation effect", and the actual carrier mobility will be difficult to reach the level corresponding to the theoretical mobility. Summary of the Invention

[0005] To overcome the shortcomings of the existing technology, the present invention aims to provide a solid-state vacuum transistor and its fabrication method. By replacing the glass encapsulation outside the vacuum region of the traditional vacuum transistor with the solid material of the present invention, the shortcomings of poor reliability and inability to miniaturize the glass encapsulation of the traditional vacuum transistor are solved. At the same time, the transport region of the charge carriers in the traditional all-solid-state semiconductor transistor is vacuumed, which solves the shortcomings of the carrier movement being scattered and the mobility improvement being limited in the solid-state transistor. The combination of unrestricted carrier movement and miniaturization of solid-state structure improves the conversion power and operating efficiency of the traditional solid-state transistor.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A solid-state vacuum transistor includes a substrate 1, with an anode 2 and a cathode 3 respectively disposed on the top two sides of the substrate. An anode contact layer 6 is disposed on the top of the anode 2, forming an ohmic contact with it. A cathode contact layer 7 is disposed on the top of the cathode 3, forming an ohmic contact with it. A dielectric layer 5 is disposed between the anode contact layer 6 and the cathode contact layer 7. A groove 51 is formed on the top surface of the dielectric layer 5. The groove 51 may be connected to or not connected to a vacuum region 4. A gate 8 is disposed within the groove 51. When the groove 51 is not connected to the vacuum region 4, the vacuum region... 4 is formed by a substrate 1, an anode 2, a cathode 3 and a dielectric layer 5, or by a substrate 1, an anode 2, a cathode 3, a dielectric layer 5, an anode contact layer 6 and a cathode contact layer 7; when the tank 51 is connected to the vacuum region 4, the vacuum region 4 is formed by a substrate 1, an anode 2, a cathode 3, a dielectric layer 5 and a gate 8, or by a substrate 1, an anode 2, a cathode 3, a dielectric layer 5, an anode contact layer 6, a cathode contact layer 7 and a gate 8, or by a substrate 1, an anode 2, a cathode 3 and a gate 8.

[0008] Furthermore, the thickness of the anode 2 and the cathode 3 is less than or equal to the depth of the vacuum region 4, and the length of the anode 2 and the cathode 3 is greater than or equal to the length of the anode contact layer 6 and the cathode contact layer 7, respectively; the tank 51 is a groove or a through groove; the depth of the tank 51 is less than or equal to the thickness of the dielectric layer 5, and the length of the tank 51 is less than or equal to the length of the vacuum region 4.

[0009] Furthermore, the anode 2 and the cathode 3 are respectively one of a single-layer structure or a multi-layer heterojunction structure, and the anode 2 and the cathode 3 have the same structure.

[0010] Furthermore, when the anode 2 and cathode 3 are both single-layer structures, the materials of the anode 2 and cathode 3 are respectively one of a metal that can provide electrons, an N-type semiconductor that can provide electrons, or a P-type semiconductor that can provide holes. The materials of the anode 2 and cathode 3 can be the same or different.

[0011] Furthermore, when the anode 2 and cathode 3 are multilayer heterojunction structures, the anode 2 includes a first channel layer 21 and a first barrier layer 22 disposed on top of the first channel layer 21, and the cathode 3 includes a second channel layer 31 and a second barrier layer 32 disposed on top of the second channel layer 32; the first channel layer 21 and the second channel layer 31 are respectively disposed on the top two sides of the substrate 1, and the tops of the first barrier layer 22 and the second barrier layer 32 are respectively in contact with the bottom surfaces of the anode contact layer 6 and the cathode contact layer 7, and the anode contact layer 6 and the cathode contact layer 7 are respectively connected to the two-dimensional structure formed by the multilayer heterojunction structure through alloy or ohmic contact. Electron gas or two-dimensional hole gas are in contact. Vacuum regions 4 are provided between the first channel layer 21 and the second channel layer 31, and between the first barrier layer 22 and the second barrier layer 32. The first channel layer 21 and the first barrier layer 22 are made of two different solid materials that can generate two-dimensional electron gas or two-dimensional hole gas, respectively. The second channel layer 31 and the second barrier layer 32 are made of two different solid materials that can generate two-dimensional electron gas or two-dimensional hole gas, respectively. The materials of the first channel layer 21 and the second channel layer 31 can be the same or different, and the materials of the first barrier layer 22 and the second barrier layer 32 can be the same or different.

[0012] Furthermore, the material of the substrate 1 is one of the intrinsic semiconductors, including but not limited to silicon, germanium, gallium arsenide, gallium nitride, and silicon carbide.

[0013] Furthermore, the dielectric layer 5 is made of one of the insulating dielectric materials compatible with semiconductor processes, including but not limited to silicon dioxide, silicon nitride, aluminum oxide, low dielectric constant materials, and high dielectric constant materials.

[0014] Furthermore, the materials of the anode contact layer 6 and the cathode contact layer 7 are respectively polycrystalline silicon, a metal capable of providing electrons, and a multilayer metal. The materials of the anode contact layer 6 and the cathode contact layer 7 may be the same or different.

[0015] Furthermore, the material of the gate 8 is one of polycrystalline silicon, a metal that can provide electrons, or a multilayer metal. The gate 8 controls the transport of charge carriers from the cathode 3 to the anode 2 and controls the magnitude of the charge carrier formation current.

[0016] A method for fabricating a solid-state vacuum transistor includes the following steps:

[0017] Step S1: Using doping, bottoming, epitaxial, or heterojunction epitaxial processes, adjacent anode and cathode layers of the same or different materials are formed on the top surface of substrate 1.

[0018] When anode 2 and cathode 3 are both single-layer structures, adjacent anode and cathode layers of the same or different materials are formed on the top surface of substrate 1 using doping or bottoming processes. The anode and cathode layers are respectively one of metal or N-type semiconductor that can provide electrons, or one of P-type semiconductor that can provide holes.

[0019] When the anode 2 and cathode 3 are both multilayer heterojunction structures, an adjacent first solid material layer and a second solid material layer with the same or different materials are first formed on the top surface of the substrate 1 using an epitaxial process. Then, an adjacent third solid material layer and a fourth solid material layer with the same or different materials are formed on the top surface of the first solid material layer and the second solid material layer using a heterojunction epitaxial process. The first solid material layer and the third solid material layer constitute the anode layer, and the second solid material layer and the fourth solid material layer constitute the cathode layer. The first solid material and the third solid material are two different solid materials that can generate two-dimensional electron gas or two-dimensional hole gas, respectively. The second solid material and the fourth solid material are two different solid materials that can generate two-dimensional electron gas or two-dimensional hole gas, respectively.

[0020] Step S2: Using an etching process, the middle region between the anode layer and the cathode layer is etched away under vacuum conditions, or the middle region between the anode layer and the cathode layer, as well as the middle region of the top surface of the substrate 1, is etched away to form a vacuum region 4. The remaining anode layer and cathode layer serve as anode 2 and cathode 3, respectively.

[0021] Step S3: Under vacuum conditions, an insulating dielectric layer compatible with semiconductor processes is deposited onto the top surfaces of the anode 2, cathode 3, and vacuum region 4 using a deposition process.

[0022] Step S4: Use an etching process to etch away the two ends of the insulating dielectric layer to form two windows that are ohmically in contact with the anode 2 and the cathode 3 respectively. The remaining insulating dielectric layer is used as dielectric layer 5.

[0023] Step S5: Within the windows of the two phase ohmic contacts, a polycrystalline silicon layer or a metal layer or a multilayer metal layer capable of providing electrons is formed using a deposition process, respectively, as the anode contact layer 6 and the cathode contact layer 7.

[0024] Step S6: Using an etching process, a trench 51 that is connected to or not connected to the vacuum region 4 is etched on the top surface of the dielectric layer 5. Then, a polysilicon layer or a metal layer or a multilayer metal layer that can provide electrons is formed in the trench 51 by a deposition process to serve as the gate 8.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] 1. This invention provides a solid-state vacuum transistor. A substrate 1 made of intrinsic semiconductor material is disposed at the bottom of a vacuum region 4. An anode 2 and a cathode 3 made of a metal material or N-type semiconductor material capable of providing electrons, or a P-type semiconductor material or solid material capable of providing holes, are disposed on both sides of the vacuum region 4 in the horizontal direction. A dielectric layer 5 made of an insulating dielectric material compatible with semiconductor processes is covered on the top of the vacuum region 4. An anode contact layer 6 and a cathode contact layer 7 made of polycrystalline silicon, a metal material capable of providing electrons, or a multilayer metal material are disposed on both sides of the dielectric layer 5. A gate 8 is disposed within a groove 51 formed at the top of the dielectric layer 5. By replacing the glass encapsulation outside the vacuum region 4 of a conventional vacuum transistor with the solid-state material of this invention, i.e., by solidifying the anode 2 and cathode 3, the shortcomings of poor reliability and inability to miniaturize the glass encapsulation of conventional vacuum transistors are solved. This allows the solid-state vacuum transistor of this invention to be fabricated using the miniaturization or integration of solid-state transistors.

[0027] 2. This invention eliminates the shortcomings of traditional solid-state transistors under high power conditions, such as the scattering of charge carriers and limited mobility due to the transport region of charge carriers in solid materials, by vacuuming the carrier transport region of traditional all-solid-state semiconductor transistors, thereby improving the conversion power of traditional all-solid-state semiconductor transistors.

[0028] 3. Compared with existing silicon-based conventional MOSFETs, the solid-state vacuum transistor of the present invention has a faster carrier movement speed. Under the same gate-source voltage, the drain current of the solid-state vacuum transistor is larger than that of the silicon-based conventional MOSFET at the same source-drain voltage. It has a stronger current carrying capacity and a smaller on-resistance, which significantly reduces conduction loss and temperature rise, thereby improving energy efficiency and enhancing device reliability and lifespan.

[0029] In summary, the solid-state vacuum transistor electrode designed in this invention can emit electrons to form an electron current, or emit holes to form a hole current, or emit a two-dimensional electron gas to form an electron current, or emit a two-dimensional hole gas to form a hole current. Electrons or holes are mainly transported in a vacuum environment, which solves the shortcomings of traditional solid-state transistors where the carrier motion is limited by the scattering of solid materials, thus improving the carrier transport speed and the operating frequency of the transistor. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the solid-state vacuum transistor of the present invention. Figure 1 ;in, Figure 1 (a) in the image is the front view of the solid-state vacuum transistor. Figure 1 ; Figure 1 (b) in the image is the left view of the solid-state vacuum transistor. Figure 1 ; Figure 1 (c) in the image is a top view of the solid-state vacuum transistor. Figure 1 ; Figure 1 (d) in the figure represents the right view of the solid-state vacuum transistor. Figure 1 .

[0031] Figure 2 This is a partial structural diagram of the solid-state vacuum transistor of the present invention. Figure 1 .

[0032] Figure 3 This is a partial structural diagram of the solid-state vacuum transistor of the present invention. Figure 2 .

[0033] Figure 4 This is the front view of the solid-state vacuum transistor of the present invention. Figure 2 .

[0034] Figure 5 This is the front view of the solid-state vacuum transistor of the present invention. Figure 3 .

[0035] Figure 6 This is the front view of the solid-state vacuum transistor of the present invention. Figure 4 .

[0036] Figure 7 This is the front view of the solid-state vacuum transistor of the present invention. Figure 5 .

[0037] Figure 8 This is the front view of the solid-state vacuum transistor of the present invention. Figure 6 .

[0038] Figure 9 This is the front view of the solid-state vacuum transistor of the present invention. Figure 7 .

[0039] Figure 10 Top view of the solid-state vacuum transistor of the present invention Figure 2 .

[0040] Figure 11 This is a schematic diagram of the solid-state vacuum transistor of the present invention. Figure 2 ;in, Figure 11 (a) in the image is the front view of the solid-state vacuum transistor. Figure 8 ; Figure 11 (b) in the image is the left view of the solid-state vacuum transistor. Figure 2 ; Figure 11 (c) in the image is a top view of the solid-state vacuum transistor. Figure 3 ; Figure 11 (d) in the figure represents the right view of the solid-state vacuum transistor. Figure 2 .

[0041] Figure 12 This is a comparison of the forward conduction current-voltage characteristic curves of the solid-state vacuum transistor and the silicon-based conventional MOSFET under different gate voltages.

[0042] In the figure: 1. Substrate; 2. Anode; 21. First channel layer; 22. First barrier layer; 3. Cathode; 31. Second channel layer; 32. Second barrier layer; 4. Vacuum region; 5. Dielectric layer; 51. Tank; 6. Anode contact layer; 7. Cathode contact layer; 8. Gate. Detailed Implementation

[0043] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0044] See Figure 1-11 A solid-state vacuum transistor includes a substrate 1, with an anode 2 and a cathode 3 respectively disposed on the top two sides of the substrate. An anode contact layer 6 is disposed on the top of the anode 2 in ohmic contact with it, and a cathode contact layer 7 is disposed on the top of the cathode 3 in ohmic contact with it. A dielectric layer 5 is disposed between the anode contact layer 6 and the cathode contact layer 7. A groove 51 is formed on the top surface of the dielectric layer 5. The groove 51 may be connected to or not connected to a vacuum region 4. A gate 8 is disposed within the groove 51. When the groove 51 is not connected to the vacuum region 4, the vacuum region... Domain 4 is formed by a substrate 1, an anode 2, a cathode 3 and a dielectric layer 5, or by a substrate 1, an anode 2, a cathode 3, a dielectric layer 5, an anode contact layer 6 and a cathode contact layer 7; when the tank 51 is in communication with the vacuum region 4, the vacuum region 4 is formed by a substrate 1, an anode 2, a cathode 3, a dielectric layer 5 and a gate 8, or by a substrate 1, an anode 2, a cathode 3, a dielectric layer 5, an anode contact layer 6, a cathode contact layer 7 and a gate 8, or by a substrate 1, an anode 2, a cathode 3 and a gate 8.

[0045] This invention provides a solid-state vacuum transistor, comprising three electrodes: an anode 2, a cathode 3, and a gate 8. The anode 2 and cathode 3 are made of metal or N-type semiconductor capable of providing electrons, or P-type semiconductor or solid material capable of providing holes, respectively. A vacuum region 4 is located between the anode 2 and cathode 3. The dielectric layer 5 on top of the anode 2, cathode 3, and vacuum region 4 mainly serves as electrical isolation. At the same time, the anode 2 and cathode 3 form ohmic contacts with the anode contact layer 6 and cathode contact layer 7, respectively, and lead out electrodes. The gate 8 is located in the groove 51 of the dielectric layer 5. The gate 8 can control the transport of charge carriers from the cathode 3 to the anode 2 and control the magnitude of the charge carrier current, thus having the performance of amplifying current and switching current.

[0046] See Figure 1-11 This invention provides several different embodiments of solid-state vacuum transistors. To ensure that electrons or holes emitted by the anode 2 or cathode 3 are transported entirely within the vacuum region 4, the thicknesses of the anode 2 and cathode 3 located on both sides of the vacuum region 4 in the horizontal direction are less than or equal to the depth of the vacuum region 4, that is, the bottom heights of the anode 2 and cathode 3 are greater than or equal to the bottom heights of the vacuum region 4, and the top heights of the anode 2 and cathode 3 are less than or equal to the top heights of the vacuum region 4. At the same time, to ensure that the anode 2 and cathode 3 form ohmic contacts with the anode contact layer 6 and cathode contact layer 7 respectively, the lengths of the anode 2 and cathode 3 are greater than or equal to the lengths of the anode contact layer 6 and cathode contact layer 7 respectively.

[0047] See Figure 2 and Figure 3 The groove 51 is a groove or a through groove; the depth of the groove 51 is less than or equal to the thickness of the dielectric layer 5, and the length of the groove 51 is less than or equal to the length of the vacuum region 4, thereby ensuring that the gate 8 is electrically isolated from the anode 2 and the cathode 3 respectively.

[0048] The anode 2 and cathode 3 are either single-layer structures or multi-layer heterojunction structures, and the structures of anode 2 and cathode 3 are identical. When it is a single-layer structure, anode 2 and cathode 3 provide electron or hole carriers. When it is a multi-layer heterojunction structure, anode 2 and cathode 3 provide two-dimensional electron gas or two-dimensional hole gas. Whether it is electron, two-dimensional electron gas, hole, or two-dimensional hole gas, they are all carriers for forming the transistor. Electrons need to be formed by anode 2 and cathode 3 through metal or N-type doped semiconductors, and holes need to be formed by anode 2 and cathode 3 through P-type doped semiconductors. Two-dimensional electron gas or two-dimensional hole gas can be generated by forming a heterojunction from undoped multi-layer solid materials, thus avoiding the material doping process.

[0049] When anode 2 and cathode 3 are both single-layer structures, the materials of anode 2 and cathode 3 are respectively one of a metal capable of donating electrons, an N-type semiconductor capable of donating electrons, and a P-type semiconductor capable of donating holes. The materials of anode 2 and cathode 3 can be the same or different. If the materials of anode 2 and cathode 3 are respectively one of an N-type semiconductor capable of donating electrons or a P-type semiconductor capable of donating holes, the doping concentration of anode 2 and cathode 3 is equal, both greater than 10. 18 cm -3 Semiconductor materials with varying doping concentrations.

[0050] The metals capable of providing electrons include, but are not limited to, aluminum, copper, gold, silver, and platinum, which are compatible with semiconductor processes in the periodic table; the N-type semiconductors capable of providing electrons include, but are not limited to, N-type semiconductors formed by doping elemental semiconductors germanium and silicon, or N-type semiconductors formed by doping compound semiconductors gallium arsenide, indium phosphide, and silicon carbide; the P-type semiconductors capable of providing holes include, but are not limited to, P-type semiconductors formed by doping elemental semiconductors germanium and silicon, or P-type semiconductors formed by doping compound semiconductors gallium arsenide, indium phosphide, and silicon carbide.

[0051] When the electrode materials of anode 2 and cathode 3 are metals or N-type semiconductors capable of providing electrons, and when the potential of anode 2 is higher than that of cathode 3, electrons emitted by thermionic electrons from cathode 3 move towards anode 2 under the influence of the electric field, forming an electron flow. When the gate 8 has a certain positive voltage, electrons emitted from cathode 3 are accepted by the gate 8, and anode 2 cannot collect electrons to form a current, so the solid-state vacuum transistor is in the off state. Therefore, the gate 8 can be used as a current switch to control anode 2 and cathode 3. When the materials of anode 2 and cathode 3 are P-type semiconductors, and when the potential of anode 2 is higher than that of cathode 3, holes emitted by thermionic electrons from anode 2 move towards cathode 3 under the influence of the electric field, forming a hole current. When the gate 8 has a certain voltage, holes emitted from anode 2 are accepted by the gate 8, and cathode 3 cannot collect holes to form a current, so the solid-state vacuum transistor is in the off state.

[0052] See Figure 11When the anode 2 and cathode 3 are multilayer heterojunction structures, the anode 2 includes a first channel layer 21 and a first barrier layer 22 disposed on top of the first channel layer 21, and the cathode 3 includes a second channel layer 31 and a second barrier layer 32 disposed on top of the second channel layer 32. The first channel layer 21 and the second channel layer 31 are respectively disposed on the top two sides of the substrate 1. The tops of the first barrier layer 22 and the second barrier layer 32 are in contact with the bottom surfaces of the anode contact layer 6 and the cathode contact layer 7, respectively. The anode contact layer 6 and the cathode contact layer 7 are in contact with the two-dimensional electron gas or two-dimensional hole gas formed by the multilayer heterojunction structure through alloy or ohmic contact. Vacuum regions 4 are provided between the first channel layer 21 and the second channel layer 31 and between the first barrier layer 22 and the second barrier layer 32.

[0053] The first channel layer 21 and the first barrier layer 22 are made of two different solid materials capable of generating two-dimensional electron gas or two-dimensional hole gas, respectively. The second channel layer 31 and the second barrier layer 32 are also made of two different solid materials capable of generating two-dimensional electron gas or two-dimensional hole gas, respectively. The materials of the first channel layer 21 and the second channel layer 31 can be the same or different, and the materials of the first barrier layer 22 and the second barrier layer 32 can be the same or different. The first channel layer 21 and the second channel layer 31 can be undoped solid materials, or they can both have a density greater than 10. 18 cm -3 Semiconductor materials with varying doping concentrations; the first barrier layer 22 and the second barrier layer 32 can be undoped solid materials, or both can have a doping concentration greater than 10. 18 cm -3 Semiconductor materials with varying doping concentrations.

[0054] When the electrode materials of anode 2 and cathode 3 are two different solid materials capable of generating two-dimensional electron gas or two-dimensional hole gas, respectively, the turn-off and current transport process of the solid-state vacuum transistor is the same as that of a single-layer structure for electron and hole transport. The gate 8 can be used as a current switch to control the anode 2 and cathode 3. In addition, the magnitude of the current formed by electrons or holes emitted from cathode 2 to anode 3 can also be adjusted by the voltage of the gate 8. Therefore, the solid-state vacuum transistor has an amplification effect.

[0055] The two different solid materials capable of generating two-dimensional electron gas or two-dimensional cavitation gas include, but are not limited to, gallium arsenide / aluminum gallium arsenide and gallium nitride / aluminum gallium nitride.

[0056] The substrate 1 is made of an intrinsic semiconductor material, including but not limited to silicon, germanium, gallium arsenide, gallium nitride, and silicon carbide.

[0057] The vacuum region 4 is a vacuum state and does not contain any matter. The range of the vacuum region is designed according to the characteristics of the solid-state vacuum transistor.

[0058] The dielectric layer 5 is made of one of the insulating dielectric materials compatible with semiconductor processes, including but not limited to silicon dioxide, silicon nitride, aluminum oxide, low dielectric constant materials, and high dielectric constant materials; the low dielectric constant materials include but are not limited to organosilicon, silicon fluoride, and polyimide; the high dielectric constant materials include but are not limited to hafnium oxide.

[0059] The anode contact layer 6 and cathode contact layer 7 are made of polycrystalline silicon, an electron-donating metal, or a multilayer metal, respectively. The materials of the anode contact layer 6 and cathode contact layer 7 may be the same or different. The electron-donating metal includes, but is not limited to, aluminum, copper, gold, silver, and platinum, which are compatible with semiconductor processes in the periodic table. The multilayer metal includes, but is not limited to, titanium / aluminum / nickel / gold and nickel / gold. The purpose of the multilayer metal is primarily to form ohmic contacts with the multilayer heterojunction structure.

[0060] To avoid Schottky or PN junction contacts between the anode contact layer 6 and the cathode contact layer 7 and the anode 2 and cathode 3, respectively, when selecting materials for the anode contact layer 6 and the cathode contact layer 7, alloy or ohmic contacts with the corresponding anode 2 and cathode 3 are required. For example, N-type polysilicon can form an ohmic contact with N-type silicon semiconductor electrode materials, P-type polysilicon can form an ohmic contact with P-type silicon semiconductor electrode materials, or highly doped germanium can form an ohmic contact with germanium electrode materials, or metal can form an ohmic contact with germanium semiconductor electrodes, or multilayer metal can form an ohmic contact with semiconductors such as gallium nitride and silicon carbide, or metal can form an ohmic contact with metal electrodes, etc.

[0061] The gate 8 is made of polycrystalline silicon, an electron-donating metal, or a multilayer metal. The gate 8 controls the transport of charge carriers from the cathode 3 to the anode 2 and controls the magnitude of the charge carrier formation current. The electron-donating metal material includes, but is not limited to, aluminum, copper, gold, silver, and platinum, which are compatible with semiconductor processes in the periodic table. The multilayer metal includes, but is not limited to, titanium / aluminum / nickel / gold and nickel / gold.

[0062] A method for fabricating a solid-state vacuum transistor includes the following steps:

[0063] Step S1: Using doping, bottoming, epitaxial, or heterojunction epitaxial processes, adjacent anode and cathode layers of the same or different materials are formed on the top surface of substrate 1; the substrate 1 includes, but is not limited to, silicon substrates, germanium substrates, or silicon carbide substrates.

[0064] When anode 2 and cathode 3 are both single-layer structures, adjacent anode and cathode layers of the same or different materials are formed on the top surface of substrate 1 using doping or bottom-dip processes. The anode and cathode layers are respectively one of a metal or N-type semiconductor that can provide electrons, or a P-type semiconductor that can provide holes. The doping process specifically includes ion implantation or diffusion processes.

[0065] For example, silicon semiconductor doping processes can be used to form adjacent N-type semiconductor layers and P-type semiconductor layers, or two adjacent N-type semiconductor layers or two adjacent P-type semiconductor layers on a silicon substrate; epitaxial processes can be used to form adjacent epitaxial N-type semiconductor layers and P-type semiconductor layers, or two adjacent N-type semiconductor layers or two adjacent P-type semiconductor layers on a silicon substrate; physical vapor deposition processes can be used to form adjacent aluminum and copper layers, or adjacent aluminum and platinum layers, or two adjacent aluminum layers or two adjacent platinum layers on a silicon or germanium substrate by electron beam evaporation or magnetron sputtering.

[0066] When the anode 2 and cathode 3 are both multilayer heterojunction structures, an adjacent first solid material layer and a second solid material layer with the same or different materials are first formed on the top surface of the substrate 1 using an epitaxial process. Then, an adjacent third solid material layer and a fourth solid material layer with the same or different materials are formed on the top surface of the first solid material layer and the second solid material layer using a heterojunction epitaxial process. The first solid material layer and the third solid material layer constitute the anode layer, and the second solid material layer and the fourth solid material layer constitute the cathode layer. The first solid material and the third solid material are two different solid materials that can generate two-dimensional electron gas or two-dimensional hole gas, respectively. The second solid material and the fourth solid material are two different solid materials that can generate two-dimensional electron gas or two-dimensional hole gas, respectively.

[0067] For example, using an epitaxial process, adjacent gallium arsenide layers and gallium nitride layers, or two adjacent gallium arsenide layers or two adjacent gallium nitride layers, are formed on the top surface of a substrate 1 made of silicon, germanium, silicon carbide, or gallium nitride. Then, using a heterojunction epitaxial process, adjacent aluminum gallium arsenide layers and aluminum gallium nitride layers, or two adjacent aluminum gallium arsenide layers or two adjacent aluminum gallium nitride layers, are formed on the top surface of the adjacent gallium arsenide layers and gallium nitride layers, or two adjacent aluminum gallium arsenide layers or two adjacent aluminum gallium nitride layers, respectively.

[0068] Step S2: Using an etching process, the middle region between the anode layer and the cathode layer is etched away under vacuum conditions, or the middle region between the anode layer and the cathode layer, as well as the middle region of the top surface of the substrate 1, is etched away to form a vacuum region 4. The remaining anode layer and cathode layer serve as anode 2 and cathode 3, respectively. The range of vacuum region 4 is designed according to the characteristic requirements of the solid-state vacuum transistor. The etching process includes, but is not limited to, wet etching, dry etching, and plasma etching.

[0069] When the above step S1 forms adjacent anode and cathode layers of the same material on a silicon substrate, for example, in a single-layer structure, two adjacent N-type semiconductor layers or two adjacent P-type semiconductor layers are formed on the silicon substrate using a silicon semiconductor doping process. In a multilayer heterojunction structure, two adjacent gallium arsenide layers or two adjacent gallium nitride layers are first formed on the top surface of a substrate 1 made of silicon, germanium, silicon carbide, or gallium nitride using an epitaxial process. Then, two adjacent gallium arsenide aluminum layers or two adjacent gallium nitride aluminum layers are formed on the top surface of the two adjacent gallium arsenide layers or the two adjacent gallium nitride layers respectively using a heterojunction epitaxial process. At this time, the anode 2 and cathode 3 of the single-layer structure or the multilayer heterojunction structure after etching are of the same material.

[0070] When the above step S1 forms adjacent anode and cathode layers of different materials on a silicon substrate, for example, in the case of a single-layer structure, adjacent N-type semiconductor layers and P-type semiconductor layers are formed on the silicon substrate using silicon semiconductor doping technology; in the case of a multi-layer heterojunction structure, adjacent gallium arsenide and gallium nitride layers are first formed on the top surface of substrate 1 made of silicon, germanium, silicon carbide, or gallium nitride using an epitaxial process, and then adjacent aluminum gallium arsenide and aluminum gallium nitride layers are formed on the top surface of the adjacent gallium arsenide and gallium nitride layers respectively using a heterojunction epitaxial process. At this time, the materials of the anode 2 and cathode 3 of the single-layer structure or the multi-layer heterojunction structure are different after etching.

[0071] Step S3: Under vacuum conditions, an insulating dielectric layer compatible with semiconductor processes, such as a silicon layer, a silicon nitride layer, or an aluminum oxide layer, is deposited onto the top surfaces of the anode 2, the cathode 3, and the vacuum region 4 using a deposition process; the deposition process includes silicon oxidation processes, such as dry oxygen oxidation, wet oxygen oxidation, and water vapor oxidation processes.

[0072] Step S4: Use an etching process to etch away the two ends of the insulating dielectric layer to form two windows that are ohmically in contact with the anode 2 and the cathode 3 respectively. The remaining insulating dielectric layer is used as dielectric layer 5.

[0073] Step S5: Within the windows of the two phase ohmic contacts, a polycrystalline silicon layer or a metal layer capable of providing electrons (e.g., aluminum layer, copper layer, platinum layer) or a multilayer metal layer (e.g., titanium / aluminum layer, titanium / aluminum / nickel / gold layer) is formed using a deposition process to serve as the anode contact layer 6 and the cathode contact layer 7; the deposition process includes chemical vapor deposition and physical vapor deposition.

[0074] Step S6: Using an etching process, a trench 51 that is connected to or not connected to the vacuum region 4 is etched on the top surface of the dielectric layer 5. Then, a polysilicon layer or a metal layer that can provide electrons (e.g., aluminum layer, copper layer, platinum layer) or a multilayer metal layer (e.g., titanium / aluminum layer, titanium / aluminum / nickel / gold layer) is formed in the trench 51 by a deposition process to serve as the gate 8.

[0075] When the anode and cathode materials are the same, in addition to the above processing method, the present invention also provides a simplified process:

[0076] Step 1: When the anode 2 and cathode 3 are both single-layer structures, a metal layer that can provide electrons, an N-type semiconductor layer that can provide electrons, or a P-type semiconductor layer that can provide holes is formed on the top surface of the substrate 1 using a doping process or a bottom-dip process.

[0077] Since the anode and cathode materials are the same, it is only necessary to form a metal layer that can provide electrons, an N-type semiconductor layer that can provide electrons, or a P-type semiconductor layer that can provide holes on the surface of substrate 1. This is equivalent to the effect of forming adjacent anode and cathode layers of the same material on the surface of substrate 1 in step S1 of the aforementioned unsimplified process.

[0078] For example, N-type or P-type semiconductor layers can be formed on a silicon substrate using silicon semiconductor doping processes, or N-type or P-type semiconductor layers can be epitaxially formed on a silicon substrate using epitaxial processes, or metal layers such as aluminum, copper, or platinum layers can be formed on a silicon or germanium substrate using physical vapor deposition processes via electron beam evaporation or magnetron sputtering.

[0079] When anode 2 and cathode 3 are both heterojunction structures, a fifth solid material layer is generated on the top surface of substrate 1 using an epitaxial process, and then a sixth solid material layer is generated on the top surface of the fifth solid material layer using a heteroepitaxial process; the fifth solid material layer and the sixth solid material layer are two different solid materials capable of generating two-dimensional electron gas or two-dimensional hole gas; for example, when the fifth solid material layer is a gallium arsenide layer, the sixth solid material layer is a gallium aluminum arsenide layer, and when the fifth solid material layer is a gallium nitride layer, the sixth solid material layer is a gallium aluminum nitride layer;

[0080] Step 2: Using an etching process, the middle region of the metal that can provide electrons, or the N-type semiconductor that can provide electrons, or the P-type semiconductor that can provide holes, or the heterojunction structure layer formed by the fifth and sixth solid material layers, is etched away. Alternatively, the middle region of the metal that can provide electrons, or the N-type semiconductor that can provide electrons, or the P-type semiconductor that can provide holes, or the heterojunction structure layer formed by the fifth and sixth solid material layers, as well as the middle region of the top surface of substrate 1, is etched away to form vacuum region 4. The regions of the metal layer that can provide electrons, or the N-type semiconductor that can provide electrons, or the P-type semiconductor that can provide holes, or the heterojunction structure layer formed by the fifth and sixth solid material layers, which are retained on both sides, serve as anode 2 and cathode 3, respectively. The range of vacuum region 4 is designed according to the characteristic requirements of the solid-state vacuum transistor.

[0081] Step 3: Under vacuum conditions, a semiconductor-compatible insulating dielectric layer, such as a silicon layer, silicon nitride layer, or aluminum oxide layer, is deposited onto the top surface of the anode 2, cathode 3, and vacuum region 4 using a deposition process.

[0082] Step 4: Use an etching process to etch away the two ends of the insulating dielectric layer to form two windows that are ohmically in contact with the anode 2 and the cathode 3 respectively. The remaining insulating dielectric layer is used as dielectric layer 5.

[0083] Step 5: Within the windows of the two phase ohmic contacts, a polycrystalline silicon layer or a metal layer capable of providing electrons (e.g., aluminum layer, copper layer, platinum layer) or a multilayer metal layer (e.g., titanium / aluminum layer, titanium / aluminum / nickel / gold layer) is formed using a deposition process to serve as the anode contact layer 6 and the cathode contact layer 7.

[0084] Step 6: Use an etching process to etch a trench 51 on the top surface of the dielectric layer 5 that is connected to or not connected to the vacuum region 4. Then, use a deposition process to form a polysilicon layer or a metal layer that can provide electrons (e.g., aluminum layer, copper layer, platinum layer) or a multilayer metal layer (e.g., titanium / aluminum layer, titanium / aluminum / nickel / gold layer) in the trench 51 as the gate 8.

[0085] The specific parameters and procedures of the above preparation process need to be determined in combination with the actual application scenario and needs, and the present invention does not make specific limitations in this regard.

[0086] The working principle of this invention is as follows:

[0087] Electrons or holes, or two-dimensional electron gas or two-dimensional hole gas, are emitted by the cathode 2 or anode 3 of the solid-state vacuum transistor of the present invention. Then, the transport of electrons or holes is controlled by the intermediate gate 8, thereby controlling the switching or current magnitude of the solid-state vacuum transistor of the present invention, and realizing the switching and amplification functions.

[0088] The solid-state vacuum transistor of the present invention is used in the same way as conventional transistors. It can be combined with components such as resistors and capacitors to form a switching circuit for switching current; or it can be combined with components such as resistors, capacitors and inductors to form an amplifying circuit for signal amplification.

[0089] Performance simulation test

[0090] See Figure 12 The forward conduction characteristics of the solid-state vacuum transistor and silicon-based conventional MOSFET of the present invention were tested using TCAD simulation software. The drain current I was measured under different gate voltages (0.5V, 1V, 2V) applied to the two devices. DS Source-drain voltage V GS The changing positive characteristic curve shows that when the same gate-source voltage V is applied to the solid-state vacuum transistor of this invention and the silicon-based conventional MOSFET... GS At the same source-drain voltage V, the solid-state vacuum transistor of the present invention... DS The corresponding drain current I DS Compared to ordinary silicon-based MOSFETs, the larger size indicates that the solid-state vacuum transistor of this invention has a faster carrier velocity, stronger current carrying capacity, and lower on-resistance.

[0091] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions, and improvements made by those skilled in the art within the scope of the technology disclosed in the present invention, and within the spirit and principles of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A solid state vacuum triode, characterized by: The application relates to a substrate (1), the top of the substrate is provided with an anode (2) and a cathode (3) respectively, the top of the anode (2) is provided with an anode contact layer (6) in ohmic contact with the anode (2), the top of the cathode (3) is provided with a cathode contact layer (7) in ohmic contact with the cathode (3), a dielectric layer (5) is arranged between the anode contact layer (6) and the cathode contact layer (7), a groove (51) is formed in the top surface of the dielectric layer (5), the groove (51) is in communication with or not in communication with a vacuum area (4), and a gate electrode (8) is arranged in the groove (51); when the groove (51) is not in communication with the vacuum area (4), the vacuum area (4) is enclosed by the substrate (1), the anode (2), the cathode (3) and the dielectric layer (5), or the vacuum area (4) is enclosed by the substrate (1), the anode (2), the cathode (3), the dielectric layer (5), the anode contact layer (6) and the cathode contact layer (7); when the groove (51) is in communication with the vacuum area (4), the vacuum area (4) is enclosed by the substrate (1), the anode (2), the cathode (3), the dielectric layer (5) and the gate electrode (8), or the vacuum area (4) is enclosed by the substrate (1), the anode (2), the cathode (3), the dielectric layer (5), the anode contact layer (6), the cathode contact layer (7) and the gate electrode (8), or the vacuum area (4) is enclosed by the substrate (1), the anode (2), the cathode (3) and the gate electrode (8).

2. A solid state vacuum triode according to claim 1, characterized in that: The thickness of the anode (2) and the cathode (3) is less than or equal to the depth of the vacuum area (4), and the length of the anode (2) and the cathode (3) is greater than or equal to the length of the anode contact layer (6) and the cathode contact layer (7); the groove (51) is a groove or a through groove; the depth of the groove (51) is less than or equal to the thickness of the dielectric layer (5), and the length of the groove (51) is less than or equal to the length of the vacuum area (4).

3. A solid state vacuum triode according to claim 1, characterized in that: The anode (2) and the cathode (3) are one of a single-layer structure or a multi-layer heterojunction structure, and the anode (2) and the cathode (3) have the same structure.

4. A solid state vacuum triode according to claim 3, characterized in that: When the anode (2) and the cathode (3) are single-layer structures, the materials of the anode (2) and the cathode (3) are one of a metal capable of providing electrons, an N-type semiconductor capable of providing electrons and a P-type semiconductor capable of providing holes, and the materials of the anode (2) and the cathode (3) can be the same or different.

5. A solid state vacuum triode according to claim 3, characterized in that: When the anode (2) and the cathode (3) are a multi-layer heterojunction structure, the anode (2) comprises a first channel layer (21) and a first barrier layer (22) arranged on the top of the first channel layer (21), and the cathode (3) comprises a second channel layer (31) and a second barrier layer (32) arranged on the top of the second channel layer (31); the first channel layer (21) and the second channel layer (31) are respectively arranged on the top of the substrate (1) on both sides, the top of the first barrier layer (22) and the top of the second barrier layer (32) are respectively in contact with the bottom surface of the anode contact layer (6) and the cathode contact layer (7), the anode contact layer (6) and the cathode contact layer (7) are respectively in contact with the two-dimensional electron gas or the two-dimensional hole gas formed by the multi-layer heterojunction structure through alloy or ohmic contact, and the vacuum region (4) is arranged between the first channel layer (21) and the second channel layer (31) and between the first barrier layer (22) and the second barrier layer (32); the materials of the first channel layer (21) and the first barrier layer (22) are two different solid materials capable of generating two-dimensional electron gas or two-dimensional hole gas, the materials of the second channel layer (31) and the second barrier layer (32) are two different solid materials capable of generating two-dimensional electron gas or two-dimensional hole gas, and the materials of the first channel layer (21) and the second channel layer (31) can be the same or different, and the materials of the first barrier layer (22) and the second barrier layer (32) can be the same or different.

6. A solid state vacuum triode according to claim 1, characterized in that: The material of the substrate (1) is one of intrinsic semiconductors, including but not limited to silicon, germanium, gallium arsenide, gallium nitride and silicon carbide.

7. A solid state vacuum triode according to claim 1, characterized in that: The material of the medium layer (5) is one of insulating medium materials compatible with semiconductor processes, including but not limited to silicon dioxide, silicon nitride, aluminum oxide, low dielectric constant materials and high dielectric constant materials.

8. A solid state vacuum triode according to claim 1, characterized in that: The materials of the anode contact layer (6) and the cathode contact layer (7) are one of polysilicon, metals capable of providing electrons and multi-layer metals, and the materials of the anode contact layer (6) and the cathode contact layer (7) can be the same or different.

9. A solid state vacuum triode according to claim 1, characterized in that: The material of the gate (8) is one of polysilicon, metals capable of providing electrons and multi-layer metals, and the gate (8) is used to control the transport of carriers from the cathode (3) to the anode (2) and the size of the current formed by the carriers.

10. A method of making a solid state vacuum triode, characterized by: The method comprises the following steps: Step S1: forming adjacent anode layers and cathode layers with the same or different materials on the top surface of the substrate (1) by using a doping process or a bottom sinking process or an epitaxy process and a heterojunction epitaxy process; When the anode (2) and the cathode (3) are single-layer structures, the adjacent anode layers and cathode layers with the same or different materials are formed on the top surface of the substrate (1) by using a doping process or a bottom sinking process, and the anode layers and the cathode layers are one of metals capable of providing electrons or N-type semiconductors or P-type semiconductors capable of providing holes. When the anode (2) and the cathode (3) are both multi-layer heterojunction structures, first, a first solid material layer and a second solid material layer which are adjacent and have the same or different materials are formed on the top surface of the substrate (1) by epitaxy, and then a third solid material layer and a fourth solid material layer which are adjacent and have the same or different materials are formed on the top surface of the first solid material layer and the second solid material layer by heterojunction epitaxy; the first solid material layer and the third solid material layer constitute the anode layer, and the second solid material layer and the fourth solid material layer constitute the cathode layer; the first solid material and the third solid material are two different solid materials capable of generating two-dimensional electron gas or two-dimensional hole gas, and the second solid material and the fourth solid material are two different solid materials capable of generating two-dimensional electron gas or two-dimensional hole gas; Step S2: the middle regions of the anode layer and the cathode layer are etched away under vacuum by etching, or the middle regions of the anode layer and the cathode layer and the middle region of the top surface of the substrate (1) are etched away, to form a vacuum region (4), and the remaining anode layer and cathode layer are used as the anode (2) and the cathode (3) respectively; Step S3: under vacuum, a layer of insulating medium compatible with semiconductor technology is deposited on the top surface of the anode (2), the cathode (3) and the vacuum region (4) by deposition; Step S4: the two end regions of the insulating medium layer are etched away by etching to form two windows which are ohmic contact with the anode (2) and the cathode (3) respectively, and the remaining insulating medium layer is used as the medium layer (5); Step S5: in the two ohmic contact windows, one of a polysilicon layer, a metal layer capable of providing electrons or a multi-layer metal layer is formed by deposition as the anode contact layer (6) and the cathode contact layer (7) respectively; Step S6: a groove (51) which is connected or not connected with the vacuum region (4) is etched on the top surface of the medium layer (5) by etching, and then one of a polysilicon layer, a metal layer capable of providing electrons or a multi-layer metal layer is formed in the groove (51) by deposition as the gate (8).

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