Interrupt processing method and interrupt processing system
By writing interrupt messages into memory devices, the problem of the limited number of interrupts between the host controller and the processor is solved, and the scalability and efficiency of interrupt handling are improved.
Patent Information
- Application Number
- CN202511437906.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-09
- Publication Date
- 2026-01-02
AI Technical Summary
In the prior art, the transmission of interrupt information between the host controller and the processor relies on physical interrupt signal lines and status registers, resulting in a limited number of interrupts and a high risk of conflicts and delays.
Interrupts are triggered by writing interrupt messages to specific memory addresses. The large space of the memory device is used to store the interrupt messages. The host controller generates the interrupt message and writes it to the memory device. The processor retrieves the interrupt message from the memory device and executes the interrupt handling, thus avoiding the limitations of physical circuitry.
It improves the scalability and efficiency of interrupt handling, avoids the limitation of physical lines on the number of interrupts, and improves the processor's processing efficiency.
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Figure CN121255682A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of interrupt processing, in particular to an interrupt processing method and an interrupt processing system. BACKGROUND
[0002] A processor issues a processing request to a storage device through a host controller, and the host controller feeds back a processing result of the storage device to the processor through an interrupt mechanism. In the related art, the transmission of interrupt information between the host controller and the processor mainly depends on a physical interrupt signal line between the host controller and the processor and a state register inside the host controller. When an interrupt occurs, the processor needs to poll each state register through the physical interrupt signal line to obtain the interrupt information. This results in a limited number of interrupts between the host controller and the processor, and shared interrupts are prone to conflict and delay. SUMMARY
[0003] The present application provides an interrupt processing method and an interrupt processing system, which can trigger an interrupt by writing an interrupt message to a specific memory address, avoid the limitation of the number of interrupts between the host controller and the processor by the physical line, and thus improve the scalability and interrupt processing efficiency.
[0004] The present application provides an interrupt processing method applied to an interrupt processing system, the interrupt processing system comprising a processor, a memory device and a host controller, the processor being connected with the memory device and the host controller, and the host controller being connected with the memory device; wherein the host controller is connected with a storage device.
[0005] The method comprises:
[0006] The host controller generates an interrupt message corresponding to an interrupt event when detecting that the storage device generates the interrupt event;
[0007] The host controller writes the interrupt message into the memory device according to a preset memory address;
[0008] The processor acquires the interrupt message from the memory device according to the preset memory address, and performs interrupt processing according to the interrupt message.
[0009] The present application also provides an interrupt processing system comprising a processor, a memory device and a host controller, the processor being connected with the memory device and the host controller, and the host controller being connected with the memory device; wherein the host controller is connected with a storage device.
[0010] The host controller is configured to generate an interrupt message corresponding to an interrupt event when detecting that the storage device generates the interrupt event, and write the interrupt message into the memory device according to a preset memory address.
[0011] The processor is used for obtaining an interrupt message from the memory device according to a preset memory address, and performing interrupt processing according to the interrupt message.
[0012] The application provides an interrupt processing method applied to an interrupt processing system, wherein the interrupt processing system comprises a processor, a memory device and a host controller, the processor is connected with the memory device and the host controller, and the host controller is connected with the memory device; wherein the host controller is connected with a storage device; the method comprises the following steps: when detecting that the storage device generates an interrupt event, the host controller generates an interrupt message corresponding to the interrupt event; the host controller writes the interrupt message into the memory device according to a preset memory address; and the processor obtains the interrupt message from the memory device according to the preset memory address, and performs interrupt processing according to the interrupt message.
[0013] The application has the beneficial effects that in the interrupt processing system to which the application is applied, when detecting that the storage device generates an interrupt event, the host controller generates an interrupt message corresponding to the interrupt event, and then writes the interrupt message into the memory device according to a preset memory address; and the processor can obtain the interrupt message from the memory device according to the same preset memory address, and perform interrupt processing according to the interrupt message. It can be seen that the application can trigger an interrupt by writing an interrupt message into a specific memory address, without a physical line, so that the application can avoid the limitation of the number of interrupts between the host controller and the processor by the physical line, thereby improving the expansibility and interrupt processing efficiency.
[0014] The application further provides an interrupt processing system, which has the beneficial effects. BRIEF DESCRIPTION OF DRAWINGS
[0015] In order to more clearly illustrate the embodiments of the application, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.
[0016] Figure 1 A structural block diagram of an interrupt processing system provided for the embodiments of the application is shown in the figure.
[0017] Figure 2 A structural block diagram of another interrupt processing system provided for the embodiments of the application is shown in the figure.
[0018] Figure 3 A flowchart of an interrupt processing method provided for the embodiments of the application is shown in the figure.
[0019] Figure 4 A schematic diagram of an interrupt message format provided for the embodiments of the application is shown in the figure.
[0020] Figure 5 A structural block diagram of a host controller is provided for an embodiment of the present application.
[0021] Figure 6 A structural block diagram of an interrupt control module is provided for an embodiment of the present application.
[0022] Figure 7 A flow chart of another interrupt processing method is provided for an embodiment of the present application. DETAILED DESCRIPTION
[0023] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, any other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present application.
[0024] It should be noted that, in the description of the present application, the terms “comprise”, “contain” or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, article or device. The terms “first”, “second” and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.
[0025] In order for those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.
[0026] The processor issues a processing request to the storage device through the host controller, and the host controller feeds back the processing result of the storage device to the processor through the interrupt mechanism. In the related art, the transmission of interrupt information between the host controller and the processor mainly depends on the physical interrupt signal line between the host controller and the processor and the state register inside the host controller. When an interrupt occurs, the processor needs to poll each state register through the physical interrupt signal line to obtain the interrupt information. This results in a limited number of interrupts between the host controller and the processor, and shared interrupts are prone to conflict and delay.
[0027] Therefore, in view of how to improve the scalability and processing efficiency of the interrupt mechanism between the host controller and the processor, the present application can provide an interrupt processing method, which can trigger an interrupt by writing an interrupt message to a specific memory address, avoiding the limitation of the number of interrupts between the host controller and the processor by the physical line, so as to improve the scalability and interrupt processing efficiency.
[0028] First, the interrupt processing system applicable to the embodiment is introduced. Please refer to Figure 1 , Figure 1 The structural block diagram of an interrupt processing system provided by the embodiment of the application is shown in FIG. 1. The system can include a processor, a memory device and a host controller, the processor being connected with the memory device and the host controller, and the host controller being connected with the memory device; wherein the host controller is connected with a storage device.
[0029] It should be noted that the connection among the processor, the memory device and the host controller can be realized through a bus, and the specific type of the bus can be set according to actual application requirements, for example, an AXI bus (Advanced eXtensible Interface) or an AHB bus (Advanced High Performance Bus).
[0030] For example, please refer to Figure 2 , Figure 2 The structural block diagram of another interrupt processing system provided by the embodiment of the application is shown in FIG. 2. In Figure 2 , the eMMC controller is the host controller, and the eMMC device is the storage device. The processor and the eMMC controller can be connected through an AHB bus. In addition, the processor, the eMMC controller and the memory device can be connected through an AXI bus. The functions of the processor, the eMMC controller, the eMMC device, the memory device, the AHB bus and the AXI bus are introduced as follows.
[0031] The processor (for example, an Arm processor) is the core component of the system, responsible for executing instructions, processing data and coordinating the work of other hardware. In the above interrupt processing system, the processor is responsible for issuing system software instructions to the eMMC controller and collecting data and information of the eMMC controller for corresponding processing.
[0032] The eMMC controller is the control host of a peripheral interface, connected to the AHB system bus of an SoC (System On Chip) chip. The processor can access the external eMMC device through the interface.
[0033] The eMMC device is a slave of the whole system, integrating a storage unit (for example, a NAND Flash), a controller and a standard packaging technology, and is widely used in smart phones, tablet computers, Internet of Things devices and embedded systems.
[0034] The memory device realizes the storage of communication data. When performing a write operation on the eMMC device, the processor reads the data of the memory device through the AXI bus and then transmits the data to the eMMC controller through the AXI bus.
[0035] AHB bus provides configuration communication between CPU and eMMC controller, and the CPU mainly implements register configuration of AHB slave of the eMMC controller through the AHB bus. In the PIO mode, the system reads and writes the data to be transmitted through the AHB bus.
[0036] AXI bus provides data communication among the processor, the eMMC controller and the memory device.
[0037] In the above interrupt control system, in order to solve the problems of poor expansibility and low processing efficiency of the interrupt mechanism caused by the physical interrupt signal line between the processor and the host controller, the processor and the host controller can realize the interrupt mechanism through the memory device. Specifically, when the host controller receives the interrupt event fed back by the storage device, the host controller can generate a corresponding interrupt message, and store the interrupt message in the memory device, and the interrupt message contains the information necessary for the processor to execute the interrupt processing. Subsequently, the processor can obtain the interrupt message through the memory device and execute the interrupt processing. Obviously, the memory space provided by the memory device is large and can accommodate more interrupt messages. Therefore, the interrupt mechanism between the host controller and the processor based on the memory device can effectively improve the expansibility and processing efficiency of the interrupt mechanism by using the memory write transaction to replace the physical interrupt line.
[0038] Based on the above system structure description, the interrupt processing method provided by the embodiment will be introduced. Please refer to Figure 3 , Figure 3 The flowchart of the interrupt processing method provided by the embodiment of the present application can include:
[0039] S101, when the host controller detects that the storage device generates an interrupt event, the host controller generates an interrupt message corresponding to the interrupt event.
[0040] In this embodiment, when the storage device completes the processing request (such as data read / write request) issued by the processor, the storage device can generate an interrupt event to return the request processing result to the processor. When the host controller detects that the storage device generates an interrupt event, the host controller can generate an interrupt message corresponding to the interrupt event. The interrupt message contains detailed information of the interrupt event, such as memory address, command sequence number, transmission mode, error interrupt, controller basic information, etc., so that the processor can execute interrupt processing. The processor will execute interrupt processing according to the interrupt message.
[0041] Wherein, the memory address refers to the address of the memory area requested by the processor to the storage device for operation (such as read / write). The command sequence number is the index of the processing command. The transmission mode is the transmission mode used by the storage device in this round of processing, such as aDMA, sDMA, PIO. The error interrupt is the error information generated when the storage device executes the request. The controller basic information is the basic information of the host controller, such as transmission speed, bus width, interrupt type, etc.
[0042] S102, the host controller writes the interrupt message into the memory device according to the preset memory address.
[0043] In this embodiment, the preset memory address is the first address of the memory agreed by the processor to the host controller for storing the interrupt message. In the configuration stage, the processor can configure the preset memory address to the host controller, such as writing into the interrupt controller register of the host controller. In this way, the host controller can write the interrupt message into the memory device according to the preset memory address after obtaining the interrupt message, so that the processor can obtain.
[0044] Specifically, since the memory device can provide a larger memory space for storing multiple interrupt messages, the host controller can write the interrupt messages of at least two interrupt events into the memory device according to the preset memory address. In this way, the processor can take out the interrupt messages of multiple interrupt events from the memory device at a time and perform batch processing, which can effectively improve the processing efficiency of the processor.
[0045] It should be noted that the number of interrupt messages that can be stored in the memory device is not limited in this embodiment, which can be set according to actual application requirements.
[0046] Further, in order to facilitate the processor to read the interrupt message, the preset memory address can also be set according to the interrupt category of the interrupt message or the storage device corresponding to the interrupt message. In this way, the host controller can write each interrupt message into the memory device according to the interrupt type of each interrupt message and the preset memory address corresponding to each interrupt type, or according to the storage device corresponding to each interrupt message and the preset memory address corresponding to each storage device. And the processor can also batch obtain the interrupt messages of a specific interrupt type or the interrupt messages of a specific storage device according to these preset memory addresses, so as to further improve the processing efficiency of the processor.
[0047] Based on this, the host controller writes the interrupt messages of at least two interrupt events into the memory device according to the preset memory address, which can include:
[0048] Step 11: the host controller writes each interrupt message into the memory device according to the interrupt type of each interrupt message and the preset memory address corresponding to each interrupt type.
[0049] In another embodiment, the host controller writes the interrupt messages of the at least two interrupt events into the memory device according to the preset memory address, and the method further comprises:
[0050] Step 21: The host controller writes the interrupt messages into the memory device according to the storage device corresponding to each interrupt message and the preset memory address corresponding to each storage device.
[0051] S103: The processor acquires the interrupt messages from the memory device according to the preset memory address, and performs interrupt processing according to the interrupt messages.
[0052] In this embodiment, the processor can acquire the interrupt messages from the memory device according to the preset memory address, and perform interrupt processing according to the interrupt messages. At this time, the processor does not need to poll the status register of the host controller through the physical interrupt signal line, but can efficiently obtain the interrupt messages from the memory device, and the memory device can store multiple interrupt messages, and the storage quantity of the interrupt messages is not limited by the physical interrupt signal line, so that the processing efficiency of the processor can be effectively improved, and the scalability of the interrupt mechanism can be improved.
[0053] It should be noted that this embodiment does not limit how the processor perceives that the host controller has written the interrupt messages into the memory device, which can be set according to actual application requirements, for example, the preset memory address can be actively detected whether new data is written; for another example, the host controller can actively send a communication signal to the processor after completing the writing of the interrupt messages, and the processor can determine the interrupt trigger after receiving the notification signal, and then acquire the interrupt messages from the memory device according to the preset memory address.
[0054] Based on this, after the host controller writes the interrupt messages into the memory device according to the preset memory address, the method further comprises:
[0055] Step 31: The host controller sends a notification signal to the processor.
[0056] Correspondingly, the processor acquires the interrupt messages from the memory device according to the preset memory address, comprising:
[0057] Step 41: The processor acquires the interrupt messages from the memory device according to the preset memory address when receiving the notification signal.
[0058] Further, since the memory device can store the interrupt messages corresponding to the plurality of interrupt events, the processor can obtain the interrupt messages corresponding to the interrupt events from the memory device according to the preset memory address when receiving the notification signal. For example, when the preset memory address corresponds to the interrupt type of the interrupt event, the processor can read the interrupt messages corresponding to the interrupt type from the memory device according to the preset memory address; when the preset memory address corresponds to the storage device, the processor can read the interrupt messages corresponding to the storage device from the memory device according to the preset memory address.
[0059] Further, the interrupt message can include a plurality of message items arranged in the interrupt message in a preset order, and the message items can include the memory address, the command sequence number, the transmission mode, the error interrupt, and the controller basic information. Further, the processor can parse the message items from the interrupt message and perform the interrupt processing according to the message items.
[0060] For the convenience of understanding the specific form of the interrupt message, please refer to Figure 4 , Figure 4 The above embodiment provides a schematic diagram of the interrupt message format. The meanings of the parts in the interrupt message are shown in the following table:
[0061] Table 1: Interrupt message description table
[0062]
[0063] Table 2: speed description
[0064]
[0065] Table 3: bus_w description
[0066]
[0067] Table 4: intr type description
[0068]
[0069] Table 5: error intr type description
[0070]
[0071] Based on the above embodiments, in the interrupt processing system applicable to the present application, when the host controller detects that the storage device generates an interrupt event, the host controller generates an interrupt message corresponding to the interrupt event, and then writes the interrupt message into the memory device according to a preset memory address. The processor can obtain the interrupt message from the memory device according to the same preset memory address, and perform interrupt processing according to the interrupt message. It can be seen that the present application can trigger an interrupt by writing an interrupt message into a specific memory address without a physical line, so that the limitation of the number of interrupts between the host controller and the processor by the physical line can be avoided, and thus the scalability and interrupt processing efficiency can be improved.
[0072] Based on the above embodiments, the improvement of the internal structure of the host controller is introduced as follows. Please refer to Figure 5 , Figure 5 A structural block diagram of a host controller provided by an embodiment of the present application is shown in FIG. 1. The host controller mainly includes an AHB slave module, an AXI master module, an interrupt control module, a DMA module, a FIFO module, a command control module, and a data control module. Among them:
[0073] The CLK&RST control module: mainly provides a required working clock for the eMMC device; provides a reset signal for the eMMC device; and provides a working clock for the card control module.
[0074] The AHB slave module: receives configuration information and control information of the AHB bus master, and transmits the information to other modules of the eMMC. In the PIO data transmission mode, the AHB slave module reads and writes data of the internal data buffer of the controller.
[0075] The AXI master module: is responsible for data transmission between the eMMC controller interface and the system memory based on the AXI bus protocol. In the SDMA or ADMA mode, the AXI master module reads and writes data of the external DDR module, and transmits the data to the eMMC device. The DMA control module is connected to the system memory through the AXI bus. In the data transmission process, the DMA control module acts as an AXI bus host to access the system storage space.
[0076] The FIFO module: includes required data buffer control logic, is connected to the DMA interface and the data control module of the eMMC controller, and realizes data buffering in two clock domains, one being the eMMC controller clock and the other being the eMMC device clock.
[0077] The command control module: mainly completes command communication between the eMMC host controller interface and the eMMC device. The command control module sends the command of the controller and receives a response, and provides CRC check.
[0078] Data control module: mainly complete eMMC host controller interface and eMMC device between the data communication. Through the data control module sends the output of the controller to receive data, and provide CRC check.
[0079] Interrupt control module: responsible for the management of interrupt signal, the present application mainly improves the interrupt control module and interrupt processing flow. Please refer to Figure 6 , Figure 6 The structure block diagram of an interrupt control module provided by the embodiment of the present application. The interrupt control module of the host controller can include at least an interrupt detection module, an interrupt cache module and an interrupt message generation module, the interrupt detection module is connected with the interrupt cache module, the interrupt cache module is connected with the interrupt message generation module, and the interrupt cache module saves the basic information of the controller. The working process of the interrupt control module is introduced as follows.
[0080] In an embodiment, the method can further include:
[0081] S201, the interrupt detection module combines at least two interrupt source signals into a single interrupt signal when receiving the interrupt source signals of the storage device, and saves the interrupt information of the interrupt signal to the interrupt cache module, and;
[0082] S202, the interrupt message generation module generates an interrupt message according to the interrupt information in the interrupt cache module and the basic information of the host controller.
[0083] In the embodiment, the interrupt detection module can receive the interrupt source signals of each interrupt source (i.e. the storage device) of the eMMC controller, and combine them into one interrupt signal. The interrupt cache module can cache the information of the current interrupt and the basic information of the eMMC controller. The interrupt message generation module generates a message according to the interrupt information in the interrupt cache according to the format of the interrupt message.
[0084] Further, the interrupt control module of the host controller can further include an interrupt register module, which is connected with the interrupt detection module, the interrupt cache module and the interrupt message generation module. In an embodiment, the method can further include:
[0085] S301, the interrupt register module receives the interrupt register configuration issued by the processor, and issues the interrupt register configuration to the interrupt detection module, the interrupt cache module and the interrupt message generation module, so as to configure the working state of the interrupt detection module, the interrupt cache module and the interrupt message generation module.
[0086] In the embodiment, the interrupt register module can receive the register configuration about the interrupt in the AHB slave, output a control signal to each module of the interrupt control module, so as to configure each module.
[0087] Further, the host controller further comprises a bus controller, such as the AXI Master described above. The host controller writes the interrupt message into the memory device according to the preset memory address, which can include:
[0088] S401, the interrupt message generation module controls the bus controller to write the interrupt message into the memory device according to the remote memory access mode at the position corresponding to the preset memory address.
[0089] In the embodiment, after the interrupt message generation module generates the message according to the information of the interrupt in the interrupt cache in the format of the interrupt message, the message can be written into the external system memory through the AXI master. Subsequently, the host controller can send a notification signal to the processor to trigger the processor to perform interrupt processing.
[0090] Further, to be compatible with the traditional interrupt mechanism, the host controller further comprises an interrupt switch logic circuit. In an embodiment, the method can further comprise:
[0091] S501, when the interrupt switch logic circuit is in the first state, the host controller enters the step of generating the interrupt message corresponding to the interrupt event when the interrupt event is detected;
[0092] S502, when the interrupt switch logic circuit is in the second state, the host controller transmits the interrupt information to the processor through the physical interrupt signal line.
[0093] In the embodiment, the interrupt control module can realize a configurable interrupt switch logic circuit to support flexible interrupt switch functions. By switching the circuit state of the interrupt switch logic circuit, the embodiment can realize flexible switching of the interrupt mechanism, that is, it can be switched to the interrupt processing mode provided by the embodiment, and it can also be switched to the traditional mode to be compatible with the traditional interrupt mechanism.
[0094] The above interrupt processing method will be introduced in detail based on the specific flowchart. Please refer to Figure 7 , Figure 7 The flowchart of another interrupt processing method provided by the embodiment of the application can include:
[0095] 1, the system software configures the first address of the interrupt message, which is realized through the AHB bus.
[0096] 2, during the communication process between the eMMC controller and the device, an interrupt event occurs, including command completion, transmission completion, error interrupt and other interrupt types
[0097] 3, the interrupt control module detects the interrupt signal and generates the interrupt signal and the interrupt state according to the interrupt control information.
[0098] 4. Get current controller information, including current data transfer speed, bus width, interrupt type, error interrupt type. If it is a command completion interrupt, get the index of current command, if it is a transfer completion interrupt, get the mode of current transfer, whether it is DMA or PIO, etc.
[0099] 5. According to the obtained controller information, generate an interrupt message in the format of the interrupt message.
[0100] 6. Write the interrupt message into the memory at the interrupt message first address.
[0101] 7. The system software triggers an interrupt.
[0102] 8. The CPU calls an interrupt processing function to process the interrupt.
[0103] Please refer to Figure 1 , Figure 1 A structural block diagram of an interrupt processing system provided by an embodiment of the application, which can include a processor, a memory device and a host controller, the processor being connected with the memory device and the host controller, and the host controller being connected with the memory device; wherein the host controller is connected with the storage device;
[0104] The host controller can be used for generating an interrupt message corresponding to an interrupt event when detecting that the storage device generates the interrupt event; and writing the interrupt message into the memory device according to a preset memory address.
[0105] The processor can be used for obtaining the interrupt message from the memory device according to the preset memory address, and performing interrupt processing according to the interrupt message.
[0106] Optionally, each message item in the interrupt message includes a memory address, a command serial number, a transfer mode, an error interrupt and controller basic information.
[0107] The processor can also be used for parsing each message item from the interrupt message, and performing interrupt processing according to the message item.
[0108] Optionally, the processor can also be used for configuring the preset memory address to the host controller.
[0109] Optionally, the host controller can also be used for sending a notification signal to the processor.
[0110] The processor can also be used for obtaining the interrupt message from the memory device according to the preset memory address when receiving the notification signal.
[0111] Optionally, the host controller can also be used for writing interrupt messages of at least two interrupt events into the memory device according to the preset memory address.
[0112] The processor can also be configured to obtain the interrupt messages corresponding to the interrupt events from the memory device according to the preset memory addresses when the interrupt signals are received.
[0113] Optionally, the host controller can also be configured to:
[0114] write the interrupt messages into the memory device according to the interrupt types of the interrupt messages and the preset memory addresses corresponding to the interrupt types;
[0115] and / or write the interrupt messages into the memory device according to the storage devices corresponding to the interrupt messages and the preset memory addresses corresponding to the storage devices.
[0116] Optionally, the host controller comprises an interrupt detection module, an interrupt cache module and an interrupt message generation module, the interrupt detection module is connected with the interrupt cache module, the interrupt cache module is connected with the interrupt message generation module, and the interrupt cache module stores the controller basic information.
[0117] The interrupt detection module can be configured to, when receiving the interrupt source signals of the storage devices, combine the at least two interrupt source signals into a single interrupt signal, save the interrupt information of the interrupt signal to the interrupt cache module, and
[0118] The interrupt message generation module can be configured to generate the interrupt messages according to the interrupt information in the interrupt cache module and the host controller basic information.
[0119] Optionally, the host controller further comprises an interrupt register module, the interrupt register module is connected with the interrupt detection module, the interrupt cache module and the interrupt message generation module.
[0120] The interrupt register module can be configured to receive the interrupt register configuration issued by the processor, and issue the interrupt register configuration to the interrupt detection module, the interrupt cache module and the interrupt message generation module, so as to configure the working states of the interrupt detection module, the interrupt cache module and the interrupt message generation module.
[0121] Optionally, the interrupt message generation module can also be configured to control the bus controller to write the interrupt messages into the memory device according to the remote memory access mode and the positions corresponding to the preset memory addresses.
[0122] Optionally, the host controller further comprises an interrupt switch logic circuit.
[0123] The host controller can also be configured to:
[0124] when the interrupt switch logic circuit is in the first state, enter the step of generating the interrupt messages corresponding to the interrupt events when the interrupt events are detected.
[0125] When the interrupt switch logic circuit is in the second state, the interrupt information is transmitted to the processor through the physical interrupt signal line.
[0126] Those skilled in the art will further appreciate that the functions of the various examples described herein-based embodiments can be implemented using electronic hardware, computer software, or any combination thereof. To clearly illustrate this interchangeability of hardware and software, various components will be described generally, in one or more specific embodiments. Implementing the functions described herein-based embodiments in hardware and / or in software can be done with an appropriate application-specific integrated circuit (ASIC), for example, for hardware or with an appropriate application-specific software using, for example, object or object-oriented software development languages, which the program code can be written in such software, for example, C. Software should not be construed to cover only software which is in object code form, and thus the actual code can be source code, which includes object code components, or in partially-compiled form, or in other non-object-oriented form (e.g., scripts). For situations in which the functions described herein-based embodiments are implemented in software, such software can be stored in any computer-readable medium, which can be any entity or device (e.g., RAM, ROM, EEPROM, flash memory, disc storage) containing, storing, communicating, or providing the program code. Those skilled in the art will recognize that the examples described herein-based embodiments can be practiced with various computer system configurations, including single-processor or multiprocessor computer systems, mini-computers, mainframe computers, as well as computer systems, networked computer systems, and the like. Any processor scheme can be used for the examples described herein-based embodiments, including a shared bus architecture, a set-associative cache architecture, and the like. It will also be appreciated that the examples described herein-based embodiments can be practiced on instructed computer as well as other programmable data processing apparatus. The examples described herein-based embodiments can be implemented in the form of control logic in software and / or hardware, firmware, or hardware. The software can be stored on or in one or more computer-readable media, such as RAM, ROM, EEPROM, flash memory or a disc storage. The control logic, in hardware and / or software, can operate and perform the processing necessary to implement functions described herein-based embodiments.
[0127] The above has carried on the detailed introduction to the interrupt processing method and the interrupt processing system provided by the present application. The principle and the implementation mode of the present application are described by applying the specific examples in the text. The above example description is only for helping to understand the method of the present application and its core idea. It should be pointed out that, for the ordinary skilled in the art, some improvements and modifications can be made to the present application without departing from the principle of the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.
Claims
1. An interrupt handling method, characterized in that, This is applied to an interrupt handling system, which includes a processor, a memory device, and a host controller. The processor is connected to the memory device and the host controller, and the host controller is connected to the memory device. The host controller is connected to a storage device. The method includes: When the host controller detects an interrupt event generated by the storage device, it generates an interrupt message corresponding to the interrupt event. The host controller writes the interrupt message into the memory device according to a preset memory address; The processor obtains the interrupt message from the memory device according to the preset memory address, and performs interrupt processing according to the interrupt message.
2. The interrupt handling method according to claim 1, characterized in that, The interrupt message includes the memory address, command number, transmission mode, error interrupt, and basic controller information. The step of performing interrupt handling according to the interrupt message includes: The processor parses each message item from the interrupt message and performs interrupt processing according to the message item.
3. The interrupt handling method according to claim 1, characterized in that, Also includes: The processor configures the preset memory address to the host controller.
4. The interruption handling method according to any one of claims 1 to 3, characterized in that, After the host controller writes the interrupt message to the memory device according to the preset memory address, the method further includes: The host controller sends a notification signal to the processor; The processor obtains the interrupt message from the memory device according to the preset memory address, including: When the processor receives the notification signal, it retrieves the interrupt message from the memory device according to the preset memory address.
5. The interrupt handling method according to claim 4, characterized in that, The host controller writes the interrupt message to the memory device according to a preset memory address, including: The host controller writes interrupt messages for at least two interrupt events into the memory device according to a preset memory address; When the processor receives the notification signal, it retrieves the interrupt message from the memory device according to the preset memory address, including: When the processor receives the notification signal, it retrieves the interrupt message corresponding to each interrupt event from the memory device according to the preset memory address.
6. The interrupt handling method according to claim 5, characterized in that, The host controller includes an interrupt detection module, an interrupt cache module, and an interrupt message generation module. The interrupt detection module is connected to the interrupt cache module, and the interrupt cache module is connected to the interrupt message generation module. The interrupt cache module stores basic controller information. The method further includes: When the interrupt detection module receives an interrupt source signal from the storage device, it merges at least two interrupt source signals into a single interrupt signal and saves the interrupt information of the interrupt signal to the interrupt cache module. The interrupt message generation module generates the interrupt message based on the interrupt information in the interrupt cache module and the host controller basic information.
7. The interrupt handling method according to claim 6, characterized in that, The host controller further includes an interrupt register module, which is connected to the interrupt detection module, the interrupt cache module, and the interrupt message generation module. The method further includes: The interrupt register module receives the interrupt register configuration sent by the processor and sends the interrupt register configuration to the interrupt detection module, the interrupt cache module, and the interrupt message generation module to configure the working status of the interrupt detection module, the interrupt cache module, and the interrupt message generation module.
8. The interrupt handling method according to claim 6, characterized in that, The host controller also includes a bus controller; The host controller writes the interrupt message to the memory device according to a preset memory address, including: The interrupt message generation module controls the bus controller to write the interrupt message into the memory device at the location corresponding to the preset memory address using remote memory access.
9. The interrupt handling method according to claim 6, characterized in that, The host controller also includes an interrupt switch logic circuit; The method further includes: When the interrupt switch logic circuit is in the first state, the host controller enters the step of generating an interrupt message corresponding to the interrupt event when an interrupt event is detected. When the interrupt switch logic circuit is in the second state, the host controller transmits interrupt information to the processor through the physical interrupt signal line.
10. An interrupt handling system, characterized in that, It includes a processor, a memory device, and a host controller, wherein the processor is connected to the memory device and the host controller, and the host controller is connected to the memory device; wherein the host controller is connected to a storage device; The host controller is configured to generate an interrupt message corresponding to the interrupt event when an interrupt event is detected in the storage device; and write the interrupt message into the memory device according to a preset memory address. The processor is configured to obtain the interrupt message from the memory device according to the preset memory address, and to perform interrupt processing according to the interrupt message.