SPICE model extraction method for improving reverse bias pn junction leakage current precision

Abstract

The invention relates to an SPICE model extraction method for improving reverse bias pn junction leakage current precision, and the method comprises the steps: adding a mathematical fitting formula related to the size to a key parameter jtssgd for adjusting the reverse bias pn junction leakage current in a BSIM4 model, introducing fitting parameters which are strongly related to the effective channel length, the effective channel width and the device area of a device, and carrying out the extraction of the reverse bias pn junction leakage current precision. The method can accurately capture and fit the complex behavior of the leakage current along with the size change of the device, achieves the accurate modeling of the cut-off leakage current caused by the reverse bias pn junction through the adjustment of the fitting parameters, and improves the simulation precision of the model for the cut-off leakage current of devices of different sizes.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a SPICE model extraction method for improving the accuracy of reverse biased pn junction leakage current. Background Technology

[0002] SPICE (Simulation Program with Integrated Circuit Emphasis) is a powerful general-purpose analog circuit simulator that has been around for decades since its first version was released in 1972. This program is primarily used in integrated circuit circuit analysis. SPICE's netlist format has become the standard industry standard for describing analog and transistor-level circuits. It is mainly used for the design and simulation of analog circuits, mixed-signal circuits, power supply circuits, and other electronic systems in IC design.

[0003] A SPICE model consists of two parts: model equations and model parameters. Model equations, based on semiconductor physics theory, define the mathematical expression of device behavior, enabling tight coupling with simulator algorithms to obtain efficient and accurate analysis results. Model parameters, on the other hand, need to be precisely extracted by modeling engineers based on device theory and experimental data. Currently, commonly used SPICE models in the industry include the BSIM series, PSP, or empirical models (macro models). The analytical accuracy of a SPICE model mainly depends on the source of the model parameters (i.e., the accuracy of the data) and the applicability of the model equations.

[0004] A mature CMOS process technology platform typically includes SPICE modeling of basic components such as MOSFETs, diodes, transistors, MOM capacitors, MIM capacitors, resistors, and MOS variable capacitors. Subsequent PDK (Process Design Kit) development, IP libraries, various standard cell libraries, and even customer-customized chip design development are all based on SPICE model libraries. Among these, the metal-oxide-semiconductor field-effect transistor (MOSFET) is a core component of integrated circuits. Its cutoff drain current (Idoff), i.e., the drain current when the gate-source voltage (Vgs) is zero, is a key parameter for measuring the device's static power consumption and determining the circuit's static operating point. The accuracy of this parameter directly affects the circuit's power consumption performance and stability. Therefore, the degree of matching between the SPICE simulation data of the cutoff drain current and the actual silicon wafer measurement data largely determines the success or failure of the circuit design.

[0005] In the BSIM4 SPICE model, there are generally three ways to fit the cutoff leakage current:

[0006] ① Leakage current caused by gate-induced drain degradation (GIDL);

[0007] ② Subthreshold leakage current;

[0008] ③ Reverse bias pn junction leakage current.

[0009] Among them, ① and ② have built-in binning parameters in BSIM4, which can be used to adjust different lengths / widths of the model; however, the leakage current caused by the reverse bias pn junction does not have a built-in binning parameter, so it is impossible to achieve an accurate match between the measured data and simulation results for different lengths / widths in the model by adjusting the binning parameter.

[0010] like Figure 1 As shown, this figure highlights three main components of the cutoff leakage current (Id) under the same temperature (25℃) and different device sizes (W / L = 0.3 / 10, 0.9 / 0.315, 9 / 9) and bias conditions (Vds). The red dots in the figure represent measured data, the solid red lines represent simulation results from the BSIM4 model, and the numerical boxes in the upper right corner (e.g., 0.00, 0.3125, 0.3124) show the different model parameter set numbers. Figure 1 As shown in (a), it reflects the leakage current fitting caused by gate-induced drain reduction (GIDL). The simulation results of the BSIM4 model agree well with the measured data points, indicating that the GIDL equation and related Binning parameters built into the BSIM4 model are effective and can accurately describe this physical effect. Figure 1 As shown in (b), it reflects the fitting of the subthreshold leakage current. The simulation results are in good agreement with the measured data points, indicating that the BSIM4 model's physical description of subthreshold conduction and its related size scaling parameters are accurate. Figure 1 As shown in (c), it reflects the fitting of the reverse-biased pn junction leakage current. Although the simulated structure and measured data are basically matched for a device of a specific size (W / L = 9 / 9), this precisely hides the shortcomings of the BSIM4 model. The model lacks a size-dependent (binning) description of this type of current, which means that when using the fixed parameters obtained from fitting this large-sized device to simulate devices of other sizes, the results will be severely mismatched.

[0011] Specifically, such as Figure 2As shown, this further systematically demonstrates the aforementioned mismatch problem under different aspect ratios (W / L): the simulation results of traditional model extraction methods cannot simultaneously and accurately fit the cutoff leakage current of devices of other sizes. Although the simulation curves of the model match the measured data well in the conduction region and subthreshold region of the transistor (roughly in the region where Id>10⁻¹⁰A), significant and systematic deviations occur in the deep cutoff region (i.e., Vgs is close to or 0V, and Id<10⁻¹⁰A). The root cause of this systematic deviation is that the reverse bias pn junction leakage current parameter (such as jtsswgd) in the traditional model is a fixed value. Modeling engineers usually use data from a device of a specific size (e.g., the largest size) to fit this parameter. When using this fixed parameter to simulate devices of other sizes (especially small sizes), the simulation results will deviate significantly from the measured data, making it impossible to accurately predict the static power consumption of the chip in actual applications. This brings significant risks and uncertainties to the design of low-power, high-performance chips at advanced process nodes.

[0012] Therefore, there is an urgent need in this field for a SPICE model extraction method that can significantly improve the accuracy of reverse-biased pn junction leakage current modeling, especially its cross-size prediction capability. Summary of the Invention

[0013] The purpose of this invention is to provide a SPICE model extraction method to improve the accuracy of reverse-biased pn junction leakage current, thereby improving the adjustability of cutoff leakage current and achieving accurate modeling of the cutoff leakage current caused by reverse-biased pn junction.

[0014] To achieve the above objectives, this invention provides a SPICE model extraction method for improving the accuracy of reverse-biased pn junction leakage current, comprising:

[0015] Within the BSIM4 model framework, a mathematical fitting formula is added to the parameter jtsswgd used to adjust the reverse bias pn junction leakage current. The mathematical fitting formula is as follows:

[0016] jtsswgd=ojtsswgd+ljtsswgd / lef+wjtsswgd / wef+pjtsswgd / (lef*wef)

[0017] Where lef and wef are the effective channel length and effective channel width of the test structure, respectively, and ojtsswgd, ljtsswgd, wjtsswgd, and pjtsswgd are fitting parameters used to fit the current value of the cutoff leakage current.

[0018] Optionally, ojtsswgd is a benchmark fitting parameter used to characterize the reverse bias pn junction leakage current characteristics of large-size devices where size effects are not significant.

[0019] Optionally, ljtsswgd is a fitting parameter strongly correlated with the effective channel length lef, used to adjust and fit the effect of the reverse bias pn junction leakage current changing with the channel length.

[0020] Optionally, wjtsswgd is a fitting parameter strongly correlated with the effective channel width wef, used to adjust and fit the effect of the reverse bias pn junction leakage current changing with the channel width.

[0021] Optionally, pjtsswgd is a fitting parameter strongly correlated with the effective area lef*wef, used to adjust and fit the synergistic effect of the reverse bias pn junction leakage current as a function of device area.

[0022] Optionally, the SPICE model extraction method for improving the accuracy of reverse-biased pn junction leakage current further includes:

[0023] Actual data on the cutoff leakage current of a series of test structures with different channel lengths and widths were measured.

[0024] Based on the mathematical fitting formula, a set of optimal model parameters ojtsswgd, ljtsswgd, wjtsswgd, and pjtsswgd are extracted using a fitting algorithm.

[0025] The optimal model parameters are integrated into the BSIM4 model file to generate the final SPICE model library.

[0026] Based on the same inventive concept, the present invention also provides an electronic device, comprising:

[0027] Memory, which stores computer programs;

[0028] The processor, which is communicatively connected to the memory, executes the SPICE model extraction method described above for improving the accuracy of reverse-biased pn junction leakage current when calling the computer program.

[0029] Based on the same inventive concept, the present invention also provides a readable storage medium having a computer program stored thereon, which, when executed, enables the SPICE model extraction method described above for improving the accuracy of reverse bias pn junction leakage current.

[0030] Based on the same inventive concept, the present invention also provides a process design package, which includes a SPICE model library extracted and constructed using the SPICE model extraction method described above for improving the accuracy of reverse bias pn junction leakage current. This library is capable of accurately simulating the cutoff leakage current caused by reverse bias pn junction in MOS devices of different sizes.

[0031] Based on the same inventive concept, the present invention also provides an integrated circuit design method that uses a process design package as described above to perform circuit simulation and verification in order to accurately predict and optimize the static power consumption of the circuit.

[0032] The SPICE model extraction method for improving the accuracy of reverse-biased pn junction leakage current provided by this invention has at least the following beneficial effects:

[0033] 1) By attaching a size-related mathematical fitting formula to the key parameter jtsswgd for adjusting the leakage current of the reverse bias pn junction in the BSIM4 model, and introducing fitting parameters ljtsswgd, wjtsswgd, and pjtsswgd that are strongly correlated with the effective channel length lef, effective channel width wef, and device area lef*wef, it is possible to accurately capture and fit the complex behavior of leakage current as the device size changes. By adjusting the fitting parameters, the accurate modeling of the cutoff leakage current caused by the reverse bias pn junction can be achieved, thereby improving the simulation accuracy of the model for the cutoff leakage current of devices of different sizes.

[0034] 2) It can be fully extended within the BSIM4 model framework without changing the model's structure or syntax. The extracted optimal parameters can be directly written into the SPICE model library, and it is 100% compatible with the existing SPICE simulation toolchain. Attached Figure Description

[0035] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0036] Figure 1 A simulation diagram of the BSIM4 model for cutoff leakage current caused by different reasons;

[0037] Figure 2 A schematic diagram of fitting the cutoff leakage current of MOSFETs of different sizes using the traditional BSIM4 model extraction method;

[0038] Figure 3 This is a schematic diagram of the fitting of the cutoff leakage current of MOSFETs of different sizes after adding an external formula according to an embodiment of the present invention;

[0039] Figure 4 This is a comparison of the fitting results of the cutoff leakage current between the traditional model extraction method and the model extraction method proposed in this invention, after local magnification.

[0040] Figure 5 This is a comparison chart showing the fitting trends of cutoff leakage current between the traditional model extraction method and the model extraction method proposed in this invention. Detailed Implementation

[0041] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clearly illustrate the purpose of the embodiments of this invention. Please refer to the accompanying drawings to make the objectives, features, and advantages of this invention more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only used to complement the content disclosed in the specification, for those skilled in the art to understand and read, and are not intended to limit the implementation conditions of this invention. Any modifications to the structure, changes in proportions, or adjustments to the size, if they are the same as or similar to the effects and objectives achieved by this invention, should still fall within the scope of the technical content disclosed in this invention.

[0042] As used herein, the singular forms “a,” “an,” and “the” include plural objects unless otherwise expressly stated. As used herein, the term “or” is generally used to mean “and / or” unless otherwise expressly stated. As used herein, the term “a number” is generally used to mean “at least one” unless otherwise expressly stated. As used herein, the term “at least two” is generally used to mean “two or more” unless otherwise expressly stated.

[0043] This invention provides a SPICE model extraction method to improve the accuracy of reverse-biased pn junction leakage current, comprising:

[0044] Within the BSIM4 model framework, a mathematical fitting formula is added to the parameter jtsswgd used to adjust the reverse bias pn junction leakage current. The mathematical fitting formula is as follows:

[0045] jtsswgd=ojtsswgd+ljtsswgd / lef+wjtsswgd / wef+pjtsswgd / (lef*wef)

[0046] Where lef and wef are the effective channel length and effective channel width of the test structure, respectively, and ojtsswgd, ljtsswgd, wjtsswgd, and pjtsswgd are fitting parameters used to fit the current value of the cutoff leakage current.

[0047] In this embodiment, the test structure is a MOSFET device. `ojtsswgd` is a baseline fitting parameter used to characterize the reverse-biased pn junction leakage current characteristics of large-size devices where size effects are not significant. `ljtsswgd` is a fitting parameter strongly correlated with the effective channel length `lef`, used to adjust and fit the effect of the reverse-biased pn junction leakage current changing with the channel length. `wjtsswgd` is a fitting parameter strongly correlated with the effective channel width `wef`, used to adjust and fit the effect of the reverse-biased pn junction leakage current changing with the channel width. `pjtsswgd` is a fitting parameter strongly correlated with the effective area `lef*wef`, used to adjust and fit the synergistic effect of the reverse-biased pn junction leakage current changing with the device area.

[0048] This invention adds a size-related mathematical fitting formula to the key parameter jtsswgd for adjusting the leakage current of the reverse-biased pn junction in the BSIM4 model. It introduces fitting parameters ljtsswgd, wjtsswgd, and pjtsswgd, which are strongly correlated with the effective channel length eef, the effective channel width wef, and the device area eef*wef. This allows for the accurate capture and fitting of the complex behavior of leakage current as it changes with device size. By adjusting the fitting parameters, the accurate modeling of the cutoff leakage current caused by the reverse-biased pn junction is achieved, thereby improving the simulation accuracy of the model for the cutoff leakage current of devices of different sizes.

[0049] Preferably, the SPICE model extraction method for improving the accuracy of reverse-biased pn junction leakage current further includes:

[0050] Actual data on the cutoff leakage current of a series of test structures with different channel lengths and widths were measured.

[0051] Based on the mathematical fitting formula, a set of optimal model parameters ojtsswgd, ljtsswgd, wjtsswgd, and pjtsswgd are extracted using a fitting algorithm.

[0052] The optimal model parameters are integrated into the BSIM4 model file to generate the final SPICE model library.

[0053] The method provided in this embodiment is a complete extension within the BSIM4 model framework, without changing the structure or syntax of the model itself. The extracted optimal parameters can be directly written into the SPICE model library, and are 100% compatible with the existing SPICE simulation toolchain.

[0054] The model fitting result after adjusting the above fitting parameters is as follows: Figure 3 As shown, Figure 3The transfer characteristic curves of PMOS transistors with different channel widths W and lengths L are shown at a fixed drain-source voltage Vds = -2.5V. Compared to Figure 2 The traditional BSIM4 model extraction method was used to extract the fitting results of the cutoff leakage current of MOSFETs of different sizes. The simulation curve of the cutoff leakage current obtained by the present invention after optimization by the external mathematical fitting formula is more consistent with the actual device data, which verifies the effectiveness of the external mathematical fitting formula and improves the simulation accuracy.

[0055] To make the fitting situation clearer, such as Figure 4 As shown, Figure 4 The diagram illustrates a comparison of the fitting results between the traditional model extraction method and the model extraction method proposed in this invention, after local magnification. The solid line represents the simulation results without the added fitting formula, while the dashed line represents the simulation results after adding the mathematical fitting formula. Clearly, while maintaining the maximum MOS cutoff leakage current unchanged, adding the mathematical fitting formula significantly improves the fitting results for cutoff leakage current at other dimensions, achieving accurate modeling. Figure 5 The fitting trend graph of the cutoff leakage current shows that the simulation trend of the model is closer to the test data, indicating that the mathematical fitting formula proposed in this invention can be applied to the SPICE accurate modeling of the cutoff leakage current caused by the reverse bias pn junction.

[0056] Based on the same inventive concept, embodiments of the present invention also provide an electronic device, including:

[0057] Memory, which stores computer programs;

[0058] The processor, which is communicatively connected to the memory, executes the SPICE model extraction method described above for improving the accuracy of reverse-biased pn junction leakage current when calling the computer program.

[0059] The memory can be used to store the computer-readable instructions, and the processor implements various functions of the terminal device by running or executing the computer-readable instructions stored in the memory and calling the data stored in the memory.

[0060] In this embodiment, the memory may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.

[0061] In this embodiment, the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor. The processor is the control center of the terminal device, connecting various parts of the terminal device via various interfaces and lines.

[0062] Since the electronic device provided by this invention belongs to the same inventive concept as the SPICE model extraction method for improving the accuracy of reverse bias pn junction leakage current described above, the electronic device provided by this invention has all the advantages of the SPICE model extraction method for improving the accuracy of reverse bias pn junction leakage current described above. Therefore, the beneficial effects of the electronic device provided by this invention will not be described in detail here.

[0063] Based on the same inventive concept, this invention also proposes a readable storage medium storing a computer program thereon, which, when executed, can implement the SPICE model extraction method described above for improving the accuracy of reverse bias pn junction leakage current.

[0064] A readable storage medium can be a tangible device capable of holding and storing instructions for use by an instruction execution device, such as, but not limited to, electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof. The computer programs described herein can be downloaded from the readable storage medium to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. Networks can include copper transmission cables, fiber optic transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. Each computing / processing device's network adapter card or network interface receives and forwards a computer program from the network for storage on a readable storage medium within the respective computing / processing device. The computer program used to perform the operations of this invention can be execution instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as "C" or similar languages. The computer program can execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuits, such as programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), are personalized by utilizing state information from a computer program. These electronic circuits can execute computer-readable program instructions, thereby realizing various aspects of the present invention.

[0065] Since the readable storage medium provided by this invention belongs to the same inventive concept as the SPICE model extraction method for improving the accuracy of reverse bias pn junction leakage current described above, the readable storage medium provided by this invention has all the advantages of the SPICE model extraction method for improving the accuracy of reverse bias pn junction leakage current described above. Therefore, the beneficial effects of the readable storage medium provided by this invention will not be described in detail here.

[0066] Based on the same inventive concept, this embodiment of the invention also proposes a process design package, which includes a SPICE model library extracted and constructed using the SPICE model extraction method described above to improve the accuracy of reverse bias pn junction leakage current. This package is capable of accurately simulating the cutoff leakage current caused by reverse bias pn junction in MOS devices of different sizes.

[0067] Since the process design package provided by this invention and the SPICE model extraction method for improving the accuracy of reverse bias pn junction leakage current described above belong to the same inventive concept, the process design package provided by this invention has all the advantages of the SPICE model extraction method for improving the accuracy of reverse bias pn junction leakage current described above. Therefore, the beneficial effects of the process design package provided by this invention will not be elaborated here.

[0068] Based on the same inventive concept, this invention also proposes an integrated circuit design method that uses the process design package described above for circuit simulation and verification to accurately predict and optimize the static power consumption of the circuit.

[0069] In summary, this invention provides a SPICE model extraction method to improve the accuracy of reverse-biased pn junction leakage current. By attaching a size-related mathematical fitting formula to the key parameter jtsswgd for adjusting the reverse-biased pn junction leakage current in the BSIM4 model, and introducing fitting parameters ljtsswgd, wjtsswgd, and pjtsswgd that are strongly correlated with the effective channel length eef, the effective channel width wef, and the device area eef*wef, it is possible to accurately capture and fit the complex behavior of leakage current as the device size changes. By adjusting the fitting parameters, accurate modeling of the cutoff leakage current caused by the reverse-biased pn junction can be achieved, thereby improving the simulation accuracy of the model for the cutoff leakage current of devices of different sizes.

[0070] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure are within the protection scope of the present invention. Obviously, those skilled in the art can make various modifications and variations to the present invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the present invention and its equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A SPICE model extraction method for improving the accuracy of reverse-biased pn junction leakage current, characterized in that, The application relates to a SPICE model extraction method for improving the precision of reverse-biased pn junction leakage current. In the BSIM4 model framework, a mathematical fitting formula is added to the parameter jtsswgd for adjusting the reverse-biased pn junction leakage current, and the mathematical fitting formula is as follows: jtsswgd=ojtsswgd+ljtsswgd / lef+wjtsswgd / wef+pjtsswgd / (lef*wef) Wherein, lef and wef are the effective channel length and the effective channel width of a test structure respectively, ojtsswgd, ljtsswgd, wjtsswgd and pjtsswgd are fitting parameters for fitting the current value of the cutoff leakage current.

2. The method for SPICE model extraction to improve the accuracy of reverse-biased pn junction leakage current according to claim 1, wherein, The ojtsswgd is a reference fitting parameter for characterizing the reverse-biased pn junction leakage current characteristics of a large-size device with no obvious size effect.

3. The method for SPICE model extraction to improve the accuracy of reverse-biased pn junction leakage current according to claim 1, wherein, The ljtsswgd is a fitting parameter strongly related to the effective channel length lef, and is used for adjusting and fitting the effect of the reverse-biased pn junction leakage current changing with the channel length.

4. The method for SPICE model extraction to improve the accuracy of reverse-biased pn junction leakage current according to claim 1, wherein, The wjtsswgd is a fitting parameter strongly related to the effective channel width wef, and is used for adjusting and fitting the effect of the reverse-biased pn junction leakage current changing with the channel width.

5. The method for SPICE model extraction to improve the accuracy of reverse-biased pn junction leakage current according to claim 1, wherein, The pjtsswgd is a fitting parameter strongly related to the effective area lef*wef, and is used for adjusting and fitting the synergistic effect of the reverse-biased pn junction leakage current changing with the device area.

6. The method for SPICE model extraction to improve the accuracy of reverse-biased pn junction leakage current according to claim 1, wherein, The SPICE model extraction method for improving the precision of reverse-biased pn junction leakage current further comprises the following steps: Measuring the actual data of the cutoff leakage current of a series of test structures with different channel lengths and widths; Based on the mathematical fitting formula, a set of optimal model parameters ojtsswgd, ljtsswgd, wjtsswgd and pjtsswgd are extracted through a fitting algorithm; The optimal model parameters are integrated into a BSIM4 model file to generate a final SPICE model library.

7. An electronic device, comprising: The application also discloses a computer program product and a computer readable storage medium. The computer program product comprises a memory storing a computer program, and a processor connected with the memory in communication and configured to execute the SPICE model extraction method for improving the precision of reverse-biased pn junction leakage current according to any one of claims 1-6 when the computer program is invoked. The computer program product comprises a memory storing a computer program, and a processor connected with the memory in communication and configured to execute the SPICE model extraction method for improving the precision of reverse-biased pn junction leakage current according to any one of claims 1-6 when the computer program is invoked.

8. A readable storage medium, having stored thereon a computer program, characterized in that, The SPICE model library contained in the computer program product is extracted and constructed by using the SPICE model extraction method for improving the precision of reverse-biased pn junction leakage current according to any one of claims 1-6, and can accurately simulate the cutoff leakage current of MOS devices of different sizes caused by reverse-biased pn junction.

9. A process design package characterized in that, The circuit simulation and verification are performed by using the process design package according to claim 9, so as to accurately predict and optimize the static power consumption of the circuit.

10. An integrated circuit design method, characterized by, ​

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