High-linearity low-noise amplifier based on harmonic suppression

Abstract

The invention discloses a high-linearity low-noise amplifier based on harmonic suppression, relates to the field of communication and the technical field of electronic devices, and is used for solving the problem that the noise coefficient of an existing Darlington structure is large. Comprising a noise matching and input matching network, a linearity enhancement structure, a negative feedback structure and a pre-distortion structure. Wherein the linearity enhancement structure at least comprises a first amplification transistor and a second amplification transistor which are arranged in parallel, and is used for improving the linearity of the circuit through harmonic cancellation; the negative feedback structure is connected with the noise matching and input matching network and the pre-distortion structure and is used for expanding circuit bandwidth and optimizing output matching; the pre-distortion structure is used for stabilizing the bias voltage of the third amplification transistor. According to the invention, the linearity of the whole circuit is effectively improved, and the source microstrip lines of the two circuits are utilized to improve the minimum noise matching and improve the noise performance. Noise is reduced, linearity is improved, low-frequency gain is suppressed, and bandwidth of the whole circuit is improved.

Description

Technical Field

[0001] This invention relates to the fields of communication and electronic device technology, and in particular to a high linearity, low noise amplifier based on harmonic suppression. Background Technology

[0002] With the advancement of wireless communication technology, the demand for high frequency and high bandwidth in radio frequency (RF) receiving systems is increasing. Low-noise amplifiers (LNAs) are front-end devices in RF receivers. LNAs play a crucial role in wireless communication, amplifying signals while simultaneously suppressing noise. LNAs are used in modern communication systems in fields including phased array radar, fiber optic communication, electromagnetic spectrum monitoring, high-speed data transmission, electronic warfare, and military radar.

[0003] In practical communication systems, radio frequency (RF) signals typically contain multiple frequency components. If the amplifier has poor linearity, nonlinear distortion can lead to intermodulation distortion, where different signal frequencies modulate each other, generating additional interference frequencies. Nonlinear distortion can also cause out-of-band interference: distorted signals exceeding the target frequency band affect system performance. High-linearity amplifiers can effectively reduce these distortions, thus ensuring signal integrity, which is particularly important in broadband, multi-carrier signal communication scenarios. Low-noise designs usually require high gain, but high gain can lead to increased nonlinear distortion; a trade-off must be struck between the two in the design. To adapt to multi-band communication, amplifiers need to have wideband linear gain characteristics while maintaining low noise and high efficiency.

[0004] In recent years, low-noise amplifiers have been developing towards higher linearity, lower noise, and wider bandwidth. As the operating frequency of amplifiers increases, the parasitic effects of transistors on the amplifier's noise and gain performance become increasingly apparent. Therefore, improving linearity while suppressing high-frequency noise degradation and reducing return loss has become crucial for designing high-linearity, low-noise amplifiers. While the Darlington structure excels in improving linearity, it lacks advantages in noise and power consumption.

[0005] Therefore, there is an urgent need to provide a more reliable high-linearity, low-noise amplifier based on harmonic suppression. Summary of the Invention

[0006] The purpose of this invention is to provide a high linearity, low noise amplifier based on harmonic suppression to solve the problem of high noise figure in current Darlington structures.

[0007] To achieve the above objectives, the present invention provides the following technical solution: In a first aspect, the present invention provides a high linearity, low noise amplifier based on harmonic suppression, comprising at least: Noise matching and input matching networks, linearity enhancement structures, negative feedback structures, and predistortion structures; The linearity enhancement structure includes at least a first amplifying transistor and a second amplifying transistor connected in parallel, used to improve the linearity of the circuit through harmonic cancellation; The negative feedback structure is connected to the noise matching and input matching network and the predistortion structure to expand the circuit bandwidth and optimize the output matching; the predistortion structure is used to stabilize the bias voltage of the third amplifying transistor.

[0008] Optionally, the high linearity, low noise amplifier based on harmonic suppression may also include: An active bias structure; the active bias structure includes at least a bias transistor, a choke resistor, a voltage divider resistor, and a bypass capacitor; the bias transistor is used for dynamic voltage division. The bias transistor includes a fourth amplifying transistor, a fifth amplifying transistor, and a sixth amplifying transistor; the choke resistor includes a first choke resistor and a second choke resistor; the voltage divider resistor includes a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor; the bypass capacitor is a fifth capacitor; The active bias structure provides bias for the first amplifying transistor, the second amplifying transistor, and the third amplifying transistor; the bias of the third amplifying transistor is provided by a resistor voltage divider, and the active bias structure is powered by a single power supply.

[0009] Optionally, in the active bias structure, the drain of the fourth amplifying transistor is connected to the second resistor, the gate of the fifth amplifying transistor, and the gate of the sixth amplifying transistor, respectively, and its source is grounded; the drain of the fifth amplifying transistor is connected to the third resistor, and its source is connected to the fifth resistor; the drain of the sixth amplifying transistor is connected to the fourth resistor, and its source is connected to the voltage node, the fifth capacitor, and the sixth resistor, respectively; the other ends of the second, third, and fourth resistors are connected to a DC power supply; the other ends of the fifth and sixth resistors are grounded; and the other end of the fifth capacitor is grounded.

[0010] Optionally, the noise matching and input matching network includes at least: The first inductor, the microstrip line, the first capacitor, the fourth capacitor, the first amplifying transistor, and the parasitic capacitance of the first amplifying transistor; The RF input port is connected to one end of the first capacitor, which is connected in parallel with the first inductor, and the other end of the first inductor is grounded; the gate of the first amplifying transistor is connected to one end of the bias resistor, and the other end of the bias resistor is connected to the DC bias voltage.

[0011] Optionally, the basic structure of the high linearity low noise amplifier based on harmonic suppression is a single-stage common-source cascode amplifier structure, in which the first amplifying transistor, the second amplifying transistor, and the third amplifying transistor constitute a common-source cascode amplifier structure, the first amplifying transistor and the second amplifying transistor constitute a common-source stage, and the third amplifying transistor constitutes a common-gate stage. The first amplifying transistor, the second amplifying transistor, and the microstrip line constitute a basic common-source common-gate amplifier circuit; a smaller third amplifying transistor is connected in parallel with the first amplifying transistor, which together with the microstrip line constitutes an auxiliary amplifying circuit. The noise matching and input matching networks and the active bias structure act on the common source stage and the auxiliary stage, while the predistortion structure acts on the common gate amplifier circuit.

[0012] Optionally, the predistortion structure includes a diode, a first resistor, and a third capacitor; wherein the anode of the diode is grounded, and the cathode of the diode is connected to the gate of the second amplifying transistor through the first resistor; the other end of the first resistor is connected to the third capacitor; and the other end of the third capacitor is grounded.

[0013] Optionally, the negative feedback structure is a dual RC negative feedback structure; the negative feedback structure includes multiple feedback resistors and multiple feedback capacitors; the dual RC negative feedback structure is connected to a second capacitor; The dual RC negative feedback structure includes a first feedback path and a second feedback path; the first feedback path feeds back from the output terminal of the third amplifying transistor to the gate of the common source stage, and the second feedback path feeds back from the output terminal of the third amplifying transistor to the gate of the common gate stage.

[0014] Optionally, the feedback resistor includes a first feedback resistor, a second feedback resistor, and a third feedback resistor; the feedback capacitor includes a first feedback capacitor and a second feedback capacitor; One end of the first feedback resistor is connected to the drain of the second amplifying transistor, and the other end of the first feedback resistor is connected to the first feedback capacitor; the other end of the first feedback capacitor is connected to the first feedback resistor, and the other end of the first feedback resistor is connected to the gate of the first amplifying transistor; one end of the third feedback resistor is connected to the drain of the second amplifying transistor, and the other end of the third feedback resistor is connected to the second feedback capacitor, and the other end of the second feedback capacitor is connected to the gate of the second amplifying transistor; the first feedback resistor, the second feedback resistor, and the third feedback resistor determine the feedback depth.

[0015] Optionally, the microstrip line includes a first microstrip line and a second microstrip line, wherein the first microstrip line is connected to the source of the first amplifying transistor, and the second microstrip line is connected to the source of the second amplifying transistor, and the microstrip line serves as a source degradation inductor. The microstrip line provides the real part of the input characteristic impedance, making the minimum noise matching point and the optimal impedance matching point close to each other on the Smith chart.

[0016] Optionally, the size of the first amplifying transistor in the linearity enhancement structure is larger than the size of the second amplifying transistor, and the first amplifying transistor and the second amplifying transistor are configured to operate at different bias voltages.

[0017] Compared with existing technologies, this invention provides a high-linearity, low-noise amplifier based on harmonic suppression, comprising at least: a noise matching and input matching network, a linearity enhancement structure, a negative feedback structure, and a predistortion structure. The linearity enhancement structure includes at least a first amplifying transistor and a second amplifying transistor connected in parallel, used to improve the linearity of the circuit through harmonic cancellation. The negative feedback structure is connected to the noise matching and input matching network and the predistortion structure, used to expand the circuit bandwidth and optimize output matching. The predistortion structure is used to stabilize the bias voltage of the third amplifying transistor. This invention applies the linearity enhancement structure to the common-source stage of a cascode structure, using different bias voltages and sizes to cancel higher-order harmonics, effectively improving the overall circuit linearity. Simultaneously, it utilizes the source microstrip lines of both transistors to improve minimum noise matching and enhance noise performance. Since adding the predistortion structure to the gate of the common-source stage or to the gate of the auxiliary transistor has a significant impact on noise performance, the predistortion structure is added to the gate of the cascode stage, reducing noise while improving linearity. Combined with dual RC negative feedback, low-frequency gain is suppressed, increasing the overall circuit bandwidth. Attached Figure Description

[0018] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 A schematic diagram of the circuit structure of a high linearity, low noise amplifier based on harmonic suppression provided by the present invention; Figure 2 A schematic diagram of the active bias circuit structure provided by the present invention; Figure 3 The simulation results of the noise figure of a high linearity low noise amplifier based on harmonic suppression provided by the present invention are shown in the figure. Figure 4 The gain simulation results of a high linearity low noise amplifier based on harmonic suppression provided by this invention are shown in the figure. Figure 5 The simulation results of the third-order intermodulation cutoff point of the output of a high linearity low noise amplifier based on harmonic suppression provided by the present invention are shown in the figure.

[0019] Figure label: 1-Noise matching and input matching network, 2-Linearity enhancement structure, 3-Negative feedback structure, 4-Predistortion structure. Detailed Implementation

[0020] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.

[0021] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0022] In this invention, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0023] Current high-linearity, low-noise amplifiers employ a post-distortion structure, where the auxiliary transistor path is connected to the output of the main transistor, which can reduce the influence of the auxiliary path on the input. In the post-distortion circuit, both the main and auxiliary transistors generally operate in the strong inversion region, which can produce a more stable nonlinear cancellation effect. However, this structure suffers from problems such as deteriorated noise figure, high overall power consumption, and large area. Besides post-distortion structures, optimal gate bias, feedforward, negative feedback, and Darlington structures can also improve linearity. Optimal gate bias selects appropriate transistor size and bias state based on nonlinear dependence to control the nonlinear characteristics of the device, thereby improving amplifier linearity. However, this technique is sensitive to PVT, which limits its practical application. Furthermore, with high power input, it can cause operating point drift, degrading gain and noise performance. It cannot handle second-order nonlinearity and has a narrow applicable bandwidth, so it is generally not used alone and is usually combined with other methods to improve linearity. Feedforward technology improves linearity by controlling the magnitude and phase of the signal in each branch of the system. Essentially, it compensates for the nonlinearity of the main amplifier path through the auxiliary amplifier path, effectively canceling higher-order nonlinearities. It has a wide applicable bandwidth but suffers from a high noise figure. The problems of degradation, high overall power consumption, and large area exist in low-noise amplifiers. Negative feedback technology applies the output signal to the input through a feedback network, suppressing IM products and expanding bandwidth and stability. It is widely used in low-noise amplifier design due to its low susceptibility to environmental influences and wide applicability; however, the feedback loop introduces additional noise. Darlington pairs consist of two cascaded transistors, with the source of the first transistor connected to the gate of the second. This significantly improves the linear operating region, provides high input impedance, reduces the load's impact on the signal source, and improves overall linearity. Internal feedback between the two transistors helps stabilize the operating point and reduce distortion. The temperature changes of the two transistors tend to be consistent, which helps maintain the temperature stability of linear characteristics. The cascaded structure mitigates the negative impact of the Miller effect on linearity, but suffers from excessive noise and high power consumption. In cascode low-noise amplifiers, noise is mainly contributed by the common-source stage; therefore, the size, bias, and preceding matching structure design of the common-source stage are crucial for low-noise amplifiers.

[0024] Therefore, this invention provides a high-linearity, low-noise amplifier based on harmonic suppression to solve the problem of high noise figure in current Darlington structures. The following description, in conjunction with the accompanying drawings, illustrates the solutions provided in the embodiments of this specification: like Figure 1 As shown, a high-linearity, low-noise amplifier based on harmonic suppression may include: Noise matching and input matching network 1, linearity enhancement structure 2, negative feedback structure 3, and predistortion structure 4; The linearity enhancement structure 2 includes at least a first amplifying transistor M1 and a second amplifying transistor M2 connected in parallel, which is used to improve the linearity of the circuit through harmonic cancellation; the negative feedback structure 3 is connected to the noise matching and input matching network 1 and the predistortion structure 4, which is used to expand the circuit bandwidth and optimize the output matching; the predistortion structure 4 is used to stabilize the bias voltage of the third amplifying transistor M3.

[0025] Figure 1 The basic structure of the high linearity low noise amplifier based on harmonic suppression is a single-stage common-source cascode amplifier. The first amplifying transistor M1, the second amplifying transistor M2, and the third amplifying transistor M3 constitute the common-source cascode amplifier structure. The first amplifying transistor M1 and the second amplifying transistor M2 constitute the common-source stage, and the third amplifying transistor M3 constitutes the common-gate stage. Among them, the first amplifying transistor M1, the second amplifying transistor M2, and the microstrip line constitute the basic common-source cascode amplifier circuit. The smaller third amplifying transistor M3 is connected in parallel with the first amplifying transistor M1, and together with the microstrip line, they constitute the auxiliary amplification circuit. The noise matching and input matching network 1 and the active bias structure act on the common-source stage and the auxiliary stage, and the predistortion structure 4 acts on the common-gate stage amplifier circuit.

[0026] The microstrip line may include a first microstrip line and a second microstrip line. The first microstrip line is connected to the source of the first amplifying transistor M1, and the second microstrip line is connected to the source of the second amplifying transistor M2. The microstrip line acts as a source degradation inductor. The microstrip line provides the real part of the input characteristic impedance, so that the minimum noise matching point and the optimal impedance matching point are close to each other on the Smith chart.

[0027] The noise matching and input matching network 1 are critical components of the amplifier front-end. The main purpose of noise matching is to minimize the amplifier's noise figure at a specific frequency, thereby improving its ability to receive weak signals. The input matching network is used to match the impedance of the signal source with the amplifier's input impedance to achieve maximum power transfer, reduce signal reflection at the input, and improve signal transmission efficiency. The design of the noise matching and input matching network 1 will vary depending on the application scenario. For example, in high-frequency communication systems, due to the higher operating frequency, distributed parameter components are more commonly used, and the impact of parameters such as the length and width of the microstrip line on impedance matching needs to be considered.

[0028] The linearity enhancement structure 2 includes at least a first amplifying transistor M1 and a second amplifying transistor M2 connected in parallel. This parallel structure utilizes the differences in nonlinear characteristics of different transistors to improve the linearity of the circuit through harmonic cancellation. When the input signal is large, a single transistor will produce significant nonlinear distortion and generate high-order harmonics. However, the two transistors connected in parallel have different nonlinear characteristics, and the harmonics they generate have differences in phase and amplitude. By reasonably designing the transistor parameters and bias conditions, the generated harmonics can be canceled out, thereby reducing the harmonic content in the output signal and improving the linearity of the circuit.

[0029] In practical applications, differences in nonlinear characteristics can be achieved by selecting transistors of different sizes and fabrication processes. For example, one transistor may have a large transconductance, making it prone to saturation distortion when the input signal is large; while another transistor may have a smaller transconductance and relatively weaker nonlinear characteristics. After parallel connection, the harmonics generated near the operating point can be canceled out by adjusting the bias voltage and current. In specific application scenarios, coupling capacitors or inductors can be introduced between the transistors according to actual application requirements to further adjust the phase relationship of the harmonics and enhance the harmonic cancellation effect.

[0030] The negative feedback structure 3, connected to the noise matching and input matching network 1 and the predistortion structure 4, plays multiple roles in the amplifier. First, by feeding a portion of the output signal back to the input and subtracting it from the input signal, it alters the amplifier's frequency response characteristics, resulting in a flatter gain over a wider frequency range. Second, the negative feedback structure 3 optimizes output matching. The feedback signal affects the output impedance; by adjusting the parameters of the feedback network, the output impedance can be better matched to the load impedance, improving power transfer efficiency. In practical applications, the negative feedback structure 3 can be divided into two types: voltage feedback and current feedback. Voltage feedback feeds a portion of the output voltage back to the input for comparison; current feedback feeds a portion of the output current back to the input. The appropriate feedback type must be selected based on the specific requirements of the amplifier.

[0031] The predistortion structure 4 can be used to stabilize the bias voltage of the third amplifying transistor M3. During amplifier operation, the transistor's bias voltage is affected by various factors, such as temperature changes and variations in input signal power. Fluctuations in the bias voltage cause changes in the transistor's operating point, thus affecting the amplifier's performance, such as gain and linearity. The predistortion structure 4 compensates for the bias voltage fluctuation by generating a predistortion signal that is opposite to the bias voltage fluctuation, thereby maintaining the stability of the bias voltage. The application of the predistortion structure 4 can effectively reduce gain changes and nonlinear distortion caused by bias voltage fluctuations, enabling the amplifier to maintain relatively consistent performance under different operating conditions, thus improving the system's reliability and stability.

[0032] In the above structure, the basic structure is a single-stage common-source common-gate circuit. An auxiliary transistor M1 is connected in parallel on the common-source stage to suppress high-order harmonics and improve linearity. Microstrip lines Ls1 and Ls2 act as source degradation inductors, balancing noise figure with input matching. The gate on the common-gate stage uses diode D predistortion technology, which makes the bias voltage more stable and reduces noise. Combined with the dual RC negative feedback structure, the overall circuit has a wider bandwidth and is more stable.

[0033] Figure 1 This invention provides a high-linearity, low-noise amplifier based on harmonic suppression, comprising at least: a noise matching and input matching network 1, a linearity enhancement structure 2, a negative feedback structure 3, and a predistortion structure 4. The linearity enhancement structure 2 includes at least a first amplifying transistor M1 and a second amplifying transistor M2 connected in parallel, used to improve the linearity of the circuit through harmonic cancellation. The negative feedback structure 3 is connected to the noise matching and input matching network 1 and the predistortion structure 4, used to expand the circuit bandwidth and optimize output matching. The predistortion structure 4 is used to stabilize the bias voltage of the third amplifying transistor M3. This invention applies the linearity enhancement structure 2 to the common-source stage of a cascode structure, using different bias voltages and dimensions to cancel higher-order harmonics, effectively improving the overall circuit linearity. Simultaneously, it utilizes the source microstrip lines of both transistors to improve minimum noise matching and enhance noise performance. Since adding the predistortion structure 4 to the gate of the common-source stage or to the gate of the auxiliary transistor has a significant impact on noise performance, the predistortion structure 4 is added to the gate of the cascode stage, reducing noise while improving linearity. By combining dual RC negative feedback, low-frequency gain is suppressed, thereby improving the overall circuit bandwidth.

[0034] Specifically, the various structures in the high-linearity, low-noise amplifier based on harmonic suppression work synergistically to achieve high performance. Noise matching and input matching networks provide excellent signal reception and transmission conditions, ensuring low noise and efficient power transfer. The linearity enhancement structure improves the amplifier's linearity through harmonic cancellation, reducing nonlinear distortion. The negative feedback structure expands the circuit bandwidth, optimizes output matching, and stabilizes overall performance. The predistortion structure stabilizes the transistor bias voltage, further improving the amplifier's linearity and stability. This organic combination of structures results in excellent performance in terms of low noise, high linearity, and wide bandwidth, meeting the stringent signal amplification requirements of modern communication and radar systems.

[0035] based on Figure 1 The structure, and embodiments of this specification also provide Figure 1 The detailed descriptions of each specific structure are explained below.

[0036] Figure 1 The structure of the high linearity low noise amplifier based on harmonic suppression may also include: Active bias structure; specifically, the specific circuit structure of the active bias structure is as follows: Figure 2 As shown, the active bias structure includes at least a bias transistor, a choke resistor, a voltage divider resistor, and a bypass capacitor; the bias transistor is used for dynamic voltage division. The bias transistors include a fourth amplifying transistor M4, a fifth amplifying transistor M5, and a sixth amplifying transistor M6; the choke resistors include a first choke resistor Rg1 and a second choke resistor Rg2; the voltage divider resistors include a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6; the bypass capacitor is a fifth capacitor C5; the active bias structure provides bias for the first amplifying transistor M1, the second amplifying transistor M2, and the third amplifying transistor M3; the bias of the third amplifying transistor M3 is provided by a resistor voltage divider, and the active bias structure is powered by a single power supply.

[0037] Furthermore, in the active bias structure, the drain of the fourth amplifying transistor M4 is connected to the second resistor R2, the gate of the fifth amplifying transistor M5, and the gate of the sixth amplifying transistor M6, respectively, and its source is grounded; the drain of the fifth amplifying transistor M5 is connected to the third resistor R3, and the source of the fifth amplifying transistor M5 is connected to the fifth resistor R5; the drain of the sixth amplifying transistor M6 is connected to the fourth resistor R4, and the source of the sixth amplifying transistor M6 is connected to the voltage node, the fifth capacitor C5, and the sixth resistor R6, respectively; the other ends of the second resistor R2, the third resistor R3, and the fourth resistor R4 are connected to a DC power supply; the other ends of the fifth resistor R5 and the sixth resistor R6 are grounded; and the other end of the fifth capacitor C5 is grounded.

[0038] Specifically, Figure 2 The active bias structure may include pHEMT transistors (M4, M5, and M6), choke resistors (first choke resistor Rg1 and second choke resistor Rg2), voltage divider resistors (R2, R3, R4, R5, and R6), and bypass capacitors (fifth capacitor C5). The pHEMT transistors (M4, M5, and M6) that provide dynamic voltage division are: the drain of the fourth amplifying transistor M4 is connected to the second resistor R2, the gate of the fifth amplifying transistor M5, and the gate of the sixth amplifying transistor M6. The source of the fifth amplifying transistor M5 is connected to the third resistor R3, and the source is connected to the fifth resistor R5. The drain of the sixth amplifying transistor M6 is connected to the fourth resistor R4, and the source is connected to the voltage node Vg, the bypass capacitor (the fifth capacitor C5), and the sixth resistor R6. The other ends of the second resistor R2, the third resistor R3, and the fourth resistor R4 are connected to the DC power supply Vdd. The other ends of the fifth resistor R5 and the sixth resistor R6 are grounded. The other end of the bypass capacitor (the fifth capacitor C5) is grounded.

[0039] Figure 2 The active bias structure in the amplifier not only provides stable and appropriate bias current and voltage for the core transistors, ensuring they operate at their optimal state, but also adapts to environmental changes (such as temperature fluctuations and power supply voltage variations) to a certain extent, maintaining stable amplifier performance. This plays a positive supporting role in achieving low noise and high linearity characteristics. It provides process compensation, temperature compensation, and power supply voltage compensation, effectively solving the problem of high sensitivity of noise, gain, and linearity to process, temperature, and power supply voltage. The common-gate level uses resistor voltage divider bias, and the entire circuit is powered by a single power supply.

[0040] The core design is based on closed-loop negative feedback regulation, relying on the feedback mechanism formed by M4, M5, and M6, and the bias voltage adjustment supported by R6. This design not only provides a precise and stable bias voltage, but also adapts to changes in load and temperature, ensuring the reliability and stability of the circuit.

[0041] In an active bias structure, a choke resistor primarily functions to block AC signals, allowing only DC current to pass through. A voltage divider resistor, consisting of two or more resistors connected in series, is used to divide the power supply voltage in a specific ratio, thereby providing a suitable base (or gate) voltage for the bias transistor. By adjusting the resistance ratio of the voltage divider resistors, the base current of the bias transistor can be precisely controlled, which in turn controls its collector (or drain) current and voltage, achieving precise adjustment of the bias of the main amplifying transistor. For example, if it is desired that the base voltage of the bias transistor is half of the power supply voltage, two voltage divider resistors with equal resistance values ​​can be connected in series between the power supply and ground, using the voltage at the intermediate node as the base voltage of the bias transistor. A bypass capacitor is connected in parallel with a voltage divider resistor. Its main function is to provide a low-impedance path for AC signals, bypassing them to ground, thus preventing the AC signal from affecting the bias voltage. Since the impedance of a capacitor to an AC signal decreases as the frequency increases, for high-frequency AC signals, the bypass capacitor exhibits a very low impedance, allowing the AC signal to flow smoothly through the capacitor to ground without entering the bias circuit and affecting the bias voltage.

[0042] Figure 2 The active bias structure in the amplifier effectively stabilizes the bias voltage of the main transistor through the dynamic voltage division of the bias transistor and the coordinated operation of the choke resistor, voltage divider resistor, and bypass capacitor. Under conditions of temperature changes and power supply voltage fluctuations, the bias transistor can automatically adjust its operating state to maintain the relative stability of the main transistor's bias voltage, ensuring that the main transistor always operates in the appropriate linear region, thereby improving the amplifier's linearity and stability. In other words, the active bias structure can provide process compensation, temperature compensation, and power supply voltage compensation, effectively solving the problems of high sensitivity of noise, gain, and linearity to process, temperature, and power supply voltage. The common-gate level uses resistor voltage division bias, and the entire circuit is powered by a single power supply.

[0043] For noise matching and input matching networks, at least the following can be included: The system includes a first inductor L1, a microstrip line, a first capacitor C1, a fourth capacitor C4, a first amplifying transistor M1, and the parasitic capacitance of the first amplifying transistor M1; an RF input port is connected to one end of the first capacitor C1, the first capacitor C1 is connected in parallel with the first inductor L1, and the other end of the first inductor L1 is grounded; the gate of the first amplifying transistor M1 is connected to one end of a bias resistor, and the other end of the bias resistor is connected to a DC bias voltage.

[0044] The noise matching and input matching network consists of LC passive devices and microstrip lines. By adjusting the value of LC, the noise matching is improved. The first microstrip line Ls1 and the second microstrip line Ls2 can provide a real part of the input characteristic impedance, so that the minimum noise matching point and the optimal impedance matching point are close to each other on the Smith chart, enabling the noise matching and input matching network to have good impedance matching and noise matching.

[0045] Specifically, such as Figure 1 As shown, the noise matching and input matching network consists of a first inductor L1, a first microstrip line Ls1, a first capacitor C1, a fourth capacitor C4, and the parasitic capacitances of pHEMT transistors (M1 and M2). The RF input port is connected to one end of the first DC blocking capacitor C1, which is connected in parallel with the matching inductor (first inductor L1), and the other end of the matching inductor (first inductor L1) is grounded. One end of the first bias resistor Rg1 is connected to the gate of the first amplifying transistor M1, and the other end of the first bias resistor Rg1 is connected to the DC bias voltage Vg1. In specific applications, noise matching can be improved by adjusting the value of LC. The first microstrip line Ls1 and the second microstrip line Ls2 can provide a real part of the input characteristic impedance, making the minimum noise matching point and the optimal impedance matching point close to each other on the Smith chart, so that the noise matching and input matching network can have good impedance matching and noise matching.

[0046] Setting up noise matching and input matching networks can enable an amplifier to achieve the minimum noise figure at a specific frequency, thereby improving the amplifier's ability to receive weak signals. At the same time, it can be used to match the impedance of the signal source with the input impedance of the amplifier to achieve maximum power transmission, reduce signal reflection at the input end, and improve signal transmission efficiency.

[0047] The linearity enhancement structure includes a common-source pHEMT transistor and an auxiliary pHEMT transistor connected in parallel, along with a first microstrip line Ls1 and a second microstrip line Ls2 connecting their sources. The drains of the common-source pHEMT transistor and the auxiliary pHEMT transistor are connected via microstrip lines, and their gates are also connected via microstrip lines. The common-source pHEMT transistor is slightly larger, while the auxiliary pHEMT transistor is smaller. By using different sizes and biases, the higher harmonics they generate cancel each other out, thereby improving linearity.

[0048] Specifically, such as Figure 1The linearity enhancement structure may include a first amplifying transistor M1 and a third amplifying transistor M3, with M1 being larger and M3 being smaller. The gate of the first amplifying transistor M1 is connected to the gate of the third amplifying transistor M3, and the two are separated by a fourth DC blocking capacitor C4. The drain of the first amplifying transistor M1 is connected to the drain of the third amplifying transistor M3. The first microstrip line Ls1 and the second microstrip line Ls2 are respectively connected to the source of the first amplifying transistor M1 and the source of the third amplifying transistor M3, and their other ends are grounded.

[0049] Specifically, in the linearity enhancement structure, the size of the first amplifying transistor M1 is larger than the size of the second amplifying transistor M2, and the first amplifying transistor M1 and the second amplifying transistor M2 are configured to operate under different bias voltages. That is, the common-source pHEMT transistor is slightly larger, while the auxiliary pHEMT transistor connected in parallel with it is smaller. Through their different sizes and biases, the higher harmonics they generate cancel each other out, thereby improving linearity.

[0050] The linearity enhancement structure can significantly improve the linearity index of the amplifier, such as the third-order intermodulation intercept (IIP3); through harmonic cancellation, the amplifier can handle higher power input signals without producing obvious nonlinear distortion, thereby improving the dynamic range and signal transmission quality of the system.

[0051] For the predistortion structure, the predistortion structure may include a diode D, a first resistor R1, and a third capacitor C3; wherein the anode of the diode D is grounded, and the cathode of the diode D is connected to the gate of the second amplifying transistor M2 through the first resistor R1; the other end of the first resistor R1 is connected to the third capacitor C3; the other end of the third capacitor C3 is grounded. Specifically, as shown... Figure 1 The predistortion structure may include a diode D, a first resistor R1, and a third capacitor C3. The anode of diode D is grounded, and its cathode is connected to the first resistor R1 and the gate of the second amplifying transistor M2. The other end of the first resistor R1 is connected to the third capacitor C3, and the other end of the third capacitor C3 is grounded. The grounding of the anode and the connection of the cathode to the first resistor R1 and the gate of the second amplifying transistor M2 stabilize the bias voltage of the common-gate second amplifying transistor M2. The first resistor R1 helps improve the overall circuit stability. The third capacitor C3 affects the output impedance matching and linearity, which must be considered during design.

[0052] The aforementioned predistortion structure can be used to stabilize the bias voltage of the third amplifying transistor. A stable bias voltage ensures that the amplifier transistor is always at its optimal operating point during operation, thereby improving the amplifier's linearity and stability. The application of the predistortion structure can effectively reduce gain variations and nonlinear distortion caused by bias voltage fluctuations, enabling the amplifier to maintain relatively consistent performance under different operating conditions, thus improving the system's reliability and stability.

[0053] For the negative feedback structure, the negative feedback structure can be a dual RC negative feedback structure; the negative feedback structure includes multiple feedback resistors and multiple feedback capacitors; the dual RC negative feedback structure is connected to the second capacitor C2; the dual RC negative feedback structure acts simultaneously on the common-source stage and the common-gate stage. Further, the dual RC negative feedback structure includes a first feedback path and a second feedback path; the first feedback path feeds back from the output terminal of the third amplifying transistor M3 to the gate of the common-source stage, and the second feedback path feeds back from the output terminal of the third amplifying transistor M3 to the gate of the common-gate stage. The feedback resistors include a first feedback resistor Rf1, a second feedback resistor Rf2, and a third feedback resistor Rf3; the feedback capacitors include a first feedback capacitor Cf1 and a second feedback capacitor Cf2.

[0054] Specifically, such as Figure 1 As shown, the dual RC negative feedback structure consists of two parts. One part feeds back from the output to the common-source gate, consisting of a first feedback resistor Rf1, a second feedback resistor Rf2, and a first feedback capacitor Cf1. The other part feeds back from the output to the common-gate, consisting of a third feedback resistor Rf3 and a first feedback capacitor Cf1. The dual RC negative feedback structure may include a first feedback resistor Rf1, a second feedback resistor Rf2, a third feedback resistor Rf3, and a fourth feedback resistor Rf4. f2 and the third feedback resistor R f3 The system consists of a first feedback capacitor Cf1 and a second feedback capacitor Cf2. One end of the first feedback resistor Rf1 is connected to the drain of the second amplifying transistor M2, and the other end is connected to the first feedback capacitor Cf1. The other end of the first feedback capacitor Cf1 is connected to the first feedback resistor Rf1. The other end of the first feedback resistor Rf1 is connected to the gate of the first amplifying transistor M1. One end of the third feedback resistor Rf3 is connected to the drain of the second amplifying transistor M2, and the other end is connected to the second feedback capacitor Cf2. The other end of the second feedback capacitor Cf2 is connected to the gate of the second amplifying transistor M2. The first feedback resistor Rf1 and the second feedback resistor Rf2... f2 and the third feedback resistor R f3 Determine the feedback depth. By sacrificing some gain, the circuit bandwidth is expanded while optimizing output matching. Compared to single RC feedback, dual RC negative feedback can better improve output matching and minimize noise performance degradation.

[0055] Next, further explanation will be provided using specific simulation results of the noise figure, gain, and third-order intermodulation intercept at the output, such as... Figure 3 As shown in the simulation results of the noise figure of a high-linearity, low-noise amplifier based on harmonic suppression, the horizontal axis represents frequency and the vertical axis represents noise figure. Figure 3 The curve in the figure shows the trend of noise figure changing with frequency, from Figure 3 As can be seen, the noise figure generally increases with frequency. In the low-frequency range (close to 0 GHz), the noise figure is relatively low, around 0.39 dB; as the frequency increases to 3 GHz, the noise figure increases to approximately 0.67 dB. This trend reflects the noise characteristics of the low-noise amplifier at different frequencies. The structure provided by this invention ensures that the system's noise performance requirements are met throughout the entire operating frequency band.

[0056] Figure 4 In the figure, the horizontal axis of the gain simulation result graph of the high linearity low noise amplifier based on harmonic suppression represents frequency, and the vertical axis represents scattering parameters (S21 parameters), with the unit being decibels (dB). Figure 4 The curves depict the trend of the S21 parameter (gain) as a function of frequency. It can be seen that the value of the S21 parameter decreases monotonically as the frequency gradually increases from 0 GHz to 3 GHz. In the low-frequency range (close to 0 GHz), the gain is relatively high, approximately 28 dB; as the frequency increases to 3 GHz, the gain decreases to approximately 18 dB. The structure provided by this invention can alter the frequency response characteristics of the amplifier, resulting in a flatter gain over a wider frequency range.

[0057] Figure 5 In the simulation results of the high linearity low noise amplifier based on harmonic suppression, the horizontal axis represents the frequency and the vertical axis represents the output third-order intermodulation intercept (OIP3), with the unit being decibels and milliwatts (dBm). Figure 5The curves in the figure illustrate the trend of OIP3 with frequency. As can be seen from the graph, the OIP3 value is relatively low in the low-frequency range (around 0.5 GHz), approximately 37 dBm; as the frequency increases to about 2 GHz, OIP3 reaches its peak at approximately 52 dBm; subsequently, as the frequency continues to rise to 3 GHz, the OIP3 value decreases to approximately 37 dBm. The peak OIP3 value near 2 GHz indicates that the amplifier's linearity is optimal near this frequency point, capable of handling higher power input signals without significant third-order intermodulation distortion. The structure provided by this invention can significantly improve the amplifier's linearity indicators such as the third-order intermodulation intercept (IIP3); through harmonic cancellation, the amplifier can handle higher power input signals without significant nonlinear distortion, thereby improving the system's dynamic range and signal transmission quality.

[0058] In summary, the high linearity, low noise amplifier based on harmonic suppression provided by this invention has a basic structure of a single-stage cascode amplifier circuit. Specifically, the first amplifying transistor M1, the second amplifying transistor M2, and the first microstrip line Ls1 constitute the basic cascode amplifier circuit. A smaller auxiliary third amplifying transistor M3 is connected in parallel with the first amplifying transistor M1, forming an auxiliary amplifier circuit together with the second microstrip line Ls2. Noise matching and input matching networks, an active bias structure, and a predistortion structure are applied to the cascode stage and auxiliary stage, respectively. A dual RC negative feedback structure is applied to both the cascode stage and the common-source stage. The linearity enhancement structure is applied to the common-source stage of the cascode structure. The auxiliary pHEMT transistor is connected in parallel with the common-source pHEMT transistor, and then connected via a microstrip line, achieving suppression of higher harmonics. Simultaneously, the source microstrip line of the auxiliary pHEMT transistor and the common-source pHEMT transistor can act as a degraded inductor, achieving both minimum noise matching and impedance matching. The linearity enhancement structure is subject to mutual constraints among noise, linearity, and matching, and a trade-off must be made during the design. In order to improve linearity, the high-order harmonics of the auxiliary pHEMT transistor and the common-source pHEMT transistor should be canceled out. A pre-distortion mechanism is added to the gate of the common-gate stage to stabilize the bias voltage of the common-gate stage. At the same time, placing this structure on the gate of the common-gate stage can reduce noise. Combined with the dual RC negative feedback structure, it can improve return loss and increase bandwidth.

[0059] Furthermore, the linearity enhancement structure is applied to the common source stage in the cascode structure. The two cancel high-order harmonics through different bias voltages and sizes, effectively improving the linearity of the overall circuit. At the same time, the source microstrip lines of the two are used to improve minimum noise matching and enhance noise performance.

[0060] Since adding the predistortion structure to the gate of the common-source stage or the gate of the auxiliary transistor has a significant impact on noise performance, the predistortion structure is added to the gate of the common-gate stage. This reduces noise while improving linearity. Combined with dual RC negative feedback, low-frequency gain is suppressed, increasing the overall circuit bandwidth.

[0061] Based on 0.25µm GaAs pHEMT technology, a bandwidth of 1.2-2.5GHz was achieved using only a single-stage cascode amplifier unit, with a noise figure of less than 0.56dB and an OIP3 of 39.5-51.8dBm within the band. This demonstrates lower noise compared to Darlington structures.

[0062] The active predistortion diode can stabilize the common-gate bias voltage because the device's VGS is relatively stable. This provides a very strong level stabilization effect on the drain of the linearity enhancement structure, thereby greatly improving linearity. Furthermore, the microstrip line structure in the linearity enhancement structure alters the node impedance of the cascode, which is more conducive to noise decoupling, thus reducing noise.

[0063] In the prior art, the structure combined with the auxiliary tube can only improve linearity within a very narrow bandwidth. The present invention combines the source microstrip line structure to change the optimal impedance matching point of IMD3 within a larger bandwidth, thereby improving input matching and noise matching, and improving linearity within a larger bandwidth.

[0064] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce a good effect.

[0065] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A high linearity low noise amplifier based on harmonic rejection, characterized by, At least comprising: a noise matching and input matching network, a linearity enhancement structure, a negative feedback structure and a pre-distortion structure; wherein the linearity enhancement structure at least comprises a first amplification transistor and a second amplification transistor arranged in parallel, for improving the linearity of the circuit through harmonic cancellation; the negative feedback structure is connected with the noise matching and input matching network, the pre-distortion structure, for expanding the bandwidth of the circuit and optimizing the output matching; the pre-distortion structure is used for stabilizing the bias voltage of the third amplification transistor.

2. The high linearity low noise amplifier based on harmonic suppression of claim 1, wherein, Further comprising: an active biasing structure; the active biasing structure at least comprises a biasing transistor, a choke resistance, a voltage dividing resistance and a bypass capacitor; the biasing transistor is used for dynamic voltage division, the biasing transistor comprises a fourth amplification transistor, a fifth amplification transistor and a sixth amplification transistor; the choke resistance comprises a first choke resistance and a second choke resistance; the voltage dividing resistance comprises a second resistance, a third resistance, a fourth resistance, a fifth resistance and a sixth resistance; the bypass capacitor is a fifth capacitor; the active biasing structure provides biasing for the first amplification transistor, the second amplification transistor and the third amplification transistor; the biasing of the third amplification transistor is provided in a resistance voltage dividing manner, and the active biasing structure is powered by a single power supply.

3. The high linearity low noise amplifier based on harmonic suppression of claim 2, wherein, In the active biasing structure, the drain of the fourth amplification transistor is connected with the second resistance, the gate of the fifth amplification transistor and the gate of the sixth amplification transistor respectively, and the source is grounded; the drain of the fifth amplification transistor is connected with the third resistance, the source of the fifth amplification transistor is connected with the fifth resistance; the drain of the sixth amplification transistor is connected with the fourth resistance, and the source of the sixth amplification transistor is connected with a voltage node, a fifth capacitor and a sixth resistance respectively; the other ends of the second resistance, the third resistance and the fourth resistance are connected with a direct current power supply; the other ends of the fifth resistance and the sixth resistance are grounded; the other end of the fifth capacitor is grounded.

4. The high linearity low noise amplifier based on harmonic suppression of claim 2, wherein, The noise matching and input matching network at least comprises: a first inductor, a microstrip line, a first capacitor, a fourth capacitor and the parasitic capacitance of the first amplification transistor and the first amplification transistor; an RF input port is connected with one end of the first capacitor, the first capacitor is connected with the first inductor in parallel, and the other end of the first inductor is grounded; the gate of the first amplification transistor is connected with one end of a biasing resistance, and the other end of the biasing resistance is connected with a direct current bias voltage.

5. The high linearity low noise amplifier based on harmonic suppression of claim 4, wherein, The basic structure of the high linearity low noise amplifier based on harmonic suppression is a single-stage common-source common-gate, the first amplification transistor, the second amplification transistor and the third amplification transistor constitute a common-source common-gate amplifier structure, the first amplification transistor and the second amplification transistor constitute a common-source stage, and the third amplification transistor constitutes a common-gate stage; wherein the first amplification transistor, the second amplification transistor and the microstrip line constitute a basic common-source common-gate amplification circuit; a smaller third amplification transistor is connected in parallel on the first amplification transistor, and together with the microstrip line, an auxiliary amplification circuit is constituted. The noise matching and input matching network, the active bias structure act on the common source stage and the auxiliary stage, and the pre-distortion structure acts on the common gate stage amplification circuit.

6. The high linearity low noise amplifier based on harmonic suppression of claim 1, wherein, The pre-distortion structure comprises a diode, a first resistor and a third capacitor. The anode of the diode is grounded, the cathode of the diode is connected to the gate of the second amplification transistor through the first resistor, the other end of the first resistor is connected to the third capacitor, and the other end of the third capacitor is grounded.

7. The high linearity low noise amplifier based on harmonic suppression of claim 5, wherein, The negative feedback structure is a double-RC negative feedback structure, the negative feedback structure comprises a plurality of feedback resistors and a plurality of feedback capacitors, and the double-RC negative feedback structure is connected to the second capacitor. The double-RC negative feedback structure comprises a first feedback path and a second feedback path, the first feedback path is fed back from the output end of the third amplification transistor to the gate of the common source stage, and the second feedback path is fed back from the output end of the third amplification transistor to the gate of the common gate stage.

8. The high linearity low noise amplifier based on harmonic suppression of claim 7, wherein, The feedback resistors comprise a first feedback resistor, a second feedback resistor and a third feedback resistor, and the feedback capacitors comprise a first feedback capacitor and a second feedback capacitor. One end of the first feedback resistor is connected to the drain of the second amplification transistor, the other end of the first feedback resistor is connected to the first feedback capacitor, the other end of the first feedback capacitor is connected to the first feedback resistor, the other end of the first feedback resistor is connected to the gate of the first amplification transistor, one end of the third feedback resistor is connected to the drain of the second amplification transistor, the other end of the third feedback resistor is connected to the second feedback capacitor, the other end of the second feedback capacitor is connected to the gate of the second amplification transistor, and the first feedback resistor, the second feedback resistor and the third feedback resistor determine the feedback depth.

9. The high linearity low noise amplifier based on harmonic suppression of claim 4, wherein, The microstrip line comprises a first microstrip line and a second microstrip line, the first microstrip line is connected to the source of the first amplification transistor, and the second microstrip line is connected to the source of the second amplification transistor. The microstrip line provides a real part for the input characteristic impedance, so that the minimum noise matching point and the optimal impedance matching point are close to each other on a Smith chart.

10. The high linearity low noise amplifier based on harmonic suppression of claim 1, wherein, The size of the first amplification transistor in the linearity enhancement structure is greater than the size of the second amplification transistor, and the first amplification transistor and the second amplification transistor are configured to work at different bias voltages.

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