Conversion method, conversion control method, and device for circuit netlist

Abstract

A method, control method, and apparatus for converting circuit netlists are disclosed. The method includes: acquiring and parsing a circuit netlist; constructing intermediate netlist data, which includes netlist component data and netlist topology data, wherein the netlist component data characterizes the electrical parameters of circuit components, and the netlist topology data characterizes the connection relationships of circuit components; converting the netlist component data into schematic component data according to the component configuration rules of a target electronic design automation (EDA) tool; determining the location information of circuit components and the routing information between circuit components based on the netlist topology data, and generating schematic layout data adapted to the target EDA tool; and generating a circuit schematic file using the target EDA tool based on the schematic component data and the schematic layout data. This application has the technical effect of improving the efficiency of circuit netlist conversion.

Description

Technical Field

[0001] This disclosure relates to the field of electronic design automation technology, and in particular to a method, control method, and apparatus for converting circuit netlists. Background Technology

[0002] Electronic Design Automation (EDA) is a core supporting technology for integrated circuit design and verification. In the EDA workflow, the netlist, as a textual language describing circuit components and their connections, is a key data carrier connecting different design stages; while the schematic is a graphical representation of the circuit's logic structure, helping engineers intuitively analyze circuits and diagnose faults. With the increasing scale of integrated circuit designs, converting netlists into visual schematics has become a crucial requirement in scenarios such as integrated circuit verification and reverse engineering. However, with the increasing complexity of circuit netlists, existing conversion technologies face significant challenges in terms of component layout readability, tool universality, and scalability. Therefore, how to efficiently and flexibly convert complex circuit netlists into clear schematics is a problem worthy of attention in the current EDA technology field. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a method, control method, and apparatus for converting circuit netlists, in order to improve the efficiency of circuit netlist conversion.

[0004] Firstly, a method for converting a circuit netlist is provided, comprising: acquiring and parsing a circuit netlist, constructing intermediate netlist data, the intermediate netlist data including: netlist component data and netlist topology data, wherein the netlist component data is used to characterize the electrical parameters of circuit components, and the netlist topology data is used to characterize the connection relationships of circuit components; converting the netlist component data into schematic component data according to the component configuration rules of the target electronic design automation tool; determining the location information of circuit components and the routing information between circuit components based on the netlist topology data, generating schematic layout data adapted to the target electronic design automation tool; and generating a circuit schematic file using the target electronic design automation tool based on the schematic component data and the schematic layout data.

[0005] Optionally, it also includes: performing data verification based on schematic component data, schematic layout data, and netlist intermediate data. The data verification includes at least one of the following methods: verifying whether the number of ports of the circuit components before and after the conversion is consistent; verifying whether the network connectivity of the circuit components before and after the conversion is consistent; verifying whether the electrical parameters of the circuit components before and after the conversion are consistent; and verifying whether there is layout overlap of the circuit components in the schematic layout data.

[0006] Optionally, the netlist topology data is constructed based on a hypergraph structure, where the ports of circuit elements are used as vertices and the set of all ports with the same connection relationship is used as a hyperedge.

[0007] Optionally, the netlist component data includes multiple circuit element units, and the data of the circuit element units is stored in the form of a key-value pair mapping table. According to the component configuration rules of the target electronic design automation tool, the netlist component data is mapped and converted into schematic component data, including: traversing the circuit element units and extracting component type information from the key-value pair mapping table; matching the component type information with the component definition of the target electronic design automation tool to determine the component data structure; and mapping and filling the attribute parameters in the key-value pair mapping table into the component data structure based on preset parameter matching rules to generate schematic component data.

[0008] Optionally, determining the location information of circuit elements and the routing information between circuit elements based on netlist topology data includes: converting the netlist topology data into a graph structure with circuit elements as vertices; calculating the graph structure based on a force-directed algorithm to determine the coordinate positions of circuit elements on the schematic map, and using the coordinate positions as location information; and calculating the interconnection paths between the ports of circuit elements based on the coordinate positions, the connection relationships in the netlist topology data, and a point-to-point obstacle avoidance algorithm, and using the interconnection paths as routing information.

[0009] Optionally, it also includes: receiving custom extension instructions from external input, and processing intermediate netlist data according to the custom extension instructions. The processing includes at least one of the following methods: loading an externally input script file, parsing the data processing logic defined in the script file, and using the data processing logic to modify the intermediate netlist data; loading an externally input dynamic link library, and calling the specified function interface in the dynamic link library to calculate or modify the intermediate netlist data.

[0010] Optionally, determining the location information of circuit components and the routing information between circuit components based on netlist topology data to generate schematic layout data adapted to the target electronic design automation tool also includes: determining whether the size of the netlist topology data exceeds a preset size threshold; when it exceeds the preset size threshold, dividing the netlist topology data into multiple sub-graph structures based on the connection relationship of the netlist topology data, determining the location information and routing information of each sub-graph structure, and merging the processing results of each sub-graph structure to generate schematic layout data.

[0011] Secondly, a method for controlling the conversion of a circuit netlist is provided, comprising: acquiring an externally input process description text, the process description text being used to define the process type and execution logic of the circuit netlist conversion; parsing the process description text, assembling internal processes and external processes to form an execution process chain, wherein the internal processes include at least the following processes: a netlist parsing process, used to parse the circuit netlist to construct intermediate netlist data including netlist component data and netlist topology data; a component mapping processing process, used to convert netlist component data into schematic component data; and a schematic layout processing process, used to generate schematic layout data based on the netlist topology data. This tool adapts to schematic layout data for target electronic design automation (EDA) tools; the schematic construction process generates circuit schematic files based on schematic component data and schematic layout data; external processes are user-defined processing processes, including: loading externally input script files, parsing the data processing logic defined in the script files, and modifying intermediate netlist data using the data processing logic; or, loading externally input dynamic link libraries and calling specified function interfaces in the dynamic link libraries to calculate or modify intermediate netlist data; and scheduling and executing processes according to the preset order defined in the execution process chain to complete the circuit netlist conversion.

[0012] Optionally, the operations are scheduled and executed in a preset order as defined by the operation chain to complete the conversion of the circuit netlist, including at least one of the following execution modes: fully automatic mode, which is configured to execute all operations continuously at once according to the operation chain; single-step debugging mode, which is configured to execute operations one by one and receive user instructions between operations, the user instructions being used to dynamically edit, insert or replace subsequent operations to be executed.

[0013] Thirdly, a circuit netlist conversion device is provided, comprising: a construction unit for acquiring and parsing a circuit netlist, constructing intermediate netlist data, the intermediate netlist data including: netlist component data and netlist topology data, wherein the netlist component data is used to characterize the electrical parameters of circuit components, and the netlist topology data is used to characterize the connection relationships of circuit components; a first conversion unit for converting the netlist component data into schematic component data according to the component configuration rules of the target electronic design automation tool; a second conversion unit for determining the location information of circuit components and the routing information between circuit components based on the netlist topology data, generating schematic layout data adapted to the target electronic design automation tool; and a generation unit for generating a circuit schematic file using the target electronic design automation tool based on the schematic component data and the schematic layout data. Attached Figure Description

[0014] The accompanying drawings used in the description of the embodiments of this disclosure are briefly introduced below:

[0015] Figure 1A schematic flowchart of a circuit netlist conversion method provided in some embodiments of this application is shown;

[0016] Figure 2 The diagram illustrates a flowchart of a method for determining the location information of circuit elements and the routing information between circuit elements based on netlist topology data, provided in some embodiments of this application.

[0017] Figure 3 The diagram shows a flowchart of a circuit netlist conversion control method provided in some embodiments of this application;

[0018] Figure 4 A schematic diagram of a circuit netlist conversion device is shown in some embodiments of this application. Detailed Implementation

[0019] To more clearly illustrate the technical solutions in the embodiments of this disclosure, examples of implementation methods of this disclosure will be described below with reference to the accompanying drawings. The accompanying drawings described below are merely some embodiments of this disclosure. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without creative effort. Adjustments and improvements made without departing from the concept of this disclosure are all within the protection scope of this disclosure.

[0020] To keep the drawings simple, each figure only schematically shows the parts relevant to the embodiment, and they do not represent the actual structure of the product. In addition, for the sake of clarity and ease of understanding, some figures only schematically show parts of components with the same structure or function, and there may actually be more or fewer components with the same structure or function.

[0021] In this disclosure, unless otherwise expressly specified and limited, ordinal numbers, such as “first”, “second”, etc., are used only to distinguish and describe related objects, and should not be construed as indicating or implying the relative importance or order between related objects; furthermore, they do not represent the quantity of related objects. “Multiple” includes two or more, and other quantifiers are similar. “ / ” is used to describe the relationship between related objects, indicating an “or” relationship between them. “And / or” is used to describe the relationship between related objects, including any combination relationship between them, such as “a and / or b” including: “a alone”, “b alone”, or “a and b”. “One or more” or “at least one” of multiple objects refers to any object or any combination of multiple objects, such as “one or more of a1, a2, a3” or “at least one of a1, a2, a3” including: “a1 alone”, “a2 alone”, “a3 alone”, “a1 and a2”, “a1 and a3”, “a2 and a3”, or “a1, a2 and a3”.

[0022] In the field of electronic design automation (EDA), the interaction and transfer of circuit design data primarily rely on netlists. Netlists meticulously record instances of all components, port attributes, and network topologies, serving as an indispensable textual description in the integrated circuit design process. In contrast, schematics visually represent the circuit's composition and logical relationships through graphical symbols and connections, providing engineers with the core basis for understanding design intent, conducting circuit analysis, and troubleshooting. Reverse engineering netlists into schematics essentially involves reconstructing machine-readable structured text into human-understandable visual images. This technology is widely used in chip design verification, reverse engineering analysis, and debugging after extracting layout circuits. However, current netlist-to-schematic conversion tools are relatively scarce, and existing technologies are mostly limited to component parameter mapping within specific EDA environments, lacking a universal conversion architecture. With the dramatic increase in the complexity of modern integrated circuit design, netlists often contain tens of thousands of components and interconnections. Traditional conversion methods often face layout difficulties when dealing with such large-scale, complex netlists, resulting in automatically generated schematics with messy component placement and severe overlapping connections, significantly impacting readability. Furthermore, existing tools typically lack a flexible intermediate representation layer and extended interfaces, making it difficult to adapt to various netlist source formats or meet users' customized processing needs. In view of this, this application provides a circuit netlist conversion method, conversion control method, and apparatus. By introducing unified netlist intermediate data and schematic layout data, combined with schematic layout and routing generation mechanisms, it reliably reconstructs arbitrarily complex circuit netlists into clear circuit schematics.

[0023] The following description is in conjunction with the accompanying drawings:

[0024] Please refer to Figure 1 It illustrates a flowchart of a circuit netlist conversion method provided in some embodiments of this application, including:

[0025] S110: Obtain and parse the circuit netlist, and construct intermediate netlist data. The intermediate netlist data includes netlist element data and netlist topology data. The netlist element data is used to characterize the electrical parameters of the circuit elements, and the netlist topology data is used to characterize the connection relationships of the circuit elements.

[0026] S120: Convert netlist component data into schematic component data according to the component configuration rules of the target electronic design automation tool;

[0027] S130: Based on netlist topology data, determine the location information of circuit components and the routing information between circuit components, and generate schematic layout data adapted to the target electronic design automation tool;

[0028] S140: Generate circuit schematic files using the target electronic design automation tool based on schematic component data and schematic layout data.

[0029] In the above embodiments, a circuit netlist file to be processed is received. Since circuit netlists from different electronic design automation (EDA) tools may use different syntax formats, this application can convert them into intermediate netlist data with a unified expression, independent of the original netlist syntax, through parsing operations. This intermediate netlist data mainly contains two parts of information: one part is netlist component data, used to characterize the electrical parameter attributes of each circuit component in the circuit. For example, these electrical parameter attributes record the type of circuit component, such as resistor, capacitor, chip, etc., identifiers, and specific parameter values, such as resistance value, capacitance value, model, etc. The other part is netlist topology data, used to characterize the connection relationships between circuit components, thereby recording the topology of each port of the circuit component and how these ports are electrically connected through the network. After constructing the unified intermediate netlist data, it needs to be adapted to the specific target EDA tool environment. Therefore, data mapping conversion can be performed according to pre-set component configuration rules. The component configuration rules define how the circuit component parameters in the netlist correspond to the component attributes in the target electronic design automation (EDA) tool. Furthermore, the general netlist component data from step S110 can be converted into schematic component data that the target EDA tool can recognize and render. This data contains all the definition information required to generate a specific component instance on the schematic canvas. Based on the connection density described in the netlist topology data, the location information of each circuit component on the 2D schematic drawing is determined through layout processing, such as the specific coordinates of the circuit component ports. Simultaneously, based on the determined locations of the circuit components and the connection relationships between ports, the routing information of the wires between the circuit components is determined, such as the path nodes of the wires. Finally, the determined location information and routing information are integrated to generate schematic layout data. At this point, the data format is adapted to the target EDA tool and can be used by the tool to guide the drawing. After preparing all the necessary data, components can be instantiated on the drawing using the converted schematic component data, and these components can be placed in designated locations and connected using the schematic layout data. Ultimately, the target electronic design automation tool outputs or saves a complete circuit schematic file, realizing the restoration from a text netlist to a graphical circuit diagram. This application constructs unified netlist intermediate data to form schematic component data and schematic layout data, enabling it to flexibly adapt to various input netlist formats without requiring the development of separate conversion logic for each format, thus significantly improving the universality and compatibility of the technical solution. Furthermore, by determining component locations and routing information based on netlist topology data, it solves the component stacking or layout chaos problems that easily occur in traditional netlist conversion. This method can automatically plan the layout based on connection relationships, generating a clear and readable schematic without manual intervention, improving the efficiency of circuit design analysis or verification.

[0030] In some embodiments of this application, the method further includes: performing data verification based on schematic component data, schematic layout data, and netlist intermediate data. The data verification includes at least one of the following methods: verifying whether the number of ports of the circuit components before and after the conversion is consistent; verifying whether the network connectivity of the circuit components before and after the conversion is consistent; verifying whether the electrical parameters of the circuit components before and after the conversion are consistent; and verifying whether there is layout overlap of the circuit components in the schematic layout data.

[0031] To ensure the accuracy and reliability of the conversion results, this application can also perform a data verification step before generating the schematic file. This step is based on a comparative analysis of schematic component data, schematic layout data, and intermediate netlist data. When verifying whether the number of ports of circuit components is consistent before and after conversion, each circuit component in the intermediate netlist data can be traversed to obtain its defined port list and quantity. Simultaneously, the number of instantiated symbol ports in the corresponding schematic component data is checked. By comparing whether the two are equal, pin loss problems caused by component library matching errors or missing mapping rules can be identified. If the quantities are inconsistent, the system will generate an error message. When verifying whether the network connectivity of circuit components is consistent before and after conversion, the routing connections in the netlist topology data and schematic layout data can be compared. For example, by verifying whether all ports connected to the same network in the netlist topology data are still electrically connected by wires in the schematic layout data, it can be ensured that the logic function of the circuit has not changed during the conversion process, preventing open circuit or short circuit errors. When verifying the consistency of electrical parameters of circuit components before and after conversion, key electrical attributes such as resistance, capacitance, chip type, or aspect ratio can be read from the netlist component data and compared one by one with the attribute values ​​in the generated schematic component data. This ensures that all design constraints and specifications are accurately preserved during parameter mapping, without data tampering or loss. When checking for layout overlaps of circuit components in the schematic layout data, a geometric collision detection algorithm can be executed based on the spatial location information and component geometry determined in the schematic layout data. This checks whether the occupied areas of any two circuit components overlap on the canvas, or whether there is illegal physical interference between circuit components and wires. If an overlap is detected, the area will be marked and a warning message will be provided for subsequent adjustment of layout algorithm parameters or manual correction. Traditional netlist conversion tools often only focus on whether generation is possible, neglecting the correctness of the generated result. This application introduces a data verification mechanism to verify the circuit's connection logic, physical parameters, and geometric layout before generating the schematic file. Through consistency verification, it effectively prevents functional distortion of the circuit due to logical errors, ensuring that the generated schematic file is completely identical to the original circuit netlist in terms of electrical characteristics. Furthermore, through layout overlap verification, it effectively avoids routing chaos that may occur during automatic layout, ensuring that the generated schematic is clear and standardized, and reducing the workload and possibility of engineers manually organizing the drawings later.

[0032] In some embodiments of this application, the netlist topology data is constructed based on a hypergraph structure, wherein the hypergraph structure uses the ports of circuit elements as vertices and the set of all ports with the same connection relationship as a hyperedge.

[0033] In traditional graph theory, an edge typically connects only two vertices. However, in electronic circuits, a network often connects multiple ports of multiple components simultaneously; for example, a power / ground wire might connect dozens of components. To accurately describe such one-to-many or many-to-many connections, this application employs a hypergraph structure. When constructing vertices, the netlist component data is traversed, and each independent port of each circuit component is instantiated as a hypergraph vertex. For example, a transistor with three ports will generate three corresponding vertices in the hypergraph. In actual storage, each vertex data structure contains the name of its associated circuit component and its port number. When constructing hyperedges, the network definition in the netlist is parsed, and the set of all port vertices with the same electrical connection is encapsulated as a hyperedge. This hyperedge represents the physical equipotential connection of the network. Besides basic connections, hyperedges can also be used to store attribute information related to the connection parsed from the netlist, i.e., connection attachment data. For example, the hyperedge data structure can store the name of the wire, the wire width requirement, or the identifier of the simulation probe connected to the network. Traditional graph structures can only represent point-to-point binary relationships. If used to represent signal networks connecting multiple pins, they need to be broken down into multiple pairs of connected edges, thus increasing data redundancy. The hypergraph structure used in this application conforms to the physical characteristics of circuit topologies and can efficiently and accurately store and retrieve complex multi-terminal connection relationships.

[0034] In some embodiments of this application, the netlist component data includes multiple circuit component units, and the data of the circuit component units is stored in the form of a key-value pair mapping table. According to the component configuration rules of the target electronic design automation tool, the netlist component data is mapped and converted into schematic component data, including: traversing the circuit component units and extracting component type information from the key-value pair mapping table; matching the component type information with the component definition of the target electronic design automation tool to determine the component data structure; and mapping and filling the attribute parameters in the key-value pair mapping table into the component data structure based on preset parameter matching rules to generate schematic component data.

[0035] To ensure compatibility with the parsing results of circuit netlists of any format, each circuit element cell is stored using a key-value pair mapping table. The key represents the parameter name, and the value represents the parameter value; both can be string types. This storage method removes the characteristics of specific circuit netlist languages, facilitating subsequent program traversal and analysis. Furthermore, the circuit element cells are traversed, and element type information is extracted from the key-value pair mapping table. Each circuit element cell is read individually, and the key field identifying the element type is searched in the key-value pair mapping table, extracted as element type information, and used as the basis for subsequent matching. The target electronic design automation tool has a pre-stored standard component definition library. This application matches the extracted component type information with components in this library, for example, performing exact name matching. Once a match is successful, the corresponding component data structure in the target electronic design automation tool can be located. This component data structure contains all the information required to instantiate the component in the schematic, such as component primitives and component port definitions. Considering that parameter naming in the circuit netlist may differ from attribute naming in the target electronic design automation (EDA) tool, preset parameter matching rules, such as rules supporting fuzzy matching or synonym mapping, can be used to assign the attribute parameters in the key-value pair mapping table to the corresponding fields in the component data structure. Through this process, the original circuit netlist data is transformed into schematic component data that the target EDA tool can directly recognize and render. The above implementation effectively solves the data compatibility problem between different netlist formats and specific EDA tools through standardized key-value pair storage and a rule-based automatic mapping mechanism, achieving the reconstruction of circuit component data.

[0036] Figure 2 This illustration shows a flowchart of a method for determining the location information of circuit elements and the routing information between circuit elements based on netlist topology data, according to some embodiments of this application. It includes:

[0037] S210: Convert netlist topology data into a graph structure with circuit elements as vertices;

[0038] S220: Calculates the graph structure based on the force-oriented algorithm, determines the coordinate position of the circuit element on the schematic diagram canvas, and uses the coordinate position as position information;

[0039] S230: Based on coordinate location, connection relationships in netlist topology data, and point-to-point obstacle avoidance connection algorithm, calculate the interconnection path between ports of circuit elements and use the interconnection path as routing information.

[0040] In netlist topology data, a hypergraph structure is typically used to store connections between ports. While this accurately describes electrical connections, it's unsuitable for direct macroscopic component placement calculations. Therefore, a graph structure transformation can be performed first. This involves traversing all hyperedges in the netlist topology data and identifying the circuit components to which each hyperedge connects to a set of ports. Next, a new simple or weighted graph is constructed, abstracting each circuit component as a vertex. If two circuit components are electrically connected (i.e., their ports belong to the same network), an edge is created between these two vertices. If multiple electrical connections exist between two components, the edge weight can be increased, or multiple edges can be created. This abstracts the complex port-level connections into a component-level topology graph, laying the data foundation for subsequent mechanical simulations. Force-oriented algorithms can iteratively calculate graph structures, simulating circuit layout problems as a physical and mechanical system. In the repulsive force simulation, each vertex (circuit element) in the graph is considered a particle with the same charge. An electrostatic repulsion force exists between any two vertices based on Coulomb's law, causing all elements on the canvas to tend to move away from each other, avoiding overlap or overcrowding. In the gravitational force simulation, each edge (electrical connection) in the graph is considered a spring, and a spring-like attraction exists between two connected vertices based on Hooke's law. This attraction causes electrically connected elements to tend to move closer together. By iteratively calculating the displacement of each vertex under the resultant force, the vertex coordinates are continuously updated until the total energy is reduced to a minimum or a preset equilibrium state is reached. At this point, the coordinates of each vertex are determined as the position information of the circuit element on the schematic diagram canvas. After determining the macroscopic position of the circuit element, the specific wire paths can be further calculated. Combining the coordinate position of the circuit element and the relative offset of the ports defined inside the element, the absolute coordinates of each port on the canvas are calculated. Furthermore, based on the connection relationships in the netlist topology data, ports to be connected are selected in pairs, and a point-to-point obstacle avoidance connection algorithm is used to plan the connection path from the starting point to the ending point. During the path planning process, the algorithm treats the placed circuit components as obstacles, and the generated path must bypass these obstacle areas to prevent wires from passing through the component bodies, while maintaining the orthogonality of the traces (such as horizontal or vertical line segments) as much as possible to conform to the schematic drawing specifications. The final calculated path, consisting of a series of polyline segments or nodes, is the routing information determined as the interconnection path, used to guide subsequent graphical drawing.

[0041] In some embodiments of this application, the method further includes: receiving custom extension instructions from external input, and processing intermediate netlist data according to the custom extension instructions. The processing includes at least one of the following methods: loading an externally input script file, parsing the data processing logic defined in the script file, and modifying the intermediate netlist data using the data processing logic; loading an externally input dynamic link library, and calling a specified function interface in the dynamic link library to calculate or modify the intermediate netlist data.

[0042] To meet users' customized needs for specific circuit netlist formats, private parameter processing, or specific design flows, this application introduces an extensible external processing mechanism. This mechanism can receive custom extended instructions from external sources and perform in-depth custom processing on the intermediate netlist data constructed in step S110 based on these instructions. For example, it can load user-specified external script files, read and parse the data processing logic defined in those script files. This logic can include, but is not limited to: custom intermediate expression definitions, declarations of specific data types, and filtering and modification rules for netlist component data or topology data. For example, it can unify the unit of all resistance values ​​to ohms or delete all dangling network nodes. After parsing, the intermediate netlist data can be accessed and modified directly in memory using this data processing logic. This approach allows users to quickly adjust the conversion logic by simply modifying the text script without recompiling the main program, greatly improving the tool's flexibility. On the other hand, it can load externally input dynamic link library files, utilizing the operating system's dynamic linking mechanism to load the library into the process's address space during program execution and locate the specified function interface based on the function name provided in the instructions. Then, the function is executed, passing the current intermediate netlist data as a parameter. This approach is not only highly efficient but also supports zero-downtime hot-swapping.

[0043] In some embodiments of this application, determining the location information of circuit elements and the routing information between circuit elements based on netlist topology data to generate schematic layout data adapted to the target electronic design automation tool further includes: determining whether the size of the netlist topology data exceeds a preset size threshold; when it exceeds the preset size threshold, dividing the netlist topology data into multiple sub-graph structures based on the connection relationship of the netlist topology data, determining the location information and routing information of each sub-graph structure, and merging the processing results of each sub-graph structure to generate schematic layout data.

[0044] To address the performance bottleneck of large-scale circuit netlists during layout calculations, the process of generating schematic layout data in step S130 can also employ subgraph partitioning. First, the scale of the netlist topology data is analyzed, counting the total number of circuit element nodes or network connections contained in the netlist. This statistical result is compared with a preset scale threshold (e.g., 1000 elements or 5000 nodes), which can be set based on the performance limits of the computing hardware or the time complexity curve of the layout algorithm. When the netlist size exceeds the preset scale threshold, it is determined that directly performing global layout may lead to excessive computation time or memory overflow. In this case, based on the connection relationships in the netlist topology data, a graph partitioning algorithm is applied to divide the massive global topology network into multiple subgraph structures. The principle of partitioning is usually to make the connections within each subgraph as close as possible, while minimizing the connections between subgraphs, thereby ensuring the functional cohesion of the circuit modules. For each segmented subgraph structure, it is treated as an independent micro-netlist, and the position determination and routing determination steps S130 are performed independently. For example, a force-directed algorithm is applied to each subgraph to calculate the position information of the circuit components within the subgraph; and path planning is performed on the internal connections of each subgraph to determine the routing information. Since the data size of each subgraph is small and they are independent of each other, this step can be executed in parallel using multi-threaded or distributed computing resources, greatly improving computational efficiency. After all subgraphs have been processed, a merging operation is performed. The relative layout positions of each subgraph on the global canvas can be determined based on the connection interfaces between the subgraphs, and the position information and routing information of the ground circuit components within each subgraph are mapped to the global coordinate system. Finally, the merged data is integrated into complete schematic layout data.

[0045] Figure 3 The diagram illustrates a flow chart of a circuit netlist switching control method provided in some embodiments of this application. The switching control method includes:

[0046] S310: Obtain the process description text from external input. The process description text is used to define the operation type and execution logic of circuit netlist conversion.

[0047] S320: Parse the process description text and assemble the internal and external processes into an execution process chain, wherein the internal processes include at least the following processes:

[0048] Netlist parsing process A1 is used to parse the circuit netlist to construct intermediate netlist data, which includes netlist component data and netlist topology data;

[0049] Component mapping process A2 is used to convert netlist component data into schematic component data;

[0050] Schematic layout processing step A3 is used to generate schematic layout data adapted to the target electronic design automation tool based on netlist topology data;

[0051] Schematic construction step A4 is used to generate circuit schematic files based on schematic component data and schematic layout data;

[0052] External processes are user-defined processing processes, including:

[0053] Load externally input script files, parse the data processing logic defined in the script files, and use the data processing logic to modify the intermediate data in the netlist; or,

[0054] Load externally input dynamic link libraries and call the specified function interfaces in the dynamic link libraries to perform calculations or modifications on the intermediate data of the netlist;

[0055] S330: Schedule and execute processes according to the preset sequence defined in the process chain to complete the conversion of the circuit netlist.

[0056] In this embodiment, the user is allowed to input a process description text, which can be written in a standardized data exchange format, such as JSON, XML, or YAML. Through the process description text, the user can explicitly define the steps required for the entire conversion task, as well as the sequential relationships and execution logic of these steps. For example, the text can define a sequence list containing parsing, correction, mapping, layout, and construction, thereby initiating the process to convert the circuit netlist. Upon reading the process description text, instantiation and assembly can be performed according to the definitions in the text. When a predefined standard function identifier is identified, the system instantiates the corresponding internal process (i.e., the netlist parsing process A1, component mapping process A2, schematic layout process A3, or schematic construction process A4 described in detail in the previous embodiment). When a custom function identifier or external path is identified, the system instantiates the external process (i.e., the user-defined processing process). At this time, a specified external script file or dynamic link library can be loaded according to the configuration and encapsulated into a unified process execution unit. Furthermore, all the instantiated process units (which may include internal or external sources, or both) are sequentially connected according to the order defined in the text to construct a linear or branching execution process chain. After the process chain is constructed, the system can create a shared process context for transferring data (i.e., intermediate netlist data) between different processes. Subsequently, the execution methods of each process unit in the chain are called sequentially according to the preset order defined in the process chain. During execution, data flows from one process to the next. Internal processes perform standardized conversion tasks, while external processes intervene at specific nodes, using loaded scripts or dynamic library functions to customize the data. When the last process in the chain (e.g., schematic construction process A4) is completed, the entire circuit netlist conversion task is finished.

[0057] In some embodiments of this application, the internal process further includes a self-inspection process, used to perform data verification based on schematic component data, schematic layout data, and netlist intermediate data. The data verification includes at least one of the following methods: verifying whether the number of ports of the circuit components before and after the conversion is consistent; verifying whether the network connectivity of the circuit components before and after the conversion is consistent; verifying whether the electrical parameters of the circuit components before and after the conversion are consistent; and verifying whether there is layout overlap of the circuit components in the schematic layout data.

[0058] In some embodiments of this application, processes are scheduled and executed in a preset order defined by the execution process chain to complete the conversion of the circuit netlist, including at least one of the following execution modes: fully automatic mode, which is configured to execute all processes continuously at once according to the execution process chain; single-step debugging mode, which is configured to execute processes one by one and receive user instructions between process execution intervals, the user instructions being used to dynamically edit, insert or replace subsequent processes to be executed.

[0059] Figure 4 The diagram illustrates a schematic of a circuit netlist conversion device provided in some embodiments of this application. The circuit netlist conversion device 400 includes: a construction unit 410, configured to acquire and parse a circuit netlist, constructing intermediate netlist data, the intermediate netlist data including: netlist element data and netlist topology data, wherein the netlist element data characterizes the electrical parameters of circuit elements, and the netlist topology data characterizes the connection relationships of circuit elements; a first conversion unit 420, configured to convert the netlist element data into schematic element data according to the element configuration rules of the target electronic design automation tool; a second conversion unit 430, configured to determine the location information of circuit elements and the routing information between circuit elements based on the netlist topology data, generating schematic layout data adapted to the target electronic design automation tool; and a generation unit 440, configured to generate a circuit schematic file using the target electronic design automation tool based on the schematic element data and the schematic layout data.

[0060] The above division of units is merely a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. Furthermore, these units can be implemented by a processor calling software; for example, a signal processing device includes a processor coupled to memory, which stores instructions. The processor calls the instructions stored in memory to implement any of the above-mentioned circuit board model mesh hole processing methods or to implement the functions of each unit. The processor can be, for example, a general-purpose processor, such as a CPU, and the memory can be memory within a cross-platform acquisition device or memory outside of a cross-platform acquisition device. Alternatively, these units can be implemented as hardware circuits. The functions of some or all units can be implemented through the design of the hardware circuit, which can be understood as one or more processors. For example, the hardware circuit includes an application-specific integrated circuit (ASIC), which implements the functions of some or all units by designing the logical relationships between the components within the circuit. Another example is that the hardware circuit can be implemented using a programmable logic device (PLD), which can include a large number of logic gates. The logical relationships between the logic gates are configured through a configuration file, thereby implementing the functions of some or all units. All units of the above circuit board model mesh hole processing device can be implemented entirely through processor calling programs, or entirely through hardware circuits, or partially through processor calling programs and the remaining parts through hardware circuits.

[0061] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail or in a particular embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, the above embodiments can be freely combined as needed.

Claims

1. A conversion control method of a circuit netlist, characterized by, The method comprises the following steps: acquiring an external input flow description text used for defining a process type and execution logic of circuit netlist conversion; parsing the flow description text to assemble endogenous processes and exogenous processes to form an execution process chain, wherein the endogenous processes at least include the following processes: a netlist parsing process for parsing a circuit netlist to construct netlist intermediate data including netlist element data and netlist topology data, wherein the netlist element data is used to represent electrical parameters of circuit elements, and the netlist topology data is used to represent connection relationships of the circuit elements; an element mapping processing process for converting the netlist element data into schematic element data; a schematic layout processing process for determining position information of the circuit elements and routing information between the circuit elements based on the netlist topology data, and generating schematic layout data suitable for a target electronic design automation tool; a schematic construction process for generating a circuit schematic file according to the schematic element data and the schematic layout data; the exogenous processes are user-defined processing processes, including: loading an externally input script file, parsing data processing logic defined by the script file, and modifying the netlist intermediate data by using the data processing logic; or loading an externally input dynamic link library, and calling a specified function interface in the dynamic link library to calculate or modify the netlist intermediate data; scheduling and executing the processes in a preset order defined by the execution process chain to complete the conversion of the circuit netlist.

2. The conversion control method of a circuit netlist according to Claim 1, characterized by, Further comprising: performing data verification based on the schematic element data, the schematic layout data, and the netlist intermediate data, wherein the data verification includes at least one of the following ways: verifying whether the number of ports of the circuit elements before and after conversion is consistent; verifying whether the network connectivity of the circuit elements before and after conversion is consistent; verifying whether the electrical parameters of the circuit elements before and after conversion are consistent; verifying whether there is layout overlap of the circuit elements in the schematic layout data.

3. The conversion control method of a circuit netlist according to claim 2, characterized by, The netlist topology data is constructed based on a hypergraph structure, wherein the hypergraph structure takes the ports of the circuit elements as vertices, and takes a set of all the ports having the same connection relationship as a hyperedge.

4. The circuit netlist conversion control method according to claim 3, wherein the netlist element data includes a plurality of circuit element units, and data of the circuit element units is stored in the form of a key-value pair mapping table; the mapping and conversion of the netlist element data into schematic element data according to the element configuration rules of the target electronic design automation tool comprises: traversing the circuit element units to extract element type information from the key-value pair mapping table; matching the element type information with element definitions of the target electronic design automation tool to determine an element data structure; mapping and filling attribute parameters in the key-value pair mapping table into the element data structure based on a preset parameter matching rule to generate the schematic element data.

5. The conversion control method of a circuit netlist according to Claim 4, characterized by, The determining the position information of the circuit elements and the routing information between the circuit elements based on the netlist topology data comprises: converting the netlist topology data into a graph structure with the circuit elements as vertices; calculating the graph structure based on a force-directed algorithm to determine coordinate positions of the circuit elements on a schematic canvas and taking the coordinate positions as the position information; calculating interconnection paths between ports of the circuit elements based on the coordinate positions, connection relationships in the netlist topology data, and a point-to-point obstacle avoidance connection algorithm, and taking the interconnection paths as the routing information.

6. The conversion control method of a circuit netlist according to any one of claims 1 to 5, characterized by, The determining the position information of the circuit elements and the routing information between the circuit elements based on the netlist topology data to generate the schematic layout data adapted to the target electronic design automation tool further comprises: judging whether a size of the netlist topology data exceeds a preset size threshold; when the preset size threshold is exceeded, splitting the netlist topology data into multiple sub-graph structures based on connection relationships of the netlist topology data, respectively determining the position information and the routing information for the multiple sub-graph structures, and merging processing results of the sub-graph structures to generate the schematic layout data.

7. The conversion control method of a circuit netlist according to Claim 1, characterized by, The scheduling and executing processes in the preset order defined by the execution process chain to complete conversion of the circuit netlist comprises at least one of the following execution modes: a full-automatic mode configured to continuously execute all processes in one time according to the execution process chain; a single-step debugging mode configured to execute the processes one by one and receive user instructions between execution of the processes, the user instructions being used for dynamically editing, inserting, or replacing subsequent processes to be executed.

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