CAN gateway high-load-rate frame loss prevention method, device, equipment and medium

Abstract

The invention relates to a CAN gateway high-load-rate frame loss prevention method and device, equipment and a medium, and belongs to the technical field of automobile electronic communication. The CAN gateway high-load-rate frame loss prevention method comprises the following steps: if a target hardware mailbox needs to send message data and the target hardware mailbox is in a non-idle state, writing the message data to be sent into a circular FIFO queue for caching; the circular FIFO queue is an independent queue set for each CAN controller channel and is used for caching to-be-sent message data when a target hardware mailbox is not idle; and after the message data stored in the target hardware mailbox is sent, triggering and transmitting a sending completion interrupt signal, and writing the to-be-sent message data cached in the circulating FIFO queue into the target hardware mailbox for sending. According to the scheme, the problems of frame loss and high CPU occupation in a high-load scene are solved through a mechanism of circulating FIFO queue caching and interrupt triggering type sending, and a communication guarantee with functional safety and system stability is provided for the vehicle-mounted ECU.

Description

Technical Field

[0001] This application relates to the field of automotive electronic communication technology, specifically to a method, device, equipment, and medium for preventing frame loss at high load rates in a CAN gateway. Background Technology

[0002] Key electronic control units (ECUs) such as vehicle gateways and domain controllers need to ensure the real-time and reliable transmission of critical messages (such as chassis control and powertrain commands) under harsh environments with high bus load rates. This is an important guarantee for achieving vehicle functional safety.

[0003] In CAN communication, message transmission typically relies on hardware-provided transmission mailboxes. The upper-level application software of the ECU configures the messages to be sent into the hardware mailboxes, and the CAN controller automatically completes the transmission. However, the number of hardware mailboxes is limited. When the system communication load is high, all hardware mailboxes may be simultaneously in a "transmitting" or "waiting to transmit" state, which is full. At this time, if a new message needs to be sent, the following two processing methods are currently commonly used, but both have obvious drawbacks: The first method is direct discarding. When the upper-layer application needs to send a message, it first checks if there are any free mailboxes in the hardware mailbox. If all mailboxes are occupied, the transmission of the current frame message is abandoned. The drawback of this method is that when the bus load rate increases to a certain level (e.g., above 80%), the probability of the hardware mailboxes being full increases sharply, which will cause a large number of messages to be dropped instantly, resulting in a sharp drop in communication reliability and failing to meet the stringent requirements of automotive electronic systems for zero loss of key frames.

[0004] In the second approach, when the hardware mailbox is full, packets are not immediately discarded. Instead, the upper-layer application software periodically retryes sending them, forming a polling mechanism. The drawbacks of this method are: first, frequent retries under high load significantly increase CPU interrupt load and processing time, leading to peak CPU utilization and potentially affecting the execution of other real-time tasks in the system; second, such retries usually require a timeout mechanism. If the packet cannot be successfully sent within the timeout period, it will ultimately be discarded, essentially not solving the frame loss problem under high load, but only delaying its occurrence.

[0005] In summary, existing technologies struggle to balance reliable communication (no frame loss) and low system resource consumption (low CPU usage) under high load scenarios. Therefore, a new technical solution is needed to achieve lossless message transmission and efficient CPU resource utilization under extremely high bus loads. Summary of the Invention

[0006] This application provides a method, apparatus, device, and medium for preventing frame loss under high load rates in CAN gateways, which can solve the problems of frame loss and high CPU resource consumption in existing CAN message transmission methods under high load rates.

[0007] In a first aspect, embodiments of this application provide a method for preventing frame loss under high load conditions in a CAN gateway, including: If the target hardware mailbox needs to send message data and the target hardware mailbox is not idle, the message data to be sent is written into a circular FIFO queue for buffering; the circular FIFO queue is an independent queue set up for each CAN controller channel, used to buffer the message data to be sent when the target hardware mailbox is not idle; Once the message data stored in the target hardware mailbox has been sent, a transmission completion interrupt signal is triggered and transmitted, and the message data to be sent that is cached in the circular FIFO queue is written into the target hardware mailbox for transmission.

[0008] In some embodiments, if the target hardware mailbox needs to send message data and the target hardware mailbox is in an idle state, the message data is directly written into the target hardware mailbox and sent.

[0009] In some embodiments, after the message data stored in the target hardware mailbox has been sent, a transmission completion interrupt signal is triggered and transmitted, and the message data to be sent buffered in the circular FIFO queue is written into the target hardware mailbox for transmission; specifically including: Once all message data stored in the target hardware mailbox has been sent, a transmission completion interrupt signal is triggered and transmitted, and the message data to be sent that is cached in the circular FIFO queue is sequentially written into the target hardware mailbox for transmission.

[0010] In some embodiments, after the message data stored in the target hardware mailbox has been sent, a transmission completion interrupt signal is triggered and transmitted, and the message data to be sent buffered in the circular FIFO queue is written into the target hardware mailbox for transmission; specifically including: When a message data stored in the target hardware mailbox is sent, a sending completion interrupt signal is triggered and transmitted, and the header message data cached in the circular FIFO queue is written into the target hardware mailbox for transmission. The header message data is the message data to be sent that is first written into the circular FIFO queue.

[0011] In some embodiments, when the message data stored in the target hardware mailbox is sent and a sending completion interrupt signal is triggered and transmitted, it is detected whether the circular FIFO queue is not empty; If not empty, the header data to be sent in the circular FIFO queue is written into the target hardware mailbox and sent. After successful sending, the header data in the circular FIFO queue is deleted. Trigger a transmission completion interrupt within the target hardware mailbox, and repeat the above process until the circular FIFO queue is empty; the header message data is the message data that was first written into the circular FIFO queue.

[0012] In some embodiments, when writing the message data to be sent into a circular FIFO queue for buffering, if the circular FIFO queue is full, the header message data of the circular FIFO queue is popped out, and new message data to be sent is written to the tail of the circular FIFO queue; the header message data is the message data to be sent that was first written into the circular FIFO queue.

[0013] In some embodiments, when the target hardware mailbox needs to send message data, if the status register of the target hardware mailbox is detected to be in an idle state, it is determined that the target hardware mailbox is in an idle state; otherwise, it is determined that the target hardware mailbox is in a non-idle state.

[0014] Secondly, embodiments of this application provide a high-load-rate anti-frame-loss device for a CAN gateway, comprising: Create a module to set up an independent circular FIFO queue for the target hardware mailbox; The judgment module is used to determine the status of the target hardware mailbox and control the writing of message data; The processing module is used to trigger a send completion interrupt and process the message data in the circular FIFO queue.

[0015] Thirdly, embodiments of this application provide a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of any of the methods described above.

[0016] Fourthly, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the methods described above.

[0017] The beneficial effects of the technical solutions provided in this application include: This application provides a method, apparatus, device, and medium for preventing frame loss under high load conditions in a CAN gateway. The method for preventing frame loss under high load conditions in a CAN gateway includes: if a target hardware mailbox needs to send message data, and the target hardware mailbox is not idle, writing the message data to be sent into a circular FIFO queue for buffering; the circular FIFO queue is an independent queue set up for each CAN controller channel, used to buffer the message data to be sent when the target hardware mailbox is not idle; Once the message data stored in the target hardware mailbox has been sent, a transmission completion interrupt signal is triggered and transmitted, and the message data to be sent that is cached in the circular FIFO queue is written into the target hardware mailbox for transmission.

[0018] The method of this application introduces an independent circular FIFO queue mechanism for each CAN controller channel. When the upper layer application software needs to send message data through the target hardware mailbox, if it detects that the mailbox is not idle (i.e., it is full), the system no longer adopts the strategy of directly discarding or polling and retrying. Instead, it caches the message data to be sent in real time into the circular FIFO queue. The circular FIFO queue is an independent queue set up for each CAN controller channel.

[0019] This design avoids the problem of critical messages being momentarily dropped due to a full hardware mailbox, ensuring that critical messages are completely preserved and transmitted in an orderly manner under harsh operating conditions with consistently high bus load rates. This achieves zero-frame-loss guarantee in communication reliability, meeting the stringent functional safety requirements of automotive electronic systems. Simultaneously, by pushing the message transmission control logic down to a hardware interrupt triggering mechanism, once the target hardware mailbox completes the transmission of the current message and automatically triggers a transmission completion interrupt signal, the system only needs to write the message data buffered in the circular FIFO queue into the mailbox to continue transmission, without requiring any periodic polling or timeout retries from the upper-layer application software. This significantly reduces the CPU's interrupt handling load and computational overhead, avoids CPU utilization peaks caused by frequent retries, ensures stable and efficient system resource consumption, and does not interfere with the execution of real-time tasks such as power control and safety algorithms.

[0020] In summary, this solution overcomes the problems of frame loss and high CPU usage in high-load scenarios through a collaborative mechanism of cyclic FIFO queue buffering and interrupt-triggered transmission, providing the vehicle ECU with communication assurance that combines functional safety and system stability. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the method flow provided in the embodiments of this application. Detailed Implementation

[0023] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0024] This application provides a method, apparatus, device, and medium for preventing frame loss under high load rates in CAN gateways, which can solve the problems of frame loss and high CPU resource consumption in existing CAN message transmission methods under high load rates.

[0025] See Figure 1 As shown, in a first aspect, embodiments of this application provide a method for preventing frame loss under high load conditions in a CAN gateway, comprising: S1. If the target hardware mailbox needs to send message data and the target hardware mailbox is not idle, write the message data to be sent into the circular FIFO queue for buffering; the circular FIFO queue is an independent queue set up for each CAN controller channel, used to buffer the message data to be sent when the target hardware mailbox is not idle; S2. After the message data stored in the target hardware mailbox is sent, a transmission completion interrupt signal is triggered and transmitted, and the message data to be sent that is buffered in the circular FIFO queue is written into the target hardware mailbox for transmission.

[0026] The method of this application introduces an independent circular FIFO queue mechanism for each CAN controller channel. When the upper layer application software needs to send message data through the target hardware mailbox, if it detects that the mailbox is not idle (i.e., it is full), the system no longer adopts the strategy of directly discarding or polling and retrying. Instead, it caches the message data to be sent in real time into the circular FIFO queue. The circular FIFO queue is an independent queue set up for each CAN controller channel.

[0027] This design avoids the problem of critical messages being momentarily dropped due to a full hardware mailbox, ensuring that critical messages are completely preserved and transmitted in an orderly manner under harsh operating conditions with consistently high bus load rates. This achieves zero-frame-loss guarantee in communication reliability, meeting the stringent functional safety requirements of automotive electronic systems. Simultaneously, by pushing the message transmission control logic down to a hardware interrupt triggering mechanism, once the target hardware mailbox completes the transmission of the current message and automatically triggers a transmission completion interrupt signal, the system only needs to write the message data buffered in the circular FIFO queue into the mailbox to continue transmission, without requiring any periodic polling or timeout retries from the upper-layer application software. This significantly reduces the CPU's interrupt handling load and computational overhead, avoids CPU utilization peaks caused by frequent retries, ensures stable and efficient system resource consumption, and does not interfere with the execution of real-time tasks such as power control and safety algorithms.

[0028] In summary, this solution overcomes the problems of frame loss and high CPU usage in high-load scenarios through a collaborative mechanism of cyclic FIFO queue buffering and interrupt-triggered transmission, providing the vehicle ECU with communication assurance that combines functional safety and system stability.

[0029] To address frame loss, the solution configures an independent circular FIFO queue for each CAN controller channel. This avoids the risk of message loss due to direct discarding or polling retries when the hardware mailbox is full. Specifically, when the upper-layer application software needs to send a message and the target hardware mailbox is not idle, the system writes the message data to be sent into a dedicated circular FIFO queue in real time for buffering, instead of abandoning the transmission. Subsequently, when the target hardware mailbox completes the transmission of the current message and triggers a transmission completion interrupt signal, the system automatically writes the buffered message data into the mailbox and continues transmission. This mechanism ensures that all critical messages (such as chassis control and powertrain commands) are fully preserved and transmitted in an orderly manner even under harsh environments with bus load rates exceeding 80% or even approaching 100%, eliminating the problem of instantaneous frame loss.

[0030] To address the issue of high CPU resource consumption, this solution eliminates the redundant operation of periodically checking the mailbox status by upper-layer application software in existing polling and retry mechanisms, fundamentally reducing CPU interrupt load and processing overhead. The solution relies solely on a hardware interrupt triggering mechanism: when the hardware mailbox completes transmission, the system automatically responds to the interrupt and processes the buffered packets in the circular FIFO queue, without requiring any polling or timeout retry logic from the application layer. This avoids CPU interrupt spikes and computational resource consumption caused by frequent retries under high load, keeping CPU utilization at a stable level. This ensures that real-time tasks (such as power control and safety algorithms) are not disturbed, while also achieving efficient utilization of system resources, thus resolving the problem of high CPU resource consumption.

[0031] In the hardware design of CAN bus communication, the "transmission completion interrupt" is a standard function of the hardware peripheral. When the CAN hardware completes the transmission of a message frame, it automatically triggers an interrupt signal to notify the CPU to perform subsequent processing. "Interrupt triggering" is a general term in embedded systems, referring to a hardware event (such as transmission completion) activating the interrupt service routine without the CPU actively polling.

[0032] In some alternative embodiments, if the target hardware mailbox needs to send message data and the target hardware mailbox is in an idle state, the message data is directly written to the target hardware mailbox for sending.

[0033] When the target hardware mailbox is idle, the system directly writes the message data to be sent into the target hardware mailbox for transmission, instead of entering the circular FIFO queue buffering process.

[0034] In some optional embodiments, after the message data stored in the target hardware mailbox has been sent, a transmission completion interrupt signal is triggered and transmitted, and the message data to be sent buffered in the circular FIFO queue is written into the target hardware mailbox for transmission; specifically including: Once all message data stored in the target hardware mailbox has been sent, a transmission completion interrupt signal is triggered and transmitted. Then, the message data to be sent, which is buffered in the circular FIFO queue, is written into the target hardware mailbox for transmission.

[0035] In this embodiment, because the system processes the queue only after the mailbox has completed sending all current messages (rather than sending only some), it ensures that the mailbox state is completely released, avoiding message overwriting or loss due to incomplete mailbox clearing. All cached messages in the circular FIFO queue (including critical chassis control, powertrain instructions, etc.) are strictly written into the mailbox and transmitted in order, achieving zero frame loss guarantee under high load (such as bus load reaching 95%), meeting the stringent requirements of automotive functional safety for the reliability of critical messages. Secondly, it reduces CPU resource consumption. This mechanism only relies on hardware to complete interrupt-triggered queue processing, without requiring any polling, status checks, or timeout retry operations from upper-layer application software, avoiding CPU interrupt peaks and computational overhead caused by frequent polling under high load.

[0036] In some optional embodiments, after the message data stored in the target hardware mailbox has been sent, a transmission completion interrupt signal is triggered and transmitted, and the message data to be sent buffered in the circular FIFO queue is written into the target hardware mailbox for transmission; specifically including: When a message data stored in the target hardware mailbox is sent, a transmission completion interrupt signal is triggered and transmitted, and the header message data buffered in the circular FIFO queue is written into the target hardware mailbox for transmission; the header message data is the message data to be sent that was first written into the circular FIFO queue.

[0037] In this embodiment, once the target hardware mailbox finishes sending a single message (rather than waiting for all messages to be sent), the system immediately triggers an interrupt and writes the earliest cached message (i.e., the header message) into the mailbox to continue sending. This mechanism shortens the waiting time of messages in the queue and avoids transmission delays caused by the mailbox being idle. Under extreme conditions with a bus load rate as high as, for example, 95%, critical messages (such as chassis control commands) can be continuously transmitted at the millisecond level, ensuring real-time response of vehicle dynamic control and eliminating the risk of instantaneous frame loss due to transmission interruptions under high load.

[0038] By adhering to the first-in, first-out (FIFO) principle of the FIFO queue, messages buffered in the circular FIFO queue (including key frames such as chassis control and powertrain commands) are always transmitted sequentially in the order they were sent, eliminating the risk of control command failure due to out-of-order transmission (for example, a misalignment of braking and steering commands could lead to vehicle loss of control). This mechanism ensures the precise timing of vehicle electronic system commands under high-load scenarios, providing a solid guarantee for functional safety. Simultaneously, it seamlessly integrates with the core solution, enabling the system to directly send messages under low load and efficiently schedule messages through queues under high load, achieving dual optimization of communication reliability and resource efficiency across the entire load range.

[0039] In some optional embodiments, when the message data stored in the target hardware mailbox is sent and a sending completion interrupt signal is triggered and transmitted, it is detected whether the circular FIFO queue is not empty; If not empty, the header data of the circular FIFO queue to be sent is written to the target hardware mailbox and sent. After successful sending, the header data of the circular FIFO queue is deleted. Trigger a send completion interrupt within the target hardware mailbox, and repeat the above process until the circular FIFO queue is empty; the header message data is the message data that was first written into the circular FIFO queue.

[0040] This optional embodiment achieves precise control and efficient resource utilization of message transmission under high load scenarios by dynamically detecting the status of the circular FIFO queue and processing header messages sequentially after a transmission completion interrupt is triggered. Specifically, when the target hardware mailbox completes the transmission of a single message and triggers an interrupt, the system immediately checks whether the circular FIFO queue is empty. If the queue is not empty, the earliest cached header message (i.e., the message written to the queue first) is written to the target hardware mailbox for transmission. After successful transmission, the header data in the queue is automatically deleted, and the system continues to respond to subsequent transmission completion interrupts to repeat the process until the queue is completely cleared. This design solves the frame loss problem under high load: all cached messages (including key frames such as chassis control and powertrain commands) are processed strictly in order, avoiding the risk of instantaneous frame loss or timeout due to a full mailbox, ensuring zero frame loss transmission under extreme conditions with a bus load rate of over 95%, and meeting the mandatory requirements of automotive functional safety for the reliability of key messages.

[0041] Meanwhile, this mechanism optimizes CPU resource usage by performing single-message processing only when a hardware interrupt is triggered (instead of polling or batch operations), avoiding periodic checks and timeout retry logic of upper-layer application software, keeping the CPU interrupt frequency at a reasonable level (processing only one message per interrupt), eliminating the problem of peak CPU utilization under high load, and ensuring that the execution of real-time tasks such as power control and safety monitoring is not interfered with.

[0042] In some optional embodiments, when writing the message data to be sent into the circular FIFO queue for buffering, if the circular FIFO queue is full, the header message data of the circular FIFO queue is popped out, and the new message data to be sent is written to the tail of the circular FIFO queue; the header message data is the message data to be sent that was first written into the circular FIFO queue.

[0043] In this optional embodiment, when writing the message data to be sent into a circular FIFO queue for buffering, if the queue is full, the header message (i.e. the message written into the queue first) is automatically popped out, and the new message is written to the tail of the queue.

[0044] This mechanism, through a first-in, first-out (FIFO) queuing system combined with an automatic expired message discard mechanism, ensures the priority transmission of the latest control commands (such as braking or steering commands), eliminating the risk of vehicle loss of control due to command timing discrepancies (for example, a conflict between an old braking command and a new command could lead to brake failure). Under high-load conditions, this strategy dynamically optimizes message scheduling: time-sensitive critical messages are always retained, while expired messages are promptly cleared, ensuring both the accuracy of vehicle dynamic control and avoiding communication congestion caused by queue accumulation. While maintaining the advantage of zero frame loss, this mechanism further enhances the system's support for functional safety, providing more reliable and efficient communication guarantees for critical ECUs such as vehicle gateways and domain controllers.

[0045] In practice, in most scenarios where FIFO is used (such as vehicle gateways, industrial sensors, and network communications), the timeliness of data is the core requirement. New data reflects the latest status, while old data reflects the past expired status. The practical value of expired data will be greatly reduced, and it may even mislead subsequent processing.

[0046] For example, the vehicle gateway forwards the "brake pedal signal"—the FIFO already contains three old signals (brake depth from 100ms ago, 80ms ago, and 50ms ago). At this point, a new "current braking signal" needs to be written, but the buffer is full. If the new data is lost, the subsequent ECU can only use the old signal from 100ms ago to determine the braking status, which may delay the braking response; if the earliest "old signal from 100ms ago" is lost and the newer signal is retained, the ECU can more accurately reflect the current vehicle condition.

[0047] In some optional embodiments, when the target hardware mailbox needs to send message data, if the status register of the target hardware mailbox is detected to be in an idle state, it is determined that the target hardware mailbox is in an idle state; otherwise, it is determined that the target hardware mailbox is in a non-idle state.

[0048] This embodiment determines the mailbox's idle status by directly reading the status register indication of the target hardware mailbox (if the status register indicates idle, it is considered idle; otherwise, it is considered non-idle). This achieves accurate detection of the mailbox status, eliminates the risk of frame loss due to misjudgment of status, and ensures zero loss of critical messages. The status register indication is strictly synchronized with the actual mailbox status, avoiding message delays or drops caused by software polling logic errors or timing deviations (such as the mailbox being actually idle but misjudged as non-idle).

[0049] Secondly, embodiments of this application provide a high-load-rate anti-frame-loss device for a CAN gateway, comprising: Create a module to set up an independent circular FIFO queue for the target hardware mailbox; The judgment module is used to determine the status of the target hardware mailbox and control the writing of message data; The processing module is used to trigger a send completion interrupt and process the message data in the circular FIFO queue.

[0050] The CAN gateway high-load-rate anti-frame-loss device provided in this application achieves breakthroughs in communication reliability and system resource efficiency under high-load scenarios through the collaborative work of the creation module, judgment module, and processing module. Specifically, the creation module independently configures a circular FIFO queue for each CAN controller channel, i.e., sets up a dedicated buffer space, avoiding message conflicts and resource contention caused by shared queues. This design ensures that all messages to be sent (including key frames such as chassis control and powertrain commands) can be completely buffered when the bus load rate is high, eliminating the risk of instantaneous frame loss caused by a full hardware mailbox.

[0051] The processing module, based on a hardware-triggered interrupt mechanism, automatically writes the header message buffered in the circular FIFO queue to the target hardware mailbox for transmission, and deletes the queue header data after successful transmission, forming a closed-loop processing flow. This module abandons the polling and retry logic of the upper-layer application software, performing single-message processing only when an interrupt is triggered, compressing the CPU interrupt handling overhead to an extremely low level, completely eliminating the problem of peak CPU utilization under high load, and ensuring that real-time task execution is not interfered with.

[0052] Thirdly, embodiments of this application provide a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of any of the above methods.

[0053] Fourthly, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the above methods.

[0054] In the description of this application, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Unless otherwise expressly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two elements. For those skilled in the art, the specific meaning of the above terms in this application can be understood according to the specific circumstances.

[0055] It should be noted that in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0056] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for preventing frame loss under high load conditions in a CAN gateway, characterized in that, include: If the target hardware mailbox needs to send message data and the target hardware mailbox is not idle, the message data to be sent is written into a circular FIFO queue for buffering; the circular FIFO queue is an independent queue set up for each CAN controller channel, used to buffer the message data to be sent when the target hardware mailbox is not idle; Once the message data stored in the target hardware mailbox has been sent, a transmission completion interrupt signal is triggered and transmitted, and the message data to be sent that is cached in the circular FIFO queue is written into the target hardware mailbox for transmission.

2. The CAN gateway high load rate frame loss prevention method as described in claim 1, characterized in that: If the target hardware mailbox needs to send message data, and the target hardware mailbox is in an idle state, the message data is directly written into the target hardware mailbox and sent.

3. The CAN gateway high-load-rate frame loss prevention method as described in claim 1, characterized in that, After the message data stored in the target hardware mailbox is sent, a transmission completion interrupt signal is triggered and transmitted, and the message data to be sent buffered in the circular FIFO queue is written into the target hardware mailbox for transmission; specifically including: Once all message data stored in the target hardware mailbox has been sent, a transmission completion interrupt signal is triggered and transmitted, and the message data to be sent that is cached in the circular FIFO queue is sequentially written into the target hardware mailbox for transmission.

4. The CAN gateway high-load-rate frame loss prevention method as described in claim 1, characterized in that, After the message data stored in the target hardware mailbox is sent, a transmission completion interrupt signal is triggered and transmitted, and the message data to be sent buffered in the circular FIFO queue is written into the target hardware mailbox for transmission; specifically including: When a message data stored in the target hardware mailbox is sent, a sending completion interrupt signal is triggered and transmitted, and the header message data cached in the circular FIFO queue is written into the target hardware mailbox for transmission. The header message data is the message data to be sent that is first written into the circular FIFO queue.

5. The CAN gateway high load rate anti-frame loss method as described in claim 1, characterized in that: When the message data stored in the target hardware mailbox is sent, and a sending completion interrupt signal is triggered and transmitted, it is checked whether the circular FIFO queue is not empty. If not empty, the header data to be sent in the circular FIFO queue is written into the target hardware mailbox and sent. After successful sending, the header data in the circular FIFO queue is deleted. Trigger a transmission completion interrupt within the target hardware mailbox, and repeat the above process until the circular FIFO queue is empty; the header message data is the message data that was first written into the circular FIFO queue.

6. The CAN gateway high load rate anti-frame loss method as described in claim 2, characterized in that: When writing the message data to be sent into the circular FIFO queue for buffering, if the circular FIFO queue is full, the header message data of the circular FIFO queue is popped out, and the new message data to be sent is written to the tail of the circular FIFO queue; the header message data is the message data to be sent that was first written into the circular FIFO queue.

7. The CAN gateway high load rate anti-frame loss method as described in claim 1, characterized in that: When a target hardware mailbox needs to send message data, if the status register of the target hardware mailbox indicates that it is in an idle state, then the target hardware mailbox is determined to be in an idle state; otherwise, the target hardware mailbox is determined to be in a non-idle state.

8. A high-load-rate anti-frame-loss device for a CAN gateway, characterized in that, include: Create a module to set up an independent circular FIFO queue for the target hardware mailbox; The judgment module is used to determine the status of the target hardware mailbox and control the writing of message data; The processing module is used to trigger a send completion interrupt and process the message data in the circular FIFO queue.

9. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method according to any one of claims 1-7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the program implements the steps of the method according to any one of claims 1-7.

Images