Real-time wavenumber space resampling method and system for ss-oct

Abstract

This invention discloses a real-time wavenumber spatial resampling method and system for SS-OCT, relating to the field of signal processing technology. The method involves simultaneously acquiring a K-clock signal and an OCT interferometer signal, and performing filtering preprocessing on each. The preprocessed K-clock signal is then subjected to a Hilbert transform to construct an analytical signal and extract the instantaneous phase, forming an instantaneous phase sequence. A preset ideal equal-wavenumber interval phase sequence is used as the target phase sequence. The target phase sequence is matched with the instantaneous phase sequence, and the position index of each target phase in the instantaneous phase sequence is calculated to obtain the remapped sampling point index. Based on the remapped sampling point index, the preprocessed OCT interferometer signal is processed using the SINC interpolation method to obtain a resampled, equal-wavenumber interval OCT signal. This application utilizes the SINC interpolation algorithm to perform real-time, high-precision resampling during the data acquisition stage, meeting the requirements of high-speed real-time imaging.

Description

Technical Field

[0001] This invention relates to the field of signal processing technology, and more specifically to a real-time wavenumber spatial resampling method and system for SS-OCT. Background Technology

[0002] Optical Coherence Tomography (OCT) is an imaging method based on low-coherence interferometry. An interferometer splits the light from a broadband light source into a reference arm and a sample arm. The light from the sample arm is reflected and scattered within the sample, and then re-interferes with the light from the reference arm within the interferometer. The frequency intensity and phase information of the interference signal directly reflect the microstructure of the sample. To extract depth information from the interference signal, a Fast Fourier Transform (FFT) is used to transform the wavenumber domain (k) data to the spatial domain (z). FFT requires that the sampling points in the wavenumber space be equally spaced; therefore, the linearity of the interference spectrum in the wavenumber space—wavenumber linearity—has a crucial impact on the imaging quality of OCT. Wavenumber space resampling, also known as wavenumber space linearization, requires that the phase of the detected signal in the spectral interferogram be linear in wavenumber, and the wavenumber corresponding to each pixel must also be linearly distributed. However, after the interference signal is split by the spectrometer, light of different wavelengths is separated in space. Light of different wavelengths enters different pixels. That is, the interference signal is approximately linearly distributed in wavelength space, which corresponds to a non-uniform distribution in wavenumber space. The non-uniformity of phase change causes the interference signal to chirp after Fourier transform, which reduces the axial resolution of the system.

[0003] In current laser scanning OCT (SS-OCT) systems, OCT utilizes a variable-wavelength laser source to emit light waves of different wavelengths; wavenumber resampling is primarily implemented in the backend computer using software algorithms. Common algorithms fall into two categories: one is the computationally simple but less accurate linear interpolation method, which produces significant errors at large imaging depths; the other is the more accurate zero-padding FFT interpolation method, but it requires a series of operations such as Fast Fourier Transform (FFT), zero-padding, and Inverse Fast Fourier Transform (IFFT), resulting in a massive computational burden. Both of these software implementation methods heavily rely on the computing power of the computer's CPU / GPU, leading to technical bottlenecks such as high system cost, large data processing latency, and difficulty in achieving high-speed real-time imaging. Summary of the Invention

[0004] The purpose of this invention is to provide a real-time wavenumber spatial resampling method and system for SS-OCT. Without relying on the computing power of the back-end computer, the SINC interpolation algorithm is used to complete resampling in real time and with high precision during the data acquisition stage, which effectively reduces system cost, reduces latency, and meets the needs of high-speed real-time imaging.

[0005] To achieve the above objectives, the following plan is adopted:

[0006] On the one hand, the present invention provides a real-time wavenumber spatial resampling method for SS-OCT, specifically including the following steps:

[0007] S1. Synchronously acquire the K clock signal and the OCT interference signal, and perform filtering and preprocessing on the K clock signal and the OCT interference signal respectively;

[0008] S2. Perform Hilbert transform on the preprocessed K clock signal to construct an analytic signal and extract the instantaneous phase from the analytic signal to form an instantaneous phase sequence;

[0009] S3. Using a preset ideal isowavenumber interval phase sequence as the target phase sequence, match the target phase sequence with the instantaneous phase sequence, calculate the position index of each target phase in the instantaneous phase sequence, and obtain the remapping sampling point index.

[0010] S4. Based on the remapped sampling point index, the preprocessed OCT interference signal is processed using the SINC interpolation method to obtain a resampled OCT signal with equal wavenumber intervals.

[0011] In some specific implementation schemes, the specific process of step S2 is as follows:

[0012] S21. Use a 128th-order FIR filter to perform Hilbert transform on the K clock signal, obtain its quadrature components, and get the Hilbert transform result.

[0013] S22. Using the K clock signal as the real part and the Hilbert transform result as the imaginary part, construct an analytic signal;

[0014] S23. Use the CORDIC algorithm to extract the instantaneous phase value of each sampling point from the analytical signal.

[0015] In some specific implementations, step S23, in the process of extracting the instantaneous phase value from the analytic signal, also requires phase expansion to eliminate ±π discontinuities caused by the arctangent function. The specific method is as follows:

[0016] The instantaneous phase sequence is traversed chronologically, and the difference between the phase value of the current sampling point and the phase value of the previous sampling point is calculated. If the difference is greater than +π, then the phase value of all subsequent sampling points starting from the current point is reduced by 2π; if the difference is less than -π, then the phase value of all subsequent sampling points starting from the current point is increased by 2π. Through this iterative process, a smooth, continuous instantaneous phase sequence without jumps is finally obtained.

[0017] In some specific implementations, the specific process of calculating the remapping sampling point index in step S3 is as follows:

[0018] S31. Based on the preset number of sampling points and the total phase change range, generate equally spaced target phases to form a target phase sequence;

[0019] S32. For each target phase, traverse the instantaneous phase sequence to find the condition that satisfies: φ(t i )≤φ target [m]<φ(t i+1 Two adjacent instantaneous phases of ), where φ(t) i ) represents the t-th i An instantaneous phase, φ(t) i+1 ) represents the t-th i+1 Each instantaneous phase, φ target [m] represents the phase of the m-th target;

[0020] S33. Based on the two instantaneous phases that are satisfied, calculate the remapping sampling point index p for each sampling point using linear interpolation. m =i+ .

[0021] In some specific implementations, boundary handling is also required for the remapped sampling point index: when the calculated remapped sampling point index exceeds the index range of the instantaneous phase sequence, an overflow flag is set for the remapped sampling point index.

[0022] In some specific implementation schemes, the process of using SINC interpolation in step S4 is as follows:

[0023] S41. The windowed SINC function is used as the interpolation kernel. The SINC interpolation kernel coefficients corresponding to all possible decimal offsets are pre-calculated and stored in the ROM lookup table of the FPGA.

[0024] S42. Obtain the integer index value of the integer part and the fractional index value of the fractional part of the remapped sampling point index value;

[0025] S43. Obtain N sampling points around the sampling point corresponding to the integer index value, where N is the interpolation kernel length. Calculate the corresponding ROM address range based on the decimal index value, and read N interpolation kernel coefficients from the ROM address range.

[0026] S44. Perform parallel multiplication calculations on N sampling points and N interpolation kernel coefficients, and accumulate all products using a parallel addition tree to obtain the interpolation result.

[0027] In some specific implementations, the method for obtaining the N sampling points surrounding the sampling point corresponding to the integer index value is as follows:

[0028] After sampling the preprocessed OCT interference signal at equal intervals, the sampled points are grouped and stored according to the interpolation kernel length to obtain several sampled point data groups;

[0029] The data sets of two adjacent sampling points are concatenated and stored in a memory of length 2N within the same clock cycle;

[0030] The clock cycle is located based on the integer index value, and N sampling points around the sampling point corresponding to the integer index value are read from the memory of the clock cycle.

[0031] In some specific implementations, the parallel addition tree adopts a balanced structure, with the number of adders at each stage decreasing exponentially by 2.

[0032] In some specific implementations, when an overflow flag is detected in the current remapped sampling point index value, the data path corresponding to the current remapped sampling point index value is set to zero.

[0033] Secondly, this application provides a real-time wavenumber spatial resampling system for SS-OCT, comprising:

[0034] SS-OCT signal source, used to generate K-clock signal and OCT interference signal;

[0035] The acquisition module is used to synchronously acquire the K clock signal and the OCT interference signal, and to perform filtering and preprocessing on the K clock signal and the OCT interference signal respectively;

[0036] The phase extraction module is used to perform Hilbert transform on the preprocessed K clock signal, construct an analytical signal, and extract the instantaneous phase from the analytical signal to form an instantaneous phase sequence.

[0037] The remapping module is used to match the target phase sequence with the instantaneous phase sequence using a preset ideal isowavenumber interval phase sequence as the target phase sequence, calculate the position index of each target phase in the instantaneous phase sequence, and obtain the remapping sampling point index.

[0038] The interpolation module is used to process the preprocessed OCT interference signal using the SINC interpolation method based on the remapped sampling point index, so as to obtain a resampled OCT signal with equal wavenumber intervals.

[0039] The beneficial effects of this invention are as follows:

[0040] This invention utilizes both the K-clock signal and the OCT signal simultaneously, with the K-Clock signal acting as a "ruler" for resampling. A Hilbert transform is performed on the K-clock signal to extract its instantaneous phase, rather than directly using its amplitude. The K-clock phase is then used to precisely locate the resampling point. The extracted instantaneous phase is compared with an ideal, equally spaced phase sequence to accurately pinpoint the non-integer index position of each target sampling point in the original OCT signal.

[0041] For OCT signals, a parallelized SINC interpolator is used at the calculated non-integer index position to obtain the amplitude with high precision, thereby achieving the technical effects of ultra-high speed, ultra-high precision and low system cost at the hardware level. Attached Figure Description

[0042] Figure 1 This is a flowchart of a real-time wavenumber spatial resampling method for SS-OCT provided in an embodiment of the present invention;

[0043] Figure 2 This is a block diagram of a real-time wavenumber spatial resampling system for SS-OCT provided in an embodiment of the present invention. Detailed Implementation

[0044] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the present invention or its application or use. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0045] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps described in these embodiments do not limit the scope of the invention.

[0046] Furthermore, for clarity and brevity, descriptions of well-known functions and methods may have been omitted. Those skilled in the art will recognize that various changes and modifications can be made to the examples described herein without departing from the spirit and scope of this disclosure.

[0047] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0048] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0049] Example 1

[0050] like Figure 1 As shown, this embodiment provides a real-time wavenumber spatial resampling method for SS-OCT, specifically including the following steps:

[0051] S1. Synchronously acquire the K clock signal and the OCT interference signal, and perform filtering and preprocessing on the K clock signal and the OCT interference signal respectively;

[0052] S2. Perform Hilbert transform on the preprocessed K clock signal to construct an analytic signal and extract the instantaneous phase from the analytic signal to form an instantaneous phase sequence;

[0053] The core of resampling position calculation is to extract the precise phase information of the KCLOCK signal through Hilbert transform. The specific process of step S2 is as follows:

[0054] S21. Use a 128th-order FIR filter to perform Hilbert transform on the K clock signal, obtain its quadrature components, and get the Hilbert transform result.

[0055] S22. Using the K clock signal as the real part and the Hilbert transform result as the imaginary part, construct an analytic signal;

[0056] S23. Use the CORDIC algorithm to extract the instantaneous phase value of each sampling point from the analytical signal.

[0057] Since the range of the inverse tangent function when using the CORDIC algorithm is [-π, π], phase expansion is required to obtain continuous phase information. Therefore, in step S23, during the extraction of the instantaneous phase value from the analytic signal, phase expansion is also required to eliminate the ±π discontinuities caused by the inverse tangent function. The specific method is as follows:

[0058] The instantaneous phase sequence is traversed chronologically, and the difference between the phase value of the current sampling point and the phase value of the previous sampling point is calculated. If the difference is greater than +π, then the phase values ​​of all subsequent sampling points starting from the current point are reduced by 2π; if the difference is less than -π, then the phase values ​​of all subsequent sampling points starting from the current point are increased by 2π. Through this iterative process, a smooth, continuous instantaneous phase sequence without jumps is finally obtained.

[0059] S3. Using the preset ideal wavenumber interval phase sequence as the target phase sequence, match the target phase sequence with the instantaneous phase sequence extracted from the KCLOCK signal, calculate the position index (which may be a non-integer) of each target phase in the instantaneous phase sequence, and thus obtain the remapping sampling point index.

[0060] Converting the extracted instantaneous phase information into specific resampling location indices is key to achieving wavenumber space linearization. The specific process for calculating the remapped sampling point index is as follows:

[0061] S31. Based on the system's preset number of sampling points and the total phase change range, generate equally spaced target phases to form a target phase sequence;

[0062] S32. For each target phase, traverse the instantaneous phase sequence to find the condition that satisfies: φ(t i )≤φ target [m]<φ(t i+1 Two adjacent instantaneous phases of ), where φ(t) i ) represents the t-th i An instantaneous phase, φ(t) i+1 ) represents the t-th i+1 Each instantaneous phase, φ target [m] represents the phase of the m-th target;

[0063] S33. Based on the two instantaneous phases that are satisfied, calculate the remapping sampling point index p for each sampling point using linear interpolation. m =i+ .

[0064] To ensure that a remapping index can be calculated for each clock cycle, providing continuous position information for subsequent SINC interpolation, boundary handling is also required for the remapping sample point index: when the calculated remapping sample point index exceeds the index range of the instantaneous phase sequence, an overflow flag is set for the remapping sample point index.

[0065] S4. Based on the remapped sampling point index, the preprocessed OCT interference signal is processed using the SINC interpolation method to obtain a resampled OCT signal with equal wavenumber intervals.

[0066] To achieve high-precision signal reconstruction using high-order SINC interpolation, the specific process of processing using the SINC interpolation method is as follows:

[0067] S41. A windowed SINC function is used as the interpolation kernel. The SINC interpolation kernel coefficients corresponding to all possible decimal offsets are pre-calculated and stored in the FPGA's ROM lookup table;

[0068] S42. Obtain the integer index value of the integer part and the fractional index value of the fractional part of the remapped sampling point index value;

[0069] S43. Obtain N sampling points around the sampling point corresponding to the integer index value within the same clock cycle, where N is the interpolation kernel length. Calculate the corresponding ROM address range based on the fractional index value, and read N interpolation kernel coefficients from the ROM address range.

[0070] To ensure that N points around any position can be read within one clock cycle under any circumstances, the method for obtaining N sampling points around the sampling point corresponding to the integer index value is as follows:

[0071] After sampling the preprocessed OCT interferometric signal, the sampled points are grouped and stored according to the interpolation kernel length N to obtain several sampled point data groups;

[0072] The data sets of two adjacent sampling points are concatenated and stored in a memory of length 2N within the same clock cycle;

[0073] The clock cycle is located based on the integer index value, and N sampling points around the sampling point corresponding to the integer index value are read from the memory of the clock cycle.

[0074] S44. Perform parallel multiplication calculations on N sampling points and N interpolation kernel coefficients, and accumulate all products using a parallel addition tree to obtain the interpolation result.

[0075] To ensure the shortest critical path, the parallel adder tree adopts a balanced structure, with the number of adders at each level decreasing exponentially by 2.

[0076] To ensure the continuity of the output, when an overflow flag is detected in the current remapped sampling point index value, the data path corresponding to the current remapped sampling point index value is set to zero.

[0077] Specifically, in some specific implementation scenarios, the above method can be implemented on the FPGA of the data acquisition card, and the implementation principle of each step is as follows:

[0078] 1. Simultaneously acquire two input signals from the SS-OCT interferometer system.

[0079] This is the data input stage of the entire resampling process, requiring the simultaneous acquisition of two key signals from the SS-OCT interferometer system. The first signal is the K-clock signal (KCLOCK), generated by the interferometer within the SS-OCT system. Its frequency varies linearly with the scanning wavelength of the light source, being uniform in the optical frequency domain but non-uniform in the time domain. The K-clock signal is essentially a chirped signal, with its instantaneous frequency proportional to the instantaneous wavenumber of the light source. The second signal is the OCT interference signal, the original interference signal formed by the interference of the light signals returning from the sample arm and the reference arm, containing information about the sample's depth structure.

[0080] In terms of hardware implementation, the two signals are synchronously sampled via a high-speed ADC, with the sampling rate typically set to 100MSPS to 1GSPS, depending on the system's bandwidth requirements. To ensure strict synchronization between the two signals, a synchronization buffer mechanism is designed within the FPGA, employing a dual-port RAM for real-time data caching and alignment to ensure precise time alignment between the K clock signal and the OCT signal. Synchronization accuracy must be controlled within one sampling clock cycle, which is crucial for subsequent phase extraction and resampling accuracy.

[0081] 2. Perform filtering preprocessing on the K clock signal and the OCT interference signal respectively.

[0082] Filtering preprocessing is a crucial step in ensuring signal quality, directly impacting the accuracy of subsequent phase extraction and interpolation calculations. For K-clock signals, the main objective is to remove high-frequency noise and DC bias while preserving the signal's phase information. Filtering the K-clock signal effectively removes dispersion caused by interference signals in the KCLOCK. This embodiment supports three configurable filtering modes.

[0083] (1) Low-pass filtering: mainly used to eliminate high-frequency noise. A 128th-order FIR filter is used, and the cutoff frequency is set to 1.2 times the maximum frequency of the KCLOCK signal. For example, for a KCLOCK signal with a maximum frequency of 80MHz, the cutoff frequency is set to 96MHz. The filter coefficients adopt a Kaiser window design (β=8.6) to ensure that the passband ripple is less than 0.01dB and the stopband attenuation is greater than 80dB.

[0084] (2) High-pass filter: mainly used to eliminate DC components and low-frequency drift. A 128th-order FIR filter is used with a cutoff frequency of 100Hz, which can effectively remove baseline drift caused by light source intensity fluctuations and temperature drift.

[0085] (3) Bandpass filtering: It combines the characteristics of low-pass and high-pass filtering, and the passband range is dynamically adjusted according to the spectral characteristics of the actual KCLOCK signal. For example, for a KCLOCK signal with a center frequency of 100MHz and a bandwidth of 40MHz, the passband is set to 80-120MHz.

[0086] For OCT interferometric signals, the filtering focus is on removing high-frequency noise and 50 / 60Hz power frequency interference. A multi-stage filtering architecture is adopted: the first stage is an analog anti-aliasing filter, and the second stage is a 128th-order digital FIR bandpass filter, with the passband range consistent with the effective spectrum range of the OCT signal. All filters are implemented in the FPGA using distributed algorithms, and real-time performance is ensured through parallel processing.

[0087] This embodiment provides multiple configurable filtering modes, offering greater flexibility and adaptability in filtering preprocessing. Filtering parameters can be adjusted in real time via the FPGA's configuration registers, allowing the system to select the optimal filtering mode based on signal quality. Existing technologies typically use fixed filtering parameters and lack this adaptability.

[0088] 3. Perform Hilbert transform on the preprocessed K clock signal to construct an analytic signal and calculate the instantaneous phase.

[0089] The core of resampling position calculation is to extract the precise phase information of the KCLOCK signal through Hilbert transform. The specific implementation process is as follows:

[0090] (1) Hilbert Transform: Implemented using a 128th-order FIR filter, with filter coefficients optimized based on the Parks-McClellan algorithm to ensure an accurate 90-degree phase shift within the passband (normalized passband 0.95). In the FPGA, the Hilbert transformer is implemented using a multiphase structure, and parallel processing ensures that a set of parallel sampling points can be processed per clock cycle.

[0091] (2) Construction of analytic signal: Using the original K clock signal S(t) as the real part and the Hilbert transform result as the imaginary part, construct the analytic signal Sa(t):

[0092] Sa(t) = S(t) + j·Η{S(t)}

[0093] Where H represents the Hilbert transform operator.

[0094] (3) Instantaneous phase calculation: Efficiently calculate phase values ​​in FPGA using the CORDIC algorithm:

[0095]

[0096] The CORDIC algorithm is implemented using a 24-stage pipeline, outputting one phase value per clock cycle, achieving a calculation accuracy of 10⁻⁶. -5 radian.

[0097] (4) Phase Unfolding: Since the range of the arctan function is [-π, π], phase unfolding is required to obtain continuous phase information. This system adopts an improved real-time phase unfolding algorithm, which ensures phase continuity by detecting phase jumps (exceeding π) between adjacent sampling points and accumulating integer multiples of 2π.

[0098] This embodiment employs a 24-stage CORDIC pipeline, achieving a phase calculation accuracy of 10⁻⁶. -5 Compared to using lookup tables or simplified algorithms, the phase accuracy is higher in radians. Through a fully pipelined design, an expanded phase value is output every clock cycle, resulting in better real-time performance. For FPGA architectures, by configuring parameters, the CORDIC algorithm's iteration count and accuracy are optimized, balancing resource overhead and precision, minimizing resource consumption while maintaining accuracy.

[0099] 4. Calculate the remapping sampling point index based on the preset target wavenumber interval phase sequence.

[0100] Converting the extracted instantaneous phase information into specific resampling position indices is key to achieving wavenumber space linearization. The specific process is as follows:

[0101] (1) Target phase sequence generation: Generate equally spaced target phase sequences according to system requirements. For an axial scan (A-Scan) with 1024 depth data points, the target phase sequence is as follows:

[0102] φ target [m]=m·△φ,m=0,1,2,...,1023

[0103] Where, △φ=φ total / 1023, φ total This represents the total range of phase changes.

[0104] (2) Remapping Index Calculation: Match the target phase sequence with the actual instantaneous phase sequence, and calculate the original signal position index corresponding to each target phase. The specific algorithm is as follows:

[0105] For each target phase value φ target [m], find the condition φ(t) in the instantaneous phase sequence. i )≤φ target [m]<φ(t i+1 The interval is defined. The accurate remapping index is calculated using linear interpolation:

[0106] p m=i+

[0107] Where, p m It is an index value with decimal places. The integer part represents the position in the original signal, and the decimal part represents the relative position between two sampling points.

[0108] (3) Boundary handling: For indices that exceed the range of the original signal, a special overflow flag is set. When an index value less than 0 or greater than the maximum number of sampling points is detected, the corresponding overflow flag is set and handled specially in subsequent processing.

[0109] High-precision index calculation is implemented in FPGA. Through fixed-point arithmetic and pipelined design, a remapping index can be calculated in each clock cycle, providing continuous position information for subsequent SINC interpolation.

[0110] Understandably, one A-Scan represents a complete depth scan, outputting a depth information curve containing 1024 data points. These 1024 points correspond to 1024 locations in the uniform wavenumber space (k-space). The target phase sequence φtarget is precisely the equally spaced phase sequence generated for these 1024 points, with each target phase point corresponding to a resampled output point. Therefore, for each A-Scan, the system needs to calculate 1024 remapping indices, each index corresponding to a target phase point.

[0111] In the FPGA implementation, resampling is pipelined: only one remapping index is calculated per clock cycle, and an output point is interpolated from the original OCT signal based on this index. Therefore, processing all 1024 points of the A-Scan requires 1024 clock cycles. The remapping index is a non-integer; its integer part is used to locate the sampling point position in the original OCT signal, and its fractional part is used for interpolation calculation.

[0112] 5. Calculate the signal amplitude using the SINC interpolation method on the preprocessed OCT interferometric signal.

[0113] The core computational step in the entire resampling process is to achieve high-precision signal reconstruction using high-order SINC interpolation. The specific process is as follows:

[0114] (1) SINC interpolation kernel design: A 64th-order SINC function is used as the interpolation kernel, and weighted by a Kaiser window (β=2.5) to reduce the Gibbs phenomenon. The SINC function is defined as:

[0115] sinc(x) = sin(πx) / πx

[0116] The cutoff range is [-32, 32], totaling 64 points. The window function's purpose is to suppress side lobes while maintaining the main lobe width, thereby improving interpolation accuracy.

[0117] (2) Coefficient storage and addressing: The windowed SINC interpolation kernel coefficients are pre-calculated and stored in the discrete memory ROM of the FPGA. To improve accuracy, the coefficient quantization bit width is 32-bit fixed-point. The ROM addressing method is specially optimized: the 64 SINC interpolation kernel coefficients are stored in address intervals according to offsets. Each address interval of the ROM stores 64 coefficients at one offset, for a total of 64 ROM address intervals (i.e., the fractional part resolution of the remapped index is 1 / 64).

[0118] (3) Parallel data reading: based on the remapped index p m The integer part of the data is read simultaneously from a register used to store sampled data, containing 64 adjacent sampled points. The register's storage strategy is carefully designed: the 64 points of the current sampled data are concatenated with the 64 points from the previous clock cycle to form a 128-point data set, which is then stored in the register as a sliding data buffer. This ensures that, under any circumstances, 64 points around any given position can be read within a single clock cycle.

[0119] Because the original OCT signal is continuously sampled at a high sampling rate (e.g., 100 MSPS to 1 GSPS), the FPGA cannot store all the sample points at once. Therefore, a small buffer is needed to process the data in real time. Each clock cycle, the register is updated: 64 new points are shifted in, 64 old points are shifted out, maintaining a 128-point window. This supports pipelined processing, processing one index per clock cycle. The 128-point register is a sliding window composed of the 64 new samples from the current clock cycle and the 64 old samples from the previous clock cycle. This design ensures that:

[0120] a. For any p m The integer part of the data can be read at once from a fixed-size register, containing 64 consecutive points without complex memory access.

[0121] b. Avoids boundary problems: when p m When the integer part of the signal is near the beginning or end, insufficient points cannot be read without historical data. By retaining 64 points from the previous clock cycle, it is ensured that even if p... m Even with a small integer part (such as i=1), points from 1 to 64 can still be read (because the register contains points from the previous cycle, covering the indices before i=1).

[0122] (4) Parallel multiply-accumulate calculation:

[0123] A fully parallel architecture is used to perform interpolation calculations, with 64 multipliers working simultaneously. Each multiplier calculates the product of a sample point and the corresponding windowed SINC coefficient. The product results are accumulated through a 6-level (log2(64)=6) addition tree to obtain the final interpolation result.

[0124] The addition tree uses a balanced structure, with the number of adders decreasing at each level (32→16→8→4→2→1) to ensure the shortest critical path.

[0125] (5) Special handling: For boundary and overflow cases, a zeroing strategy is adopted. When an index is detected to be out of the valid range or a boundary condition is detected, the corresponding data path is zeroed to ensure the continuity of the output results.

[0126] To facilitate understanding, the following examples with specific data are provided:

[0127] Assuming the original OCT signal sampling data is x=[0.1,-0.1,1.2,3.4,-5.6,…], the calculated remapping index is p=[1.25,2.45,3.75,…]. The interpolation process for index p=2.45 is as follows:

[0128] Take the 64 points around index 2: x[2-31] to x[2+31]. Based on the fractional part 0.45, read 64 windowed SINC coefficients from ROM address range 29 (0.45×64≈29). Use 64 parallel multipliers to calculate: x[i]×sinc(i-0.45)×w(i-0.45). Accumulate all products through a 6-level addition tree to obtain the interpolation result y[2.45].

[0129] Compared to the linear interpolation used in conventional methods, the 64th-order windowed SINC interpolation in this embodiment offers a significant improvement in accuracy. Linear interpolation uses only 2 points for calculation, while windowed SINC interpolation uses 64 points, enabling better reconstruction of the high-frequency components of the signal and reducing aliasing distortion.

[0130] 6. Output the resampled, equal-wavenumber-interval OCT signal and transmit the processed signal to the subsequent data packaging and uploading module.

[0131] It is understood that the resampling method proposed in this embodiment has the following characteristics:

[0132] (1) High real-time performance: By utilizing the parallel hardware processing capability of FPGA, the resampling algorithm is solidified at the hardware level, and the processing speed is fully matched with the A-Scan rate, realizing true real-time processing and overcoming the latency bottleneck of software processing.

[0133] (2) High accuracy: The amplitude calculation is performed using the SINC interpolation method, which is far more accurate than linear interpolation and comparable to the computationally intensive zero-padding interpolation method, ensuring image quality, especially in deep-depth imaging.

[0134] (3) High flexibility: The filtering of the K clock signal supports multiple modes such as low pass, high pass, and band pass. It can be optimized according to different light source characteristics and noise environment, with strong universality and can effectively suppress various "artifacts".

[0135] (4) Low system cost: It significantly reduces the requirements for backend computer data processing capabilities, eliminating the need for high-end GPUs and effectively reducing the cost and power consumption of the entire system. Compared to the previous method of transmitting raw data from the acquisition card to the computer for software resampling using the CPU / GPU and finally FFT imaging, this application implements real-time resampling in the acquisition card FPGA at the forefront of the data flow, directly transmitting the sampling results to the computer for FFT imaging, thus eliminating data transmission delay.

[0136] (5) High integration: The most computationally intensive steps are completed at the data acquisition end, which greatly reduces the burden on the data transmission bus and simplifies the system architecture.

[0137] Parallel implementation of high-order SINC interpolation: A parallel algorithm for 64th-order SINC interpolation was successfully implemented on an FPGA.

[0138] Generally, due to the inherent parallelism of hardware and resource bottlenecks, the higher the order and the higher the precision, the more exponentially the FPGA logic resources (DSP, LUT) consumed. The number of dedicated hardware multiplier DSP blocks in an FPGA is fixed (for example, a mid-range FPGA may have hundreds to thousands of DSPs). A 64th-order parallel interpolator consumes 64 DSPs. If there are multiple such interpolators in the system, DSP resources will be quickly exhausted; and connecting these 64 multipliers and adders requires huge wiring resources, leading to wiring congestion. Resource consumption does not increase linearly; due to the sharp increase in wiring complexity, resource consumption also increases sharply. Since SINC interpolation is a multiply-accumulate operation, to implement 64th-order SINC interpolation, 64th order means that 64 multipliers and 63 adders need to work simultaneously within one clock cycle.

[0139] The multiplication results from the outputs of 64 multipliers need to be summed through a multi-level adder tree. This adder tree is very deep (logic level). Furthermore, signal propagation within the FPGA takes time. This long adder tree forms a critical path, preventing the signal from settling within a single clock cycle. Forcing an increase in the clock frequency will lead to timing violations and calculation errors. Simply instantiating 64 multipliers and connecting them will result in a design that is almost impossible to stably operate at high sampling clock frequencies.

[0140] To address the excessively long critical path of the 64-input addition tree, this embodiment employs deep pipelined architecture, breaking down the long combinational logic chain and inserting multi-stage pipelined registers along the way. Specifically, the summation process of the 64 data points is divided into multiple stages, for example, six stages (64 -> 32 -> 16 -> 8 -> 4 -> 2 -> 1). After each stage, the result is stored in a register before proceeding to the next stage. This reduces the number of addition operations performed at each stage within a single clock cycle. Although this introduces a delay of a few clock cycles, it significantly shortens the critical path, enabling the design to operate stably at high clock frequencies. This is crucial for achieving high-speed real-time processing.

[0141] On the other hand, to efficiently provide 64 consecutive sampling points for the 64th-order interpolator, the memory access architecture was optimized by employing a 128-bit wide shift register group. This ensures that 64 consecutive data points centered at any index can be accessed in parallel within a single clock cycle. This avoids the latency and complexity caused by multiple memory accesses, guaranteeing that the interpolator can always maintain data processing continuity, which is a prerequisite for maintaining high throughput. High-precision 64th-order SINC interpolation was achieved, improving image quality (especially sidelobe suppression and signal-to-noise ratio). Through pipelined optimization, the output throughput was ensured to meet the real-time requirements of high-speed A-Scan.

[0142] Example 2

[0143] like Figure 2 As shown, this embodiment proposes a real-time wavenumber spatial resampling system for SS-OCT, comprising:

[0144] The SS-OCT signal source includes a linearly swept laser source, a Mach-Zehnder interferometer, and a photoelectric conversion module connected in sequence. The photoelectric conversion module sends the K clock signal and the OCT interference signal to the acquisition module of the FPGA, respectively.

[0145] The data acquisition card FPGA includes:

[0146] The acquisition module has two data acquisition channels, which simultaneously acquire the K clock signal and the OCT interference signal, and perform filtering preprocessing on the K clock signal and the OCT interference signal respectively;

[0147] The phase extraction module is used to perform Hilbert transform on the preprocessed K clock signal, construct an analytical signal, and extract the instantaneous phase from the analytical signal to form an instantaneous phase sequence.

[0148] The remapping module is used to match the target phase sequence with the instantaneous phase sequence using a preset ideal isowavenumber interval phase sequence as the target phase sequence, calculate the position index of each target phase in the instantaneous phase sequence, and obtain the remapping sampling point index.

[0149] The interpolation module is used to process the pre-processed OCT interference signal using the SINC interpolation method based on the remapped sampling point index, and the resulting resampled OCT signal with equal wavenumber intervals is directly uploaded to the computer for FFT image display.

[0150] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Based on the technical essence of the present invention, any simple modifications, equivalent substitutions, and improvements made to the above embodiments within the spirit and principles of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A real-time wavenumber space resampling method for SS-OCT, characterized in that, Specifically comprising the following steps: S1, synchronously collecting K clock signals and OCT interference signals, and performing filtering pretreatment on the K clock signals and the OCT interference signals respectively; S2, performing Hilbert transform on the pretreated K clock signals, constructing an analytic signal, and extracting an instantaneous phase from the analytic signal to form an instantaneous phase sequence; S3, using a preset ideal equal-wavenumber-interval phase sequence as a target phase sequence, matching the target phase sequence with the instantaneous phase sequence, calculating a corresponding position index of each target phase in the instantaneous phase sequence, and obtaining a remapping sampling point index; The specific process of calculating the remapping sampling point index in step S3 is as follows: S31, generating equal-interval target phases according to a preset sampling point number and a total phase variation range to form a target phase sequence; S32, for each target phase, traverse in the instantaneous phase sequence, find two adjacent instantaneous phases satisfying: φ(t i )≤φ target [m]<φ(t i+1 ) of, wherein φ(t i ) represents the t i th instantaneous phase, φ(t i+1 ) represents the t i+1 th instantaneous phase, and φ target [m] represents the mth target phase; S33. According to the two instantaneous phases that are satisfied, the remapping sample point index p of each sample point is calculated by linear interpolation m = i + ;​ S4, using a SINC interpolation method to process the remapping sampling point index in the pretreated OCT interference signal to obtain an equal-wavenumber-interval OCT signal after resampling.

2. The method for real-time wavenumber-space resampling for SS-OCT according to claim 1, wherein, The specific process of step S2 is as follows: S21, using a 128-order FIR filter to perform Hilbert transform on the K clock signal to obtain its quadrature component and obtain a Hilbert transform result; S22, constructing an analytic signal by taking the K clock signal as a real part and the Hilbert transform result as an imaginary part; S23, using a CORDIC algorithm to extract an instantaneous phase value of each sampling point from the analytic signal.

3. The method for real-time wavenumber-space resampling for SS-OCT according to claim 2, wherein, In the process of extracting the instantaneous phase value from the analytic signal in step S23, phase unwrapping is also needed, and the specific method is as follows: Traverse the instantaneous phase sequence in time sequence, calculate the difference between the current sampling point phase value and the previous sampling point phase value, if the difference is greater than +π, subtract 2π from the phase values of all subsequent sampling points starting from the current point; if the difference is less than -π, add 2π to the phase values of all subsequent sampling points starting from the current point.

4. The method of claim 1, wherein, For the remapping sampling point index, boundary processing is also needed: when the calculated remapping sampling point index exceeds the index range of the instantaneous phase sequence, set an overflow flag for the remapping sampling point index.

5. The method of claim 1, wherein, The specific process of using the SINC interpolation method for processing in step S4 is as follows: S41, using a windowed SINC function as an interpolation kernel, precalculating SINC interpolation kernel coefficients corresponding to all possible decimal offsets, and storing them in a ROM lookup table of an FPGA; S42, obtaining an integer index value of an integer part of the remapping sampling point index value and a decimal index value of a decimal part; S43, obtaining N sampling points around the sampling point corresponding to the integer index value, N being an interpolation kernel length, calculating a corresponding ROM address interval according to the decimal index value, and reading N interpolation kernel coefficients from the ROM address interval; S44, performing parallel multiplication calculation on the N sampling points and the N interpolation kernel coefficients, and accumulating all products by using a parallel addition tree to obtain an interpolation result.

6. The method for real-time wavenumber-space resampling for SS-OCT according to claim 5, wherein, The method for obtaining N sampling points around the sampling point corresponding to the integer index value is as follows: After sampling the pretreated OCT interference signal, store the sampled sampling points in groups according to the interpolation kernel length to obtain a plurality of sampling point data groups; The two adjacent sample point data groups are spliced and stored in a memory with a length of 2N in a same clock cycle; According to the clock cycle where the integer index value is located, N sample points around the integer index value are read from the memory of the clock cycle.

7. The method for real-time wavenumber-space resampling for SS-OCT according to claim 6, wherein, The parallel addition tree adopts a balanced structure, and the number of adders at each level exponentially decreases by 2.

8. The method for real-time wavenumber-space resampling for SS-OCT according to claim 5, wherein, When it is detected that the current remapping sample point index value is set with an overflow flag, the data path corresponding to the current remapping sample point index value is set to zero.

9. A real-time wavenumber space resampling system for SS-OCT, comprising: The application of the real-time wave number space resampling method for SS-OCT according to claim 1 comprises: An SS-OCT signal source is used to generate a K clock signal and an OCT interference signal. A collection module is used to synchronously collect the K clock signal and the OCT interference signal, and filter and pretreat the K clock signal and the OCT interference signal respectively. A phase extraction module is used to perform Hilbert transform on the pretreated K clock signal, construct an analytic signal, and extract an instantaneous phase from the analytic signal to form an instantaneous phase sequence. A remapping module is used to use a preset ideal equal wave number interval phase sequence as a target phase sequence, match the target phase sequence with the instantaneous phase sequence, calculate the position index corresponding to each target phase in the instantaneous phase sequence, and obtain a remapping sample point index. An interpolation module is used to use a SINC interpolation method to process the pretreated OCT interference signal according to the remapping sample point index, and obtain an OCT signal resampled and with equal wave number intervals.

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