Multi-output isolated power supply

Abstract

The embodiment of the invention provides a multi-output isolated power supply, which comprises a power transformer comprising a single primary side coil and a single secondary side coil; a switch driving circuit coupled to the primary coil to output a driving voltage to the primary coil based on the input voltage; a rectification circuit coupled to the secondary coil and configured to rectify a voltage across the secondary coil to output a first DC voltage at a first rectified voltage output end and a second DC voltage at a second rectified voltage output end; and an output unit coupled to the first rectified voltage output terminal and the second rectified voltage output terminal, the output unit comprising one or more low dropout linear regulator circuits, where an output terminal of a predetermined low dropout linear regulator circuit is coupled to the secondary circuit ground, the output unit is configured to output at least one positive voltage and at least one negative voltage with a voltage at an output terminal of a predetermined low dropout linear regulator circuit as a reference.

Description

TECHNICAL FIELD

[0001] Example embodiments of the present disclosure generally relate to the technical field of isolated power supply, and in particular, to a multi-output isolated power supply. BACKGROUND

[0002] A positive and negative voltage multi-output isolated power supply has become an important part of many complex circuit and system designs due to its advantages of providing multiple output voltages, ensuring electrical isolation, reducing electrical interference, and improving system reliability. A conventional positive and negative voltage multi-output isolated power supply usually uses a multi-output transformer to achieve multi-output positive and negative isolated voltages. However, the multi-output transformer occupies a large chip area and has a high cost. SUMMARY

[0003] Embodiments of the present disclosure provide a multi-output isolated power supply to at least partially address the above and other potential problems.

[0004] In one aspect of the present disclosure, a multi-output isolated power supply is provided. The multi-output isolated power supply includes: a power transformer including a single primary winding and a single secondary winding; a switch driving circuit coupled to the primary winding and configured to output a driving voltage to the primary winding based on an input voltage; a rectification circuit coupled to the secondary winding and configured to rectify a voltage across the secondary winding to output a first direct current voltage at a first rectification voltage output and a second direct current voltage at a second rectification voltage output, the first direct current voltage being higher than the second direct current voltage; and an output unit coupled to the first rectification voltage output and the second rectification voltage output, the output unit including one or more low dropout linear regulator circuits, an output terminal of a predetermined low dropout linear regulator circuit among the one or more low dropout linear regulator circuits being coupled to a secondary circuit ground, and the output unit being configured to output at least one positive voltage and at least one negative voltage with a voltage at the output terminal of the predetermined low dropout linear regulator circuit as a reference.

[0005] In some embodiments, the one or more low dropout linear regulator circuits include a first low dropout linear regulator circuit, two input terminals of the first low dropout linear regulator circuit being coupled to the first rectification voltage output and the second rectification voltage output, respectively, to receive the first direct current voltage and the second direct current voltage.

[0006] In some embodiments, the output unit further comprises a first low dropout linear regulator circuit, an input terminal of the first low dropout linear regulator circuit is coupled to the output terminal of the first rectifier voltage output terminal, and another input terminal of the first low dropout linear regulator circuit is coupled to the second rectifier voltage output terminal.

[0007] In some embodiments, the output unit further comprises a second low dropout linear regulator circuit, an input terminal of the second low dropout linear regulator circuit is coupled to the output terminal of the first low dropout linear regulator circuit, and another input terminal of the second low dropout linear regulator circuit is coupled to the second rectifier voltage output terminal.

[0008] In some embodiments, the output unit further comprises a first low dropout linear regulator circuit, an input terminal of the first low dropout linear regulator circuit is coupled to the output terminal of the first rectifier voltage output terminal, and another input terminal of the first low dropout linear regulator circuit is coupled to the second rectifier voltage output terminal.

[0009] In some embodiments, the output unit further comprises a first low dropout linear regulator circuit, an input terminal of the first low dropout linear regulator circuit is coupled to the output terminal of the first rectifier voltage output terminal, and another input terminal of the first low dropout linear regulator circuit is coupled to the second rectifier voltage output terminal.

[0010] In some embodiments, the output terminal of the first low-dropout linear regulator circuit is coupled to the secondary-side circuit ground to make the first low-dropout linear regulator circuit as the predetermined low-dropout linear regulator circuit. The output unit further includes a first output terminal coupled to the first rectified voltage output terminal to output the first direct current voltage as at least one positive voltage, a second output terminal coupled to the output terminal of the second low-dropout linear regulator circuit, and a third output terminal coupled to the second rectified voltage output terminal to output the voltage at the output terminal of the second low-dropout linear regulator circuit and the second direct current voltage as at least one negative voltage. The multi-output isolated power supply further includes a feedback circuit and an isolator. The feedback circuit is coupled to the first rectified voltage output terminal and the second rectified voltage output terminal and is configured to generate a control signal based on a sampled voltage between the first direct current voltage and the second direct current voltage and a reference voltage. The isolator is configured to transmit the control signal to the switch driving circuit to control the on-off state of the switch driving circuit.

[0011] In some embodiments, the output terminal of the first low-dropout linear regulator circuit is coupled to the secondary-side circuit ground to make the first low-dropout linear regulator circuit as the predetermined low-dropout linear regulator circuit. The output unit further includes a first output terminal coupled to the first rectified voltage output terminal to output the first direct current voltage as at least one positive voltage, a second output terminal coupled to the output terminal of the second low-dropout linear regulator circuit, and a third output terminal coupled to the second rectified voltage output terminal to output the voltage at the output terminal of the second low-dropout linear regulator circuit and the second direct current voltage as at least one negative voltage. The multi-output isolated power supply further includes a feedback circuit and an isolator. The feedback circuit is coupled to the first rectified voltage output terminal and the second rectified voltage output terminal and is configured to generate a control signal based on a sampled voltage between the first direct current voltage and the second direct current voltage and a reference voltage. The isolator is configured to transmit the control signal to the switch driving circuit to control the on-off state of the switch driving circuit.

[0012] In some embodiments, the secondary-side soft-start circuit is further configured to, in response to the voltage difference being lower than the under-voltage protection threshold, cause the soft-start voltage to vary in proportion to the voltage difference; and in response to the voltage difference reaching the under-voltage protection threshold, cause the soft-start voltage to vary in the plurality of soft-start stages.

[0013] In some embodiments, the secondary-side soft-start circuit is further configured to, in response to the voltage difference being lower than the under-voltage protection threshold, cause the soft-start voltage to vary based on a state indication signal. The state indication signal is used to indicate whether the first low-dropout linear regulator circuit is working normally and whether a ratio of a first voltage difference and a second voltage difference is within a predetermined range. The first voltage difference is a difference between the voltage at the output terminal of the first low-dropout linear regulator circuit and the second DC voltage. The second voltage difference is a difference between the first DC voltage and the voltage at the output terminal of the first low-dropout linear regulator circuit.

[0014] In some embodiments, the secondary-side soft-start circuit is further configured to, in response to the state indication signal indicating that the first low-dropout linear regulator circuit has not worked normally or that the ratio of the first voltage difference and the second voltage difference is outside the predetermined range, cause the soft-start voltage to increase to a first voltage threshold in a first soft-start stage; and in response to the state indication signal indicating that the first low-dropout linear regulator circuit is working normally and that the ratio of the first voltage difference and the second voltage difference is within the predetermined range, cause the soft-start voltage to increase from the first voltage threshold to a second voltage threshold in a second soft-start stage.

[0015] In some embodiments, the output unit further comprises: a first switch unit coupled between the first output terminal and the output terminal of the first low-dropout linear regulator circuit and configured to switch between a conductive state and a non-conductive state; a first comparison unit coupled to the first switch unit and configured to switch the first switch unit to the conductive state in response to the ratio of the first voltage difference and the second voltage difference being lower than a first target value; a second switch unit coupled between the output terminal of the first low-dropout linear regulator circuit and the second output terminal and configured to switch between a conductive state and a non-conductive state; and a second comparison unit coupled to the second switch unit and configured to switch the second switch unit to the conductive state in response to the ratio of the first voltage difference and the second voltage difference being higher than a second target value, wherein the second target value is greater than or equal to the first target value.

[0016] In some embodiments, the feedback circuit includes a comparator having a negative input, a positive input, and an output, the positive input receiving the reference voltage, the output of the comparator being coupled to the isolator to output the control signal; and a sampling circuit including a first resistor, a second resistor, and a third resistor connected in series between the second rectified voltage output and the first rectified voltage output, a first node between the first resistor and the second resistor being coupled to the negative input of the comparator via the low-side switch, a second node between the second resistor and the third resistor being coupled to the negative input of the comparator via the high-side switch. In response to the voltage at the second node being lower than the reference voltage, the comparator outputs the control signal to operate the power transformer, the high-side switch is turned off, and the low-side switch is turned on. In response to the voltage at the first node being higher than the reference voltage, the comparator outputs the control signal to stop operating the power transformer, the high-side switch is turned on, and the low-side switch is turned off.

[0017] In some embodiments, the feedback circuit includes a sampling circuit including a first resistor and a second resistor connected in series between the second rectified voltage output and the first rectified voltage output; an error amplifier having a positive input, a negative input, and an amplifier output, the positive input receiving the reference voltage, the negative input being coupled to a sampling node between the first resistor and the second resistor; and a comparator including a first input, a second input, and an output, the first input being coupled to the amplifier output, the second input receiving a triangular wave signal, the output of the comparator being coupled to the isolator to output the control signal.

[0018] It will be appreciated from the following description that, according to embodiments of the present disclosure, a single-output power transformer in combination with a low-dropout linear regulator circuit can achieve multi-output of positive and negative voltages. Compared with a conventional solution of using a multi-output transformer, the multi-output isolated power supply of embodiments of the present disclosure has significantly reduced chip area, significantly reduced cost, and simple structure, and stable output. Other benefits will be described below in conjunction with corresponding embodiments.

[0019] It should be understood that the content described in this section is not intended to limit the key features or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0020] The above and other features, advantages, and aspects of embodiments of the present disclosure will become more apparent from the following detailed description in conjunction with the accompanying drawings. In the drawings, the same or similar reference numerals designate the same or similar elements, in which:

[0021] Figure 1 A principle block diagram of a conventional multi-output isolated power supply is shown;

[0022] Figures 2 to 6 A schematic block diagram of a multi-output isolated power supply according to some embodiments of the present disclosure is shown;

[0023] Figures 7 to 9 A schematic block diagram of a low-dropout linear regulator circuit according to some embodiments of the present disclosure is shown;

[0024] Figures 10 to 13 A schematic block diagram of a feedback circuit according to some embodiments of the present disclosure is shown;

[0025] Figure 14 Circuit diagrams of low-dropout linear regulator circuits according to some embodiments of the present disclosure are shown; and

[0026] Figure 15 and Figure 16 A schematic block diagram of a multi-output isolated power supply chip according to some embodiments of the present disclosure is shown. Detailed Implementation

[0027] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0028] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may also be included below. The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0029] The term "in response to" as used in this document refers to a state in which a corresponding event occurs or a condition is satisfied. It will be understood that the timing of subsequent actions performed in response to an event or condition is not necessarily strongly correlated with the time when the event occurs or the condition is met. For example, in some cases, subsequent actions may be performed immediately upon the occurrence of the event or the fulfillment of the condition; while in others, they may be performed some time after the occurrence of the event or the fulfillment of the condition.

[0030] As briefly mentioned above, conventional positive and negative voltage multi-output isolated power supplies typically use multi-output transformers to achieve multi-output positive and negative voltage isolation. Figure 1 A schematic block diagram of a conventional multi-output isolated power supply 100 is shown. Figure 1 As shown, the multi-output isolated power supply 100 generally includes a drive circuit 21, a multi-output transformer 22, a rectifier and filter circuit 23, a feedback control circuit 24, and an isolation circuit 25. To achieve multi-channel positive and negative isolated voltage output, the multi-output transformer 22 includes multiple secondary-side coils. For example, as... Figure 1 As shown, when the multi-output isolated power supply 100 needs to output two voltages V1 and V2, the multi-output transformer 22 includes two secondary-side coils, each of which outputs the corresponding voltages V1 and V2 via a corresponding rectifier and filter circuit 23. Due to the use of multiple secondary-side coils, the multi-output transformer 22 is relatively large, thus occupying a large chip area, which limits its application in space-constrained environments. Furthermore, the conventional multi-output isolated power supply 100 is relatively expensive, which also limits its application in cost-sensitive applications.

[0031] This disclosure provides a multi-output isolated power supply, in which a single-output power transformer combined with a low-dropout linear regulator circuit can achieve multiple outputs of positive and negative voltages. Compared with conventional solutions using multi-output transformers, the multi-output isolated power supply of this disclosure significantly reduces the chip area occupied, substantially lowers the cost, and has a simple structure and stable output. In the following sections, it will be combined with... Figures 2 to 16 To describe the principles of this disclosure.

[0032] Figure 2 A schematic block diagram of a multi-output isolated power supply 200 according to a first embodiment of the present disclosure is shown. Figure 2 As shown, the multi-output isolated power supply 200 described herein generally includes a switch drive circuit 11, a power transformer T1, a rectifier circuit 12, an output unit 13, a feedback circuit 14, and an isolator 15.

[0033] The power transformer T1 is the core energy component, comprising a single primary winding 101 and a single secondary winding 102, as follows: Figure 2 As shown. The primary coil 101 can be electromagnetically coupled to the secondary coil 102.

[0034] like Figure 2As shown, the switch drive circuit 11 is coupled to the primary coil 101. The on / off state of the switch drive circuit 11 can be controlled by a control signal provided by the isolator 15. The control signal can be, for example, a pulse width modulation (PWM) signal. Through on / off control, the switch drive circuit 11 can output a drive voltage to the primary coil 101 based on the input voltage VDD to charge and discharge the primary coil 101. Through electromagnetic coupling, the power transformer T1 can transfer energy from the primary coil 101 to the secondary coil 102, thereby generating a periodic voltage across the secondary coil 102.

[0035] like Figure 2 As shown, rectifier circuit 12 is coupled to secondary coil 102. Rectifier circuit 12 can rectify the voltage across secondary coil 102 to provide a DC voltage at its output. For example, rectifier circuit 12 can output a first DC voltage VISO at a first rectified voltage output terminal 121 and a second DC voltage VSS at a second rectified voltage output terminal 122. The first DC voltage VISO is higher than the second DC voltage VSS.

[0036] In one embodiment, such as Figure 2 As shown, the rectifier circuit 12 may include diodes D1-D4. In other embodiments, diodes D1-D4 may be replaced with metal-oxide-semiconductor field-effect transistors (MOSFETs). By controlling the on / off state of each MOSFET, the rectification function can be achieved.

[0037] like Figure 2 As shown, output unit 13 is coupled to a first rectified voltage output terminal 121 and a second rectified voltage output terminal 122. Output unit 13 includes a first low-dropout linear regulator circuit LDO1. One input terminal of LDO1 is coupled to the first rectified voltage output terminal 121 to receive a first DC voltage VISO. The other input terminal of LDO1 is coupled to the second rectified voltage output terminal 122 to receive a second DC voltage VSS. The main function of LDO1 is to generate a stable output voltage VGND based on the first DC voltage VISO and the second DC voltage VSS. Regardless of changes in input voltage or load current, LDO1 can adjust the magnitude of the output voltage VGND through an internal negative feedback mechanism to maintain it at a predetermined stable value. The output terminal of LDO1 is coupled to the secondary circuit ground GND2, allowing output unit 13 to use the secondary circuit ground GND2 as a reference point, i.e., the voltage VGND as a voltage reference point. In this case, voltages higher than VGND can be used as positive voltages, and voltages lower than VGND can be used as negative voltages.

[0038] like Figure 2As shown, the output unit 13 also includes a first output terminal 131 and a second output terminal 132. The first output terminal 131 is coupled to the first rectified voltage output terminal 121 to output a first DC voltage VISO as the positive voltage V1+. The second output terminal 132 is coupled to the second rectified voltage output terminal 122 to output a second DC voltage VSS as the negative voltage V1-. Both the positive voltage V1+ and the negative voltage V1- are referenced to the voltage VGND at the output terminal of LDO1. With this arrangement, the multi-output isolated power supply 200 can simultaneously output the positive voltage V1+ and the negative voltage V1-.

[0039] In some examples, LDO1 can be a source-type LDO circuit, which will be discussed below. Figure 7 A detailed description will follow. In some examples, the LDO1 can be a sink-type LDO circuit, which will be discussed below. Figure 8 A detailed description will follow. In some examples, the LDO1 can be a source / sink type LDO circuit, which will be discussed in detail below. Figure 9 Provide a detailed description.

[0040] like Figure 2 As shown, feedback circuit 14 is coupled to the first rectified voltage output terminal 121 and the second rectified voltage output terminal 122 to generate a control signal based on a sampled voltage between the first DC voltage VISO and the second DC voltage VSS, and a reference voltage Vref. The sampled voltage reflects the voltage difference VISO-VSS between the first DC voltage VISO and the second DC voltage VSS. The reference voltage Vref is used for comparison with the sampled voltage. The sampled voltage can be, as will be discussed below... Figure 10 and Figure 11 The sampled voltage described is VISO_H or VISO_L, or in combination below. Figure 12 and Figure 13 The sampling voltage VISO_FB is described, or any other suitable sampling voltage. In one embodiment, the feedback circuit 14 can generate a PWM signal as a control signal, which will be discussed below. Figures 10 to 13 Provide a detailed description.

[0041] like Figure 2As shown, the isolator 15 can transmit the control signal to the switch driving circuit 11 in isolation to control the on-off state of the switch driving circuit 11, thereby controlling whether the power transformer T1 works or not, and finally realizing the stable control of the voltage difference VISO-VSS between the first DC voltage VISO and the second DC voltage VSS. When the voltage difference VISO-VSS increases, the feedback circuit 14 can control the duty cycle of the PWM signal to decrease, thereby controlling the working time of the power transformer T1 to decrease through the switch driving circuit 11. Conversely, when the voltage difference VISO-VSS decreases, the feedback circuit 14 can control the duty cycle of the PWM signal to increase, thereby controlling the working time of the power transformer T1 to increase through the switch driving circuit 11. Through dynamic control, the stable output of the voltage difference VISO-VSS can finally be realized.

[0042] The target voltage difference between the first DC voltage VISO and the second DC voltage VSS is determined by the input voltage VDD of the primary side circuit and the transformation ratio of the power transformer T1. As an example, the input voltage VDD of the primary side circuit can be 5V, and the transformation ratio of the power transformer T1 can be 3. In this case, the target voltage difference between the first DC voltage VISO and the second DC voltage VSS is 15V.

[0043] It should be noted that the numbers, values, etc. mentioned above and possibly elsewhere in the present disclosure are exemplary and are not intended to limit the scope of the present disclosure in any way. Any other appropriate numbers, values, etc. are possible.

[0044] In addition, it should be understood that, according to the required voltage level requirement, the power transformer T1 can be a step-up, step-down or flat power transformer, and the embodiments of the present disclosure do not limit this.

[0045] In some examples, as Figure 2 As shown, the output unit 13 further includes capacitors C1, C2 and C3 for energy storage. The capacitor C1 is coupled between the first rectified voltage output end 121 and the second rectified voltage output end 122. The capacitor C2 is coupled between the first output end 131 and the output end of the LDO1. The capacitor C3 is coupled between the output end of the LDO1 and the second output end 132.

[0046] In some examples, the isolator 15 can include any one of an optical coupler, a magnetic isolator and a capacitive isolator to realize the isolated transmission of the signal. It should be understood that the isolator 15 can also be any other appropriate type, and the embodiments of the present disclosure do not limit this.

[0047] According to the first embodiment, the single-output power transformer T1 in combination with the LDO1 can realize the multi-output of positive and negative voltages, avoiding the use of multi-output transformer, thus significantly reducing the size and cost of the multi-output isolated power supply, and being suitable for occasions where the chip area and cost are limited.

[0048] Figure 3 A principle block diagram of a multi-output isolated power supply 300 according to a second embodiment of the present disclosure is shown. As Figure 3 shown, the multi-output isolated power supply 300 described herein generally includes a switch driving circuit 11, a power transformer T1, a rectifier circuit 12 and an output unit 13. Unlike the multi-output isolated power supply 200 shown in Figure 2 , Figure 3 the multi-output isolated power supply 300 shown in does not include a feedback circuit 14 and an isolator 15, forming an open-loop structure. Another difference between the multi-output isolated power supply 300 and the multi-output isolated power supply 200 lies in the structure of the output unit 13. The switch driving circuit 11, the power transformer T1 and the rectifier circuit 12 in the multi-output isolated power supply 300 are similar to those in the multi-output isolated power supply 200. In the following, the differences between the multi-output isolated power supply 300 and the multi-output isolated power supply 200 will be mainly described, and the same or similar parts will not be described again.

[0049] Figure 3 As shown, the output unit 13 includes a first low dropout linear regulator circuit LDO1 and a second low dropout linear regulator circuit LDO2. The main function of LDO1 and LDO2 is to provide a stable output voltage. Regardless of the change of input voltage or load current, LDO1 and LDO2 can adjust the output voltage through the internal negative feedback mechanism, so that the corresponding output voltage remains at a predetermined stable value. One input terminal of LDO1 is coupled to the first rectified voltage output terminal 121 to receive the first direct current voltage VISO. The other input terminal of LDO1 is coupled to the second rectified voltage output terminal 122 to receive the second direct current voltage VSS. One input terminal of LDO2 is coupled to the output terminal of LDO1. The other input terminal of LDO2 is coupled to the second rectified voltage output terminal 122. The output terminal of LDO2 is coupled to the secondary circuit ground GND2, so that the output unit 13 can take the secondary circuit ground GND2 as a reference point, i.e. take the voltage VGND as a voltage reference point. In this case, the voltage higher than the voltage VGND can be used as a positive voltage, and the voltage lower than the voltage VGND can be used as a negative voltage.

[0050] Figure 3As shown, the output unit 13 further includes a first output terminal 131 and a second output terminal 132. The first output terminal 131 is coupled to the output terminal of the LDO1 to output the voltage at the output terminal of the LDO1 as a positive voltage V1+. The second output terminal 132 is coupled to the second rectified voltage output terminal 122 to output the second DC voltage VSS as a negative voltage V1-. Both the positive voltage V1+ and the negative voltage V1- are referenced to the voltage VGND at the output terminal of the LDO2. With this arrangement, the multi-output isolated power supply 200 can output both the positive voltage V1+ and the negative voltage V1- simultaneously.

[0051] In some examples, the LDO1 can be a source-type LDO circuit. In some examples, the LDO2 can be any one of a source-type LDO circuit, a sink-type LDO circuit, and a source / sink-type LDO circuit.

[0052] In some examples, as Figure 3 As shown, the output unit 13 further includes capacitors C1, C2, C3 and C4 for energy storage. The capacitor C1 is coupled between the first rectified voltage output terminal 121 and the second rectified voltage output terminal 122. The capacitor C2 is coupled between the output terminal of the LDO1 and the second rectified voltage output terminal 122. The capacitor C3 is coupled between the first output terminal 131 and the output terminal of the LDO2. The capacitor C4 is coupled between the output terminal of the LDO2 and the second output terminal 132.

[0053] According to the second embodiment, the multi-output of positive and negative voltages can be achieved by using a single-output power transformer T1 in combination with the LDO1 and the LDO2, avoiding the use of a multi-output transformer, and the output voltage can be stabilized without the feedback circuit 14 and the isolator 15, thus significantly reducing the volume and cost of the multi-output isolated power supply, which is suitable for occasions where the chip occupation area and cost are limited.

[0054] Figure 4 A schematic diagram of a multi-output isolated power supply 400 according to a third embodiment of the present disclosure is shown. As Figure 4As shown, the multi-output isolated power supply 400 described herein generally includes a switch drive circuit 11, a power transformer T1, a rectifier circuit 12, an output unit 13, a feedback circuit 14, and an isolator 15. The switch drive circuit 11, power transformer T1, rectifier circuit 12, feedback circuit 14, and isolator 15 in the multi-output isolated power supply 400 are similar to those in the multi-output isolated power supply 200. The difference between the multi-output isolated power supply 400 and the multi-output isolated power supply 200 lies in the structure of the output unit 13. The following text will primarily describe the differences between the multi-output isolated power supply 400 and the multi-output isolated power supply 200, while identical or similar parts will not be repeated.

[0055] like Figure 4 As shown, output unit 13 includes a first low-dropout linear regulator circuit LDO1 and a second low-dropout linear regulator circuit LDO2. The main function of LDO1 and LDO2 is to provide a stable output voltage. Regardless of changes in input voltage or load current, LDO1 and LDO2 can adjust the output voltage through an internal negative feedback mechanism to maintain the corresponding output voltage at a predetermined stable value. One input terminal of LDO1 is coupled to the first rectified voltage output terminal 121 to receive the first DC voltage VISO. The other input terminal of LDO1 is coupled to the second rectified voltage output terminal 122 to receive the second DC voltage VSS. One input terminal of LDO2 is coupled to the output terminal of LDO1. The other input terminal of LDO2 is coupled to the second rectified voltage output terminal 122. The output terminal of LDO2 is coupled to the secondary circuit ground GND2, so that output unit 13 can use the secondary circuit ground GND2 as a reference point, that is, use the voltage VGND as a voltage reference point. In this case, a voltage higher than VGND can be used as a positive voltage, while a voltage lower than VGND can be used as a negative voltage.

[0056] like Figure 4 As shown, the output unit 13 also includes a first output terminal 131, a second output terminal 132, and a third output terminal 133. The first output terminal 131 is coupled to the first rectified voltage output terminal 121 to output a first DC voltage VISO as the positive voltage V1+. The second output terminal 132 is coupled to the output terminal of LDO1 to output the voltage at the output terminal of LDO1 as the positive voltage V2+. The third output terminal 133 is coupled to the second rectified voltage output terminal 122 to output a second DC voltage VSS as the negative voltage V1-. The positive voltages V1+, V2+, and negative voltage V1- are all referenced to the voltage VGND at the output terminal of LDO2. Using this arrangement, the multi-output isolated power supply 200 can simultaneously output the positive voltages V1+, V2+, and negative voltage V1-.

[0057] In some examples, LDO1 can be a source type LDO circuit. In some examples, LDO2 can be any one of a source type LDO circuit, a sink type LDO circuit, and a source / sink type LDO circuit.

[0058] In some examples, as Figure 4 shown, output unit 13 further includes capacitors C1, C2, C3, C4, and C5 for energy storage. Capacitor C1 is coupled between first rectified voltage output terminal 121 and second rectified voltage output terminal 122. Capacitor C2 is coupled between the output terminal of LDO1 and second rectified voltage output terminal 122. Capacitor C3 is coupled between second output terminal 132 and the output terminal of LDO2. Capacitor C4 is coupled between the output terminal of LDO2 and third output terminal 133. Capacitor C5 is coupled between first output terminal 131 and the output terminal of LDO2.

[0059] Figure 5 A schematic block diagram of a multi-output isolated power supply 500 according to a fourth embodiment of the present disclosure is shown. As Figure 5 shown, multi-output isolated power supply 500 described herein generally includes switch driving circuit 11, power transformer T1, rectifier circuit 12, output unit 13, feedback circuit 14, and isolator 15. Switch driving circuit 11, power transformer T1, rectifier circuit 12, feedback circuit 14, and isolator 15 in multi-output isolated power supply 500 are similar to switch driving circuit 11, power transformer T1, rectifier circuit 12, feedback circuit 14, and isolator 15 in multi-output isolated power supply 200. Multi-output isolated power supply 500 differs from multi-output isolated power supply 200 in the structure of output unit 13. In the following, the differences between multi-output isolated power supply 500 and multi-output isolated power supply 200 will be mainly described, and the same or similar parts will not be described again.

[0060] As Figure 5As shown, output unit 13 includes a first low-dropout linear regulator circuit LDO1 and a second low-dropout linear regulator circuit LDO2. The main function of LDO1 and LDO2 is to provide a stable output voltage. Regardless of changes in input voltage or load current, LDO1 and LDO2 can adjust the output voltage through an internal negative feedback mechanism to maintain the corresponding output voltage at a predetermined stable value. One input terminal of LDO1 is coupled to the first rectified voltage output terminal 121 to receive the first DC voltage VISO. The other input terminal of LDO1 is coupled to the second rectified voltage output terminal 122 to receive the second DC voltage VSS. One input terminal of LDO2 is coupled to the output terminal of LDO1. The other input terminal of LDO2 is coupled to the second rectified voltage output terminal 122. The output terminal of LDO1 is coupled to the secondary circuit ground GND2, so that output unit 13 can use the secondary circuit ground GND2 as a reference point, that is, use the voltage VGND as a voltage reference point. In this case, a voltage higher than VGND can be used as a positive voltage, while a voltage lower than VGND can be used as a negative voltage.

[0061] like Figure 5 As shown, the output unit 13 further includes a first output terminal 131, a second output terminal 132, and a third output terminal 133. The first output terminal 131 is coupled to the first rectified voltage output terminal 121 to output a first DC voltage VISO as the positive voltage V1+. The second output terminal 132 is coupled to the output terminal of LDO2 to output the voltage at the output terminal of LDO2 as the negative voltage V1-. The third output terminal 133 is coupled to the second rectified voltage output terminal 122 to output a second DC voltage VSS as the negative voltage V2-. The positive voltage V1+ and the negative voltages V1- and V2- are all referenced to the voltage VGND at the output terminal of LDO1. Using this arrangement, the multi-output isolated power supply 200 can simultaneously output the positive voltage V1+ and the negative voltages V1- and V2-.

[0062] In some examples, LDO1 can be any of a source-type LDO circuit, a sink-type LDO circuit, and a source / sink-type LDO circuit. In some examples, LDO2 can be any of a source-type LDO circuit, a sink-type LDO circuit, and a source / sink-type LDO circuit.

[0063] In some examples, such as Figure 5As shown, the output unit 13 further includes capacitors C1, C2, C3, C4 and C5 for energy storage. The capacitor C1 is coupled between the first rectified voltage output terminal 121 and the second rectified voltage output terminal 122. The capacitor C2 is coupled between the output terminal of the LDO1 and the second rectified voltage output terminal 122. The capacitor C3 is coupled between the output terminal of the LDO1 and the second output terminal 132. The capacitor C4 is coupled between the first output terminal 131 and the output terminal of the LDO1. The capacitor C5 is coupled between the output terminal of the LDO1 and the third output terminal 133.

[0064] Figure 6 A principle block diagram of a multi-output isolated power supply 600 according to a fifth embodiment of the present disclosure is shown. As shown, in order to avoid damage to the load during the startup process of the multi-output isolated power supply 600, a soft-start function is added in the multi-output isolated power supply 600. The multi-output isolated power supply 600 generally includes a switch driving circuit 11, a power transformer T1, a rectifier circuit 12, an output unit 13, a feedback circuit 14, an isolator 15, and circuits related to the soft-start function. The switch driving circuit 11, the power transformer T1, the rectifier circuit 12, the output unit 13, the feedback circuit 14, and the isolator 15 in the multi-output isolated power supply 600 are similar to those in the multi-output isolated power supply 200. In the following, the parts of the multi-output isolated power supply 600 related to the soft-start function will be mainly described, and the other same or similar parts will not be described again. Figure 6 As shown, in order to implement the soft-start function, the multi-output isolated power supply 600 further includes a multiplexer 16, a primary side soft-start circuit 17, and a secondary side soft-start circuit 18. The multiplexer 16 includes a first input terminal 161, a second input terminal 162, and a selector output terminal 163 to implement a two-way selection function. The first input terminal 161 is coupled to the output terminal of the primary side soft-start circuit 17. The second input terminal 162 is coupled to the output terminal of the isolator 15. The feedback circuit 14 can generate a control signal based on a sampling voltage between the first DC voltage VISO and the second DC voltage VSS and a reference voltage Vref. The isolator 15 can isolate and transmit the control signal generated by the feedback circuit 14 to the second input terminal 162 of the multiplexer 16. The selector output terminal 163 is coupled to the switch driving circuit 11. The secondary side soft-start circuit 18 is coupled to the feedback circuit 14 to provide a soft-start voltage Vsoft as the reference voltage Vref to the feedback circuit 14 during the soft-start process.

[0065] Figure 6

[0066] ​​The multiplexer 16 can divide the soft-start process into different stages that are responsible by the primary-side soft-start circuit 17 and the secondary-side soft-start circuit 18. In response to the voltage difference VISO-VSS between the first DC voltage VISO and the second DC voltage VSS being lower than an under-voltage protection threshold (also referred to as UVLO threshold), the multiplexer 16 can pass the signal at the first input 161 to the selector output 163. In response to the voltage difference VISO-VSS reaching the under-voltage protection threshold, the multiplexer 16 can pass the signal at the second input 162 to the selector output 163.

[0067] In some examples, the signal VISO_OK and the signal UVLO_B can both be a first value, e.g., 0, when the voltage difference VISO-VSS is lower than the under-voltage protection threshold, and can both be a second value, e.g., 1, when the voltage difference VISO-VSS reaches the under-voltage protection threshold. The signal UVLO_B can be provided by an under-voltage lockout circuit 190. The under-voltage lockout circuit 190 is coupled between the first rectified voltage output 121 and the second rectified voltage output 122. The signal VISO_OK can vary in synchronization with the signal UVLO_B or be generated based on the signal UVLO_B, and can be passed to the primary-side circuit of the isolated power supply via the isolator 15 or other circuitry provided additionally.

[0068] The working state of the multiplexer 16 can be controlled by the signal VISO_OK. As an example, when the signal VISO_OK is 0, the multiplexer 16 can pass the signal at the first input 161 to the selector output 163. When the signal VISO_OK is 1, the multiplexer 16 can pass the signal at the second input 162 to the selector output 163.

[0069] The primary-side soft-start circuit 17 is configured to control the initial start-up of the multi-output isolated power supply 600. The primary-side soft-start circuit 17 can output a primary-side soft-start signal in response to the voltage difference VISO-VSS being lower than the under-voltage protection threshold (i.e., the signal VISO_OK being 0). The primary-side soft-start signal can be a PWM square wave signal or any other appropriate type of signal. After the input voltage VDD is powered up, the duty cycle of the primary-side soft-start signal can start from a predetermined value and increase. As an example, the duty cycle of the primary-side soft-start signal can slowly increase from a minimum duty cycle (e.g., 5% or any other predetermined value) to a maximum duty cycle (e.g., 95% or any other predetermined value). During the process of increasing the duty cycle, the primary-side soft-start circuit 17 stops outputting the primary-side soft-start signal in response to the voltage difference VISO-VSS reaching the under-voltage protection threshold (i.e., the signal VISO_OK becoming 1). Subsequently, the secondary-side soft-start circuit 18 starts to work and continues the soft-start process.

[0070] In some examples, the primary side soft start signal can have a fixed frequency. For example, the primary side soft start signal can have a frequency of 625 kHz or any other suitable frequency value. In some examples, the primary side soft start signal can also have a varying frequency.

[0071] In some examples, during the soft start process performed by the primary side soft start circuit 17, in response to the voltage difference VISO-VSS being below an under-voltage protection threshold (i.e. the signal UVLO_B being zero), the secondary side soft start circuit 18 can cause the soft start voltage Vsoft to follow the voltage difference VISO-VSS, i.e. to vary proportionally to the voltage difference. As an example, in a case where the target voltage difference is 10 V, the maximum value of the soft start voltage Vsoft is 1.2 V, and the under-voltage protection threshold is 2.5 V, during the process in which the voltage difference VISO-VSS increases from 0 V to 2.5 V, the soft start voltage Vsoft can increase proportionally from 0 V to 0.3 V.

[0072] In some examples, in response to the voltage difference VISO-VSS reaching the under-voltage protection threshold (i.e. the signal UVLO_B becoming 1), the secondary side soft start circuit 18 can discontinue following the voltage difference VISO-VSS, and instead cause the soft start voltage Vsoft to vary based on a state indication signal ESOFT_OK. The state indication signal ESOFT_OK is used to indicate whether the LDO1 is working normally and whether the ratio of a first voltage difference VGND-VSS and a second voltage difference VISO-VGND is within a predetermined range. The first voltage difference VGND-VSS is the difference between the voltage VGND at the output of the LDO1 and the second DC voltage VSS. The second voltage difference VISO-VGND is the difference between the first DC voltage VISO and the voltage VGND at the output of the LDO1.

[0073] In some examples, the state indication signal ESOFT_OK can be provided by an AND gate 191. The AND gate 191 has three input terminals, a first input terminal receiving a signal LDO_OK, a second input terminal receiving a signal SOGN_OK, and a third input terminal receiving a signal GNSS_OK via an inverter 192. The signal LDO_OK can be provided by the LDO 1 to indicate whether the LDO 1 is working properly. In the case that the LDO 1 is working properly, the signal LDO_OK can be 1, while in the case that the LDO 1 is not working properly, the signal LDO_OK can be 0. The signal SOGN_OK is used to indicate whether the second voltage difference VISO-VGND is too high. In the case that the second voltage difference VISO-VGND is too high, the signal SOGN_OK can be 0, while in the case that the second voltage difference VISO-VGND is normal, the signal SOGN_OK can be 1. The signal GNSS_OK is used to indicate whether the first voltage difference VGND-VSS is too high. In the case that the first voltage difference VGND-VSS is too high, the signal GNSS_OK can be 1, while in the case that the first voltage difference VGND-VSS is normal, the signal GNSS_OK can be 0.

[0074] In some examples, in response to the state indication signal ESOFT_OK indicating that the LDO 1 is not working properly or the ratio of the first voltage difference VGND-VSS to the second voltage difference VISO-VGND is out of a predetermined range (i.e., the state indication signal ESOFT_OK is 0), the secondary side soft start circuit 18 can cause the soft start voltage Vsoft to increase to a first voltage threshold VREF1 in a first soft start stage, to implement a first stage soft start. As an example, the first voltage threshold VREF1 can be 0.6V. In response to the state indication signal ESOFT_OK indicating that the LDO 1 is working properly and the ratio of the first voltage difference VGND-VSS to the second voltage difference VISO-VGND is within the predetermined range (i.e., the state indication signal ESOFT_OK is 1), the secondary side soft start circuit 18 can cause the soft start voltage Vsoft to increase from the first voltage threshold VREF1 to a second voltage threshold VREF2 in a second soft start stage, to implement a second stage soft start. The second voltage threshold VREF2 is greater than the first voltage threshold VREF1. The second voltage threshold VREF2 is a reference value corresponding to a target voltage difference. As an example, the second voltage threshold VREF2 can be 1.2V.

[0075] In this way, in the case that the voltage difference VISO-VSS is less than the target voltage difference, it can be ensured that both the first voltage difference VGND-VSS and the second voltage difference VISO-VGND do not exceed the preset values, to avoid damaging the subsequent circuit.

[0076] It should be appreciated that the gradual increase of the soft-start voltage Vsoft in the first soft-start phase and the second soft-start phase described herein is merely an example soft-start manner implemented by the secondary-side soft-start circuit 18. In other embodiments, the secondary-side soft-start circuit 18 can vary the soft-start voltage Vsoft in more soft-start phases and / or in other manners, which implementations are equally within the scope of the present disclosure.

[0077] In some examples, in the soft-start process, in addition to ensuring that the first voltage difference VGND-VSS and the second voltage difference VISO-VGND do not exceed the preset values, it is also desirable to keep the ratio of the first voltage difference VGND-VSS to the second voltage difference VISO-VGND at a target proportion. To this end, the output unit 13 can further include a first switch unit 134, a first comparison unit 135, a second switch unit 136, and a second comparison unit 137, as shown in Figure 6

[0078] The first switch unit 134 is coupled between the first output end 131 and the output end of the LDO1, and can be switched between a conductive state and a disconnected state. As an example, the first switch unit 134 can include a PMOS transistor MP11 and a resistor connected in series.

[0079] The first comparison unit 135 is coupled to the first switch unit 134, and can switch the first switch unit 134 to the conductive state in response to the ratio of the first voltage difference VGND-VSS to the second voltage difference VISO-VGND being lower than a first target value. As an example, the first comparison unit 135 can include a comparator CMP1. The positive input end of the comparator CMP1 receives a voltage (VISO-VSS)*(1-k)*(1+x%). The voltage (VISO-VSS)*(1-k)*(1+x%) can be provided by a plurality of resistors connected in series through voltage division. The negative input end of the comparator CMP1 receives the second voltage difference VISO-VGND. The output end of the comparator CMP1 outputs a signal SOGN_OK to the control end of the MP11. k is the target proportion between the first voltage difference VGND-VSS and the voltage difference VISO-VSS. 1-k is the target proportion between the second voltage difference VISO-VGND and the voltage difference VISO-VSS. x% is a preset hysteresis window.

[0080] The second switch unit 136 is coupled between the output end of the LDO1 and the second output end 132, and can be switched between a conductive state and a disconnected state. As an example, the second switch unit 136 can include an NMOS transistor MN11 and a resistor connected in series.

[0081] ​The second comparison unit 137 is coupled to the second switch unit 136, and can switch the second switch unit 136 to the on state in response to the ratio of the first voltage difference VGND-VSS to the second voltage difference VISO-VGND being higher than a second target value. As an example, the second comparison unit 137 can include a comparator CMP2. The negative input terminal of the comparator CMP2 receives a voltage (VISO-VSS)*k*(1+y%). The voltage (VISO-VSS)*k*(1+y%) can be provided by a plurality of resistors in series through voltage division. The positive input terminal of the comparator CMP2 receives the first voltage difference VGND-VSS. The output terminal of the comparator CMP2 outputs a signal GNSS_OK to the control terminal of the MN11. The second target value is greater than or equal to the first target value. y% is a preset hysteresis window. x% and y% can be the same or different.

[0082] As shown in Figure 6 If the ratio of the first voltage difference VGND-VSS to the second voltage difference VISO-VGND is lower than the target ratio, the signal SOGN_OK=0, indicating that the voltage VGND at GND2 is too low at this time. In this case, the MP11 is turned on, thereby increasing the voltage VGND at GND2 to the target value.

[0083] On the contrary, if the ratio of the first voltage difference VGND-VSS to the second voltage difference VISO-VGND is higher than the target ratio, the signal GNSS_OK=1, indicating that the voltage VGND at GND2 is too high at this time. In this case, the MN11 is turned on, thereby reducing the voltage VGND at GND2 to the target value.

[0084] By setting the hysteresis windows x% and y%, when the voltage VGND at GND2 is x% lower than the target value, the MP11 can be turned on, and when the voltage VGND at GND2 is y% higher than the target value, the MN11 can be turned on.

[0085] In the above manner, it can be ensured that the first voltage difference VGND-VSS and the second voltage difference VISO-VGND are within the preset safe range during the soft start stage, protecting the subsequent circuit and avoiding damage thereto.

[0086] In the above, the Figures 2 to 6Several example embodiments of a multiple-output isolated power supply are described. It should be appreciated that, in accordance with embodiments of the present disclosure, the output unit 13 can include one or more low-dropout linear regulator circuits. The output terminal of a predetermined low-dropout linear regulator circuit among the one or more low-dropout linear regulator circuits can be coupled to the secondary circuit ground GND2, so that the output unit 13 is able to take the secondary circuit ground GND2 as a reference point, i.e., take the voltage VGND as a voltage reference point. A voltage higher than the voltage VGND can be used as a positive voltage, while a voltage lower than the voltage VGND can be used as a negative voltage. For example, in the embodiments described in conjunction with Figure 2 , Figure 5 and Figure 6 , the output terminal of the first low-dropout linear regulator circuit LDO1 is coupled to the secondary circuit ground GND2, so that LDO1 serves as the predetermined low-dropout linear regulator circuit. While in the embodiments described in conjunction with Figure 3 and Figure 4 , the output terminal of the second low-dropout linear regulator circuit LDO2 is coupled to the secondary circuit ground GND2, so that LDO2 serves as the predetermined low-dropout linear regulator circuit. In other embodiments, any suitable low-dropout linear regulator circuit can be selected as the predetermined low-dropout linear regulator circuit as needed, so that its output terminal is coupled to the secondary circuit ground GND2. With this arrangement, the output unit 13 is able to output at least one positive voltage and at least one negative voltage that take the voltage at the output terminal of the predetermined low-dropout linear regulator circuit as a reference.

[0087] Next, the working principle of the LDO circuit in accordance with some embodiments of the present disclosure will be described in conjunction with Figures 7 to 9 .

[0088] Figure 7The shown LDO circuit is a source type LDO circuit, which is a voltage regulator that current flows from input to load, that is, the source type LDO circuit provides current from the power supply to the load. The LDO circuit can include resistors R1-R5, an operational amplifier A1, a PMOS transistor MP1, and a capacitor C1. The input voltage V- of the inverting input terminal of the operational amplifier A1 is (VISO*R4+VISO*R5+VSS*R3) / (R3+R4+R5). The output voltage of the LDO circuit is divided by resistors R1 and R2 and then used as the non-inverting input voltage of the operational amplifier A1. The output signal of the operational amplifier A1 is used to control the working state of MP1 to work in the linear region. The size of the output current is controlled by controlling the gate voltage of MP1, so as to maintain a stable output. When the output voltage of the LDO circuit is lower than the set value, MP1 can be adjusted to increase its on state, so that more current flows to the load, thereby increasing the output voltage. By setting the resistance values of resistors R1-R5, the first voltage difference VGND-VSS and the second voltage difference VISO-VGND can be ensured to maintain a target ratio at all times.

[0089] Figure 8 The shown LDO circuit is a sink type LDO circuit, which is a voltage regulator that current flows from the load back to the LDO output, that is, the sink type LDO circuit absorbs current from the load, that is, from GND to VSS. The LDO circuit can include resistors R1-R5, an operational amplifier A2, an NMOS transistor MN1, and a capacitor C1. The input voltage V- of the inverting input terminal of the operational amplifier A2 is (VSS*R4+VISO*R5+VSS*R3) / (R3+R4+R5). The output voltage of the LDO circuit is divided by resistors R1 and R2 and then used as the non-inverting input voltage of the operational amplifier A2. The output signal of the operational amplifier A2 is used to control the working state of MN1 to work in the linear region. The size of the output current is controlled by controlling the gate voltage of MN1, so as to maintain a stable output. When the output voltage of the LDO circuit is higher than the set value, MN1 can be adjusted to increase its on state, so that more current flows from GND to VSS. Thus, the output voltage is reduced. By setting the resistance values of resistors R1-R5, the first voltage difference VGND-VSS and the second voltage difference VISO-VGND can be ensured to maintain a target ratio at all times.

[0090] Figure 9The illustrated LDO circuit is a source / sink type LDO circuit, which is commonly used in situations where bidirectional control of current flow is required. The LDO circuit can include resistors R1-R5, an AB class operational amplifier A3, an NMOS transistor MN1, a PMOS transistor MP1, and a capacitor C1. The input voltage at the inverting input of the operational amplifier A3 is V- = (VSS*R4 + VISO*R5 + VSS*R3) / (R3+R4+R5). The output voltage of the LDO circuit is divided by resistors R1 and R2 and then applied as the non-inverting input voltage of the operational amplifier A3. When current is drawn from GND, the voltage VGND becomes lower, the input voltage at the non-inverting input of the operational amplifier A3 becomes smaller, the output of the operational amplifier A3 becomes lower, and the current flowing through MP1 becomes larger, while the current flowing through MN1 becomes smaller. When current is supplied to GND, the voltage VGND becomes higher, the input voltage at the non-inverting input of the operational amplifier A3 becomes larger, the output of the operational amplifier A3 becomes higher, and the current flowing through MP1 becomes smaller, while the current flowing through MN1 becomes larger. In this way, the voltage VGND can be kept stable, and the outputs of VISO and VSS can be ensured to be stable. By setting the resistance values of R1-R5, the first voltage difference VGND-VSS and the second voltage difference VISO-VGND can be ensured to always maintain a target ratio.

[0091] Reference Figures 7 to 9 The described LDO circuit can be used to implement the first low dropout linear regulator circuit LDO1 and the second low dropout linear regulator circuit LDO2 in the multi-output isolated power supply described above in connection with Figures 2 to 6 The described LDO circuit can be used to implement the first low dropout linear regulator circuit LDO1 and the second low dropout linear regulator circuit LDO2 in the multi-output isolated power supply described above in connection with

[0092] Next, an example working principle of the feedback circuit 14 according to an example embodiment of the present disclosure will be described in connection with Figures 10 to 13

[0093] As Figure 10 illustrated, the feedback circuit 14 includes a comparator CMP and a sampling circuit 140. The feedback circuit 14 employs hysteresis control, i.e., the first DC voltage VISO is maintained within a hysteresis width centered on an internal reference voltage. The comparator CMP can be a hysteretic comparator having a negative input, a positive input, and an output. The positive input of the comparator CMP receives a reference voltage Vref, which can have a predetermined value. The output of the comparator CMP can be coupled to the isolator 15 to output a control signal, e.g., a PWM signal, in connection with Figure 2 , Figure 4 , Figure 5 and Figure 6 ​The sampling circuit 140 includes a first resistor R1, a second resistor R2 and a third resistor R3 connected in series between the second rectified voltage output terminal 122 and the first rectified voltage output terminal 121. A first node N1 between the first resistor R1 and the second resistor R2 is coupled to the negative input terminal of the comparator CMP via a low-side switch 141. A second node N2 between the second resistor R2 and the third resistor R3 is coupled to the negative input terminal of the comparator CMP via a high-side switch 142. The sampling circuit 140 samples the voltage difference VISO-VSS and outputs two sampled voltages, i.e. a voltage VISO_L at the first node N1 and a voltage VISO_H at the second node N2, for comparison with the reference voltage Vref. The voltage VISO_H is higher than the voltage VISO_L.

[0094] VISO_H = (VISO*(R1+R2)+VSS*R3) / (R1+R2+R3),

[0095] VISO_L = (VISO*R1+VSS*R2+VSS*R3) / (R1+R2+R3).

[0096] Based on the control signal (e.g. PWM signal) output by the comparator CMP, the voltages VISO_H and VISO_L can be alternately switched to the negative input terminal of the comparator CMP, so that the first DC voltage VISO is transformed between fixed binary values. During operation, in response to the voltage VISO_H being lower than the reference voltage Vref, the comparator CMP outputs a control signal, e.g. high level, for operating the power transformer T1, so as to control the power transformer T1 to operate through the switch driving circuit 11, so as to increase the first DC voltage VISO. At the same time, the high-side switch 142 is turned off and the low-side switch 141 is turned on, so as to disconnect the voltage VISO_H from the negative input terminal of the comparator CMP, while the voltage VISO_L is connected to the negative input terminal of the comparator CMP. In response to the voltage VISO_L being higher than the reference voltage Vref, the comparator CMP outputs a control signal, e.g. low level, for stopping the power transformer T1 from operating, so as to control the power transformer T1 to stop operating through the switch driving circuit 11, so as to decrease the first DC voltage VISO. At the same time, the high-side switch 142 is turned on and the low-side switch 141 is turned off, so as to disconnect the voltage VISO_L from the negative input terminal of the comparator CMP, while the voltage VISO_H is connected to the negative input terminal of the comparator CMP. This is repeated, so as to control the voltage difference VISO-VSS to vary within a certain range.

[0097] In combination Figure 6 and Figure 11As shown, the output of the secondary soft-start circuit 18 is connected to the positive input of the comparator CMP to provide a soft-start voltage Vsoft as a reference voltage Vref to the feedback circuit 14 during the soft-start process. When the voltage difference VISO-VSS is below the undervoltage protection threshold, the comparator CMP does not operate, and the secondary soft-start circuit 18 allows the soft-start voltage Vsoft to follow the voltage difference VISO-VSS. When the voltage difference VISO-VSS reaches the undervoltage protection threshold, the secondary soft-start circuit 18 can disconnect from following the voltage difference VISO-VSS and instead allow the soft-start voltage Vsoft to change based on the status indication signal ESOFT_OK. If the status indication signal ESOFT_OK is 0, the secondary soft-start circuit 18 can slowly increase the soft-start voltage Vsoft to the first voltage threshold VREF1, achieving the first stage of soft-start. If the status indication signal ESOFT_OK is 1, the secondary soft-start circuit 18 can slowly increase the soft-start voltage Vsoft from the first voltage threshold VREF1 to the second voltage threshold VREF2, achieving the second stage of soft-start. In this way, it can be ensured that when the voltage difference VISO-VSS is less than the target voltage difference, the first voltage difference VGND-VSS and the second voltage difference VISO-VGND will not exceed the preset value, thus avoiding damage to the subsequent circuits.

[0098] like Figure 12 As shown, the feedback circuit 14 includes a sampling circuit 140, an error amplifier EA, and a comparator CMP. The sampling circuit 140 includes a first resistor R1 and a second resistor R2 connected in series between the second rectified voltage output terminal 122 and the first rectified voltage output terminal 121. The error amplifier EA has a positive input terminal, a negative input terminal, and an amplifier output terminal. The positive input terminal of the error amplifier EA receives a reference voltage Vref. The negative input terminal of the error amplifier EA is coupled to a sampling node N0 between the first resistor R1 and the second resistor R2. The output terminal of the error amplifier EA is coupled to its negative input terminal via a compensation network. The compensation network is used to control loop stability. The comparator CMP includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the comparator CMP is coupled to the output terminal of the error amplifier EA. The second input terminal of the comparator CMP receives a triangular wave signal. The output terminal of the comparator CMP is coupled to an isolator 15 to output a control signal, such as a PWM signal.

[0099] like Figure 12As shown, sampling circuit 140 samples the voltage difference VISO-VSS and outputs a sampled voltage VISO_FB = (VISO*R1 + VSS*R2) / (R1 + R2). The sampled voltage VISO_FB is applied to the negative input of error amplifier EA. Error amplifier EA compares and amplifies the sampled voltage VISO_FB and the reference voltage Vref to obtain the error signal Vea. Comparator CMP compares the error signal Vea with a triangular wave signal provided by a triangular wave generator (not shown) to generate a duty cycle adjustable control signal, such as a periodic rectangular wave PWM signal. When the sampled voltage VISO_FB is detected to be higher than the reference voltage Vref, the duty cycle of the PWM control signal decreases to reduce the on-time of the switch drive circuit 11, causing the voltage difference VISO-VSS to decrease. Conversely, when the sampled voltage VISO_FB is detected to be lower than the reference voltage Vref, the duty cycle of the PWM control signal increases to increase the on-time of the switch drive circuit 11, causing the voltage difference VISO-VSS to increase. The entire process is a voltage negative feedback control process, which ultimately achieves a stable output of the voltage difference VISO-VSS.

[0100] Combination Figure 6 and Figure 13 As shown, the output of the secondary soft-start circuit 18 is connected to the positive input of the error amplifier EA to provide a soft-start voltage Vsoft as a reference voltage Vref to the feedback circuit 14 during the soft-start process. When the voltage difference VISO-VSS is below the undervoltage protection threshold, the error amplifier EA does not operate, and the secondary soft-start circuit 18 allows the soft-start voltage Vsoft to follow the voltage difference VISO-VSS. When the voltage difference VISO-VSS reaches the undervoltage protection threshold, the secondary soft-start circuit 18 can disconnect from following the voltage difference VISO-VSS and instead allow the soft-start voltage Vsoft to change based on the status indication signal ESOFT_OK. If the status indication signal ESOFT_OK is 0, the secondary soft-start circuit 18 can slowly increase the soft-start voltage Vsoft to the first voltage threshold VREF1, achieving the first stage of soft-start. If the status indication signal ESOFT_OK is 1, the secondary soft-start circuit 18 can slowly increase the soft-start voltage Vsoft from the first voltage threshold VREF1 to the second voltage threshold VREF2, achieving the second stage of soft-start. In this way, it can be ensured that when the voltage difference VISO-VSS is less than the target voltage difference, the first voltage difference VGND-VSS and the second voltage difference VISO-VGND will not exceed the preset value, thus avoiding damage to the subsequent circuits.

[0101] Figure 14 A circuit diagram of a low-dropout linear regulator circuit according to some embodiments of the present disclosure is shown. Figure 14The LDO circuit shown is a sink-type LDO circuit.

[0102] As Figure 14 shown, the reference voltage VREF of this sink-type LDO circuit is obtained by resistors R5 and R6 dividing the voltage difference between VCC and VSS. The reference voltage VREF changes following the voltage difference between VCC and VSS. The feedback voltage VFB is obtained by resistors R3 and R4 dividing the voltage difference between VCC and VOUT. The two ends of the load capacitor CL are respectively connected to the output voltage VOUT and VCC. This sink-type LDO circuit has the ability to respond quickly to changes in VCC and generates an output voltage VOUT that is in a fixed ratio to VCC.

[0103] Resistor R1 and transistors MP2, MP3, MP4, MP5 form a current mirror to provide the bias current Ibias1 for the sink-type LDO circuit. Transistors MN2, MN3, MN8, MN9, MN12 form a current mirror with this current source. The aspect ratios of the transistors MN2, MN3, MN8, MN9, MN12 can be 1:2:1:1:2.

[0104] Transistors MN3, MN4, MN5, MP7, MP8 form a first operational amplifier, whose positive input is the reference voltage VREF, the negative input is connected to the feedback voltage VFB, and forms a negative feedback with transistors MP19, MN14, MN15, resistors R3, R4 to regulate the output voltage.

[0105] Transistor MN15 is a power transistor, and MN14 and MN15 form a current mirror. MN14 provides a bias voltage for the gate of MN15 during normal operation of the LDO to ensure the normal function of the LDO circuit, and limits the maximum current of the LDO circuit by a certain ratio to provide overcurrent protection for the LDO and prevent damage to the circuit caused by excessive current. In one embodiment, the aspect ratios of the transistors MN14 and MN15 can be 1:100.

[0106] When VREF > VFB, the gate voltage of MP19 increases, making the conduction ability of MP19 weaken, the branch current flowing through MP15, MP19 and MN14 decreases, the voltage V2 drops, the conduction ability of MN15 weakens, and VOUT increases. Conversely, when VREF < VFB, the gate voltage of MP19 decreases, making the conduction ability of MP19 increase, the branch current flowing through MP15, MP19 and MN14 increases, the voltage V2 rises, the conduction ability of MN15 increases, and VOUT decreases.

[0107] The transistors MN6, MN7, MN8, MP10, MP11, MN9, MP12, MN18, MN11, MN19, and the capacitor C2 constitute a frequency compensation circuit. The MN6, MN7, MN8, MP10, MP11 constitute a second operational amplifier. The gates of MN18, MN19 are connected together, and their sources are connected to the two inputs of the second operational amplifier respectively, to ensure that the gate-source voltages of MN18, MN19 are equal, i.e. MN18 VGS MN19 The gate of MN11 is connected to the gate of the power transistor MN15, constituting a current mirror, thereby mirroring the load current. With this arrangement, the output impedance of MN19 follows the load current variation, and a zero point following the positive variation of the load current is generated in the loop, constituting a zero-pole following compensation structure, ensuring the loop stability in the entire load current variation range, and avoiding the circuit from oscillating.

[0108] Figure 15 and Figure 16 A schematic block diagram of a multi-output isolated power supply chip according to some embodiments of the present disclosure is shown.

[0109] As shown in Figure 15 , the multi-output isolated power supply chip includes a multi-output isolated power supply 300 as described in Figure 3 . The chip is composed of two die packages. The first die 151 includes the switch driving circuit 11. The first die 151 also includes an input voltage pin for receiving an input voltage VDD and a ground pin GND1. The second die 152 includes the power transformer T1, the rectifier circuit 12, and the output unit 13. The second die 152 also includes output voltage pins for outputting voltage V1+ and V1-, and a ground pin GND2. The output of the LDO2 is connected to the ground pin GND2. It should be understood that the power transformer T1 can also be fabricated on the first die 151.

[0110] As shown in Figure 16 , the multi-output isolated power supply chip includes a multi-output isolated power supply 300 as described in Figure 2A multiple output isolated power supply 200 is described. The chip is composed of two die packages. The first die 151 includes the switch driving circuit 11 and a portion of the isolator 15, such as the demodulation circuit RX. The first die 151 also includes an input voltage pin for receiving the input voltage VDD and a ground pin GND1. The second die 152 includes the power transformer T1, the rectification circuit 12, the output unit 13, the feedback circuit 14, and a portion of the isolator 15, such as the modulation circuit TX and the signal transformer. The second die 152 also includes output voltage pins for outputting the voltages V1+ and V1- and a ground pin GND2. The output of the LDO2 is connected to the ground pin GND2. It should be understood that the power transformer T1 and the signal transformer can also be fabricated on the first die 151.

[0111] It should be understood that the packaging of the multiple output isolated power supply chip described in connection with Figure 15 and Figure 16 is merely used as an example and does not limit the scope of the present disclosure in any way. The multiple output isolated power supply according to embodiments of the present disclosure can take any appropriate chip packaging form.

[0112] The above has described embodiments of the present disclosure, the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes are obvious to those skilled in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, practical application, or improvement of technology in the market, or to enable other ordinary skilled in the art to understand the embodiments disclosed herein.

Claims

1. A multi-output isolated power supply, comprising: a power transformer including a single primary winding and a single secondary winding; a switch driving circuit coupled to the primary winding and configured to output a driving voltage to the primary winding based on an input voltage; a rectifying circuit coupled to the secondary winding and configured to rectify a voltage across the secondary winding to output a first direct current voltage at a first rectifying voltage output and a second direct current voltage at a second rectifying voltage output, the first direct current voltage being higher than the second direct current voltage; and an output unit coupled to the first rectifying voltage output and the second rectifying voltage output, the output unit including one or more low dropout linear regulator circuits, an output of a predetermined low dropout linear regulator circuit among the one or more low dropout linear regulator circuits being coupled to a secondary circuit ground, and the output unit being configured to output at least one positive voltage and at least one negative voltage with reference to a voltage at the output of the predetermined low dropout linear regulator circuit.

2. The multi-output isolated power supply of claim 1, wherein the one or more low dropout linear regulator circuits include a first low dropout linear regulator circuit, two inputs of the first low dropout linear regulator circuit being coupled to the first rectifying voltage output and the second rectifying voltage output respectively to receive the first direct current voltage and the second direct current voltage.

3. The multi-output isolated power supply of claim 2, wherein an output of the first low dropout linear regulator circuit is coupled to the secondary circuit ground to make the first low dropout linear regulator circuit as the predetermined low dropout linear regulator circuit; wherein the output unit further includes a first output coupled to the first rectifying voltage output to output the first direct current voltage as the at least one positive voltage, and a second output coupled to the second rectifying voltage output to output the second direct current voltage as the at least one negative voltage; and wherein the multi-output isolated power supply further includes a feedback circuit coupled to the first rectifying voltage output and the second rectifying voltage output and configured to generate a control signal based on a sampling voltage between the first direct current voltage and the second direct current voltage and a reference voltage, and an isolator configured to transmit the control signal to the switch driving circuit to control a turn-on / off state of the switch driving circuit.

4. The multi-output isolated power supply of claim 2, wherein the output unit further includes a second low dropout linear regulator circuit, one input of the second low dropout linear regulator circuit being coupled to an output of the first low dropout linear regulator circuit, and another input of the second low dropout linear regulator circuit being coupled to the second rectifying voltage output. ​ ​ 5. The multiple output isolated power supply of claim 4, wherein the output terminal of the second low dropout linear regulator circuit is coupled to the secondary side circuit ground to make the second low dropout linear regulator circuit as the predetermined low dropout linear regulator circuit; wherein the output unit further comprises a first output terminal coupled to the output terminal of the first low dropout linear regulator circuit to output the voltage at the output terminal of the first low dropout linear regulator circuit as the at least one positive voltage, and a second output terminal coupled to the second rectified voltage output terminal to output the second direct current voltage as the at least one negative voltage.

6. The multiple output isolated power supply of claim 4, wherein the output terminal of the second low dropout linear regulator circuit is coupled to the secondary side circuit ground to make the second low dropout linear regulator circuit as the predetermined low dropout linear regulator circuit; wherein the output unit further comprises a first output terminal coupled to the first rectified voltage output terminal, a second output terminal coupled to the output terminal of the first low dropout linear regulator circuit to output the first direct current voltage and the voltage at the output terminal of the first low dropout linear regulator circuit as the at least one positive voltage, and a third output terminal coupled to the second rectified voltage output terminal to output the second direct current voltage as the at least one negative voltage; and wherein the multiple output isolated power supply further comprises a feedback circuit coupled to the first rectified voltage output terminal and the second rectified voltage output terminal and configured to generate a control signal based on a sampled voltage between the first direct current voltage and the second direct current voltage and a reference voltage, and an isolator configured to transmit the control signal to the switch driving circuit to control the on-off state of the switch driving circuit.

7. The multiple output isolated power supply of claim 4, wherein the output terminal of the first low dropout linear regulator circuit is coupled to the secondary side circuit ground to make the first low dropout linear regulator circuit as the predetermined low dropout linear regulator circuit; wherein the output unit further comprises a first output terminal coupled to the first rectified voltage output terminal to output the first direct current voltage as the at least one positive voltage, a second output terminal coupled to the output terminal of the second low dropout linear regulator circuit, and a third output terminal coupled to the second rectified voltage output terminal to output the voltage at the output terminal of the second low dropout linear regulator circuit and the second direct current voltage as the at least one negative voltage; and wherein the multi-output isolated power supply further comprises a feedback circuit coupled to the first rectified voltage output and the second rectified voltage output and configured to generate a control signal based on a sampled voltage between the first DC voltage and the second DC voltage and a reference voltage, and an isolator configured to transmit the control signal to the switch driving circuit across an isolation barrier to control a state of the switch driving circuit.

8. The multi-output isolated power supply of claim 2, wherein an output of the first low-dropout linear regulator circuit is coupled to the secondary-side circuit ground to cause the first low-dropout linear regulator circuit to function as the predetermined low-dropout linear regulator circuit. wherein the output unit further comprises a first output coupled to the first rectified voltage output to output the first DC voltage as the at least one positive voltage and a second output coupled to the second rectified voltage output to output the second DC voltage as the at least one negative voltage; wherein the multi-output isolated power supply further comprises: a multiplexer having a first input, a second input, and a selector output coupled to the switch driving circuit, the multiplexer configured to: in response to a voltage difference between the first DC voltage and the second DC voltage being below an under-voltage protection threshold, pass a signal at the first input to the selector output, and in response to the voltage difference reaching the under-voltage protection threshold, pass a signal at the second input to the selector output; a primary-side soft-start circuit having an output coupled to the first input and configured to: in response to the voltage difference being below the under-voltage protection threshold, output a primary-side soft-start signal having a duty cycle that increases from a predetermined value, and in response to the voltage difference reaching the under-voltage protection threshold, cease outputting the primary-side soft-start signal; a feedback circuit coupled to the first rectified voltage output and the second rectified voltage output and configured to generate a control signal based on a sampled voltage and a reference voltage, and an isolator configured to transmit the control signal to the second input of the multiplexer across an isolation barrier; and a secondary-side soft-start circuit coupled to the feedback circuit and configured to provide a soft-start voltage to the feedback circuit as the reference voltage.

9. The multi-output isolated power supply of claim 8, wherein the secondary-side soft-start circuit is further configured to: in response to the voltage difference being below the under-voltage protection threshold, cause the soft-start voltage to vary in proportion to the voltage difference; and in response to the voltage difference reaching the under-voltage protection threshold, cause the soft-start voltage to vary in a plurality of soft-start stages.

10. The multi-output isolated power supply of claim 9, wherein the secondary-side soft-start circuit is further configured to: in response to the voltage difference reaching the under-voltage protection threshold, causing the soft-start voltage to change based on a status indication signal, wherein the status indication signal is used to indicate whether the first low-dropout linear regulator circuit is functioning properly and whether a ratio of a first voltage difference and a second voltage difference is within a predetermined range, the first voltage difference being a difference between the second DC voltage and a voltage at an output of the first low-dropout linear regulator circuit, the second voltage difference being a difference between the first DC voltage and the voltage at the output of the first low-dropout linear regulator circuit.

11. The multi-output isolated power supply of claim 10, wherein the secondary-side soft-start circuit is further configured to: in response to the status indication signal indicating that the first low-dropout linear regulator circuit is not functioning properly or that the ratio of the first voltage difference and the second voltage difference is outside the predetermined range, causing the soft-start voltage to increase to a first voltage threshold in a first soft-start phase; and in response to the status indication signal indicating that the first low-dropout linear regulator circuit is functioning properly and that the ratio of the first voltage difference and the second voltage difference is within the predetermined range, causing the soft-start voltage to increase from the first voltage threshold to a second voltage threshold in a second soft-start phase.

12. The multi-output isolated power supply of claim 11, wherein the output unit further comprises: a first switch unit coupled between the first output and an output of the first low-dropout linear regulator circuit and configured to switch between a conductive state and a non-conductive state; a first comparison unit coupled to the first switch unit and configured to switch the first switch unit to the conductive state in response to the ratio of the first voltage difference and the second voltage difference being below a first target value; a second switch unit coupled between the output of the first low-dropout linear regulator circuit and the second output and configured to switch between a conductive state and a non-conductive state; and a second comparison unit coupled to the second switch unit and configured to switch the second switch unit to the conductive state in response to the ratio of the first voltage difference and the second voltage difference being above a second target value, wherein the second target value is greater than or equal to the first target value.

13. The multi-output isolated power supply of claim 3, 6, 7, or 8, wherein the feedback circuit comprises: a comparator having a negative input, a positive input, and an output, the positive input receiving the reference voltage, the output of the comparator being coupled to the isolator to output the control signal; and a sampling circuit comprising a first resistor, a second resistor, and a third resistor connected in series between the second rectified voltage output and the first rectified voltage output, a first node between the first resistor and the second resistor being coupled to the negative input of the comparator via a low-side switch, a second node between the second resistor and the third resistor being coupled to the negative input of the comparator via a high-side switch, ​ ​ wherein in response to the voltage at the second node being below the reference voltage, the comparator outputs the control signal that causes the power transformer to operate, the high-side switch is off, and the low-side switch is on; and wherein in response to the voltage at the first node being above the reference voltage, the comparator outputs the control signal that causes the power transformer to stop operating, the high-side switch is on, and the low-side switch is off.

14. The multiple output isolated power supply of claim 3, 6, 7, or 8, wherein the feedback circuit comprises: a sampling circuit comprising a first resistor and a second resistor connected in series between the second rectified voltage output and the first rectified voltage output; an error amplifier having a positive input that receives the reference voltage, a negative input coupled to a sampling node between the first resistor and the second resistor, and an amplifier output; and a comparator comprising a first input coupled to the amplifier output, a second input that receives a triangular wave signal, and an output coupled to the isolator to output the control signal.

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