Silicon controlled rectifier impact resistance testing method and system

Abstract

The invention relates to the technical field of silicon controlled rectifier testing, in particular to a silicon controlled rectifier impact resistance testing method and system. The method comprises the following steps: acquiring a zero-crossing signal monitoring moment and a driving signal monitoring moment, acquiring delay duration controlled by a relay each time, and synchronously acquiring environment monitoring data at the monitoring moments; calculating a time extension error coefficient based on the delay duration, calculating an environment error coefficient based on the environment monitoring data, and forming a coefficient vector; collecting all coefficient vectors, calculating a time delay controllable coefficient of each time of relay control, constructing a two-dimensional sample space, and calculating error influence expressions corresponding to different time delays; carrying out statistical analysis on the error influence performance data of all the silicon controlled elements, and determining an error influence performance threshold value; and comparing the error influence performance at each monitoring moment with an error influence performance threshold value, and evaluating the impact resistance of the silicon controlled element. The accuracy of the impact resistance test result of the silicon controlled rectifier is remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of thyristor testing technology, and specifically to a method and system for testing the impact resistance of thyristors. Background Technology

[0002] Thyristor surge resistance testing is a core test for evaluating the stable operation of thyristor components under transient voltage and current surges. It is widely used in power electronics, industrial control, and other fields, and is directly related to the operational safety and service life of equipment. The core requirement of the test is to simulate transient surge scenarios that may occur in actual working conditions, such as lightning strikes and circuit switching, and accurately obtain key parameters of the thyristor, such as trigger voltage stability, response time consistency, and holding current reliability.

[0003] Traditional testing often uses a switching scheme with multiple thyristors and optocouplers, which is prone to short circuit risks due to the influence of component parameters. Although the improved scheme replaces some thyristors with relays, the accuracy and reliability of the test results are insufficient due to factors such as temperature, software and hardware delays, and contact oxidation. Summary of the Invention

[0004] To address the technical problem of inaccurate impact resistance test results for silicon controlled rectifiers (SCRs), the present invention aims to provide a method and system for testing the impact resistance of SCRs. The specific technical solution adopted is as follows: In a first aspect, embodiments of the present invention provide a method for testing the impact resistance of a silicon controlled rectifier (SCR), the method comprising: The zero-crossing signal monitoring time and the drive signal monitoring time are obtained. Based on the zero-crossing signal monitoring time and the drive signal monitoring time, the delay time of each relay control is obtained, and the environmental monitoring data at the monitoring time is obtained synchronously. Calculate the time extension error coefficient based on the delay duration, calculate the environmental error coefficient based on the environmental monitoring data, and combine the extension error coefficient and the environmental error coefficient into a coefficient vector. Collect all the coefficient vectors, calculate the controllable time delay coefficient for each relay control, construct a two-dimensional sample space containing the controllable time delay coefficient, and calculate the error impact performance corresponding to different time delays; The impact performance of the error at each monitoring time is compared with the error impact threshold to evaluate the shock resistance of the thyristor.

[0005] In some embodiments, obtaining the zero-crossing signal monitoring time and the drive signal monitoring time, and obtaining the delay duration of each relay control based on the zero-crossing signal monitoring time and the drive signal monitoring time, includes: The zero-crossing point of the AC current is detected by the zero-crossing detection circuit and a pulse signal is output. The zero-crossing signal monitoring time is determined based on the pulse signal, and the driving signal monitoring time is determined based on the relay driving signal. The time difference between the zero-crossing signal monitoring time and the drive signal monitoring time is read using an oscilloscope, and the time difference is used as the delay duration for the corresponding relay control.

[0006] In some embodiments, calculating the time extension error coefficient based on the delay duration includes: Set a preset number of relay control operations and record the delay time corresponding to each relay control operation. Calculate the average delay duration corresponding to the preset number of relay controls; For each relay control, calculate the deviation of the delay duration of the relay control from the average value; The deviation is normalized to obtain the time extension error coefficient corresponding to each relay control.

[0007] In some embodiments, calculating the environmental error coefficient based on the environmental monitoring data includes: Acquire environmental monitoring data at the time of zero-crossing signal monitoring corresponding to each relay control, and environmental monitoring data at the time of drive signal monitoring corresponding to the relay control; Calculate the numerical difference of the same environmental factor in the environmental monitoring data at the zero-crossing signal monitoring time and the drive signal monitoring time, respectively; The numerical differences corresponding to each type of environmental factor are standardized, and the mean of the numerical differences after standardization of all types of environmental factors is calculated. The mean is then determined as the environmental error coefficient for the corresponding relay control.

[0008] In some embodiments, forming a coefficient vector from the extension error coefficient and the environmental error coefficient includes: For each relay control, determine the corresponding time delay error coefficient and environmental error coefficient for the relay control; The time extension error coefficient corresponding to the relay control is taken as the first element, and the environmental error coefficient corresponding to the relay control is taken as the second element. The first element and the second element are combined in a preset order to form the coefficient vector corresponding to the relay control.

[0009] In some embodiments, collecting all the coefficient vectors and calculating the time delay controllable coefficient for each relay control includes: Collect the coefficient vector corresponding to each relay control, forming a set containing all coefficient vectors; Analyze the overall differences among all coefficient vectors and determine the degree of correlation between the environmental error coefficient and the time extension error coefficient; Based on the overall differences and the degree of correlation, the controllable time delay coefficient corresponding to each relay control is calculated.

[0010] In some embodiments, constructing a two-dimensional sample space containing the controllable time delay coefficient and calculating the error impact performance corresponding to different time delays includes: All time delay controllable coefficients are classified according to the relay control sequence number. A two-dimensional sample space is constructed based on the classified time delay controllable coefficients. All the time delay controllable coefficients are marked as sample points in the two-dimensional sample space. For each time delay value, extract all time delay controllable coefficients before that time delay value; Calculate the ratio of the extracted time delay controllable coefficient to the corresponding relay control sequence number; The error impact corresponding to the time delay value is determined based on the ratio.

[0011] In some embodiments, the statistical analysis of the error impact performance data of all thyristor elements, and the determination of the error impact performance threshold, include: Collect error impact data for all thyristor components at each monitoring time; Calculate the cumulative percentage of all errors affecting performance data, and determine the threshold value corresponding to the cumulative percentage; The error impact performance data corresponding to the aforementioned threshold value is determined as the threshold value for error impact performance.

[0012] In some embodiments, comparing the error impact performance at each monitoring time with an error impact performance threshold to evaluate the shock resistance of the thyristor includes: Test results with error impact less than the aforementioned error impact threshold are selected as valid test data for the impact resistance of the thyristor element. For test results where the error impact performance is greater than or equal to the error impact performance threshold, a secondary test is performed on the thyristor element. If the error impact of the second test is still greater than or equal to the error impact threshold, the corresponding thyristor element will be recycled. If the error impact of the secondary detection is less than the error impact threshold, then the secondary detection result will be included in the valid detection data. The impact resistance test results of the silicon controlled rectifier (SCR) element are determined based on all the valid test data.

[0013] Secondly, embodiments of the present invention provide a thyristor impact resistance testing system, the system comprising the following modules: The acquisition module is used to acquire the zero-crossing signal monitoring time and the drive signal monitoring time, acquire the delay duration of each relay control based on the zero-crossing signal monitoring time and the drive signal monitoring time, and synchronously acquire environmental monitoring data at the monitoring time. The calculation module is used to calculate the time extension error coefficient based on the delay duration, calculate the environmental error coefficient based on the environmental monitoring data, and combine the time extension error coefficient and the environmental error coefficient into a coefficient vector; A construction module is used to collect all the coefficient vectors, calculate the controllable time delay coefficient for each relay control, construct a two-dimensional sample space containing the controllable time delay coefficient, and calculate the error impact performance corresponding to different time delays. The evaluation module is used to compare the error impact performance at each monitoring time with the error impact performance threshold to evaluate the shock resistance of the thyristor.

[0014] Thirdly, embodiments of the present invention provide an electronic device, including a memory and a processor, wherein the memory stores executable code, and when the processor executes the executable code, it implements the various possible implementations of the first aspect.

[0015] Fourthly, embodiments of the present invention provide a computer program product comprising: computer program code, which, when executed on a computer, causes the computer to perform the method described in the first aspect or any possible implementation thereof.

[0016] Fifthly, embodiments of the present invention provide a computer-readable storage medium having a computer program stored thereon, which, when executed in a computer, causes the computer to perform the various possible implementations of the first aspect.

[0017] The embodiments of the present invention have at least the following beneficial effects: This invention accurately obtains the relay control delay time by collecting zero-crossing signals, drive signal monitoring times, and environmental monitoring data in stages. Then, through error coefficient calculation, coefficient vector construction, and time delay controllability coefficient analysis, it quantifies the error impact of different time delays using a two-dimensional sample space. Statistical analysis determines reasonable thresholds to filter valid data. This process systematically distinguishes between environmental fluctuations and abnormal factors that interfere with the test, corrects errors caused by temperature, contact oxidation, etc., significantly improves the accuracy of timing control and data reliability, and ultimately achieves accurate assessment of the impact resistance of thyristors, providing a scientific basis for component performance determination. Attached Figure Description

[0018] To more clearly illustrate the technical solutions and advantages in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A flowchart illustrating a method for testing the impact resistance of a thyristor according to an embodiment of the present invention; Figure 2 A system block diagram of a thyristor impact resistance testing system provided in one embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of a computer device provided in one embodiment of the present invention. Detailed Implementation

[0020] To further illustrate the technical means and effects of the present invention in achieving its intended purpose, the following detailed description, in conjunction with the accompanying drawings and preferred embodiments, details the specific implementation, structure, features, and effects of a thyristor impact resistance testing method and system proposed according to the present invention.

[0021] In the following description, different "one embodiment" or "another embodiment" do not necessarily refer to the same embodiment. Furthermore, specific features, structures, or characteristics in one or more embodiments may be combined in any suitable form.

[0022] In the description of the embodiments of the present invention, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of the present invention, "multiple" means two or more.

[0023] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as implying or suggesting relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0025] The embodiments of the present invention will now be described with reference to the accompanying drawings. Those skilled in the art will recognize that, with technological advancements and the emergence of new scenarios, the technical solutions provided by the embodiments of the present invention are also applicable to similar technical problems.

[0026] The following description, in conjunction with the accompanying drawings, details the specific scheme of the thyristor impact resistance testing method and system provided by this invention.

[0027] Example 1: Please see Figure 1 The diagram illustrates a flowchart of a method for testing the impact resistance of a thyristor according to an embodiment of the present invention. The method includes the following steps: S10. Obtain the zero-crossing signal monitoring time and the drive signal monitoring time, obtain the delay duration of each relay control based on the zero-crossing signal monitoring time and the drive signal monitoring time, and simultaneously obtain the environmental monitoring data at the monitoring time.

[0028] The zero-crossing signal monitoring time refers to the specific point in time when the zero-crossing detection circuit identifies the AC zero-crossing point, that is, the instant the voltage is zero and outputs a pulse signal. The zero-crossing detection circuit is a dedicated circuit specifically designed to capture the AC zero-crossing point. The drive signal monitoring time is the specific point in time when the relay receives the drive signal, that is, the electrical signal that controls its on / off state, and begins to operate. Specifically, first connect the output terminal of the zero-crossing detection circuit to oscilloscope channel 1, and capture the pulse signal output by the zero-crossing detection circuit through oscilloscope channel 1 to lock the zero-crossing signal monitoring time. Next, connect the relay drive signal terminal to oscilloscope channel 2 and determine the drive signal monitoring time by capturing the rising edge of the drive signal. The delay duration is the time difference between the zero-crossing signal monitoring time and the drive signal monitoring time during the same relay control process. This time difference can be directly read using the oscilloscope's measurement function to obtain the delay duration for each relay control. Environmental monitoring data consists of environmental parameters that affect test accuracy, including environmental factors such as temperature, humidity, and air pressure, which are collected simultaneously using an environmental parameter monitoring device to ensure a one-to-one correspondence between environmental data and time data.

[0029] S11. Calculate the time extension error coefficient based on the delay duration, calculate the environmental error coefficient based on the environmental monitoring data, and combine the extension error coefficient and the environmental error coefficient into a coefficient vector.

[0030] Specifically, first, a preset number of relay control operations are performed, and the delay duration for each operation is recorded. Then, the average delay duration within the preset number of operations is calculated, which is the average difference in time extension between multiple relay control operations. Next, for each relay control operation, the deviation of its delay duration from this average is calculated. Specifically, the preset number of operations can be 10, or it can be adjusted according to testing requirements. Furthermore, the... Time delay error coefficient during secondary relay control The calculation formula is as follows: in, Indicates the first Monitoring time of drive signal during secondary relay control Indicates the first Zero-crossing signal monitoring time during secondary relay control This represents the average of all delay times for the relay control of the preset number of times the thyristor element is used. Time delay error coefficient. It is a parameter that quantifies the degree to which the delay time of each relay control deviates from the average delay time, and is used to reflect the stability of the delay time.

[0031] Furthermore, first, acquire various environmental monitoring data at the zero-crossing signal monitoring time and drive signal monitoring time corresponding to each relay control. Specifically, the environmental monitoring data can include multiple environmental factors, such as temperature, humidity, and air pressure. Then, calculate the numerical difference of the same environmental factor at the zero-crossing signal monitoring time and drive signal monitoring time. Further, the environmental error coefficient for the i-th relay control... The calculation formula is as follows: in, Indicates the first The first time the drive signal monitoring moment is during the secondary relay control The values ​​of each environmental factor, Indicates the first The zero-crossing signal monitoring time during secondary relay control is the first The values ​​of each environmental factor, This indicates the number and types of environmental factors involved in multiple relay controls of the thyristor. Environmental error coefficient. It is a parameter that measures the impact of changes in environmental factors on the test between the zero-crossing signal monitoring time and the drive signal monitoring time.

[0032] Furthermore, by integrating the time extension error coefficient and environmental error coefficient of the same relay control, the time extension error coefficient is... As the first element, the environmental error coefficient As the second element; combined according to the preset order of "first element first, second element last", to form a coefficient vector. : S12. Collect all the coefficient vectors, calculate the controllable time delay coefficient for each relay control, construct a two-dimensional sample space containing the controllable time delay coefficient, and calculate the error impact performance corresponding to different time delays.

[0033] Specifically, first collect the coefficient vectors corresponding to all relay controls. This forms a complete set of coefficient vectors; then, the overall differences between all coefficient vectors are analyzed to reflect the relay control error, and the time extension error coefficient is determined through correlation analysis. Environmental error coefficient The degree of correlation is used to reflect the effect of control in reducing errors; Furthermore, based on the overall differences and correlations, the controllable time delay coefficient for each relay control is obtained through weighted calculation. Specifically, the first... The time delay controllability coefficient of a thyristor device The calculation formula is: in, The total number of coefficient vectors Indicates the first Time delay error coefficient during secondary relay control Indicates the first Time delay error coefficient during secondary relay control Indicates the first Environmental error coefficient during secondary relay control. Indicates the first Environmental error coefficient during secondary relay control. Indicates the first The coefficient vector during secondary relay control. Indicates the first The coefficient vector during secondary relay control. The difference indicates the variation in time delay of the thyristor element during relay control. The smaller the difference, the better the stability of the control weakening of the entire thyristor element and the more obvious the error weakening effect.

[0034] Furthermore, the two-dimensional sample space is a coordinate system used to represent the distribution characteristics of the controllable time delay coefficients, which can intuitively show the distribution patterns of different controllable time delay coefficients. First, all controllable time delay coefficients are numbered according to the relay control sequence number, i.e., the order in which the relay control operations are performed. Categorize them; based on the controllable time delay coefficient A two-dimensional coordinate system is constructed with the value of [value] on the horizontal axis and the corresponding number of collected data points on the vertical axis; all time delay controllable coefficients are [value]. As independent sample points, they are labeled in this coordinate system to form a complete two-dimensional sample space.

[0035] Furthermore, errors affect performance. The calculation formula is: in, This represents the controllable time delay coefficients from sequence number 1 to k. This represents the index value before the time delay value k. This indicates the index of the current time delay value. This represents the ratio of each extracted time delay controllable coefficient to the corresponding relay control sequence number. A larger ratio indicates a more significant relay control error before that value. Finally, the average of all ratios is taken and normalized to obtain the error impact corresponding to that time delay value. Errors affect performance It is a parameter that quantifies the impact of different time delay values ​​on the accuracy of test results.

[0036] S13. Compare the error impact performance at each monitoring time with the error impact performance threshold to evaluate the shock resistance of the thyristor element.

[0037] Specifically, first, collect error impact data for all SCR components at each monitoring time; perform normal distribution statistical analysis on the error impact data, and calculate the cumulative percentage in ascending order of values; specifically, the cumulative percentage threshold can be set to 0.903, but can be adjusted according to actual needs. Test results with a cumulative percentage greater than 0.903 are considered unreliable; error impact threshold. The calculation formula is as follows: In the formula, The threshold representing the impact of error on performance, i.e., the specific value used to distinguish between reliable and unreliable test results; This indicates the impact of the error on the performance corresponding to the k-th time delay value. This represents the total number of values ​​that can be selected for the time delay. This represents the number of sampled data points acquired at the time corresponding to the k-th time delay value; where, for The normalization function is also known as the standardization function.

[0038] Specifically, when according to Accumulate in ascending order At this point, a critical point will appear: the accumulated result is exactly ≤0.903. If a larger value is added next... Accumulating these values ​​will result in a value exceeding 0.903. At this point, the critical point corresponds to... The error affects the performance threshold. The cumulative percentage threshold is set at 0.903, meaning that data with a cumulative percentage ≤ 0.903 is considered reliable. Therefore, all data less than 0.903 is considered reliable. of Both the data and their corresponding test results are considered reliable data, while data greater than or equal to... of The corresponding test results are unreliable data with a cumulative proportion exceeding 0.903, and need to be excluded or retested.

[0039] The impact resistance of a thyristor refers to its ability to maintain stable operation under instantaneous voltage and current surges, and is a core performance indicator of the thyristor. In practice, the error impact at each monitoring moment is compared with a set error impact threshold. Test results with an error impact less than the threshold are selected as valid impact resistance data, as these results are less affected by error interference. Thyristors with error impact greater than or equal to the threshold undergo secondary testing to eliminate the influence of random errors. If the secondary test result is still greater than or equal to the threshold, it indicates that the component is affected by abnormal factors and cannot be accurately assessed, requiring recycling. If the secondary test result is less than the threshold, it is included in the valid test data. Finally, based on all valid test data, key parameters such as the trigger voltage stability and response time consistency of the thyristor are comprehensively analyzed to determine the final impact resistance test result.

[0040] Example 2: Please see Figure 2 This illustrates a thyristor impact resistance testing system provided in an embodiment of the present invention, the system comprising: The acquisition module 20 is used to acquire the zero-crossing signal monitoring time and the drive signal monitoring time, acquire the delay duration of each relay control based on the zero-crossing signal monitoring time and the drive signal monitoring time, and synchronously acquire environmental monitoring data at the monitoring time. Calculation module 21 is used to calculate the time extension error coefficient based on the delay duration, calculate the environmental error coefficient based on the environmental monitoring data, and combine the extension error coefficient and the environmental error coefficient into a coefficient vector; Module 22 is used to collect all the coefficient vectors, calculate the controllable time delay coefficient for each relay control, construct a two-dimensional sample space containing the controllable time delay coefficient, and calculate the error impact performance corresponding to different time delays. Evaluation module 23 is used to compare the error impact performance at each monitoring time with the error impact performance threshold to evaluate the shock resistance of the thyristor element.

[0041] Alternatively, the transmission medium may be a wired link, such as, but not limited to, coaxial cable, fiber optic cable and digital subscriber line, or a wireless link, such as, but not limited to, wireless Fidelity (WIFI), Bluetooth and mobile device networks.

[0042] It should be noted that the device provided in the above embodiments is only an example of the division of the above functional modules. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the computer device can be divided into different functional modules to complete all or part of the functions described above.

[0043] Figure 3 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. For example, as shown... Figure 3 As shown, the computer device 30 includes: a memory 31, a processor 32, and a computer program 33 stored in the memory 31 and running on the processor 32, wherein when the processor 32 executes the computer program 33, the computer device can perform any of the aforementioned thyristor impact resistance test methods.

[0044] Furthermore, embodiments of the present invention also protect an apparatus that may include a memory and a processor, wherein the memory stores executable program code, and the processor is used to call and execute the executable program code to perform a thyristor impact resistance testing method provided in embodiments of the present invention.

[0045] In this embodiment of the invention, the device can be divided into functional modules according to the above method example. For example, each module can correspond to a separate function, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware. It should be noted that the module division in this embodiment is illustrative and is only a logical functional division. In actual implementation, there may be other division methods.

[0046] It should be understood that the apparatus provided in this embodiment of the invention is used to perform the above-described method for testing the impact resistance of a thyristor, and therefore can achieve the same effect as the above-described implementation method.

[0047] When using integrated units, the device may include a processing module and a storage module. When applied to a device, the processing module can be used to control and manage the device's operations. The storage module can be used to support the device in executing program code, etc. The processing module may be a processor or a controller, which can implement or execute various exemplary logic blocks, modules, and circuits as described in this disclosure. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of Digital Signal Processing (DSP) and a microprocessor, etc., and the storage module may be a memory.

[0048] In addition, the device provided in the embodiments of the present invention may specifically be a chip, component or module. The chip may include a connected processor and a memory. The memory is used to store instructions. When the processor calls and executes the instructions, the chip can execute the thyristor impact resistance test method provided in the above embodiments.

[0049] This invention also provides a computer-readable storage medium storing computer program code. When the computer program code is run on a computer, the computer executes the aforementioned method steps to implement the thyristor impact resistance testing method provided in the above embodiments.

[0050] This invention also provides a computer program product that, when run on a computer, causes the computer to perform the aforementioned steps to implement the thyristor impact resistance testing method provided in the above embodiments.

[0051] In this invention, the apparatus, computer-readable storage medium, computer program product, or chip provided in the embodiments are all used to execute the corresponding methods described above. Therefore, the beneficial effects they achieve can be referred to the beneficial effects in the corresponding methods described above, and will not be repeated here. Through the above description of the embodiments, those skilled in the art will understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In the embodiments provided by this invention, it should be understood that the disclosed apparatus and method can be implemented in other ways.

[0052] The device embodiments described above are merely illustrative. For example, the division of modules or units is only a logical functional division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0053] It should also be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0054] It should be noted that the order of the above embodiments of the present invention is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. The processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0055] The various embodiments in this specification are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0056] The above content is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the protection scope of the present invention.

Claims

1. A method for testing the impact resistance of a thyristor, characterized in that, The method includes the following steps: The zero-crossing signal monitoring time and the drive signal monitoring time are obtained. Based on the zero-crossing signal monitoring time and the drive signal monitoring time, the delay time of each relay control is obtained, and the environmental monitoring data at the monitoring time is obtained synchronously. Calculate the time extension error coefficient based on the delay duration, calculate the environmental error coefficient based on the environmental monitoring data, and combine the extension error coefficient and the environmental error coefficient into a coefficient vector. Collect all the coefficient vectors, calculate the controllable time delay coefficient for each relay control, construct a two-dimensional sample space containing the controllable time delay coefficient, and calculate the error impact performance corresponding to different time delays; The impact performance of the thyristor element is evaluated by comparing the error impact performance at each monitoring time with the error impact performance threshold.

2. The method for testing the impact resistance of a thyristor according to claim 1, characterized in that, The process of acquiring the zero-crossing signal monitoring time and the drive signal monitoring time, and acquiring the delay duration of each relay control based on the zero-crossing signal monitoring time and the drive signal monitoring time, includes: The zero-crossing point of the AC current is detected by the zero-crossing detection circuit and a pulse signal is output. The zero-crossing signal monitoring time is determined based on the pulse signal, and the driving signal monitoring time is determined based on the relay driving signal. The time difference between the zero-crossing signal monitoring time and the drive signal monitoring time is read using an oscilloscope, and the time difference is used as the delay duration for the corresponding relay control.

3. The method for testing the impact resistance of a thyristor according to claim 1, characterized in that, The calculation of the time extension error coefficient based on the delay duration includes: Set a preset number of relay control operations and record the delay time corresponding to each relay control operation. Calculate the average delay duration corresponding to the preset number of relay controls; For each relay control, calculate the deviation of the delay duration of the relay control from the average value; The deviation is normalized to obtain the time extension error coefficient corresponding to each relay control.

4. The method for testing the impact resistance of a thyristor according to claim 1, characterized in that, The calculation of the environmental error coefficient based on the environmental monitoring data includes: Acquire environmental monitoring data at the time of zero-crossing signal monitoring corresponding to each relay control, and environmental monitoring data at the time of drive signal monitoring corresponding to the relay control; Calculate the numerical difference of the same environmental factor in the environmental monitoring data at the zero-crossing signal monitoring time and the drive signal monitoring time, respectively; The numerical differences corresponding to each type of environmental factor are standardized, and the mean of the numerical differences after standardization of all types of environmental factors is calculated. The mean is then determined as the environmental error coefficient for the corresponding relay control.

5. The method for testing the impact resistance of a thyristor according to claim 1, characterized in that, The step of forming a coefficient vector from the extension error coefficient and the environmental error coefficient includes: For each relay control, determine the corresponding time delay error coefficient and environmental error coefficient for the relay control; The time extension error coefficient corresponding to the relay control is taken as the first element, and the environmental error coefficient corresponding to the relay control is taken as the second element. The first element and the second element are combined in a preset order to form the coefficient vector corresponding to the relay control.

6. The method for testing the impact resistance of a thyristor according to claim 1, characterized in that, The process of collecting all the coefficient vectors and calculating the controllable time delay coefficient for each relay control includes: Collect the coefficient vector corresponding to each relay control, forming a set containing all coefficient vectors; Analyze the overall differences among all coefficient vectors and determine the degree of correlation between the environmental error coefficient and the time extension error coefficient; Based on the overall differences and the degree of correlation, the controllable time delay coefficient corresponding to each relay control is calculated.

7. The method for testing the impact resistance of a thyristor according to claim 1, characterized in that, The construction of a two-dimensional sample space containing the controllable time delay coefficient, and the calculation of the error impact performance corresponding to different time delays, include: All time delay controllable coefficients are classified according to the relay control sequence number. A two-dimensional sample space is constructed based on the classified time delay controllable coefficients. All the time delay controllable coefficients are marked as sample points in the two-dimensional sample space. For each time delay value, extract all time delay controllable coefficients before that time delay value; Calculate the ratio of the extracted time delay controllable coefficient to the corresponding relay control sequence number; The error impact corresponding to the time delay value is determined based on the ratio.

8. The method for testing the impact resistance of a thyristor according to claim 1, characterized in that, The determination of the performance threshold for the impact of the error includes: Collect error impact data for all thyristor components at each monitoring time; Calculate the cumulative percentage of all errors affecting performance data, and determine the threshold value corresponding to the cumulative percentage; The error impact performance data corresponding to the aforementioned threshold value is determined as the threshold value for error impact performance.

9. The method for testing the impact resistance of a thyristor according to claim 1, characterized in that, The comparison of the error impact performance at each monitoring time with the error impact performance threshold to evaluate the shock resistance of the thyristor includes: Test results with error impact less than the aforementioned error impact threshold are selected as valid test data for the impact resistance of the thyristor element. For test results where the error impact performance is greater than or equal to the error impact performance threshold, a secondary test is performed on the thyristor element. If the error impact of the second test is still greater than or equal to the error impact threshold, the corresponding thyristor element will be recycled. If the error impact of the secondary detection is less than the error impact threshold, then the secondary detection result will be included in the valid detection data. The impact resistance test results of the silicon controlled rectifier (SCR) element are determined based on all the valid test data.

10. A thyristor impact resistance testing system, characterized in that, The system includes the following modules: The acquisition module is used to acquire the zero-crossing signal monitoring time and the drive signal monitoring time, acquire the delay duration of each relay control based on the zero-crossing signal monitoring time and the drive signal monitoring time, and synchronously acquire environmental monitoring data at the monitoring time. The calculation module is used to calculate the time extension error coefficient based on the delay duration, calculate the environmental error coefficient based on the environmental monitoring data, and combine the time extension error coefficient and the environmental error coefficient into a coefficient vector; A construction module is used to collect all the coefficient vectors, calculate the controllable time delay coefficient for each relay control, construct a two-dimensional sample space containing the controllable time delay coefficient, and calculate the error impact performance corresponding to different time delays. The evaluation module is used to compare the error impact performance at each monitoring time with the error impact performance threshold to evaluate the shock resistance of the thyristor.

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