A method and system for testing the impact resistance of silicon-controlled rectifiers

Abstract

The present application relates to thyristor testing technical field, specifically to a kind of thyristor impact resistance test method and system.The method includes the following steps: obtaining zero-crossing signal monitoring moment and driving signal monitoring moment, obtain the delay length of each relay control, and synchronously obtain the environmental monitoring data of monitoring moment;Based on the delay length calculation time extension error coefficient, based on environmental monitoring data calculation environmental error coefficient, and form coefficient vector;Collect all coefficient vectors, calculate the time delay controllable coefficient of each relay control, construct two-dimensional sample space, calculate the error influence performance corresponding to different time delay;Statistical analysis is carried out to the error influence performance data of all thyristor elements, and the threshold of error influence performance is determined;The error influence performance of each monitoring moment is compared with error influence performance threshold, and the impact resistance of thyristor element is evaluated.The present application realizes the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of the accuracy of

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of silicon controlled rectifier testing, and in particular to a silicon controlled rectifier impact resistance testing method and system. BACKGROUND

[0002] The silicon controlled rectifier impact resistance testing is a core detection for evaluating the stable working capability of the silicon controlled rectifier under the instantaneous voltage and current impact, is widely used in the fields of power electronics and industrial control, and is directly related to the equipment operation safety and service life. The core requirement of the testing is to simulate the lightning impact and circuit switching instantaneous impact scenes that may occur in the actual working conditions, and to accurately obtain the trigger voltage stability, response time consistency, holding current reliability and other key parameters of the silicon controlled rectifier.

[0003] The traditional testing adopts a switching scheme of multiple silicon controlled rectifiers cooperating with a driving optical coupling, and is easy to cause a short circuit risk due to the element parameter influence; although the improved scheme uses a relay to replace part of the silicon controlled rectifiers, the testing result accuracy and reliability are insufficient due to the influence of factors such as temperature, hardware and software time delay, and contact oxidation. SUMMARY

[0004] In order to solve the technical problem of inaccurate silicon controlled rectifier impact resistance testing result, the purpose of the present application is to provide a silicon controlled rectifier impact resistance testing method and system, and the technical solution adopted is as follows:

[0005] In a first aspect, the present application provides a silicon controlled rectifier impact resistance testing method, which comprises:

[0006] acquiring a zero-crossing signal monitoring time and a driving signal monitoring time, acquiring a delay duration of each relay control based on the zero-crossing signal monitoring time and the driving signal monitoring time, and synchronously acquiring environmental monitoring data of the monitoring time;

[0007] calculating a time extension error coefficient based on the delay duration, calculating an environmental error coefficient based on the environmental monitoring data, and composing a coefficient vector with the extension error coefficient and the environmental error coefficient;

[0008] collecting all the coefficient vectors, calculating a time delay controllable coefficient of each relay control, constructing a two-dimensional sample space containing the time delay controllable coefficient, and calculating error influence performances corresponding to different time delays;

[0009] comparing the error influence performances of each monitoring time with the error influence performance threshold, and evaluating the impact resistance of the silicon controlled rectifier element.

[0010] In some embodiments, the acquiring of the zero-crossing signal monitoring time and the driving signal monitoring time, and the acquiring of the delay duration of each relay control based on the zero-crossing signal monitoring time and the driving signal monitoring time comprises:

[0011] detecting a zero-crossing point of the alternating current through a zero-crossing detection circuit and outputting a pulse signal, determining a zero-crossing signal monitoring time based on the pulse signal, and determining a driving signal monitoring time based on a driving signal of the relay;

[0012] reading a time difference between the zero-crossing signal monitoring time and the driving signal monitoring time by using an oscilloscope, and taking the time difference as a delay duration corresponding to relay control.

[0013] In some embodiments, the calculating a time extension error coefficient based on the delay duration comprises:

[0014] setting a preset number of relay control operations, and recording a delay duration corresponding to each relay control;

[0015] calculating an average value of the delay durations corresponding to the preset number of relay controls;

[0016] for each relay control, calculating a deviation degree of the delay duration of the relay control from the average value;

[0017] normalizing the deviation degree to obtain a time extension error coefficient corresponding to each relay control.

[0018] In some embodiments, the calculating an environment error coefficient based on the environment monitoring data comprises:

[0019] obtaining environment monitoring data of a zero-crossing signal monitoring time corresponding to each relay control and environment monitoring data of a driving signal monitoring time corresponding to the relay control;

[0020] respectively calculating a numerical difference of a same environmental factor in the environment monitoring data between the zero-crossing signal monitoring time and the driving signal monitoring time;

[0021] respectively performing standardization processing on the numerical difference corresponding to each environmental factor, calculating a mean value of the numerical differences after standardization processing of all types of environmental factors, and determining the mean value as an environment error coefficient corresponding to the relay control.

[0022] In some embodiments, the forming a coefficient vector with the extension error coefficient and the environment error coefficient comprises:

[0023] for each relay control, determining a time extension error coefficient and an environment error coefficient corresponding to the relay control;

[0024] taking the time extension error coefficient corresponding to the relay control as a first element and taking the environment error coefficient corresponding to the relay control as a second element;

[0025] combining the first element and the second element in a preset order to form a corresponding coefficient vector of the relay control.

[0026] In some embodiments, the collecting all the coefficient vectors and calculating the time delay controllable coefficient of each relay control comprises:

[0027] collecting the corresponding coefficient vector of each relay control to form a set containing all the coefficient vectors;

[0028] analyzing the overall difference between all the coefficient vectors and determining the correlation degree of the environmental error coefficient and the time extension error coefficient;

[0029] calculating the time delay controllable coefficient corresponding to each relay control based on the overall difference and the correlation degree.

[0030] In some embodiments, the constructing a two-dimensional sample space containing the time delay controllable coefficient and calculating the error influence performance corresponding to different time delays comprises:

[0031] classifying all the time delay controllable coefficients according to the relay control sequence number, building a two-dimensional sample space according to the classified time delay controllable coefficients, and marking all the time delay controllable coefficients as sample points in the two-dimensional sample space;

[0032] for each time delay value, extracting all the time delay controllable coefficients before the time delay value;

[0033] calculating the ratio of the extracted time delay controllable coefficients to the corresponding relay control sequence number;

[0034] determining the error influence performance corresponding to the time delay value according to the ratio.

[0035] In some embodiments, the statistical analysis of the error influence performance data of all the thyristors and the determination of the error influence performance threshold value comprise:

[0036] collecting the error influence performance data of all the thyristors at each monitoring time;

[0037] calculating the cumulative proportion of all the error influence performance data and determining the limit value corresponding to the cumulative proportion;

[0038] determining the error influence performance data corresponding to the limit value as the threshold value of the error influence performance.

[0039] In some embodiments, the comparing the error influence performance at each monitoring time with the error influence performance threshold value and evaluating the impact resistance of the thyristor comprises:

[0040] Screening test results with error influence performance less than the error influence performance threshold as valid detection data of the impact resistance of the silicon controlled element;

[0041] Performing secondary detection on the silicon controlled element corresponding to the test result with error influence performance greater than or equal to the error influence performance threshold;

[0042] If the error influence performance of the secondary detection is still greater than or equal to the error influence performance threshold, the corresponding silicon controlled element is recycled;

[0043] If the error influence performance of the secondary detection is less than the error influence performance threshold, the secondary detection result is included in the valid detection data;

[0044] Determining the impact resistance test result of the silicon controlled element based on all the valid detection data.

[0045] In a second aspect, an embodiment of the present application provides a silicon controlled element impact resistance test system, and the system comprises the following modules:

[0046] An acquisition module is configured to acquire a zero-crossing signal monitoring time and a driving signal monitoring time, acquire a delay time length of each relay control based on the zero-crossing signal monitoring time and the driving signal monitoring time, and synchronously acquire environmental monitoring data of the monitoring time;

[0047] A calculation module is configured to calculate a time extension error coefficient based on the delay time length, calculate an environmental error coefficient based on the environmental monitoring data, and form a coefficient vector with the extension error coefficient and the environmental error coefficient;

[0048] A construction module is configured to collect all the coefficient vectors, calculate a time delay controllable coefficient of each relay control, construct a two-dimensional sample space containing the time delay controllable coefficient, and calculate error influence performance corresponding to different time delays;

[0049] An evaluation module is configured to compare the error influence performance of each monitoring time with an error influence performance threshold, and evaluate the impact resistance of the silicon controlled element.

[0050] In a third aspect, an embodiment of the present application provides an electronic device, which comprises a memory and a processor, the memory stores executable code, and the processor executes the executable code to implement the embodiments of each possible implementation of the first aspect.

[0051] In a fourth aspect, an embodiment of the present application provides a computer program product, which comprises computer program code, and when the computer program code runs on a computer, the computer executes the method in the first aspect or any one of the possible implementation manners of the first aspect.

[0052] In a fifth aspect, an embodiment of the present application provides a computer readable storage medium having stored thereon a computer program which, when executed in a computer, causes the computer to perform the embodiments of the possible implementation of the first aspect.

[0053] The embodiments of the present application have at least the following beneficial effects:

[0054] The present application can accurately obtain the relay control delay time by step-by-step acquisition of the zero-crossing signal, driving signal monitoring time and environmental monitoring data, and then through error coefficient calculation, coefficient vector construction and time delay controllable coefficient analysis, combined with the two-dimensional sample space quantization of the error influence performance of different time delays, the reasonable threshold is determined by statistical analysis to screen the effective data. This process system distinguishes the interference of environmental fluctuations and abnormal factors on the test, corrects the errors caused by temperature, contact oxidation, etc., greatly improves the timing control accuracy and data reliability, and finally realizes the accurate evaluation of the impact resistance of thyristor, and provides a scientific basis for component performance determination. BRIEF DESCRIPTION OF DRAWINGS

[0055] In order to more clearly illustrate the technical solutions and advantages of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creative labor.

[0056] Figure 1 A method flowchart of a thyristor impact resistance test method provided by an embodiment of the present application;

[0057] Figure 2 A system block diagram of a thyristor impact resistance test system provided by an embodiment of the present application;

[0058] Figure 3 A structure schematic diagram of a computer device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0059] In order to further illustrate the technical means and effects taken by the present application to achieve the predetermined invention purpose, the specific implementation, structure, features and effects of the thyristor impact resistance test method and system according to the present application are described in detail as follows by combining with the drawings and preferred embodiments.

[0060] In the following description, different "one embodiment" or "another embodiment" do not necessarily refer to the same embodiment. In addition, the specific features, structures or characteristics in one or more embodiments can be combined in any suitable form.

[0061] In the description of the embodiments of the present application, unless otherwise specified, " / " represents the meaning of or, for example, A / B can represent A or B: "and / or" in the text is only a description of the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent: A exists alone, A and B exist together, and B exists alone, and in addition, in the description of the embodiments of the present application, "multiple" means two or more than two.

[0062] Hereinafter, the terms "first", "second" are only for descriptive purposes, and cannot be understood as implying or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features.

[0063] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as understood by a person skilled in the art to which the present application belongs.

[0064] The embodiments of the present application will be described below with reference to the accompanying drawings. Those skilled in the art can know that with the development of technology and the appearance of new scenes, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0065] The specific scheme of the silicon controlled rectifier impact resistance test method and system provided by the present application will be specifically described below with reference to the accompanying drawings.

[0066] Embodiment one:

[0067] Please refer to Figure 1 which shows the step flow chart of a silicon controlled rectifier impact resistance test method provided by an embodiment of the present application, which comprises the following steps:

[0068] S10. Obtain the zero-crossing signal monitoring time and the driving signal monitoring time, obtain the delay time length of each relay control based on the zero-crossing signal monitoring time and the driving signal monitoring time, and synchronously obtain the environmental monitoring data of the monitoring time.

[0069] The zero-crossing signal monitoring time refers to the specific time point when the zero-crossing detection circuit identifies the zero-crossing point of alternating current, that is, the moment when the voltage is zero and outputs a pulse signal. The zero-crossing detection circuit is a special circuit specially used for capturing the zero-crossing point of alternating current. The driving signal monitoring time is the specific time point when the relay starts to act after receiving the driving signal, that is, the control signal of its on-off. Specifically, the output end of the zero-crossing detection circuit is connected to the oscilloscope channel 1, and the pulse signal output by the zero-crossing detection circuit is captured through the oscilloscope channel 1, so as to lock the zero-crossing signal monitoring time;

[0070] Next, connect the relay drive signal terminal to oscilloscope channel 2 and determine the drive signal monitoring time by capturing the rising edge of the drive signal. The delay duration is the time difference between the zero-crossing signal monitoring time and the drive signal monitoring time during the same relay control process. This time difference can be directly read using the oscilloscope's measurement function to obtain the delay duration for each relay control. Environmental monitoring data consists of environmental parameters that affect test accuracy, including environmental factors such as temperature, humidity, and air pressure, which are collected simultaneously using an environmental parameter monitoring device to ensure a one-to-one correspondence between environmental data and time data.

[0071] S11. Calculate the time extension error coefficient based on the delay duration, calculate the environmental error coefficient based on the environmental monitoring data, and combine the extension error coefficient and the environmental error coefficient into a coefficient vector.

[0072] Specifically, first, a preset number of relay control operations are performed, and the delay duration for each operation is recorded. Then, the average delay duration within the preset number of operations is calculated, which is the average difference in time extension between multiple relay control operations. Next, for each relay control operation, the deviation of its delay duration from this average is calculated. Specifically, the preset number of operations can be 10, or it can be adjusted according to testing requirements. Furthermore, the... Time delay error coefficient during secondary relay control The calculation formula is as follows:

[0073]

[0074] in, Indicates the first Monitoring time of drive signal during secondary relay control Indicates the first Zero-crossing signal monitoring time during secondary relay control This represents the average of all delay times for the relay control of the preset number of times the thyristor element is used. Time delay error coefficient. It is a parameter that quantifies the degree to which the delay time of each relay control deviates from the average delay time, and is used to reflect the stability of the delay time.

[0075] Furthermore, first, acquire various environmental monitoring data at the zero-crossing signal monitoring time and drive signal monitoring time corresponding to each relay control. Specifically, the environmental monitoring data can include multiple environmental factors, such as temperature, humidity, and air pressure. Then, calculate the numerical difference of the same environmental factor at the zero-crossing signal monitoring time and drive signal monitoring time. Further, the environmental error coefficient for the i-th relay control... The calculation formula is as follows:

[0076]

[0077] in, Indicates the first The first time the drive signal monitoring moment is during the secondary relay control The values ​​of each environmental factor, Indicates the first The zero-crossing signal monitoring time during secondary relay control is the first The values ​​of each environmental factor, This indicates the number and types of environmental factors involved in multiple relay controls of the thyristor. Environmental error coefficient. It is a parameter that measures the impact of changes in environmental factors on the test between the zero-crossing signal monitoring time and the drive signal monitoring time.

[0078] Furthermore, by integrating the time extension error coefficient and environmental error coefficient of the same relay control, the time extension error coefficient is... As the first element, the environmental error coefficient As the second element; combined according to the preset order of "first element first, second element last", to form a coefficient vector. :

[0079]

[0080] S12. Collect all the coefficient vectors, calculate the controllable time delay coefficient for each relay control, construct a two-dimensional sample space containing the controllable time delay coefficient, and calculate the error impact performance corresponding to different time delays.

[0081] Specifically, first collect the coefficient vectors corresponding to all relay controls. This forms a complete set of coefficient vectors; then, the overall differences between all coefficient vectors are analyzed to reflect the relay control error, and the time extension error coefficient is determined through correlation analysis. Environmental error coefficient The degree of correlation is used to reflect the effect of control in reducing errors;

[0082] Furthermore, based on the overall differences and correlations, the controllable time delay coefficient for each relay control is obtained through weighted calculation. Specifically, the first... The time delay controllability coefficient of a thyristor device The calculation formula is:

[0083]

[0084] in, The total number of coefficient vectors Indicates the first Time delay error coefficient during secondary relay control a time extension error coefficient of the first relay control, a time extension error coefficient of the first relay control, a time extension error coefficient of the first relay control, a time extension error coefficient of the first relay control, a coefficient vector of the first relay control, The difference represents the variation of the time delay of the thyristor element during relay control. The smaller the difference, the better the stability of the control weakening of the entire thyristor element, and the more obvious the error weakening effect.

[0085] Further, the two-dimensional sample space is a coordinate system for presenting the distribution characteristics of the time delay controllable coefficient. First, all time delay controllable coefficients are classified according to the relay control sequence number, i.e., the sequence number of the relay control operation. The numerical value of the time delay controllable coefficient is taken as the horizontal axis, and the number of collected data corresponding to the numerical value is taken as the vertical axis to build a two-dimensional coordinate system. All time delay controllable coefficients are marked as independent sample points in the coordinate system to form a complete two-dimensional sample space.

[0086] Further, the calculation formula of the error influence performance is:

[0087]

[0088] wherein, represents the time delay controllable coefficient with the sequence number from 1 to k, represents the sequence number value before the time delay value k, represents the sequence number of the current time delay value, represents the ratio of each extracted time delay controllable coefficient to the corresponding relay control sequence number. The larger the ratio, the more obvious the relay control error performance before the value. After taking the average of all ratios and normalizing, the error influence performance of the time delay value is obtained. The error influence performance is a parameter for quantifying the influence degree of different time delay values on the accuracy of the test result.

[0089] S13. Compare the error influence performance of each monitoring moment with the error influence performance threshold to evaluate the impact resistance of the thyristor element.

[0090] Specifically, first, collect the error influence performance data of all thyristors at each monitoring time; perform normal distribution statistical analysis on the error influence performance data, and calculate the cumulative proportion in order from small to large. Specifically, the cumulative proportion limit value can be set to 0.903, or it can be adjusted according to actual needs. Test results with a cumulative proportion greater than 0.903 are determined to be unreliable; the error influence performance threshold is calculated as follows:

[0091]

[0092] In the formula, represents the threshold of error influence performance, that is, the specific value used to distinguish reliable and unreliable test results; represents the error influence performance corresponding to the kth time delay value, is the total number of time delay values, represents the number of sampling data corresponding to the kth time delay value at the corresponding time; wherein, is a normalization function, that is, a standardization function.

[0093] Specifically, when adding in order from small to large, a critical point will appear: at this time, the cumulative result is just ≤0.903, and if the next value is added, the result will exceed 0.903. At this time, the corresponding to this critical point is the error influence performance threshold The cumulative proportion limit value is set to 0.903 above, that is, the part with a cumulative proportion ≤0.903 is reliable data. Therefore, all and its corresponding test results are reliable data, while and its corresponding test results are unreliable data with a cumulative proportion exceeding 0.903, which need to be excluded or retested.

[0094] ​​The impact resistance of the thyristor refers to the ability of the thyristor to maintain stable operation under instantaneous voltage and current impact, and is a core performance index of the thyristor. In specific implementation, the error influence performances at each monitoring time are compared with the set error influence performance threshold one by one; the test results with the error influence performances less than the threshold are screened out, and such results are less affected by errors and are used as effective detection data of the impact resistance; the thyristor corresponding to the test result with the error influence performance greater than or equal to the threshold is detected again to exclude accidental error influence; if the secondary detection result is still greater than or equal to the threshold, it is indicated that the element is affected by abnormal factors and cannot be accurately evaluated, and needs to be recycled; if the secondary detection result is less than the threshold, it is included in the effective detection data; finally, based on all the effective detection data, key parameters such as the trigger voltage stability and response time consistency of the thyristor are comprehensively analyzed, and the final impact resistance test result of the thyristor is determined.

[0095] Embodiment two:

[0096] Please refer to Figure 2 which shows a thyristor impact resistance test system provided by an embodiment of the application, and the system comprises:

[0097] The acquisition module 20 is configured to acquire a zero-crossing signal monitoring time and a driving signal monitoring time, acquire a delay duration of each relay control based on the zero-crossing signal monitoring time and the driving signal monitoring time, and synchronously acquire environmental monitoring data at the monitoring time.

[0098] The calculation module 21 is configured to calculate a time extension error coefficient based on the delay duration, calculate an environmental error coefficient based on the environmental monitoring data, and form a coefficient vector by combining the extension error coefficient and the environmental error coefficient.

[0099] The construction module 22 is configured to collect all the coefficient vectors, calculate a time delay controllable coefficient of each relay control, construct a two-dimensional sample space containing the time delay controllable coefficient, and calculate an error influence performance corresponding to different time delays.

[0100] The evaluation module 23 is configured to compare the error influence performance at each monitoring time with the error influence performance threshold, and evaluate the impact resistance of the thyristor.

[0101] Optionally, the transmission medium can be a wired link such as, but not limited to, a coaxial cable, an optical fiber, a digital subscriber line, and the like, or a wireless link such as, but not limited to, Wireless Fidelity (WIFI), Bluetooth, and a mobile device network.

[0102] It should be noted that the device provided in the above embodiment is only used as an example for the division of the above functional modules, and in actual applications, the above functions can be completed by different functional modules according to needs, that is, the internal structure of the computer device is divided into different functional modules to complete all or part of the functions described above.

[0103] Figure 3 is a structural schematic diagram of a computer device provided by an embodiment of the present application. As shown in the example, Figure 3 the computer device 30 includes a memory 31, a processor 32, and a computer program 33 stored in the memory 31 and running on the processor 32, wherein the processor 32 executes the computer program 33, so that the computer device can execute any one of the above-mentioned controllable silicon impact resistance test methods.

[0104] In addition, an embodiment of the present application also protects a device, which can include a memory and a processor, wherein the memory stores executable program code, and the processor is used to call and execute the executable program code to execute a controllable silicon impact resistance test method provided by an embodiment of the present application.

[0105] An embodiment of the present application can divide the device into functional modules according to the above method examples, for example, each functional module can be corresponding, or two or more functions can be integrated in one processing module, and the above integrated module can be realized in the form of hardware. It should be noted that the division of the modules in the present embodiment is illustrative, and is only a logical function division, and another division mode can be used in actual implementation.

[0106] It should be understood that the device provided by an embodiment of the present application is used to execute the above-mentioned controllable silicon impact resistance test method, so as to achieve the same effect as the above-mentioned implementation method.

[0107] In the case of using an integrated unit, the device can include a processing module and a storage module. When the device is applied to a device, the processing module can be used to control and manage the actions of the device. The storage module can be used to support the device to execute mutual program codes and the like. The processing module can be a processor or a controller, which can realize or execute various exemplary logical blocks, modules and circuits described in combination with the disclosure of the present application. The processor can also be a combination of computing functions, such as one or more microprocessor combinations, combinations of digital signal processing (Digital Signal Processing, DSP) and microprocessors, and the like, and the storage module can be a memory.

[0108] In addition, the device provided by the embodiment of the present application can be a chip, a component or a module, the chip can include a processor and a memory connected to each other, and the memory is used to store instructions, and when the processor calls and executes the instructions, the chip can execute the thyristor impact resistance test method provided by the above embodiment.

[0109] The embodiment of the present application also provides a computer readable storage medium, which stores computer program codes, and when the computer program codes run on a computer, the computer program codes make the computer execute the above related method steps to realize the thyristor impact resistance test method provided by the above embodiment.

[0110] The embodiment of the present application also provides a computer program product, and when the computer program product runs on a computer, the computer program product makes the computer execute the above related steps to realize the thyristor impact resistance test method provided by the above embodiment.

[0111] The device, the computer readable storage medium, the computer program product or the chip provided by the embodiment of the present application are used to execute the corresponding method provided above, so the beneficial effects achieved by the device, the computer readable storage medium, the computer program product or the chip can refer to the beneficial effects in the corresponding method provided above, and details are not repeated here. Through the description of the above implementation manners, those skilled in the art can understand that, for the convenience and brevity of description, only the division of the above functional modules is taken as an example for illustration, and in actual application, the above functions can be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In the embodiments provided by the present application, it should be understood that the disclosed device and method can be implemented in other ways.

[0112] The device embodiment described above is only schematic, for example, the division of the modules or units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another device, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the shown or discussed mutual ones can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0113] It should also be noted that, as used in this document, the terms "comprises" or "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0114] It should be noted that the above-mentioned order of the embodiments of the present application is only for description, and does not represent the advantages and disadvantages of the embodiments. The processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multi-task processing and parallel processing are also possible or can be advantageous.

[0115] Each of the embodiments in the specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the difference from other embodiments.

[0116] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered within the protection scope of the present application.

Claims

1. A method for testing the impact resistance of a thyristor, characterized in that, The method includes the following steps: The zero-crossing signal monitoring time and the drive signal monitoring time are obtained. Based on the zero-crossing signal monitoring time and the drive signal monitoring time, the delay time of each relay control is obtained, and the environmental monitoring data at the monitoring time is obtained synchronously. Calculate the time extension error coefficient based on the delay duration, calculate the environmental error coefficient based on the environmental monitoring data, and combine the time extension error coefficient and the environmental error coefficient into a coefficient vector. Specifically, for each relay control, determine the time extension error coefficient and the environmental error coefficient corresponding to the relay control; use the time extension error coefficient corresponding to the relay control as the first element, and the environmental error coefficient corresponding to the relay control as the second element; combine the first element and the second element in a preset order to form the coefficient vector corresponding to the relay control. Collect all the aforementioned coefficient vectors, calculate the controllable time delay coefficient for each relay control, construct a two-dimensional sample space containing the controllable time delay coefficients, and calculate the error impact performance corresponding to different time delays. Specifically, this involves: collecting the coefficient vectors corresponding to each relay control to form a set containing all coefficient vectors; analyzing the overall differences among all coefficient vectors and determining the correlation between the environmental error coefficient and the time delay error coefficient; calculating the controllable time delay coefficient for each relay control based on the overall differences and the correlation; classifying all controllable time delay coefficients according to the relay control sequence number, constructing a two-dimensional sample space based on the classified controllable time delay coefficients, and labeling all controllable time delay coefficients as sample points in the two-dimensional sample space; extracting all controllable time delay coefficients before each time delay value; calculating the ratio of the extracted controllable time delay coefficient to the corresponding relay control sequence number; and determining the error impact performance corresponding to the time delay value based on the ratio. The impact performance of the thyristor element is evaluated by comparing the error impact performance at each monitoring time with the error impact performance threshold.

2. The method for testing the impact resistance of a thyristor according to claim 1, characterized in that, The process of acquiring the zero-crossing signal monitoring time and the drive signal monitoring time, and acquiring the delay duration of each relay control based on the zero-crossing signal monitoring time and the drive signal monitoring time, includes: The zero-crossing point of the AC current is detected by the zero-crossing detection circuit and a pulse signal is output. The zero-crossing signal monitoring time is determined based on the pulse signal, and the driving signal monitoring time is determined based on the relay driving signal. The time difference between the zero-crossing signal monitoring time and the drive signal monitoring time is read using an oscilloscope, and the time difference is used as the delay duration for the corresponding relay control.

3. The method for testing the impact resistance of a thyristor according to claim 1, characterized in that, The calculation of the time extension error coefficient based on the delay duration includes: Set a preset number of relay control operations and record the delay time corresponding to each relay control operation. Calculate the average delay duration corresponding to the preset number of relay controls; For each relay control, calculate the deviation of the delay duration of the relay control from the average value; The deviation is normalized to obtain the time extension error coefficient corresponding to each relay control.

4. The method for testing the impact resistance of a thyristor according to claim 1, characterized in that, The calculation of the environmental error coefficient based on the environmental monitoring data includes: Acquire environmental monitoring data at the time of zero-crossing signal monitoring corresponding to each relay control, and environmental monitoring data at the time of drive signal monitoring corresponding to the relay control; Calculate the numerical difference of the same environmental factor in the environmental monitoring data at the zero-crossing signal monitoring time and the drive signal monitoring time, respectively; The numerical differences corresponding to each type of environmental factor are standardized, and the mean of the numerical differences after standardization of all types of environmental factors is calculated. The mean is then determined as the environmental error coefficient for the corresponding relay control.

5. The method for testing the impact resistance of a thyristor according to claim 1, characterized in that, The determination of the performance threshold for the impact of the error includes: Collect error impact data for all thyristor components at each monitoring time; Calculate the cumulative percentage of all errors affecting performance data, and determine the threshold value corresponding to the cumulative percentage; The error impact performance data corresponding to the aforementioned threshold value is determined as the threshold value for error impact performance.

6. The method for testing the impact resistance of a thyristor according to claim 1, characterized in that, The comparison of the error impact performance at each monitoring time with the error impact performance threshold to evaluate the shock resistance of the thyristor includes: Test results with error impact less than the aforementioned error impact threshold are selected as valid test data for the impact resistance of the thyristor element. For test results where the error impact performance is greater than or equal to the error impact performance threshold, a secondary test is performed on the thyristor element. If the error impact of the second test is still greater than or equal to the error impact threshold, the corresponding thyristor element will be recycled. If the error impact of the secondary detection is less than the error impact threshold, then the secondary detection result will be included in the valid detection data. The impact resistance test results of the silicon controlled rectifier (SCR) element are determined based on all the valid test data.

7. A thyristor impact resistance testing system, characterized in that, The system includes the following modules: The acquisition module is used to acquire the zero-crossing signal monitoring time and the drive signal monitoring time, acquire the delay duration of each relay control based on the zero-crossing signal monitoring time and the drive signal monitoring time, and synchronously acquire environmental monitoring data at the monitoring time. The calculation module is used to calculate the time extension error coefficient based on the delay duration, calculate the environmental error coefficient based on the environmental monitoring data, and form a coefficient vector by combining the time extension error coefficient and the environmental error coefficient. Specifically, for each relay control, the time extension error coefficient and the environmental error coefficient corresponding to the relay control are determined; the time extension error coefficient corresponding to the relay control is used as the first element, and the environmental error coefficient corresponding to the relay control is used as the second element; the first element and the second element are combined in a preset order to form the coefficient vector corresponding to the relay control. A construction module is used to collect all the coefficient vectors, calculate the controllable time delay coefficient for each relay control, construct a two-dimensional sample space containing the controllable time delay coefficients, and calculate the error impact performance corresponding to different time delays. Specifically, it involves: collecting the coefficient vectors corresponding to each relay control to form a set containing all coefficient vectors; analyzing the overall differences between all coefficient vectors and determining the correlation between the environmental error coefficient and the time delay error coefficient; calculating the controllable time delay coefficient for each relay control based on the overall differences and the correlation; classifying all controllable time delay coefficients according to the relay control sequence number, constructing a two-dimensional sample space based on the classified controllable time delay coefficients, and labeling all controllable time delay coefficients as sample points in the two-dimensional sample space; extracting all controllable time delay coefficients before each time delay value; calculating the ratio of the extracted controllable time delay coefficient to the corresponding relay control sequence number; and determining the error impact performance corresponding to the time delay value based on the ratio. The evaluation module is used to compare the error impact performance at each monitoring time with the error impact performance threshold to evaluate the shock resistance of the thyristor.

Images