A semiconductor structure and a method of fabricating the same

Abstract

The application relates to a semiconductor structure and a preparation method thereof, which comprises the following steps: providing a substrate containing a substrate, a floating diffusion region and a source follower, a gate structure of the source follower is located on the upper surface of the substrate, and the floating diffusion region is located on both sides of the gate structure in a first direction; forming an interlayer dielectric layer covering the substrate and the gate structure; forming grooves located on both sides of the gate structure in the interlayer dielectric layer, the bottom of the groove and the top of the gate structure are arranged in a second direction; forming a mask layer covering the sidewall of the groove; etching to form a first contact hole, a second contact hole and a connecting hole connecting the two holes based on the mask layer, the bottom of the first contact hole and the second contact hole respectively exposes the floating diffusion region and the gate structure; forming a low dielectric constant layer covering the sidewall of the first contact hole, the second contact hole and the connecting hole; and forming a connecting structure filling the first contact hole, the second contact hole and the connecting hole and covering the low dielectric constant layer. The semiconductor structure and the preparation method thereof reduce the contact resistance of the device and reduce the parasitic capacitance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] CMOS image sensor (CIS) is a device that converts photons into electronic signals through photoelectric effect, which is widely used in mobile phones, security, automotive cameras and other scenarios. With the continuous reduction of pixel size, higher requirements are put forward for the electrical performance of pixel circuit structure.

[0003] Among them, the floating diffusion (FD) and the source follower (SF) in the pixel circuit constitute the core structure of the signal chain. In order to reduce the dark current, the pixel area often adopts a metal-free silicide structure, but the contact resistance of this structure is high, which directly affects the reading efficiency.

[0004] The traditional method connects the metal layer with the floating diffusion and the source follower respectively to expand the contact area and reduce the resistance, but it will significantly increase the parasitic capacitance, resulting in a decrease in pixel conversion gain, which will affect the image quality.

[0005] Therefore, how to reduce the contact resistance while reducing the parasitic capacitance has become a technical problem that needs to be solved by those skilled in the art. SUMMARY

[0006] Therefore, it is necessary to provide a semiconductor structure and a preparation method thereof to solve the problem that it is difficult to simultaneously reduce the contact resistance and the parasitic capacitance in the pixel circuit of the image sensor in the prior art.

[0007] In order to achieve the above purpose, on the one hand, the present application provides a preparation method of a semiconductor structure, comprising the following steps:

[0008] providing a substrate, the substrate comprising a substrate, a floating diffusion and a source follower, the source follower comprising a gate structure located on the upper surface of the substrate, the floating diffusion being located on the upper surface layer of the substrate and being respectively located on both sides of the gate structure in a first direction;

[0009] forming an interlayer dielectric layer covering the substrate and the gate structure;

[0010] forming a groove in the interlayer dielectric layer and respectively located on both sides of the gate structure in the first direction, and the bottom of the groove and the top of the gate structure are spaced apart in a second direction, wherein the second direction is the thickness direction of the substrate, and the second direction intersects the first direction;

[0011] forming a mask layer covering the sidewall of the groove;

[0012] forming a first contact hole, a second contact hole and a connection hole in the interlayer dielectric layer based on the mask layer, a bottom of the first contact hole exposing the floating diffusion region, a bottom of the second contact hole exposing the gate structure, the connection hole being above and communicating with the first contact hole and the second contact hole;

[0013] forming a low dielectric constant layer covering sidewalls of the first contact hole, the second contact hole and the connection hole;

[0014] forming a connection structure filling the first contact hole, the second contact hole and the connection hole and covering the low dielectric constant layer.

[0015] In one of the embodiments, in the second direction, the depth of the groove is one fourth of the thickness of the interlayer dielectric layer.

[0016] In one of the embodiments, the gate structure includes a gate dielectric layer, a gate layer and a sidewall, the gate dielectric layer and the gate layer are stacked in sequence in the second direction, the sidewall is respectively located on both sides of the gate layer in the first direction, and a normal projection of the edge of the groove on the substrate is located within a normal projection of the sidewall on the substrate.

[0017] In one of the embodiments, the forming of the mask layer covering the sidewall of the groove includes:

[0018] forming a mask material layer covering the interlayer dielectric layer and filling the groove;

[0019] forming a patterned first photoresist layer on the mask material layer;

[0020] based on the patterned first photoresist layer, etching the mask material layer to obtain the mask layer covering the sidewall of the groove.

[0021] In one of the embodiments, the forming of the low dielectric constant layer covering the sidewall of the first contact hole, the second contact hole and the connection hole includes:

[0022] forming a low dielectric constant material layer covering the upper surface of the interlayer dielectric layer, the sidewall of the first contact hole, the sidewall of the second contact hole and the sidewall of the connection hole;

[0023] using anisotropic etching, etching the low dielectric constant material layer in the second direction to form the low dielectric constant layer covering the sidewall of the first contact hole, the sidewall of the second contact hole and the sidewall of the connection hole.

[0024] In one of the embodiments, before forming the interlayer dielectric layer covering the substrate and the gate structure, the method further comprises:

[0025] forming a first protective layer on the upper surface of the substrate and the upper surface of the gate structure;

[0026] forming a second protective layer covering the sidewall of the first protective layer;

[0027] forming an etching stop layer covering the first protective layer and the second protective layer.

[0028] In another aspect, the application further provides a semiconductor structure prepared by the method for preparing a semiconductor structure according to any one of the above embodiments, comprising:

[0029] a substrate comprising a substrate, a floating diffusion region and a source follower, the source follower comprising a gate structure on the upper surface of the substrate, the floating diffusion region being on the upper surface of the substrate and being respectively on both sides of the gate structure in a first direction;

[0030] an interlayer dielectric layer above the substrate and the gate structure;

[0031] a first contact hole, a second contact hole and a connecting hole in the interlayer dielectric layer, the bottom of the first contact hole exposing the floating diffusion region, the bottom of the second contact hole exposing the gate structure, the connecting hole being above and communicating with the first contact hole and the second contact hole;

[0032] a low dielectric constant layer covering the sidewall of the first contact hole, the sidewall of the second contact hole and the sidewall of the connecting hole;

[0033] a connecting structure filling the first contact hole, the second contact hole and the connecting hole and covering the low dielectric constant layer.

[0034] In one of the embodiments, the thickness of the low dielectric constant layer is one-tenth to one-third of the opening size of the first contact hole, and / or the thickness of the low dielectric constant layer is one-tenth to one-third of the opening size of the second contact hole.

[0035] In one of the embodiments, the substrate further comprises a plurality of photodiodes arranged in an array, a plurality of transfer transistors arranged correspondingly on the photodiodes and used for controlling the turn-off of the photodiodes, a floating diffusion region arranged between two of the transfer transistors arranged oppositely in the third direction, and the two of the transfer transistors sharing the floating diffusion region, and the source follower is arranged between the plurality of photodiodes arranged in an array, and the plurality of photodiodes arranged in an array share the source follower.

[0036] In one of the embodiments, the floating diffusion regions arranged on both sides of the gate structure have different sizes in the first direction.

[0037] The semiconductor structure and the preparation method thereof form recesses respectively arranged on both sides of the gate structure in the first direction in the interlayer dielectric layer, and the bottom of the recess and the top of the gate structure are arranged apart in the second direction; a mask layer covering the sidewall of the recess is formed; based on the mask layer, a first contact hole, a second contact hole and a connecting hole are etched and formed in the interlayer dielectric layer, the bottom of the first contact hole exposes the floating diffusion region, the bottom of the second contact hole exposes the gate structure, and the connecting hole is arranged above the first contact hole and the second contact hole and communicates the first contact hole and the second contact hole; the connecting structure filling the first contact hole, the second contact hole and the connecting hole formed based on the above process connects the floating diffusion region and the source follower, ensures the transmission efficiency and stability of the electrical signal of the floating diffusion region and the source follower, increases the contact area of the connecting structure with the substrate and the gate structure, reduces the contact resistance, and forms a low dielectric constant layer covering the sidewall of the first contact hole, the second contact hole and the connecting hole, which reduces the contact resistance, reduces the parasitic capacitance between the connecting structures, and improves the conversion gain of the device. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0039] Figure 1 The flow chart of the preparation method of the semiconductor structure provided in an embodiment;

[0040] Figure 2 The cross-sectional structure schematic diagram after the first protective layer is formed in the preparation method of the semiconductor structure provided in an embodiment;

[0041] Figure 3A cross-sectional view of a semiconductor structure after forming a second protective material layer in a method of fabricating a semiconductor structure according to an embodiment;

[0042] Figure 4 A cross-sectional view of a semiconductor structure after forming a second protective layer in a method of fabricating a semiconductor structure according to an embodiment;

[0043] Figure 5 A cross-sectional view of a semiconductor structure after forming an interlayer dielectric layer in a method of fabricating a semiconductor structure according to an embodiment;

[0044] Figure 6 A cross-sectional view of a semiconductor structure after forming a patterned second photoresist layer in a method of fabricating a semiconductor structure according to an embodiment;

[0045] Figure 7 A cross-sectional view of a semiconductor structure after forming a recess in a method of fabricating a semiconductor structure according to an embodiment;

[0046] Figure 8 A cross-sectional view of a semiconductor structure after forming a hard mask material layer and a first photoresist material layer in a method of fabricating a semiconductor structure according to an embodiment;

[0047] Figure 9 A cross-sectional view of a semiconductor structure after forming a patterned first photoresist layer in a method of fabricating a semiconductor structure according to an embodiment;

[0048] Figure 10 A cross-sectional view of a semiconductor structure after forming a mask layer in a method of fabricating a semiconductor structure according to an embodiment;

[0049] Figure 11 A cross-sectional view of a semiconductor structure after forming a first contact hole, a second contact hole, and a connection hole in a method of fabricating a semiconductor structure according to an embodiment;

[0050] Figure 12 A cross-sectional view of a semiconductor structure after forming a low dielectric constant material layer in a method of fabricating a semiconductor structure according to an embodiment;

[0051] Figure 13 A cross-sectional view of a semiconductor structure after forming a low dielectric constant layer in a method of fabricating a semiconductor structure according to an embodiment;

[0052] Figure 14 A cross-sectional view of a semiconductor structure after forming a connection structure in a method of fabricating a semiconductor structure according to an embodiment;

[0053] Figure 15 A top view of a semiconductor structure after forming a connection structure in a method of fabricating a semiconductor structure according to an embodiment.

[0054] Reference Signs List:

[0055] 1 - substrate, 11 - substrate, 12 - floating diffusion region, 13 - source follower, 131 - gate structure, 131a - gate dielectric layer, 131b - gate layer, 131c - side wall, 14 - photodiode, 15 - pass transistor, 16 - isolation structure, 2 - interlayer dielectric layer, 21 - first protective layer, 22 - second protective layer, 221 - second protective material layer, 23 - etching stop layer, 24 - second photoresist layer, 3 - recess, 4 - mask layer, 41 - mask material layer, 42 - first photoresist layer, 421 - first photoresist material layer, 5 - first contact hole, 6 - second contact hole, 7 - connection hole, 8 - low dielectric constant layer, 81 - low dielectric constant material layer, 9 - connection structure. DETAILED DESCRIPTION

[0056] For the purpose of facilitating the understanding of the present application, the present application will be described in greater detail below with reference to the attached drawings. The embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, the purpose of the embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0058] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected" or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first doped type could be termed a second doped type; and similarly, a second doped type could be termed a first doped type; a first doped type and a second doped type are different doped types, e.g., a first doped type can be P-type and a second doped type can be N-type, or a first doped type can be N-type and a second doped type can be P-type.

[0059] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0060] The singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", or the like, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

[0061] Referring to Figure 1 The application provides a preparation method of a semiconductor structure, comprising the following steps:

[0062] Step S1: providing a substrate 1, the substrate 1 comprising a substrate 11, a floating diffusion region 12 and a source follower 13, the source follower 13 comprising a gate structure 131 on the upper surface of the substrate 11, and the floating diffusion region 12 being located on the upper surface layer of the substrate 11 and on both sides of the gate structure 131 in a first direction respectively;

[0063] Step S2: forming an interlayer dielectric layer 2 covering the substrate 11 and the gate structure 131;

[0064] Step S3: forming a groove 3 in the interlayer dielectric layer 2 and on both sides of the gate structure 131 in the first direction respectively, and the bottom of the groove 3 and the top of the gate structure 131 being spaced apart in a second direction, wherein the second direction is the thickness direction of the substrate 1, and the second direction intersects the first direction;

[0065] S4: forming a mask layer 4 covering the sidewall of the groove 3;

[0066] S5: based on the mask layer 4, etching to form a first contact hole 5, a second contact hole 6 and a connecting hole 7 in the interlayer dielectric layer 2, the bottom of the first contact hole 5 exposing the floating diffusion region 12, the bottom of the second contact hole 6 exposing the gate structure 131, and the connecting hole 7 being located above the first contact hole 5 and the second contact hole 6 and connecting the first contact hole 5 and the second contact hole 6;

[0067] S6: forming a low dielectric constant layer 8 covering the sidewall of the first contact hole 5, the sidewall of the second contact hole 6 and the sidewall of the connecting hole 7;

[0068] S7: forming a connecting structure 9 filling the first contact hole 5, the second contact hole 6 and the connecting hole 7 and covering the low dielectric constant layer 8.

[0069] In the above example, the recesses 3 are formed in the interlayer dielectric layer 2 on both sides of the gate structure 131 in the first direction, and the bottom of the recess 3 is spaced apart from the top of the gate structure 131 in the second direction; the mask layer 4 is formed to cover the sidewall of the recess 3; based on the mask layer 4, the first contact hole 5, the second contact hole 6 and the connecting hole 7 are etched and formed in the interlayer dielectric layer 2, the bottom of the first contact hole 5 exposes the floating diffusion region 12, the bottom of the second contact hole 6 exposes the gate structure 131, the connecting hole 7 is located above the first contact hole 5 and the second contact hole 6 and is connected to the first contact hole 5 and the second contact hole 6, the connecting structure 9 filled in the first contact hole 5, the second contact hole 6 and the connecting hole 7 is formed based on the above process, which connects the floating diffusion region 12 and the gate structure 131 of the source follower 13, ensures the electrical signal transmission efficiency and transmission stability of the floating diffusion region 12 and the source follower 13, increases the contact area of the connecting structure 9 and the substrate 11 and the gate structure 131, reduces the contact resistance, and forms the low dielectric constant layer 8 covering the sidewall of the first contact hole 5, the second contact hole 6 and the connecting hole 7, which reduces the contact resistance, reduces the parasitic capacitance between the connecting structures, and improves the conversion gain of the device.

[0070] Specifically, referring to Figure 2 and Figure 15 , step S1 is performed to provide a substrate 1, which includes a substrate 11, a floating diffusion region 12 and a source follower 13, the source follower 13 includes a gate structure 131 located on the upper surface of the substrate 11, and the floating diffusion region 12 is located on the upper surface of the substrate 11 and on both sides of the gate structure 131 in the first direction.

[0071] In one embodiment, the substrate 1 further comprises a plurality of photodiodes 14 arranged in an array, a plurality of transfer transistors 15 arranged on the photodiodes 14 and used for controlling the turn-off of the photodiodes 14, a floating diffusion region 12 arranged between two oppositely arranged transfer transistors 15, and the two transfer transistors 15 sharing the floating diffusion region 12, a source follower 13 arranged between the plurality of photodiodes 14 arranged in an array, and the photodiodes 14 arranged in an array sharing the source follower 13, the photodiodes 14 are used for generating photo-generated electrons, the transfer transistors 15 are arranged obliquely relative to the photodiodes 14, for example, arranged at an angle of 45 degrees, further optimizing the arrangement space, improving the space utilization and the pixel arrangement density, and further, the plurality of photodiodes 14, the plurality of transfer transistors 15, the plurality of floating diffusion regions 12 and the source follower 13 constitute a pixel unit, the structure design of the photodiodes sharing the floating diffusion region 12 and the source follower 13 can significantly improve the pixel arrangement density of the image sensor, and in the embodiment, one pixel unit comprises four photodiodes 14, four transfer transistors 15, two floating diffusion regions 12 and one source follower 13.

[0072] Exemplarily, the substrate 11 is doped with a first conductive type, the photodiode 14 is composed of a doped region with a second conductive type and part of the substrate 11 located in the substrate 11, has no direct leading electrode, and its potential is controlled by the on-off of the transmission gate (TG) of the transfer transistor 15, which can be regarded as the source region of the transfer transistor 15, the transfer transistor 15 is equivalent to a transistor with a second conductive type channel, taking the photodiode 14 as the source region and the floating diffusion region 12 as the drain region, the floating diffusion region 12 is used for storing photo-generated electrons transferred from the photodiode 14, the floating diffusion region 12 is an active region doped with the second conductive type in the substrate 11, and has a trapezoidal shape, which facilitates the two oppositely arranged transfer transistors 15 to share one floating diffusion region 12, and further optimizes the pixel arrangement. The source follower 13 (SF) is used as an amplifier to amplify the potential change of the floating diffusion region 12 and convert it into a current signal.

[0073] In addition, the substrate 1 is further provided with a reset transistor (not shown) and a row selection transistor (not shown), the reset transistor is used to reset the photodiode 14 and the floating diffusion region 12 after the start or end of the photodiode 14 operation, to ensure the consistency of the initial state of each photoelectric signal conversion, and the row selection transistor is used to select a specific row when reading out a signal, so as to sequentially read the signals of each row of pixels, and realize effective acquisition of image information. Further, the reset transistor and the row selection transistor can be integrated with the photodiode, the transfer transistor and the source follower in the same pixel unit to form a four-transistor structure (4T Pixel), which is widely used in CMOS image sensor (CIS) chips.

[0074] The floating diffusion regions 12 on both sides of the gate structure 131 have different sizes, which can provide more flexible wiring space at the layout level. For example, the larger floating diffusion region 12 can be used to set the lead electrodes of other devices (such as row selection transistors and / or reset transistors), thereby being electrically connected to the floating diffusion region 12 to form a complete pixel circuit path, which helps to realize the shared connection of multi-transistor devices in a single pixel unit, and further improves the integration and wiring efficiency of the pixel circuit.

[0075] Exemplarily, the substrate 1 is further provided with an isolation structure 16, the photodiode 14 and the floating diffusion region 12 are isolated and defined by the isolation structure 16, and the isolation structure 16 is also used to isolate the gate structure 131 and the bottom of the floating diffusion region 12. The material of the isolation structure 16 includes silicon dioxide or other suitable materials.

[0076] Specifically, referring to Figures 2 to 5 , a step S2 of forming an interlayer dielectric layer 2 covering the substrate 11 and the gate structure 131 is performed.

[0077] In one embodiment, as shown in Figures 2 to 4 , before forming the interlayer dielectric layer 2 covering the substrate 11 and the gate structure 131, the following steps are further included:

[0078] A first protective layer 21 is formed on the upper surface of the substrate 11 and the upper surface of the gate structure 131. The material of the first protective layer 21 includes silicon dioxide or other suitable materials, and the thickness of the first protective layer 21 ranges from 250 Å to 350 Å. In this embodiment, the thickness of the first protective layer 21 is 300 Å, and the first protective layer 21 is used to protect the pixel array area.

[0079] A second protective layer 22 is formed covering the sidewall of the first protective layer 21. The second protective layer 22 covering the sidewall of the first protective layer 21 is formed by:

[0080] A second protective material layer 221 covering the first protective layer 21 is formed. The material of the second protective material layer 221 includes silicon nitride or other suitable material. The method of forming the second protective material layer 221 includes low pressure chemical vapor deposition or other suitable method. The thickness of the second protective material layer 221 ranges from 120 Å to 180 Å. In this embodiment, the thickness of the second protective material layer 221 is 150 Å.

[0081] The second protective material layer 221 is etched to form a second protective layer 22 on the sidewall of the first protective layer 21, which serves as a protective layer of the sidewall of the gate structure 131 and a protective layer of the substrate 11 in the region of the floating diffusion region 12. The method of etching the second protective material layer 221 includes dry etching or other suitable method.

[0082] An etching stop layer 23 covering the first protective layer 21 and the second protective layer 22 is formed. The etching stop layer 23 is used to further protect the gate structure 131 and the floating diffusion region 12 in subsequent etching processes. The thickness and material of the etching stop layer 23 can be selected according to actual conditions and are not limited herein.

[0083] Exemplarily, the gate structure 131 includes a gate dielectric layer 131a, a gate electrode layer 131b, and a sidewall 131c. The gate dielectric layer 131a and the gate electrode layer 131b are sequentially stacked in the second direction. The sidewall 131c is located on both sides of the gate electrode layer 131b in the first direction. The sidewall 131c includes multiple layers of buffer layers which are stacked to protect the gate dielectric layer 131a and the gate electrode layer 131b. Exemplarily, the buffer layers include two layers. The materials of the buffer layers are silicon dioxide and silicon nitride, respectively. The material of the gate electrode layer 131b includes polysilicon or other suitable material. The material of the gate dielectric layer 131a includes silicon dioxide, high dielectric constant material, or other suitable material.

[0084] Exemplarily, as shown in Figure 5 , the method of forming the interlayer dielectric layer 2 includes chemical vapor deposition or other suitable method. The material of the interlayer dielectric layer 2 includes silicon dioxide or other suitable material. The thickness of the interlayer dielectric layer 2 ranges from 3500 Å to 4000 Å. In this embodiment, the thickness of the interlayer dielectric layer 2 is 3800 Å.

[0085] Specifically, referring to Figures 6 to 7 , step S3 is performed to form grooves 3 in the interlayer dielectric layer 2, which are located on both sides of the gate structure 131 in the first direction. The bottom of the groove 3 and the top of the gate structure 131 are spaced apart in the second direction. The second direction is the thickness direction of the substrate 1, and the second direction intersects the first direction.

[0086] In one embodiment, as shown in Figures 6 to 7As shown, recesses 3 are formed in the interlayer dielectric layer 2 on both sides of the gate structure 131 in the first direction, including:

[0087] A patterned second photoresist layer 24 is formed on the upper surface of the interlayer dielectric layer 2;

[0088] Based on the patterned second photoresist layer 24, recesses 3 are formed in the interlayer dielectric layer 2 on both sides of the gate structure 131 in the first direction, and the bottom of the recess 3 is spaced apart from the top of the gate structure 131 in the second direction.

[0089] In one embodiment, in the second direction, the depth of the recess 3 is one fourth of the thickness of the interlayer dielectric layer 2. Reasonable design of the depth of the recess 3 can to some extent regulate the morphology and size characteristics of the subsequent connection structure 9, thereby directly affecting the parasitic capacitance and contact resistance of the overall structure, and achieving dynamic adjustment of the parasitic capacitance and contact resistance, that is, the depth of the recess 3 will determine the size relationship of the first contact hole 5, the second contact hole 6 and the connection hole 7 formed, and also affect the filling uniformity and sidewall contact area, therefore, experimental optimization finds that when the depth of the recess 3 is controlled to be about one fourth of the thickness of the interlayer dielectric layer 2, a better contact morphology can be obtained, which reduces the difficulty of metal filling while ensuring good sidewall coverage and electrical connection stability, thereby effectively realizing lower contact resistance and smaller parasitic capacitance, meeting the requirements of high-performance image sensors for signal integrity and low power consumption.

[0090] It should be noted that the opening size of the formed recess 3 is related to the size of the corresponding floating diffusion region 12, specifically, when the size of the floating diffusion region 12 is large, the size of the corresponding formed recess 3 is large, and when the size of the floating diffusion region 12 is small, the size of the corresponding formed recess 3 is small, that is, the size of the recess 3 can be flexibly adjusted according to the size of the floating diffusion region 12, thereby ensuring a large contact area while ensuring performance, thereby reducing the contact area.

[0091] In one embodiment, the edge of the recess 3 close to the gate structure 131 is located in the orthographic projection of the sidewall 131c on the substrate 11, which can effectively reduce the potential impact on the control performance of the gate structure 131 while ensuring that the formed recess 3 has sufficient size and contact area, especially in the subsequent etching and other pattern transfer processes, to avoid etching damage to the gate structure 131.

[0092] Further, before the formation of the recess 3, a first protective layer 21, a second protective layer 22 covering the sidewall of the first protective layer 21 and an etching stop layer 23 covering the whole are sequentially formed on the surface of the substrate 11 and the gate structure 131. The multi-layer protective structure not only improves the resistance of the gate structure 131 in the etching stage, but also effectively prevents the etching erosion or lateral damage of the sidewall 131c material, thereby ensuring the gate control ability and the electrical stability of the device.

[0093] Specifically, referring to Figures 8 to 10 , a step S4 is performed to form a mask layer 4 covering the sidewall of the recess 3.

[0094] In one embodiment, as shown in Figures 8 to 10 , the mask layer 4 covering the sidewall of the recess 3 is formed, including:

[0095] forming a mask material layer 41 covering the interlayer dielectric layer 2 and filling the recess 3;

[0096] The method for forming the mask material layer 41 includes chemical vapor deposition or other suitable methods. The mask material layer 41 includes a buffer layer, an intermediate layer and a photosensitive material layer stacked in sequence. The buffer layer is made of silicon dioxide or other suitable materials, which is used to provide a safe etching buffer. The intermediate layer is made of silicon oxynitride or other suitable materials, which is used for antireflection and etching stop. The photosensitive material layer is made of photoresist, which is used to define the etching pattern. Due to the presence of the recess 3, the mask material layer 41 located on the sidewall of the recess 3 has a first thickness in the second direction, and the mask material layer 41 located on the bottom of the recess 3 and above the gate structure 131 has a second thickness in the second direction. The first thickness is greater than the second thickness.

[0097] forming a patterned first photoresist layer 42 on the mask material layer 41; wherein the patterned first photoresist layer 42 on the mask material layer 41 is formed, including:

[0098] forming a first photoresist material layer 421 covering the mask material layer 41; the method for forming the first photoresist material layer 421 includes spin coating or other suitable methods;

[0099] removing the first photoresist material layer 421 located above the floating diffusion region 12 and above the gate structure 131 to obtain the patterned first photoresist layer 42, wherein the patterned first photoresist layer 42 is located on the upper surface of the sidewall of the recess 3 away from the gate structure 131;

[0100] Based on the patterned first photoresist layer 42, the mask material layer 41 is etched to obtain the mask layer 4 covering the side wall of the groove 3. That is, the pattern of the patterned first photoresist layer 42 is transferred to the mask material layer 41. Since the patterned first photoresist layer 42 is located on the upper surface of the side wall of the groove 3 away from the gate structure 131, based on the patterned first photoresist layer 42, the mask material layer 41 is etched to obtain the hard mask layer 4 also covering the upper surface of the side wall of the groove 3 away from the gate structure 131. In addition, the mask material layer 41 formed based on the groove 3 has different topography and height at the bottom and the side wall of the groove 3. Therefore, when the target height of the mask material layer 41 etched away is the second thickness, the mask material layer 41 with the first thickness located on the side wall will remain on the side wall of the groove 3 when the mask material layer 41 is etched based on the patterned first photoresist layer 42.

[0101] Specifically, referring to Figure 11 , step S5 is performed to etch the first contact hole 5, the second contact hole 6 and the connection hole 7 in the interlayer dielectric layer 2 based on the mask layer 4, the bottom of the first contact hole 5 exposes the floating diffusion region 12, the bottom of the second contact hole 6 exposes the gate structure 131, and the connection hole 7 is located above the first contact hole 5 and the second contact hole 6 and communicates the first contact hole 5 and the second contact hole 6.

[0102] In one embodiment, as shown in Figure 11 , the first contact hole 5, the second contact hole 6 and the connection hole 7 are etched in the interlayer dielectric layer 2 based on the mask layer 4, including:

[0103] Dry etching is adopted to etch the interlayer dielectric layer 2 based on the mask layer 4. Since the mask layer 4 and the interlayer dielectric layer 2 have different etching selectivity, the exposed interlayer dielectric layer 2 and the mask layer 4 are etched synchronously to obtain the corresponding first contact hole 5, the second contact hole and the connection hole 7 with a certain depth. The interlayer dielectric layer 2 exposed from the bottom of the groove 3 is etched to the hole exposing the floating diffusion region 12 as the first contact hole 5, and the interlayer dielectric layer 2 exposed from above the gate structure 131 is etched to the hole exposing the gate structure 131 as the second contact hole 6. The interlayer dielectric layer 2 after etching of the mask layer 4 covering the upper surface of the side wall of the groove 3 away from the gate structure 131 serves as the side wall of the connection hole 7.

[0104] Specifically, referring to Figures 12 to 13 , step S6 is performed to form the low dielectric constant layer 8 covering the side wall of the first contact hole 5, the second contact hole 6 and the connection hole 7.

[0105] In one embodiment, as shown in Figures 12 to 13As shown, a low dielectric constant layer 8 is formed to cover the sidewalls of the first contact hole 5, the sidewalls of the second contact hole 6, and the sidewalls of the connection hole 7, including:

[0106] A low dielectric constant material layer 81 is formed to cover the upper surface of the interlayer dielectric layer 2, the hole walls of the first contact hole 5, the hole walls of the second contact hole 6, and the hole walls of the connection hole 7; that is, the low dielectric constant material layer 81 is formed on the exposed surface of the interlayer dielectric layer 2 after the formation of the first contact hole 5, the second contact hole 6, and the connection hole 7; the method for forming the low dielectric constant material layer 81 includes physical vapor deposition, chemical vapor deposition, or other suitable methods; the material of the low dielectric constant material layer 81 includes silicon oxycarbonitride (SiCON) or other suitable materials, which can effectively reduce the parasitic capacitance, reduce the capacitive coupling in the signal transmission process, improve the signal integrity, reduce the signal crosstalk and noise interference, improve the signal-to-noise ratio of the image sensor, and improve the electrical performance and stability of the overall device, while ensuring good process compatibility and reliability.

[0107] Anisotropic etching is adopted to etch the low dielectric constant material layer 81 along the second direction, so as to form the low dielectric constant layer 8 covering the sidewalls of the first contact hole 5, the sidewalls of the second contact hole 6, and the sidewalls of the connection hole 7. Based on the anisotropic etching, the corresponding low dielectric constant layer 8 can be effectively controlled to cover only the sidewalls of the first contact hole 5, the second contact hole 6, and the connection hole 7.

[0108] In one embodiment, the thickness of the low dielectric constant layer 8 is one-tenth to one-third of the opening size of the first contact hole 5, and / or the thickness of the low dielectric constant layer 8 is one-tenth to one-third of the opening size of the second contact hole 6. Here, the opening size refers to the opening size at the bottom of the recess 3 when the interlayer dielectric layer 2 is etched based on the mask layer 4, that is, the distance between the starting points of the straight-line portions on the sidewalls of the first contact hole 5 and the second contact hole 6. On the one hand, this can effectively reduce the parasitic capacitance between the contact hole and the surrounding medium, improve the signal isolation, and optimize the electrical performance in the readout path. On the other hand, it can avoid significant occupation of the effective contact area, so as not to cause excessive contact resistance and ensure the low-impedance characteristics of the electrical signal transmission path. In this embodiment, the thickness of the low dielectric constant layer 8 is one-tenth to one-third of the opening size of the first contact hole 5.

[0109] Specifically, referring to Figures 14 to 15 , step S7 is performed to form a connection structure 9 filling the first contact hole 5, the second contact hole 6, and the connection hole 7 and covering the low dielectric constant layer 8.

[0110] In one embodiment, as shown in Figures 14 to 15 , the connection structure 9 filling the first contact hole 5, the second contact hole 6, and the connection hole 7 and covering the low dielectric constant layer 8 is formed, including:

[0111] A barrier layer is formed to cover the low dielectric constant layer 8; the barrier layer is used to prevent the subsequent metal material connection layer from diffusing to the substrate 11, so as to improve the thermal stability and reliability of the device; the material of the barrier layer includes a titanium / titanium nitride alloy layer; the method for forming the barrier layer includes sputtering or other suitable methods;

[0112] A connection layer is formed to cover the barrier layer and fill the first contact hole 5, the second contact hole 6 and the connection hole 7; the material of the connection layer includes tungsten, which has good electrical conductivity and thermal stability; the method for forming the connection layer includes electroplating, physical vapor deposition or other suitable methods;

[0113] The upper surface of the connection layer is subjected to a planarization treatment, which helps to remove the excess part of the connection layer, restore the flatness between layers and facilitate the subsequent patterning of the metal interconnection; the method for planarizing the connection layer includes chemical mechanical polishing or other suitable methods.

[0114] The connection structure 9 is formed in the first contact hole 5, the second contact hole 6 and the connection hole 7, which realizes the electrical connection of the floating diffusion region 12 and the gate structure 131, constructs the electrical signal transmission path during the working process of the image sensor, ensures the conduction connection between different device units and effectively improves the efficiency and integrity of signal transmission. In addition, the setting of the connection structure 9 can reduce the signal attenuation and delay caused by the contact resistance, long wiring or material interface, so as to ensure that the photoelectric conversion signal in the pixel unit can be stably and quickly transmitted to the peripheral circuit. Further, the optimized design of the connection structure 9 and the cooperation with the low dielectric constant layer 8 can significantly reduce the parasitic capacitance coupling, improve the readout speed of the pixel array and the imaging quality.

[0115] In one embodiment, please refer to Figures 14 to 15The application further provides a semiconductor structure prepared by the method for preparing a semiconductor structure according to any one of the above embodiments, comprising a substrate 1, an interlayer dielectric layer 2, a first contact hole 5, a second contact hole 6, a connecting hole 7, a low dielectric constant layer 8 and a connecting structure 9. The substrate 1 comprises a substrate 11, a floating diffusion region 12 and a source follower 13. The source follower 13 comprises a gate structure 131 on the upper surface of the substrate 11. The floating diffusion region 12 is on the upper surface of the substrate 11 and is respectively on both sides of the gate structure 131 in the first direction. The interlayer dielectric layer 2 is above the substrate 11 and the gate structure 131. The first contact hole 5, the second contact hole 6 and the connecting hole 7 are in the interlayer dielectric layer 2. The bottom of the first contact hole 5 exposes the floating diffusion region 12. The bottom of the second contact hole 6 exposes the gate structure 131. The connecting hole 7 is above and communicates with the first contact hole 5 and the second contact hole 6. The low dielectric constant layer 8 covers the sidewalls of the first contact hole 5, the sidewalls of the second contact hole 6 and the sidewalls of the connecting hole 7. The connecting structure 9 fills the first contact hole 5, the second contact hole 6 and the connecting hole 7 and covers the low dielectric constant layer 8.

[0116] The semiconductor structure is suitable for high-performance image sensors, can ensure device miniaturization layout while taking into account excellent electrical signal transmission capability and high reliability of pixel output, and helps to realize high-resolution and high signal-to-noise ratio image acquisition.

[0117] In one embodiment, the substrate 1 further comprises a plurality of photodiodes 14 arranged in an array, a transfer transistor 15 arranged correspondingly on the photodiode 14 and used for controlling the turn-off of the photodiode 14. A floating diffusion region 12 is arranged between two oppositely arranged transfer transistors 15, and the two transfer transistors 15 share the floating diffusion region 12. The source follower 13 is between the plurality of photodiodes 14 arranged in an array, and the photodiodes 14 arranged in an array share the source follower 13.

[0118] In one embodiment, the sizes of the floating diffusion regions 12 on both sides of the gate structure 131 are different. The larger floating diffusion region can be used to arrange an extraction electrode connected with peripheral control devices such as reset transistors and row selection transistors, so as to form a complete circuit path, ensure stable transmission of electrical signals of the pixel unit, and ensure normal operation of the image sensor.

[0119] In one embodiment, the thickness of the low dielectric constant layer 8 is one-tenth to one-third of the opening size of the first contact hole 5, and / or the thickness of the low dielectric constant layer 8 is one-tenth to one-third of the opening size of the second contact hole 6. Here, the opening size refers to the distance between the starting points of the straight lines on the sidewalls of the first contact hole 5 and the second contact hole 6, such as Figure 14The effective opening width of the contact hole is defined as shown by the dashed line portion. By limiting the thickness of the low dielectric constant layer 8 within the above range, the effective area of the contact hole can be prevented from being excessively reduced while the parasitic capacitance is effectively reduced, thereby ensuring low contact resistance of the connection structure and realizing high efficiency and reliability of signal transmission.

[0120] It should be noted that the forming process and material selection of each component structure of the semiconductor structure in the embodiment can be referred to the description in the preparation method of the semiconductor structure, which will not be described here.

[0121] It should be understood that, although Figure 1 The steps in the flowchart of the method can be executed in the order shown by the arrows, but the steps are not necessarily executed in the order shown by the arrows. Unless otherwise specified herein, the steps are not necessarily limited in the order of execution, and the steps can be executed in other orders. Moreover, Figure 1 At least some of the steps in the method can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times. The execution order of the steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least some of the other steps or steps or stages in other steps.

[0122] In the description of the present specification, the description of the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.

[0123] The technical features of the above-described embodiments can be combined in any manner. In order to make the description concise, all possible combinations of the technical features of the above-described embodiments are not described, but as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present application.

[0124] The above-described embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be noted that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: A substrate is provided, the substrate including a substrate, a floating diffusion region and a source follower, the source follower including a gate structure located on the upper surface of the substrate, the floating diffusion region being located on the upper surface layer of the substrate and respectively located on both sides of the gate structure in a first direction; An interlayer dielectric layer is formed covering the substrate and the gate structure; Grooves are formed in the interlayer dielectric layer on both sides of the gate structure in a first direction, and the bottom of the groove and the top of the gate structure are spaced apart in a second direction, wherein the second direction is the thickness direction of the substrate and intersects the first direction; A mask layer is formed to cover the sidewalls of the groove; Based on the mask layer, a first contact hole, a second contact hole, and a connecting hole are etched in the interlayer dielectric layer. The bottom of the first contact hole exposes the floating diffusion region, the bottom of the second contact hole exposes the gate structure, and the connecting hole is located above the first contact hole and the second contact hole and connects the first contact hole and the second contact hole. A low dielectric constant layer is formed covering the sidewalls of the first contact hole, the second contact hole, and the connecting hole. A connection structure is formed that fills the first contact hole, the second contact hole, and the connection hole and covers the low dielectric constant layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, In the second direction, the depth of the groove is one-quarter of the thickness of the interlayer dielectric layer.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The gate structure includes a gate dielectric layer, a gate layer, and sidewalls. The gate dielectric layer and the gate layer are stacked sequentially in the second direction. The sidewalls are located on both sides of the gate layer in the first direction. The orthogonal projection of the edge of the groove near the gate structure on the substrate is located within the orthogonal projection of the sidewall on the substrate.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The mask layer forming the sidewalls covering the groove includes: A mask material layer is formed that covers the interlayer dielectric layer and fills the groove; A patterned first photoresist layer is formed on the mask material layer; Based on the patterned first photoresist layer, the mask material layer is etched to obtain the mask layer covering the sidewalls of the groove.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, The formation of a low dielectric constant layer covering the sidewalls of the first contact hole, the second contact hole, and the connecting hole includes: A low dielectric constant material layer is formed covering the upper surface of the interlayer dielectric layer, the wall of the first contact hole, the wall of the second contact hole, and the wall of the connecting hole; Anisotropic etching is used to etch the low dielectric constant material layer along the second direction to form the low dielectric constant layer covering the sidewalls of the first contact hole, the second contact hole, and the connecting hole.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that, Before forming the interlayer dielectric layer covering the substrate and the gate structure, the method further includes: A first protective layer is formed on the upper surface of the substrate and the upper surface of the gate structure; A second protective layer is formed, covering the sidewalls of the first protective layer; An etching stop layer is formed covering the first protective layer and the second protective layer.

7. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the method for preparing a semiconductor structure as described in any one of claims 1 to 6, comprising: The substrate includes a substrate, a floating diffusion region, and a source follower, wherein the source follower includes a gate structure located on the upper surface of the substrate, and the floating diffusion region is located on the upper surface layer of the substrate and is respectively located on both sides of the gate structure in a first direction; An interlayer dielectric layer is located above the substrate and the gate structure; A first contact hole, a second contact hole, and a connecting hole are located in the interlayer dielectric layer. The bottom of the first contact hole exposes the floating diffusion region, the bottom of the second contact hole exposes the gate structure, and the connecting hole is located above the first contact hole and the second contact hole and connects the first contact hole and the second contact hole. A low dielectric constant layer covers the sidewall of the first contact hole, the second contact sidewall, and the sidewall of the connection hole; The connection structure fills the first contact hole, the second contact hole, and the connection hole, and covers the low dielectric constant layer.

8. The semiconductor structure according to claim 7, characterized in that, The thickness of the low dielectric constant layer is one-tenth to one-third of the opening size of the first contact hole, and / or the thickness of the low dielectric constant layer is one-tenth to one-third of the opening size of the second contact hole.

9. The semiconductor structure according to claim 7, characterized in that, The substrate further includes a plurality of photodiodes arranged in an array, a transmission transistor correspondingly disposed on the photodiodes and used to control the turn-off of the photodiodes, a floating diffusion region is disposed between two transmission transistors arranged opposite each other in a third direction, and the two transmission transistors share the floating diffusion region, the source follower is located between the plurality of photodiodes arranged in an array, and the plurality of photodiodes arranged in an array share the source follower.

10. The semiconductor structure according to claim 7, characterized in that, The floating diffusion regions located on both sides of the gate structure have different dimensions in the first direction.

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