Compensation method and device of display panel and display screen

Abstract

The invention is suitable for the technical field of display, and provides a compensation method and device of a display panel and a display screen. The display panel comprises a frame buffer. The frame buffer comprises a first storage area used for storing current frame data and a second storage area used for storing previous complete frame data of the current frame data. The compensation method of the display panel comprises the following steps: acquiring a phase difference between an input end synchronizing signal and a display panel synchronizing signal; based on the phase difference, entering a frame compensation mode under the condition of determining that the output frame rate of the graphic processing unit is not synchronous with the fixed refresh rate of the display panel; in the frame compensation mode, stopping writing the current frame data into the first storage area; and circularly outputting the previous complete frame data to the display panel from the second storage area at the first refresh rate, so as to compensate the condition that the front-end input frame rate is different from the refresh rate of the display panel, and improve the problem of picture tearing caused by asynchronization of the input frame rate and the refresh rate of the display panel in a high-frame-rate display process.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of display, and particularly relates to a compensation method and device of a display panel and a display screen. BACKGROUND

[0002] In a high frame rate display scenario such as a game or a video playing, when the frame rate output by a graphics processing unit is not synchronized with the fixed refresh rate of a display panel, a tearing phenomenon is likely to occur. In the prior art, FreeSync matches the input frame rate through variable refresh rate (VRR), which can reduce tearing, but may cause problems such as flicker and gamma shift. To improve these defects, some schemes introduce variable gamma control (VGC) function, and compensation is performed by adjusting a gamma curve.

[0003] However, the VRR+VGC scheme still has the following deficiencies: due to the panel-to-panel difference of the display panel, the same gamma lookup table (LUT) has inconsistent effects under different batches and different optical compensation conditions, and color shift is likely to occur under a non-nominal refresh rate; different models need to re-measure and configure the LUT due to the difference in panel process and brightness compensation nodes, which increases the debugging manpower. SUMMARY

[0004] Therefore, the embodiments of the present application provide a compensation method and device of a display panel and a display screen to improve the tearing problem caused by the unsynchronized input frame rate and the refresh rate of the display panel in a high frame rate display process.

[0005] A first aspect of the embodiments of the present application provides a compensation method of a display panel, The display panel includes a frame buffer, the frame buffer includes a first storage area and a second storage area, the first storage area is used to store current frame data, and the second storage area is used to store previous complete frame data of the current frame data; and the method includes the following steps: obtaining a phase difference between an input end synchronization signal and a display panel synchronization signal; determining, based on the phase difference, that the frame compensation mode is entered when the frame rate output by a graphics processing unit is not synchronized with the fixed refresh rate of the display panel; the display panel synchronization signal refers to a refresh period signal inside the display panel; stopping writing the current frame data to the first storage area in the frame compensation mode; recycling and outputting the previous complete frame data from the second storage area to the display panel at a first refresh rate to compensate for the case that the input frame rate of the front end is different from the refresh rate of the display panel.

[0006] The compensation method of the display panel in the embodiment of the present application acquires the phase difference between the input end synchronization signal and the display panel synchronization signal, switches to the frame compensation mode in time in the case of detecting that the input end output frame rate is asynchronous with the fixed refresh rate of the display panel, stops writing the current frame data to the first storage area in the frame compensation mode, and cyclically outputs the last complete frame data from the second storage area at the first refresh rate, thereby preventing the effective frame data that has not been displayed from being overwritten in the output process, and ensuring the integrity and continuity of the frame data. Thus, in the high frame rate display process, the picture tearing phenomenon caused by the asynchronization between the input frame rate and the refresh rate of the display panel can be effectively improved, and the stability and smoothness of the display picture are improved. Compared with the existing scheme that depends on variable refresh rate and variable gamma control, the method eliminates the picture tearing while reducing the dependence on additional hardware and complex debugging, thereby improving the compensation effect consistency and reducing the hardware cost.

[0007] In a possible implementation, the determining that the graphics processing unit output frame rate is asynchronous with the fixed refresh rate of the display panel based on the phase difference comprises: In the case that the phase difference is located outside the deviation range of the refresh period of the display panel, it is determined that the graphics processing unit output frame rate is asynchronous with the fixed refresh rate of the display panel.

[0008] In a possible implementation, the compensation method of the display panel further comprises: In the case that the phase difference is located within the deviation range of the refresh period of the display panel in the continuous multiple refresh periods, switching to the normal mode and resuming the data writing and data output of the first storage area.

[0009] In a possible implementation, the number of the continuous multiple refresh periods is three.

[0010] In a possible implementation, the frame buffer is arranged in the timing controller of the display panel, and the compensation method of the display panel further comprises: In the case that the duration of the compensation output exceeds a preset duration threshold in the frame compensation mode, black frame data is inserted into the display panel; An interrupt signal is sent to the graphics processing unit through an auxiliary channel, and the interrupt signal instructs the graphics processing unit to reduce the output frame rate, wherein the auxiliary channel is a communication channel for transmitting control instructions or state information between the timing controller and the graphics processing unit.

[0011] In a possible implementation, the acquiring the phase difference between the input end synchronization signal and the display panel synchronization signal comprises: The phase comparison unit of the digital phase-locked loop detects effective edges of the input synchronization signal and the display panel synchronization signal respectively; According to a local clock reference of a timing controller in the display panel, the effective edge of the input synchronization signal and the effective edge of the display panel synchronization signal are digitally sampled to obtain a first timestamp and a second timestamp; According to a time interval between the first timestamp and the second timestamp, the phase difference is obtained.

[0012] In a possible implementation, after stopping writing current frame data to the first storage area in the frame compensation mode, the method further includes: The write address pointer of the first storage area is controlled to remain at a current address.

[0013] In a possible implementation, the cyclic output of the last complete frame data from the second storage area to the display panel at a first refresh rate includes: The readout address pointer of the second storage area is reset to a start position of the last complete frame data, and all pixel information of the complete frame is output at the first refresh rate; After the output is completed, the readout address pointer is reset to the start position again, and the output process is repeated until the frame rate of the graphics processing unit is synchronized with the fixed refresh rate of the display panel.

[0014] A second aspect of an embodiment of the application provides a compensation device of a display panel, The display panel includes a frame buffer, and the frame buffer includes a first storage area and a second storage area; the first storage area is used to store current frame data, and the second storage area is used to store last complete frame data of the current frame data. The device includes: The acquisition module is configured to acquire a phase difference between an input synchronization signal and a display panel synchronization signal. The determination module is configured to determine, based on the phase difference, that a frame compensation mode is entered in a case where a frame rate of a graphics processing unit is not synchronized with a fixed refresh rate of the display panel; the display panel synchronization signal refers to a refresh period signal inside the display panel. The first compensation module is configured to stop writing the current frame data to the first storage area in the frame compensation mode. The second compensation module is configured to cyclically output last complete frame data from the second storage area to the display panel at a first refresh rate, to compensate for a case where a front-end input frame rate is different from a display panel refresh rate.

[0015] The third aspect of the embodiments of the present application provides a display screen, comprising a display panel, wherein the display panel is provided with a display panel compensation device, and the display panel compensation device is configured to execute the method steps of the first aspect.

[0016] The fourth aspect of the embodiments of the present application provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program is configured to execute the display panel compensation method of the first aspect when executed by a processor.

[0017] The fifth aspect of the embodiments of the present application provides a computer program product, which is configured to execute the display panel compensation method of the first aspect when the computer program product is executed on a display screen.

[0018] The beneficial effects of the second aspect to the fifth aspect are the same as those of the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0020] Figure 1 is a schematic diagram of the working principle of VRR provided by the embodiments of the present application; Figure 2 is a schematic diagram of the working principle of frame compensation provided by the embodiments of the present application; Figure 3 is a flowchart of a display panel compensation method provided by the embodiments of the present application; Figure 4 is a schematic diagram of a hardware architecture provided by the embodiments of the present application; Figure 5 is a flowchart of another display panel compensation method provided by the embodiments of the present application; Figure 6 is a structural schematic diagram of a display panel compensation device provided by the embodiments of the present application; Figure 7 is a structural schematic diagram of another display screen provided by the embodiments of the present application. DETAILED DESCRIPTION

[0021] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0022] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0023] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0024] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0025] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0026] It should be understood that the sequence number of each step in this embodiment does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of this application embodiment.

[0027] In high frame rate display scenarios such as gaming and video playback, screen tearing can easily occur when the output frame rate of the graphics processing unit is out of sync with the fixed refresh rate of the display panel. Existing technology, FreeSync, uses VRR to match the input frame rate, which can reduce tearing; see [link to relevant documentation] for details. Figure 1 The diagram shown illustrates the working principle of VRR. Figure 1As shown, the left side is the input end (for example, a graphics processing unit) outputting a video signal at a frame rate of 144 frames per second, and the right side is the refresh rate of the display panel being reduced to 60 Hz when the frame rate of the input end is reduced to 60 frames per second. In this mode, by dynamically adjusting the refresh rate of the display panel to match the input frame rate, picture tearing can be reduced to a certain extent. However, brightness fluctuations, gamma offset and other problems may be caused. To improve these defects, some schemes introduce a VGC function to compensate by adjusting the gamma curve.

[0028] However, the VRR+VGC scheme still has deficiencies: due to panel-to-panel differences, the same gamma lookup table (LUT) has inconsistent effects under different batches and different optical compensation conditions, and color offset is easily generated at a non-nominal refresh rate; different models need to re-measure and configure the LUT due to differences in panel process and brightness compensation nodes, increasing debugging manpower.

[0029] To solve the above problems, the embodiments of the present application provide a compensation method and device for a display panel and a display screen. The compensation method for the display panel acquires a phase difference between an input end synchronization signal and a display panel synchronization signal, and switches to a frame compensation mode in a case where it is detected that the input end output frame rate is asynchronous with the fixed refresh rate of the display panel. In the frame compensation mode, the current frame data is stopped from being written to a first storage area, and the last complete frame data is cyclically output from a second storage area at a first refresh rate, so as to prevent the valid frame data that has not been displayed from being overwritten in the output process, and to ensure the integrity and continuity of the frame data. Thus, in a high frame rate display process, the picture tearing phenomenon caused by the asynchrony between the input frame rate and the refresh rate of the display panel can be effectively improved, and the stability and smoothness of the display picture are improved. Compared with the existing scheme that relies on variable refresh rate and variable gamma control, the method eliminates picture tearing while reducing the dependence on additional hardware and complex debugging, thereby improving the consistency of the compensation effect and reducing the hardware cost.

[0030] The working principle of the frame compensation performed by the present application can be referred to Figure 2 The frame compensation working principle diagram is shown, the left side is the input end outputting a video signal at a frame rate of 60 frames per second, and the right side is the case where the display panel maintains a fixed refresh rate of 144 Hz. Among them, the light color frame is the current frame data received in real time, and the dark color frame is the compensation frame generated from the last complete frame data. When it is detected that the input frame rate is lower than the refresh rate of the display panel, the time sequence controller (TCON) stores the last complete frame in the second storage area of the frame buffer, and repeatedly outputs the frame data in the spare refresh period, so as to ensure that the refresh rate of the display panel is unchanged.

[0031] The frame compensation method of the present application can keep the display panel outputting at a fixed refresh rate, avoiding the brightness fluctuation and gamma offset caused by the refresh rate fluctuation in the VRR mode. When the input frame rate is insufficient, the complete frame is repeatedly output to prevent the picture tearing caused by the half-frame display and ensure the picture integrity. Moreover, the method does not depend on the variable refresh rate and variable gamma control function, and does not need to measure and configure the gamma compensation parameters for different refresh rates, reducing the special design requirements of the TCON chip and the driving circuit.

[0032] The compensation method, device, display screen and computer readable storage medium of the display panel proposed in the present application will be described in detail below according to the drawings.

[0033] Figure 3 A flowchart of a compensation method of a display panel provided by an embodiment of the present application is shown. In the embodiment of the present application, the display panel includes a frame buffer, the frame buffer includes a first storage area and a second storage area, the first storage area is used to store the data of a current frame, and the second storage area is used to store the data of a previous complete frame of the current frame. In a possible implementation, the compensation method of the display panel of the present application can specifically depend on Figure 4 A hardware architecture diagram is shown. The hardware architecture of the present embodiment includes a graphics processing unit (GPU) and a display panel. The display panel in the embodiment includes a display interface, a phase comparator, a first storage area, a second storage area and a timing controller.

[0034] The graphics processing unit is used to generate video frame data to be displayed and transmit the frame data and an input end synchronization signal to the timing controller through the display interface (for example, DisplayPort or HDMI interface). The phase comparator is arranged in the timing controller and is used to collect the input end synchronization signal and the display panel synchronization signal and perform phase difference calculation based on a unified clock reference. If there is a phase difference between the input end synchronization signal and the display panel synchronization signal and the phase difference is outside the deviation range of the refresh period of the display panel, it is determined that the output frame rate of the graphics processing unit is out of synchronization with the fixed refresh rate of the display panel, and the frame compensation mode is entered. If there is a phase difference between the input end synchronization signal and the display panel synchronization signal and the phase difference is within the deviation range of the refresh period of the display panel, or there is no phase difference between the two, it is determined that the output frame rate of the graphics processing unit is in synchronization with the fixed refresh rate of the display panel, and the frame compensation mode is not entered.

[0035] The first storage area is used for receiving and buffering current frame data in real time in a normal mode, and outputting the data to a display panel and synchronously copying the data to a second storage area. It should be understood that the synchronous copying action is performed by the buffer control logic of the internal frame buffer of the timing controller, which writes the real-time received current frame data into the second storage area at the same time as writing the data into the first storage area by means of bus direct writing or DMA transfer, to ensure that the data of the two storage areas is consistent.

[0036] The second storage area is used for storing last complete frame data. In the case where the phase difference is detected to be out of the deviation range of the refresh period of the display panel, the timing controller switches to a frame compensation mode, stops data writing of the first storage area, and cyclically outputs the last complete frame data from the second storage area to the display panel at a first refresh rate.

[0037] In the normal mode, the video data is directly transmitted to the display panel via the first storage area, to realize real-time display; in the frame compensation mode, the video data is provided by the second storage area, to realize fixed refresh rate output, so as to maintain picture integrity and eliminate tearing phenomenon when the input frame rate is lower than the refresh rate of the display panel.

[0038] Specifically, referring to Figure 3 The method can include the following steps: Step 301, obtaining a phase difference between an input end synchronization signal and a display panel synchronization signal; The input end synchronization signal refers to a vertical synchronization signal output by a graphics processing unit, which is used to indicate a time point at which the graphics processing unit completes output of one frame of image data and is about to start output of the next frame. The signal can be used as a representation of the input end frame output rhythm, and can be specifically obtained by analyzing timing information in an input video stream. The display panel synchronization signal refers to a refresh period signal generated internally by the display panel, which is used to indicate a time point at which a display circuit of the display panel completes scanning of a current frame of picture and starts a next frame refresh process. The signal can be used as a representation of the refresh rhythm of the display panel end, and can be specifically generated by the timing controller according to a nominal refresh rate. The phase difference refers to a time offset between effective edges of the two synchronization signals, which can be specifically detected by a phase comparison unit of a digital phase-locked loop, to determine whether the frame rate difference exceeds a permitted range by quantizing the time offset.

[0039] In the embodiments of the present application, a digital phase-locked loop circuit can be arranged internally in the timing controller, to perform phase comparison on the input end synchronization signal and the display panel synchronization signal, that is, to detect effective edges of the input end synchronization signal and the display panel synchronization signal, and to determine the phase difference between the two according to the effective edges of the two.

[0040] Specifically, in a possible implementation, obtaining the phase difference between the input end synchronization signal and the display panel synchronization signal includes: The phase comparison unit of the digital phase-locked loop detects the active edges of the input synchronization signal and the display panel synchronization signal respectively. According to the local clock reference of the timing controller in the display panel, the active edges of the input synchronization signal and the display panel synchronization signal are digitally sampled to obtain a first timestamp and a second timestamp. According to the time interval between the first timestamp and the second timestamp, the phase difference is obtained.

[0041] The phase comparison unit of the digital phase-locked loop refers to a circuit module for detecting the active edge of the synchronization signal, which can be realized by a logic circuit with edge triggering function, and the rising edge or falling edge of the input signal is locked for phase tracking.

[0042] The active edge detection refers to identifying the jump edge of the active data in the synchronization signal, which can be realized by a voltage comparator or a Schmidt trigger, and is used to determine the accurate time of signal state switching.

[0043] The digital sampling refers to converting the active edge of the analog signal into a digital time mark, which can be realized by a clock-driven time-to-digital converter, and the signal edge is timestamped by the local clock reference.

[0044] The time interval calculation refers to determining the phase difference according to the difference between the two timestamps, which can be realized by a subtracter or a counter, and the time difference is quantized to reflect the degree of phase shift of the synchronization signal.

[0045] Exemplarily, the calculation process of the phase difference is as follows: After detecting the active edge of the input synchronization signal, the first timestamp t1 is recorded, and after detecting the active edge of the display panel synchronization signal, the second timestamp t2 is recorded; according to the formula△t=min(|t1-t2|,|T ref -|t1-t2|), the time difference is calculated, where T ref is the nominal refresh period.

[0046] The time difference△t is divided by the nominal refresh period T ref to obtain the phase difference△φ.

[0047] In another possible implementation, the timing controller realizes the phase difference calculation by a double-channel counter, that is, the input synchronization signal and the panel synchronization signal are counted independently, and the difference between the count values is periodically compared to obtain the phase difference.

[0048] Step 302, based on the phase difference, determine that the graphics processing unit output frame rate is different from the fixed refresh rate of the display panel, and enter the frame compensation mode.

[0049] In a possible implementation, the phase difference is used to determine whether the frame rate output by the graphics processing unit is asynchronous with the fixed refresh rate of the display panel, including: When the phase difference is out of the deviation range of the refresh period of the display panel, it is determined that the frame rate output by the graphics processing unit is asynchronous with the fixed refresh rate of the display panel.

[0050] The refresh period of the display panel refers to a single-frame display period of the display panel at the fixed refresh rate, which can be calculated by the reciprocal of the nominal refresh rate of the display panel. For example, when the nominal refresh rate is 144 Hz, the refresh period is about 6.94 ms.

[0051] In the embodiments of the present application, the deviation range can be configured as ±5% of the nominal refresh period of the panel. For example, when the nominal refresh rate is 144 Hz, the deviation range is set to 6.94±0.35 ms.

[0052] When the phase difference is out of 6.94±0.35 ms, it is determined that the frame rate output by the graphics processing unit is asynchronous with the fixed refresh rate of the display panel and enters the frame compensation mode. When the phase difference is within 6.94±0.35 ms, it is determined that the frame rate output by the graphics processing unit is synchronous with the fixed refresh rate of the display panel and remains in the normal mode.

[0053] In another possible implementation, to prevent false triggering caused by transient fluctuations, the compensation mode can be entered only when the out-of-limit phase difference is detected for two or three times in succession. This multi-cycle confirmation mechanism can improve stability.

[0054] In step 303, in the frame compensation mode, the writing of current frame data to the first storage area is stopped.

[0055] The frame compensation mode refers to a running state in which the reception of new frame data is suspended and historical frames are repeatedly output. The frame compensation mode can be implemented by controlling the read / write enable signals of the frame buffer, and is used to maintain display stability when the input frame rate is abnormal.

[0056] In a possible implementation, the present application further provides that after the frame compensation mode is detected and the writing of current frame data to the first storage area is stopped, the writing address pointer of the first storage area is kept in a frozen state.

[0057] The freeze state refers to a state in which a write operation is paused and an address pointer is no longer updated, and can be implemented by locking a clock signal of an address generation circuit or forcing an address counter to keep a current value. The freeze state is used to prevent new data from overwriting original data and ensure the integrity of the last complete frame data stored in the second storage area. The write address pointer refers to a register variable used to indicate a data write position, and can be implemented by using a circular counter structure of a circular buffer. By keeping the freeze state of the pointer, the logical consistency of the data storage position can be maintained, and data misplacement caused by address jumping in the frame compensation mode can be avoided.

[0058] Specifically, when the phase difference exceeds the deviation range of the nominal refresh period, the timing controller generates a mode switching instruction to trigger the freeze operation. At this time, the write enable signal of the first storage area is set to an invalid state, for example, by using a gate circuit to cut off the data bus transmission path. At the same time, the address pointer control module latches the value of the current write address register, for example, using a D flip-flop to save the current address value, and continuously outputs the fixed address value to the address bus of the memory during the freeze period. This mechanism allows the first storage area to maintain a static storage state during the compensation phase, while the second storage area cyclically outputs the stored complete frame data at a preset refresh rate, for example, continuously reading the pixel information of the last frame at a fixed frequency of 60Hz or 120Hz.

[0059] Step 304: cyclically outputting the last complete frame data from the second storage area to the display panel at a first refresh rate to compensate for the case that the front-end input frame rate is different from the refresh rate of the display panel.

[0060] The first storage area and the second storage area refer to two physically isolated or logically divided storage spaces in the frame buffer, which ensure that real-time reception and historical data reading do not interfere with each other.

[0061] The first refresh rate can refer to the nominal refresh rate of the display panel, which is configured by the timing controller, for example, 120Hz or 144Hz, and is used to maintain a fixed output rhythm in the compensation mode.

[0062] In the embodiments of the present application, when the phase difference is outside the deviation range of the refresh period of the display panel, it is determined that there is a risk of mismatch between the input frame rate and the display refresh rate. At this time, the write operation of the first storage area is stopped, and the reception of new current frame data is stopped, and the last complete frame data stored in the second storage area is cyclically output to the display panel at a first refresh rate. By using historical frame data to fill the display blank period caused by input frame rate fluctuation, picture tearing or display interruption caused by sudden change of input frame rate is avoided.

[0063] In another possible implementation, the present application further proposes to cyclically output the last complete frame data from the second storage area to the display panel at a first refresh rate, comprising: resetting the readout address pointer of the second storage area to the start position of the previous full frame data, and outputting all pixel information of the full frame at the first refresh rate; After the output is completed, the readout address pointer is reset to the start position again, and the above output process is repeated until the frame rate output by the graphics processing unit is synchronized with the fixed refresh rate of the display panel. The readout address pointer reset refers to resetting the read position of the storage area to the start of the data, which can be implemented by clearing the address register or presetting the initial value, ensuring that each cycle of output starts from the first pixel of the full frame data.

[0064] The all pixel information refers to the frame buffer content containing complete image data, which can be implemented by line-by-line scanning or block transmission, ensuring that the brightness and color information of each pixel are completely output to the display panel.

[0065] Specifically, in the frame compensation mode, the previous full frame data stored in the second storage area is set as the object of cyclic output. When it is detected that the input frame rate is out of synchronization with the refresh rate of the display panel, the readout address pointer of the second storage area is forcibly reset to the start address of the frame data by the timing controller, and then all pixel data is periodically traversed and output according to the first refresh rate of the display panel. For example, in a display panel with a refresh rate of 60Hz, the cyclic output of the full frame data is completed every 16.67ms until the input frame rate returns to the synchronized state. Compared with the prior art, the conventional scheme needs to dynamically adjust the gamma parameters to compensate for color deviation when the input frame rate fluctuates, while the present scheme maintains a stable data source by stopping the write operation, avoiding multiple gamma parameter adjustments caused by the difference between the input frame rate and the refresh rate. For example, in the prior art, different lookup tables need to be called for compensation every time the input frame rate changes, while in the present scheme, the previous full frame data is fixedly output, so that the display panel always works at the first refresh rate during the compensation stage, without triggering the gamma correction process under the non-first refresh rate.

[0066] The above is a compensation method of a display panel provided by the embodiment of the present application. By obtaining the phase difference between the input end synchronization signal and the display panel synchronization signal, the frame compensation mode is switched in time in the case that the input end output frame rate is detected to be asynchronous with the display panel fixed refresh rate. In the frame compensation mode, the current frame data is stopped from being written to the first storage area, and the last complete frame data is output in a cycle from the second storage area at the first refresh rate, so as to prevent the valid frame data that has not been displayed yet from being overwritten in the output process, and ensure the integrity and continuity of the frame data. Thus, in the high frame rate display process, the picture tearing phenomenon caused by the asynchronization between the input frame rate and the display panel refresh rate can be effectively improved, and the stability and smoothness of the display picture are improved. Compared with the existing scheme that relies on variable refresh rate and variable gamma control, the method eliminates the picture tearing while reducing the dependence on additional hardware and complex debugging, thereby improving the compensation effect consistency and reducing the hardware cost.

[0067] In a possible implementation, the present application further proposes that when the phase difference is detected to be located in the deviation range of the refresh period of the display panel in continuous multiple refresh periods, the normal mode is switched to, and the data writing and data output of the first storage area are resumed.

[0068] The continuous multiple refresh periods refer to that the phase difference detection needs to be verified for stability in a time window of multiple complete refresh periods, and the number of periods meeting the deviation range can be accumulated by using a counter, for example, the mode switching is triggered when the counter reaches a set threshold. The normal mode refers to the state that the timing controller receives the current frame data in real time and outputs the current frame data to the display panel according to the standard working process, and the normal mode can be realized by resetting the write address pointer and canceling the freezing operation of the storage area.

[0069] Specifically, when the phase difference is in the deviation range in continuous multiple refresh periods, it is indicated that the synchronization state of the input end and the display panel has been restored to stability. At this time, the number of periods meeting the deviation range is accumulated by using a counter, and when the accumulated value reaches a set threshold, the timing controller switches the working mode from the frame compensation mode back to the normal mode. In the switching process, the write address pointer of the first storage area is reactivated to allow the new current frame data to overwrite the original stopped input content, and the data output channel is switched to the first storage area to restore the real-time display update. This mechanism ensures that the mode switching is performed only after the input frame rate and the display panel refresh rate are kept synchronous for a long time, thereby avoiding the display abnormalities caused by frequent switching due to instantaneous phase fluctuation.

[0070] Compared with the prior art, the traditional scheme switches the working mode immediately when detecting single phase difference recovery, which is easy to misjudge due to noise interference or instantaneous jitter, resulting in repeated switching of the mode. The scheme effectively filters short-term phase fluctuation interference through a continuous multi-cycle detection mechanism, and only performs mode switching after the input signal and the panel refresh rate are stably synchronized, thereby significantly improving the anti-interference ability and operation stability of the system.

[0071] In another possible implementation, the application further proposes, in the frame compensation mode, when the duration of the compensation output exceeds a preset duration threshold, inserting black frame data into the display panel; sending an interrupt signal to the graphics processing unit through an auxiliary channel to instruct the graphics processing unit to reduce the output frame rate, wherein the auxiliary channel is a communication channel for transmitting control instructions or state information between the timing controller and the graphics processing unit.

[0072] The preset duration threshold refers to a time threshold for triggering the insertion of black frame data, which can be a fixed time value, for example, 2 to 5 nominal refresh periods. The threshold is used to determine whether the duration of the compensation mode is too long to avoid picture retention or color shift caused by repeatedly outputting the same frame data. The black frame data refers to an image frame containing all black pixel information, which can be implemented by generating a pixel matrix with all zero luminance values. Its role is to temporarily stop the output of valid images during the compensation process, reducing visual retention caused by long-term display of static images.

[0073] Specifically, in the frame compensation mode, when it is detected that the compensation duration exceeds the preset duration threshold, the timing controller generates black frame data and inserts it into the driving signal of the display panel. At this time, the pixel units of the display panel are forced to refresh to the all-black state, avoiding picture retention caused by continuously outputting the last complete frame data. At the same time, an interrupt signal is sent to the graphics processing unit through the auxiliary channel, which carries frame rate adjustment instructions, such as reducing the output frame rate by a certain percentage or switching to a specific frame rate mode. After receiving the interrupt signal, the graphics processing unit adjusts the frame rate output of the image generation module according to the instructions, so that it is re-synchronized with the refresh rate of the display panel. For example, if the nominal refresh rate of the display panel is 120Hz, and the current output frame rate of the input end is 144Hz, the interrupt signal can instruct the input end to reduce the frame rate to 120Hz.

[0074] This embodiment solves the problems of picture retention and color shift in long-term frame compensation mode, actively intervenes in the frame rate output of the input end, realizes dynamic synchronization of the input and display ends, and avoids visual abnormalities caused by repeatedly outputting the same frame data. At the same time, the interrupt signal is transmitted through the auxiliary channel, without relying on complex gamma adjustment algorithms to achieve frame rate matching, thereby reducing the risk of color consistency caused by panel batch differences.

[0075] According to the above-mentioned embodiments, the specific process of the present application can be seen from Figure 5 The flowchart of another compensation method of the display panel provided by the embodiment of the present application is shown, and the specific scheme will be exemplarily described below.

[0076] Firstly, the display panel receives the frame data signal input from the GPU and detects whether the input terminal synchronization signal and the display panel synchronization signal are in a synchronization state. If the detection result is synchronization, the current frame data is written into the first storage area, and the refresh output is performed in the normal mode.

[0077] If the detection result is not synchronization, the data reading operation of the second storage area (i.e. the storage area for storing the last complete frame data) is started. During the data reading operation, the system continuously detects the phase difference between the input terminal synchronization signal and the display panel synchronization signal. Each time the phase difference is detected, if the phase difference still exceeds the deviation range, the delay counter is increased by 1; if this exceeding range occurs in the continuous n refresh cycles (n is a preset value, such as 3), the subsequent action (such as inserting a black frame, reducing the GPU frame rate, etc.) is triggered.

[0078] When the continuous delay count does not reach n, the compensation output flow is executed, that is, a compensation frame is inserted in the display output to maintain the continuity and stability of the picture, and the refresh output is performed according to the nominal refresh rate of the display panel.

[0079] When the continuous delay count reaches or exceeds n, the protection mechanism (inserting a black frame) is triggered, and an interrupt signal is sent to the GPU through the auxiliary channel to indicate that the output frame rate is reduced to restore the synchronization state.

[0080] Through the above-mentioned flow, when the front-end input frame rate and the display panel refresh rate do not match, the compensation mode or the protection mode can be dynamically switched, so as to effectively reduce the picture tearing and the lag phenomenon, and improve the display fluency and stability.

[0081] Referring to Figure 6 The structure diagram of a compensation device of a display panel provided by the embodiment of the present application is shown, and only the part related to the embodiment of the present application is shown for the convenience of description.

[0082] The display panel includes a frame buffer, and the frame buffer includes a first storage area and a second storage area. The first storage area is used for storing current frame data, and the second storage area is used for storing the last complete frame data of the current frame data. The compensation device 600 of the display panel includes: The acquisition module 601 is configured to acquire the phase difference between the input terminal synchronization signal and the display panel synchronization signal. The determining module 602 is configured to determine, based on the phase difference, that the GPU output frame rate is asynchronous with the fixed refresh rate of the display panel, and enter a frame compensation mode; the display panel synchronization signal refers to a refresh cycle signal inside the display panel. The first compensation module 603 is configured to, in the frame compensation mode, stop writing current frame data to the first storage area. The second compensation module 604 is configured to cyclically output the last complete frame data from the second storage area to the display panel at the first refresh rate, to compensate for the case that the front-end input frame rate is different from the refresh rate of the display panel.

[0083] In the embodiments of the present application, the determining module 602 can further include: The judging unit is configured to determine that the GPU output frame rate is asynchronous with the fixed refresh rate of the display panel, in the case that the phase difference is located outside the deviation range of the refresh cycle of the display panel.

[0084] In the embodiments of the present application, the compensation device 600 of the display panel can further include: The switching module is configured to, when it is detected that the phase difference is located within the deviation range of the refresh cycle of the display panel in the continuous multiple refresh cycles, switch to a normal mode, and restore the data writing and data output of the first storage area.

[0085] In the embodiments of the present application, the frame buffer is arranged in a timing controller of the display panel, and the compensation device 600 of the display panel can further include: The insertion module is configured to, in the frame compensation mode, insert black frame data into the display panel in the case that the duration of the compensation output exceeds a preset duration threshold. The interrupt sending module is configured to send an interrupt signal to the GPU through an auxiliary channel, the interrupt signal instructing the GPU to reduce the output frame rate, wherein the auxiliary channel is a communication channel for transmitting control instructions or state information between the timing controller and the GPU.

[0086] In the embodiments of the present application, the acquiring module 601 further includes: The phase comparison unit is configured to detect the active edges of the input synchronization signal and the display panel synchronization signal respectively. The digital sampling unit is configured to digitally sample the active edges of the input synchronization signal and the display panel synchronization signal according to a local clock reference of the timing controller in the display panel, to obtain a first timestamp and a second timestamp. The calculation unit is configured to acquire the phase difference according to the time interval between the first timestamp and the second timestamp.

[0087] In the embodiments of the present application, the compensation device 600 of the display panel can further include: The pointer freeze unit is used to keep the write address pointer of the first storage area in a frozen state.

[0088] In this embodiment of the application, the second compensation module 604 further includes: The pointer reset unit is used to reset the read address pointer of the second storage area to the starting position of the previous complete frame data, and output all pixel information of the complete frame at the first refresh rate. The loop output unit is used to reset the read address pointer to the starting position after the output is completed, and repeat the above output process until the output frame rate of the graphics processing unit is synchronized with the fixed refresh rate of the display panel.

[0089] In this embodiment of the application, the number of consecutive refresh cycles is three.

[0090] The display panel compensation device 600 provided in this application embodiment can be applied to the display panel compensation method provided in the foregoing embodiment. For details, please refer to the description of the display panel compensation method provided in the above embodiment, which will not be repeated here.

[0091] In one possible embodiment of this application, the display screen includes a display panel, and the display panel is provided with a compensation device for the display panel, which is used to execute the process in the above method embodiment.

[0092] Figure 7 This is a schematic diagram of the structure of a display screen provided in an embodiment of this application. For example... Figure 7 As shown, the display screen 700 of this embodiment includes: at least one processor 710 ( Figure 7 (Only one is shown in the diagram) a processor, a memory 720, and a computer program 721 stored in the memory 720 and executable on at least one processor 710. When the processor 710 executes the computer program 721, it implements the steps in the above-described compensation method embodiment for the display panel.

[0093] The display screen 700 can be an LED display screen, an LCD display screen, or a miniLED display screen, etc. This display screen may include, but is not limited to, a processor 710 and a memory 720. Those skilled in the art will understand that... Figure 7 The display screen 700 is merely an example and does not constitute a limitation on the display screen 700. It may include more or fewer components than shown, or combine certain components, or different components, such as input / output devices, network access devices, etc.

[0094] The processor 710 can be a central processing unit (CPU), and can also be other general-purpose processors, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor.

[0095] The memory 720 can be an internal storage unit of the display screen 700 in some embodiments, for example, a hard disk or a memory of the display screen 700. The memory 720 can also be an external storage device of the display screen 700 in other embodiments, for example, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. Further, the memory 720 can include both the internal storage unit and the external storage device of the display screen 700. The memory 720 is used to store an operating system, an application program, a boot loader, data and other programs, for example, program codes of computer programs, etc. The memory 720 can also be used to temporarily store data that has been output or will be output.

[0096] In a specific implementation, the processor 710, the memory 720 and the computer program 721 described in the embodiments of the present application can execute the embodiments of the compensation method of the display panel of the present application, which will not be described herein again.

[0097] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above-mentioned division of each functional unit and module is exemplified, and in actual application, the above-mentioned functions can be completed by different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be realized in the form of hardware or software function unit. In addition, the specific name of each functional unit and module is only for the convenience of mutual distinction, and does not limit the protection scope of the present application. The specific working process of the unit and module in the above system can refer to the corresponding process in the foregoing method embodiment, which will not be described here.

[0098] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described or recorded in detail in a certain embodiment can be referred to the related description of other embodiments.

[0099] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized in electronic hardware or a combination of computer software and electronic hardware. Whether the functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. A person skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0100] In the embodiments provided in the present application, it should be understood that the disclosed device / display screen and method can be implemented in other ways. For example, the device / display screen embodiments described above are only schematic, and the division of modules or units is only a logical function division, and there can be another division in actual implementation, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units or components shown or discussed can be indirect coupling or communication connection through some interface, device or unit, and can be electrical, mechanical or other forms.

[0101] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0102] In addition, each of the function units in each of the embodiments of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software function unit.

[0103] If the integrated module / unit is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on such understanding, all or part of the processes in the above-mentioned embodiment methods can also be completed by a computer program instructing related hardware, and the computer program can be stored in a computer readable storage medium. When the computer program is executed by a processor, the steps of each method embodiment described above can be implemented. The computer program includes computer program code, which can be in the form of source code, object code, executable file, or some intermediate form. The computer readable medium can include any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium, etc. It should be noted that the content included in the computer readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction, for example, in some jurisdictions, according to legislation and patent practice, the computer readable medium does not include electrical carrier signals and telecommunication signals.

[0104] The above-mentioned embodiment methods can also be completed by a computer program product, when the computer program product runs on the display screen, so that the display screen can implement the steps in each of the above-mentioned method embodiments.

[0105] The above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements to some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A compensation method of a display panel, characterized by, The display panel comprises a frame buffer, the frame buffer comprises a first storage area and a second storage area, the first storage area is used for storing current frame data, and the second storage area is used for storing previous complete frame data of the current frame data; the method comprises the following steps: obtaining a phase difference between an input end synchronization signal and a display panel synchronization signal; determining, based on the phase difference, that the output frame rate of a graphics processing unit is out of synchronization with the fixed refresh rate of the display panel, and entering a frame compensation mode; the display panel synchronization signal refers to a refresh cycle signal inside the display panel; in the frame compensation mode, stopping writing the current frame data to the first storage area; recycling the previous complete frame data from the second storage area to the display panel at a first refresh rate to compensate for the case that the input frame rate of the front end is different from the refresh rate of the display panel.

2. The method of claim 1, wherein determining, based on the phase difference, that the output frame rate of the graphics processing unit is out of synchronization with the fixed refresh rate of the display panel comprises: determining that the output frame rate of the graphics processing unit is out of synchronization with the fixed refresh rate of the display panel when the phase difference is outside the deviation range of the refresh cycle of the display panel.

3. The compensation method of a display panel according to claim 1, wherein The compensation method of the display panel further comprises: when it is detected that the phase difference is within the deviation range of the refresh cycle of the display panel for a plurality of continuous refresh cycles, switching to a normal mode and resuming data writing and data output of the first storage area.

4. The compensation method of a display panel according to claim 1, wherein The frame buffer is arranged in a timing controller of the display panel, and the compensation method of the display panel further comprises: in the frame compensation mode, inserting black frame data into the display panel when the duration of the compensation output exceeds a preset duration threshold; sending an interrupt signal to the graphics processing unit through an auxiliary channel, the interrupt signal instructing the graphics processing unit to reduce the output frame rate, wherein the auxiliary channel is a communication channel for transmitting control instructions or state information between the timing controller and the graphics processing unit.

5. The compensation method of a display panel according to claim 1, wherein The method of obtaining a phase difference between an input end synchronization signal and a display panel synchronization signal comprises: detecting, by a phase comparison unit of a digital phase-locked loop, active edges of the input end synchronization signal and the display panel synchronization signal, respectively; digitally sampling the active edges of the input end synchronization signal and the display panel synchronization signal according to a local clock reference of a timing controller in the display panel to obtain a first timestamp and a second timestamp; obtaining the phase difference according to a time interval between the first timestamp and the second timestamp.

6. The compensation method of a display panel according to claim 1, wherein After stopping writing the current frame data to the first storage area in the frame compensation mode, the method further comprises: maintaining the write address pointer of the first storage area in a frozen state.

7. The compensation method of a display panel according to any one of claims 1 to 6, wherein The method of recycling the previous complete frame data from the second storage area to the display panel at a first refresh rate comprises: resetting a readout address pointer of the second storage area to the starting position of the previous complete frame data and outputting all pixel information of the complete frame at the first refresh rate; After the output is completed, the readout address pointer is reset to the start position again, and the above output process is repeated until the frame rate of the graphics processing unit is synchronized with the fixed refresh rate of the display panel.

8. A compensation device of a display panel, characterized by, The display panel comprises a frame buffer, the frame buffer comprises a first storage area and a second storage area, the first storage area is used for storing current frame data, and the second storage area is used for storing previous complete frame data of the current frame data. The device comprises: an acquisition module configured to acquire a phase difference between an input end synchronization signal and a display panel synchronization signal; a determination module configured to determine, based on the phase difference, whether to enter a frame compensation mode when a frame rate of a graphics processing unit is not synchronized with a fixed refresh rate of the display panel; the display panel synchronization signal refers to a refresh period signal inside the display panel; a first compensation module configured to, in the frame compensation mode, stop writing the current frame data to the first storage area; a second compensation module configured to, in the frame compensation mode, output previous complete frame data from the second storage area to the display panel at a first refresh rate to compensate for a case where an input end frame rate is different from a display panel refresh rate.

9. A display screen, characterized by A display panel comprising a compensation device for the display panel, the compensation device for the display panel being configured to perform the method of any one of claims 1 to 7.

10. A computer program product, characterised in that, The program product, when running on a display screen, causes the display screen to perform the method of any one of claims 1 to 7.

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