Constant-speed high-frame-rate projection control circuit and method and industrial light machine

Abstract

The application discloses a kind of constant-speed high frame rate projection control circuit, method and industrial light machine, circuit includes: main control module, DLP control module, DLP display module, light source driving module, first external control module and second external control module;Main control module includes main control unit and PWM trigger unit;Main control unit is used to receive the trigger input signal of first external control module, and PWM trigger unit is used to generate PWM pulse signal and trigger DLP control module;DLP control module is used to control projection picture according to PWM pulse signal;DLP display module and light source driving module are used to realize structured light output according to projection picture;DLP control module is used to send synchronization signal to camera acquisition when controlling projection picture;Main control unit is used to generate trigger output signal to second external control module after synchronization signal reaches preset quantity.The application can output structured light at constant speed and high frame rate;Support external one-time trigger, the function of projecting one group or multiple groups of patterns.

Description

Technical Field

[0001] This invention relates to the field of structured light projection technology, and in particular to a uniform speed high frame rate projection control circuit, method, and industrial optomechanic. Background Technology

[0002] Structured light is a system consisting of a projector and a camera. Specific light information is projected onto the surface of an object and its background by the projector, and then captured by the camera. Based on the changes in the light signal caused by the object, information such as the object's position and depth is calculated, thus reconstructing the entire three-dimensional space.

[0003] TI has launched industrial DMDs (Digital Micromirror Devices) such as the DLP2010LC, 3010LC, and 4710LC, along with matching DLPC controllers (optical controllers for DLP technology). The DLPC controller provides internal 1-bit and 8-bit 1D stripe pattern structured light projection, commonly used in 3D AOI (Automated Optical Inspection), SPI (Solder's Solder Paste Inspection), and visual scanning. The DLPC internal mode projection supports accepting external `runonce` commands to trigger a complete batch of image projections at once, and `trigger in` to trigger single-image projection. It supports configuring the pattern set exposure sequence (Pattern set order table), i.e., setting 1-N pattern set exposure cycles (pre-dark time + exposure time + post-dark time) to control the frame rate. Digital structured light projection is achieved by controlling the LED light source and the DMD micromirrors through the DLP controller. However, it has the following shortcomings:

[0004] 1) DLPC supports RUNONCE command projection, which requires sending an IIC command to DLPC and waiting for preloading processing. The delay is more than 5-20ms before projection begins (the configured exposure cycle time affects the projection delay time), resulting in a decrease in the overall frame rate.

[0005] 2) DLPC supports TRIGGER IN single-image projection, but only a single image can be projected at a time. Multiple external triggers are required to complete a full projection round. It does not support projecting an entire pattern set group at once, or projecting all pattern sets in one round at once.

[0006] 3) The internal pattern is stored and loaded in groups according to pattern set. Each pattern set can store a maximum of 7-8 8-bit 1D images (taking DLP4710 as an example, a maximum of 7 horizontal images and a maximum of 8 vertical images). It cannot directly support pattern set sets with more patterns.

[0007] 4) If the exposure projection frame rate of a pattern that loops within a single pattern set can reach a maximum of 427 frames per second (because it does not need to be reloaded), the total number of patterns in a single pattern set cannot meet the customer's needs.

[0008] 5) Since most structured light projection applications use at least 10 patterns, multiple pattern sets are needed for projection. When switching to the next pattern set, there is an additional loading time; the more patterns the next pattern set contains, the longer the loading time. Therefore, it is impossible to project structured light at a uniform high frame rate.

[0009] 6) Due to cost and other reasons, the maximum frame rate of the matching high-resolution industrial camera is lower than that of the DLP optical engine projection. In this case, the projection frame rate must be reduced to match the camera's maximum frame rate to ensure the industrial camera can work normally. However, after reducing the frame rate, due to the switching loading time in multiple pattern sets mentioned above, the average combined projection frame rate and camera acquisition frame rate will again be lower than the camera's maximum frame rate, resulting in camera idle waiting. Therefore, inventing a uniform high frame rate projection control circuit is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0010] The purpose of this application is to provide a uniform high frame rate projection control circuit and an industrial optical engine. In this solution, the main control unit receives the trigger input signal from the first external control module, and the PWM trigger unit generates a PWM pulse signal to trigger the DLP control module. The DLP control module controls the projected image according to the PWM pulse signal. The DLP display module and the light source driving module are used to realize structured light output based on the projected image. When controlling the projected image, the DLP control module sends a synchronization signal to the camera for acquisition. After the synchronization signal reaches a preset number, the main control unit generates a trigger output signal to the second external control module, realizing the function of projecting one or more patterns with one external trigger, and realizing uniform high frame rate projection output of structured light.

[0011] To address the aforementioned technical problems, this application provides a uniform high frame rate projection control circuit, comprising a main control module, a DLP control module, a DLP display module, a light source driving module, a first external control module, and a second external control module; the main control module includes a main control unit and a PWM triggering unit;

[0012] The main control unit is electrically connected to the first external control module, the PWM triggering unit is electrically connected to the main control unit, the DLP control module is electrically connected to the PWM triggering unit, and the DLP display module is electrically connected to the DLP control module;

[0013] The light source driving module is electrically connected to the DLP control module, and both the DLP control module and the main control unit are electrically connected to the second external control module.

[0014] The main control unit is used to receive the trigger input signal from the first external control module, and the PWM triggering unit is used to generate a PWM pulse signal to trigger the DLP control module.

[0015] The DLP control module is used to control the display processing of the projected image based on the PWM pulse signal; the DLP display module and the light source driving module are used to realize structured light output based on the projected image;

[0016] The DLP control module is used to send a synchronization signal to the camera for acquisition when controlling the projected image;

[0017] The main control unit is used to generate a trigger output signal to the second external control module after the synchronization signal reaches a preset number.

[0018] Preferably, the uniform high frame rate projection control circuit further includes an input filtering module;

[0019] The first external control module is electrically connected to the input filtering module, and the main control unit is electrically connected to the input filtering module.

[0020] Preferably, the uniform high frame rate projection control circuit further includes an isolation output module;

[0021] The second external control module is electrically connected to the isolation output module, and the isolation output module is electrically connected to the main control unit.

[0022] Preferably, the uniform high frame rate projection control circuit further includes a USB module and a FLASH storage module;

[0023] The USB module is electrically connected to the host computer, the DLP control module, and the FLASH storage module, respectively, and the FLASH storage module is electrically connected to the DLP control module.

[0024] The USB module is used to burn projection data;

[0025] The FLASH storage module is used to load the configuration for startup initialization.

[0026] Preferably, the main control module further includes a bus transceiver unit, an input buffer unit, and an output buffer unit;

[0027] The bus transceiver unit is electrically connected to the input buffer unit and the output buffer unit, respectively;

[0028] The input buffer unit is electrically connected to the input filtering module and the DLP control module, respectively;

[0029] The output buffer unit is electrically connected to both the isolated output module and the DLP control module.

[0030] Preferably, the main control module further includes a debugging unit;

[0031] The debugging unit is electrically connected to the main control unit.

[0032] To address the aforementioned technical problems, this application also provides a uniform high frame rate projection control method, the method comprising:

[0033] Receive the trigger input signal from the first external control module;

[0034] The DLP control module is triggered by generating a PWM pulse signal based on the trigger input signal.

[0035] The display processing control of the projected image is performed based on the PWM pulse signal;

[0036] Structured light output is achieved based on the projected image;

[0037] When controlling the projected image, a synchronization signal is sent to the camera for acquisition;

[0038] After the synchronization signal reaches a preset number, a trigger output signal is generated and sent to the second external control module.

[0039] Preferably, the method further includes:

[0040] The pattern set is encapsulated by performing a pattern set encapsulation at the upper layer of the host computer.

[0041] Keep the loading time of each pattern set consistent.

[0042] Preferably, the method further includes:

[0043] Obtain the total cycle time of the pattern set, including the pre-dark time, exposure time, post-dark time, and loading time, for a complete exposure cycle.

[0044] Obtain the total dark field time by combining the previous dark field time and the subsequent dark field time;

[0045] Obtain the difference between the total dark field time and the loading time, wherein the difference satisfies the condition of minimizing the sum of the dark field times before and after loading.

[0046] To address the aforementioned technical problems, this application provides an industrial optical engine, including the aforementioned uniform high frame rate projection control circuit.

[0047] The present invention discloses a uniform high frame rate projection control circuit with the following beneficial effects. The uniform high frame rate projection control circuit includes: a main control module, a DLP control module, a DLP display module, a light source driving module, a first external control module, and a second external control module. The main control module includes a main control unit and a PWM trigger unit. The main control unit receives a trigger input signal from the first external control module, and the PWM trigger unit generates a PWM pulse signal to trigger the DLP control module. The DLP control module controls the display processing of the projected image based on the PWM pulse signal. The DLP display module and the light source driving module implement structured light output based on the projected image. The DLP control module sends a synchronization signal to the camera for acquisition when controlling the projected image. The main control unit generates a trigger output signal to the second external control module after the synchronization signal reaches a preset number. This invention triggers the DLP control module via a PWM trigger unit, allowing the DLP control module to project one image at a time. Furthermore, each time the DLP control module begins projecting an image, it sends a synchronization signal to an external camera for acquisition. After a preset number of synchronization signals are received, the main control module outputs continuous trigger signals, achieving uniform high-frame-rate projection control. Therefore, this invention can project structured light at a uniform high frame rate with high reliability. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the present invention will be further described below in conjunction with the accompanying drawings and embodiments. The drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort:

[0049] Figure 1 This is a schematic diagram of a uniform high frame rate projection control circuit according to a preferred embodiment of the present invention.

[0050] Figure 2 This is a schematic diagram of a uniform high frame rate projection control circuit according to a preferred embodiment of the present invention.

[0051] Figure 3 This is a schematic diagram of a uniform high frame rate projection control circuit according to a preferred embodiment of the present invention.

[0052] Figure 4 This is a schematic diagram of a uniform high frame rate projection control circuit according to a preferred embodiment of the present invention.

[0053] Figure 5 This is a schematic diagram of a uniform high frame rate projection control circuit according to a preferred embodiment of the present invention.

[0054] Figure 6 This is a schematic diagram of a preferred embodiment of the present invention for a uniform high frame rate projection control method;

[0055] Figure 7 This is a timing diagram of a uniform high frame rate projection control method according to a preferred embodiment of the present invention;

[0056] Figure 8 This is an exposure configuration data chart of a preferred embodiment of the present invention for a uniform high frame rate projection control method;

[0057] Figure 9 This is an exposure configuration data chart of a preferred embodiment of the present invention for a uniform high frame rate projection control method;

[0058] Figure 10 This is an exposure configuration data chart of a uniform high frame rate projection control method according to a preferred embodiment of the present invention. Detailed Implementation

[0059] The core of this application is to provide a uniform high frame rate projection control circuit and an industrial optical engine. In this solution, the PWM trigger unit triggers the DLP control module, which supports projecting one image at a time. Furthermore, each time the DLP control module starts projecting an image, it sends a synchronization signal to the external camera for acquisition. After the synchronization signal reaches a preset number, the main control module outputs continuous trigger signals, achieving uniform high frame rate projection control.

[0060] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0061] Please see Figure 1 , Figure 1 A schematic diagram of a uniform high frame rate projection control circuit provided in this application includes a main control module 1, a DLP control module 2, a DLP display module 3, a light source driving module 4, a first external control module 5, and a second external control module 6; the main control module 1 includes a main control unit 11 and a PWM triggering unit 12.

[0062] The main control unit 11 is electrically connected to the first external control module 5, the PWM trigger unit 12 is electrically connected to the main control unit 11, the DLP control module 2 is electrically connected to the PWM trigger unit 12, and the DLP display module 3 is electrically connected to the DLP control module 2.

[0063] The light source driving module 4 is electrically connected to the DLP control module 2, and both the DLP control module 2 and the main control unit 11 are electrically connected to the second external control module 6.

[0064] The main control unit 11 is used to receive the trigger input signal of the first external control module 5, and the PWM trigger unit 12 is used to generate a PWM pulse signal to trigger the DLP control module 2;

[0065] DLP control module 2 is used to control the projected image based on PWM pulse signals; DLP display module 3 and light source driving module 4 are used to realize structured light output based on the projected image.

[0066] DLP control module 2 is used to send a synchronization signal to the camera for acquisition when controlling the projected image;

[0067] The main control unit 11 is used to generate a trigger output signal to the second external control module 6 after the synchronization signal reaches a preset number.

[0068] In existing technologies, structured light is a system consisting of a projector and a camera. Specific light information is projected onto the surface of an object and its background by the projector, and then captured by the camera. Based on the changes in the light signal caused by the object, information such as the object's position and depth is calculated, thus reconstructing the entire three-dimensional space. In a DLP projector, the display chip is the imaging device. The chip contains millions of micromirrors, each with the ability to independently control the switching of light. When light from the light source passes through the color wheel and reaches the display chip, the micromirrors adjust the reflected light, thereby forming images with different levels of grayscale.

[0069] TI's DLPC controller supports RUNONCE command projection in its internal mode, but this requires sending an IIC command to the DLPC and waiting for preloading, resulting in a delay of 5-20ms or more before external projection begins, leading to a decrease in the overall frame rate. Furthermore, due to the limitations of the DLPC runonce command mechanism, and the influence of IIC command processing, pattern loading, and configured projection exposure cycles, the 5-20ms trigger wait time cannot be eliminated.

[0070] To address the aforementioned shortcomings, such as Figure 1As shown, this application utilizes a main control module 1, a DLP control module 2, a DLP display module 3, a light source driving module 4, a first external control module 5, and a second external control module 6. The main control module 1 includes a main control unit 11 and a PWM trigger unit 12 working together to switch to DLPC trigger input. By setting the PWM trigger unit, the DLP control module is triggered. When the DLP control module starts projecting an image, it sends a synchronization signal to the external camera for acquisition. After the synchronization signal reaches a preset number, the main control module outputs continuous trigger signals to achieve uniform high frame rate projection control.

[0071] In summary, this application of the present invention provides a uniform high frame rate projection control circuit. In this scheme, the main control unit 11 is used to receive the trigger input signal from the first external control module 5, and the PWM trigger unit 12 is used to generate a PWM pulse signal to trigger the DLP control module 2. The DLP control module 2 is used to control the display processing of the projected image according to the PWM pulse signal. The DLP display module 3 and the light source driving module 4 are used to realize structured light output according to the projected image. The DLP control module 2 is used to send a synchronization signal to the camera for acquisition when controlling the projected image. The main control unit 11 is used to generate a trigger output signal to the second external control module after the synchronization signal reaches a preset number. The present invention triggers the DLP control module through the PWM trigger unit, and the DLP control module supports projecting one image at a time. In addition, when the DLP control module starts projecting one image, it sends a synchronization signal to the external camera for acquisition. After the synchronization signal reaches a preset number, the main control module outputs continuous trigger signals to realize uniform high frame rate projection control. Therefore, the present invention can project structured light at a uniform high frame rate with high reliability.

[0072] Based on the above embodiments:

[0073] Please refer to Figure 2 , Figure 2 This is a schematic diagram of a uniform high frame rate projection control circuit provided in this application.

[0074] In one preferred embodiment, a uniform high frame rate projection control circuit further includes an input filtering module 7;

[0075] The first external control module 5 is electrically connected to the input filtering module 7, and the main control unit 11 is electrically connected to the input filtering module 7.

[0076] Specifically, after being triggered by the trigger, the main control unit 11 receives the trigger input signal trigger in from the first external control module 5. The input filtering module is used to filter the trigger input signal trigger in, thereby filtering out high-frequency noise from the trigger input signal trigger in and ensuring the stability of the signal input.

[0077] Specifically, the first external control module 5 can be set as the previous optical engine, and the second external control module 6 can be set as the next optical engine.

[0078] In one preferred embodiment, a uniform high frame rate projection control circuit further includes an isolation output module 8;

[0079] The second external control module 6 is electrically connected to the isolation output module 8, and the isolation output module 8 is electrically connected to the main control unit 11.

[0080] Specifically, the main control unit 11 of this application is used to generate a trigger output signal to the second external control module 6 after the synchronization signal reaches a preset number. The isolation output module 8 is used to realize signal isolation between the main control unit 11 and the second external control module 6, reduce signal interference, and improve signal transmission stability.

[0081] Please refer to Figure 3 , Figure 3 This is a schematic diagram of a uniform high frame rate projection control circuit provided in this application.

[0082] In a preferred embodiment, a uniform high frame rate projection control circuit further includes a USB module 9 and a FLASH storage module 10;

[0083] USB module 9 is electrically connected to the host computer, DLP control module 2 and FLASH storage module 10 respectively, and FLASH storage module 10 is electrically connected to DLP control module 2.

[0084] USB module 9 is used to burn projection data; when writing pattern data, only one pattern image is stored for each pattern set to ensure consistent load time and achieve uniform pattern output.

[0085] The FLASH storage module 10 is used to load the configuration for startup initialization.

[0086] Please refer to Figure 5 , Figure 5 This is a schematic diagram of a uniform high frame rate projection control circuit provided in this application.

[0087] In a preferred embodiment, this application uses USB module 9 to burn the pattern and timing table, and initiates the initialization loading of flash configuration. USB module 9 can be connected to a host computer, mobile terminal, or external hard drive, and is not limited thereto. The trigger-in signal is filtered by capacitor filtering. After receiving the trigger input signal trigger-in via IO interrupt, the main control module 1 generates a certain number of PWM pulses to trigger the DLP control module 2. The DLP control module 2 supports projecting one image at a time. Each time the DLP control module 2 starts projecting an image, it sends a synchronization signal to the camera for acquisition. After accumulating a certain number of signals, the main control module 1 outputs a trigger output signal trigger-out.

[0088] In a preferred embodiment, the main control module 1 is a microcontroller, model MSP430F2132, and the hardware model of the main control module 1 is not specifically limited.

[0089] In one preferred embodiment, the chip model of the DLP control module 2 is DLPC347X, and the hardware model of the DLP control module is not specifically limited.

[0090] In a preferred embodiment, the chip model of the DLP display module 3 is DLP2010LC, DLP3010 or DLP4710LC, and the hardware model of the DLP display module 3 is not specifically limited.

[0091] In one preferred embodiment, the chip model of the light source driving module 4 is DLPA3005, and the hardware model of the light source driving module 4 is not specifically limited.

[0092] In a preferred embodiment, the chip model of the USB module 9 is CY7C65215-32LTXI, and the hardware model of the USB module 9 is not specifically limited.

[0093] In a preferred embodiment, the chip model of the FLASH storage module 10 is W25Q64FVZPIG, and the hardware model of the FLASH storage module 10 is not specifically limited.

[0094] Please refer to Figure 4 , Figure 4 This is a schematic diagram of a uniform high frame rate projection control circuit provided in this application.

[0095] In a preferred embodiment, the main control module 1 further includes a bus transceiver unit 13, an input buffer unit 14, and an output buffer unit 15;

[0096] The bus transceiver unit 13 is electrically connected to the main control unit 11, the input buffer unit 14, and the output buffer unit 15, respectively.

[0097] The input buffer unit 14 is electrically connected to the main control unit 11, the input filtering module 7 and the DLP control module 2 respectively;

[0098] The output buffer unit 15 is electrically connected to the main control unit 11, the isolation output module 8 and the DLP control module 2 respectively.

[0099] Specifically, the bus transceiver unit 13 is used to achieve data isolation transmission between the main control module 1 and the first external control module 5; the input buffer unit 14 is used to temporarily store data sent from the peripheral device so that the main control unit 11 can retrieve it; the output buffer unit 15 is used to temporarily store data sent from the main control unit 11 to the peripheral device. It can be understood that the input buffer unit 14 and the output buffer unit 15 are numerical control buffers, which enable the high-speed main control unit 11 and the slow-speed peripheral device to coordinate and buffer each other, so as to achieve the synchronization of data transmission.

[0100] Specifically, the input buffer unit 14 and the output buffer unit 15 are connected to the data bus of the bus transceiver unit 13 and have tri-state output functionality. In this application, the input buffer unit 14 and the output buffer unit 15 are model SN74LVC1G07DCKR.

[0101] In one preferred embodiment, the main control module 1 further includes a debugging unit 16;

[0102] The debugging unit 16 is electrically connected to the main control unit 11 and the keyboard. It can be understood that the debugging unit 16 is used to implement debugging control of the main control module 1.

[0103] To address the aforementioned technical problems, this application also provides a uniform high frame rate projection control method.

[0104] Please see Figure 6 , Figure 6 This is a flowchart of a uniform high frame rate projection control method according to this application.

[0105] The methods include:

[0106] S1. Receive the trigger input signal from the first external control module;

[0107] S2. Generate a PWM pulse signal to trigger the DLP control module;

[0108] S3. Control the display of projected images based on PWM pulse signals;

[0109] S4. Execute structured light output based on the projected image;

[0110] S5. When controlling the projected image, a synchronization signal is sent to the camera for acquisition;

[0111] S6. After the synchronization signal reaches a preset number, a trigger output signal is generated to the second external control module.

[0112] Preferably, the method further includes:

[0113] The pattern set is encapsulated by performing a pattern set encapsulation at the upper layer of the host computer.

[0114] Keep the loading time of each pattern set consistent.

[0115] Preferably, the method further includes:

[0116] Obtain the total cycle time of the pattern set, including the pre-dark time, exposure time, post-dark time, and loading time, for a complete exposure cycle.

[0117] Obtain the sum of the pre-dark time and the post-dark time;

[0118] Obtain the difference between the sum and the loading time, where the difference satisfies the condition of minimizing the sum of the dark field times before and after.

[0119] Specifically, in this application, the internal pattern of the DLP control module 2 is stored and loaded in groups according to pattern sets, with each pattern set capable of storing up to 7-8 8-bit 1D images. To offset the varying loading times when switching between multiple pattern sets in the DLP control module 2, this application implements pattern set encapsulation at the upper layer of the host computer. When the underlying layer initially writes pattern data via USB module 9, it stores only one pattern image per pattern set. While this cannot completely eliminate loading time, the loading time for all pattern sets is essentially the same. This reduces the loading time by minimizing the dark field time before and after the dark field.

[0120] Specifically, assume t1 = pre-dark time (µs, minimum 171µs), t2 = exposure time (µs, minimum 2084µs), t3 = post-dark time (µs, minimum 33µs), and t4 = loading time for each pattern set (µs). The complete exposure cycle is: T = t1 + t2 + t3 + t4. Subtract t4 from the total dark time of t1, t3, or t1 + t3. The result must satisfy the minimum sum of the pre- and post-dark times.

[0121] The new total dark time is set to (t1 + t3 - t4). After cancellation, the new full exposure period T1 = t1 + t2 + t3. Therefore, the projection exposure frame rate can be matched to the highest frame rate captured by the camera, and the capture frame rate can also be relatively uniform. Here, the frame rate is the frequency (rate) at which a bitmap image, in units of frames, continuously appears on the projection surface. Frame rate matching reflects the coordination between the camera and the optical engine.

[0122] In this application, when t1, t2, and t3 are at their minimum values, the highest frame rate within a single pattern set can reach 427. However, with multiple pattern sets, due to loading time, the original combined frame rate is much lower than 427. Furthermore, considering that the projection frame rate must be matched to the camera's maximum frame rate, the projection frame rate typically cannot be set to its maximum value.

[0123] Please see Figure 7 , Figure 7 This is a timing diagram of a uniform high frame rate projection control method according to this application.

[0124] Please see Figure 8 , Figure 8 This is a chart showing the exposure configuration data of a uniform high frame rate projection control method in this application.

[0125] If the camera's maximum frame rate is 180, the maximum frame rate of the 12 projected pattern sets must also be less than or equal to 180. The exposure cycle time can be T = 1000000 / 180 = 5556 (µs). Figure 8 The original pattern set can be divided into three groups: 4+4+4. Following the original configuration, as follows: Figure 8 The overall frame rate was only 158-169. With the new storage configuration and internal triggerin DLPC, the overall and peak frame rates are approximately 180.

[0126] Please see Figure 9 , Figure 9 This is a chart showing the exposure configuration data of a uniform high frame rate projection control method in this application.

[0127] If the camera's maximum frame rate is 240, and the frame rate is configured to match, 12 pattern sets need to be projected, with a maximum period of 4155. Using the original 6+6 configuration, as follows... Figure 9 The overall frame rate was 204-223, and the improved overall constant-speed frame rate is close to 240.

[0128] Please see Figure 10 , Figure 10 This is a chart showing the exposure configuration data of a uniform high frame rate projection control method in this application.

[0129] If the camera's maximum frame rate is 356, such as Figure 10 With 12 pattern sets, the overall frame rate configured in the original way is only 281-319, but after the improvement, the overall uniform frame rate can basically reach 355.

[0130] In summary, with one pattern set, a maximum constant frame rate of 427 can be configured (this must be matched with the camera's frame rate). With more than one pattern set, a maximum constant frame rate of 355 can be configured.

[0131] To generate one trigger out1 after displaying one pattern set, or to display only N images from one pattern set per trigger, the MCU in main control module 1 reads the total number P and trigger interval T of each original pattern set in the DLPC exposure timing table during initialization. The MCU stores a virtual pattern set x table, where pattern set x1 corresponds to the number of patterns P1 in the original pattern set 1, and so on, up to P2...Px. After receiving an external trigger signal, the MCU internally sends a certain number of trigger in signals PX to the DLPC to achieve PWM triggering. The MCU can also count the camera synchronization signal trigger out2 generated by the DLPC.

[0132] If it is necessary to trigger the projection of one pattern at a time, PX is set to 1, DLPC is triggered sequentially, and then the count is made. When the count is exactly PX, the MCU trigger out1 signal is output. When the count is a complete P, the MCU trigger out complete signal is output.

[0133] If a set of pattern sets (P1, ..., Px) needs to be triggered at once, PX is set sequentially. PX is triggered at corresponding intervals, cycling periodically. After each pattern set is completed, a trigger out1 signal is emitted. When the count reaches a complete P, an MCU trigger out completion signal is output.

[0134] If it is necessary to trigger all pattern projections at once, PX is set to P. After triggering P times internally at once, multiple MCU trigger out1 signals and one MCU trigger out completion signal are output after counting, which are used to realize cascading or notify external devices.

[0135] Because the MCU requires 20-50µs to process external I / O signals, and each frame has a complete exposure cycle including pre-dark time, exposure time, post-dark time, and post-set loading time, the post-dark time plus the post-load time exceeds 600µs. To offset the overall frame rate I / O processing time, the MCU out signal can be output 100µs before the last frame exposure to cascade to the next unit or provide feedback to the external control terminal.

[0136] Therefore, this application can increase the uniform projection frame rate of the DLP4710LC optical engine to a maximum of 356fps. If the maximum frame rate of a high-resolution industrial camera cannot be achieved, the projection frame rate can also be adjusted by configuring the projection exposure period to match the camera's maximum acquisition frame rate.

[0137] This application also provides an industrial optical engine, including a uniform high frame rate projection control circuit.

[0138] For a description of the uniform high frame rate projection control circuit provided in this application, please refer to the above embodiments; further details will not be repeated here.

[0139] It should be noted that, in this specification, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0140] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A constant velocity high frame rate projection control circuit, characterized by, The application relates to a kind of uniform speed high frame rate projection control circuit, including: main control module, DLP control module, DLP display module, light source driving module, first external control module and second external control module;The main control module includes main control unit and PWM trigger unit; The main control unit is electrically connected with the first external control module, the PWM trigger unit is electrically connected with the main control unit, the DLP control module is electrically connected with the PWM trigger unit, and the DLP display module is electrically connected with the DLP control module; The light source driving module is electrically connected with the DLP control module, and the DLP control module and the main control unit are electrically connected with the second external control module; The main control unit is used for receiving the trigger input signal of the first external control module, and the PWM trigger unit is used for generating the PWM pulse signal to trigger the DLP control module; The DLP control module is used for display processing control of projection picture according to the PWM pulse signal;The DLP display module and the light source driving module are used for realizing structured light output according to the projection picture; The DLP control module is used for sending a synchronization signal to a camera for acquisition when controlling the projection picture; The main control unit is used for generating a trigger output signal to the second external control module when the synchronization signal reaches a preset number; The DLP control module is used for loading and projecting a plurality of pattern sets, and the loading time of each pattern set is configured to be consistent; The main control unit is also used for reducing the dark field time to offset the loading time, so that the projection output frame rate is uniform; Once a pattern set is encapsulated on the upper computer; The loading time of each pattern set is kept consistent; The total cycle time of the front dark field time, exposure time, rear dark field time and loading time of each pattern set in a complete exposure cycle is obtained respectively; The total dark field time of the front dark field time and the rear dark field time is obtained; The difference between the total dark field time and the loading time is obtained, wherein the difference satisfies the sum of the minimum front and rear dark field time; The exposure frame rate of projection can match the highest frame rate of camera acquisition. The uniform speed high frame rate projection control circuit further includes an input filtering module; 2. The constant velocity high frame rate projection control circuit of claim 1, wherein, The first external control module is electrically connected with the input filtering module, and the main control unit is electrically connected with the input filtering module. The uniform speed high frame rate projection control circuit further includes an isolation output module; 3. The constant velocity high frame rate projection control circuit of claim 2, wherein, The second external control module is electrically connected with the isolation output module, and the isolation output module is electrically connected with the main control unit. The uniform speed high frame rate projection control circuit further includes a USB module and a FLASH storage module; 4. The constant velocity high frame rate projection control circuit of claim 1, wherein, The USB module is electrically connected with the upper computer, the DLP control module and the FLASH storage module respectively, and the FLASH storage module is electrically connected with the DLP control module; The USB module is used for realizing the burning of projection data; The FLASH storage module is used for realizing the configuration loading of startup initialization. The main control module further includes a bus transceiver unit, an input buffer unit and an output buffer unit.

5. The constant velocity high frame rate projection control circuit of claim 3, wherein, ​ The bus transceiver units are electrically connected with the input buffer units and the output buffer units respectively; The input buffer units are electrically connected with the input filter modules and the DLP control modules respectively; The output buffer units are electrically connected with the isolation output modules and the DLP control modules respectively.

6. The constant velocity high frame rate projection control circuit of claim 1, wherein, The master control module further comprises a debugging unit; The debugging unit is electrically connected with the master control unit.

7. A constant velocity high frame rate projection control method, characterized by, The method is applied to the uniform high frame rate projection control circuit of claim 1, and the method comprises: Receiving a trigger input signal of the first external control module; Generating a PWM pulse signal to trigger the DLP control module according to the trigger input signal; Performing display processing control of a projection picture according to the PWM pulse signal; Realizing structured light output according to the projection picture; Sending a synchronization signal to a camera for acquisition when the projection picture is controlled; Generating a trigger output signal to the second external control module after the synchronization signal reaches a preset number.

8. The constant speed high frame rate projection control method of claim 7, wherein, The method further comprises: Packaging a pattern set once on an upper computer layer; Controlling the loading time of each pattern set to be consistent.

9. The constant speed high frame rate projection control method of claim 7, wherein, The method further comprises: Respectively acquiring the total cycle time of the front dark field time, the exposure time, the rear dark field time and the loading time of each pattern set in a complete exposure cycle; Acquiring the total dark field time of the front dark field time and the rear dark field time; Acquiring the difference value of the total dark field time and the loading time, wherein the difference value meets the sum of the minimum front and rear dark field time.

10. An industrial light engine characterized in that, The uniform high frame rate projection control circuit of any one of claims 1-6.

Images