Advanced 3D packaging platform with adaptive thermal management

Abstract

The invention discloses an advanced 3D packaging platform with adaptive thermal management, and belongs to the technical field of semiconductor packaging. Comprising a shape memory alloy network, phase change material microcapsules, a prestressed filler system, through silicon vias and a monitoring system, the warping compensation of the shape memory alloy network is lower than 2 microns through a shape memory alloy wire with the diameter of 100 microns, and the shape memory alloy network has 8% reversible strain; the phase-change material microcapsule provides thermal buffer of 180 Joules per gram, and the cycle stability is greater than 10,000 times; the prestress filling material system has the initial pressure stress of-50 MPa; the silicon through holes have the diameter of 5 microns and the spacing of 10 microns, and the bandwidth of 8 bits per second is realized. Phase-change material microcapsules (packaging a paraffin base material, and having a transformation temperature of 55 DEG C) provide a high-thermal-conductivity buffer of 180 Joules / g, and can quickly absorb local hot spot heat; and meanwhile, the cycle stability is up to 10,000 times, no performance degradation is caused after long-term use, and the material is adaptive to a high-frequency thermal cycle scene.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and more particularly to an advanced 3D packaging platform with adaptive thermal management. Background Technology

[0002] The advanced packaging market is projected to reach $44 billion by 2026, facing the following challenges:

[0003] - Thermal density exceeds 1000 W / cm³ 2

[0004] - Core alignment requirement <1μm

[0005] -Reliability Requirements-40°C to +175°C operation

[0006] - Existing solutions lack active warp compensation. Summary of the Invention

[0007] Purpose of the invention: The purpose of this invention is to provide an advanced 3D packaging platform with adaptive thermal management, which can solve the problem of lack of active warp compensation in existing solutions.

[0008] Technical solution: To solve the above-mentioned technical problems, according to one aspect of the present invention, more specifically, an advanced 3D packaging platform with adaptive thermal management, comprising: a shape memory alloy network, phase change material microcapsules, a prestressed filler system, through-silicon vias, and a monitoring system;

[0009] Shape memory alloy network: Warp compensation of less than 2 micrometers is achieved through 100-micrometer diameter shape memory alloy wires, with 8% reversible strain;

[0010] Phase change material microcapsules: provide 180 joules per gram of thermal buffer and have a cycle stability of more than 10,000 cycles;

[0011] Prestressed filler system: with an initial compressive stress of -50 MPa;

[0012] Through-silicon vias (TSVs): 5 micrometer diameter, 10 micrometer pitch, achieving 8 terabits per second bandwidth;

[0013] Monitoring system: running at 100Hz, verifying that the nine thermal drift factors are equal to η_B=1×10^-10;

[0014] Its reliability exceeds JEDEC standards, with a mean time between failures (MTBF) of more than 30 years.

[0015] Furthermore, the shape memory alloy wire is composed of Ni-Ti alloy and has an activation temperature of 45±2 degrees Celsius.

[0016] Furthermore, the phase change material is composed of encapsulated paraffin and has a transition temperature of 55 degrees Celsius.

[0017] Furthermore, the prestressed filler contains 75% by weight silica and 10% by weight aluminum nitride filler.

[0018] Furthermore, the 3D packaging platform operates in a temperature range of -40 to +175 degrees Celsius.

[0019] Furthermore, the through-silicon via achieves a resistance of less than 20 milliohms and a capacitance of 20 femtofarads.

[0020] Furthermore, the 3D packaging platform has a heat dissipation capacity exceeding 1500 watts.

[0021] Furthermore, the nine drift factors include CTE mismatch, warpage, stress relaxation, creep rate, fatigue accumulation, delamination risk, void growth, interface degradation, and phase separation.

[0022] Furthermore, the 3D packaging platform can achieve hybrid Cu-Cu bonding with an alignment accuracy of 0.5 micrometers.

[0023] Furthermore, the monitoring system uses a 64-point strain gauge array.

[0024] Beneficial effects:

[0025] 1. Addressing the core pain point of "lack of active warp compensation".

[0026] Active warp control is achieved through a Ni-Ti shape memory alloy network (100-micron diameter wires), with a warp compensation of less than 2 microns. It also features 8% reversible strain and a precise activation temperature of 45±2℃, which can dynamically offset warp caused by temperature changes and material thermal expansion coefficient (CTE) mismatch during the packaging process. This avoids problems such as core misalignment and bonding failure, and makes up for the shortcomings of existing solutions that rely solely on passive structures.

[0027] 2. Highly efficient adaptive thermal management capability

[0028] Phase change material microcapsules (encapsulating paraffin substrate, transition temperature 55℃) provide a high thermal conductivity buffer of 180 joules / gram, which can quickly absorb local hot spot heat; at the same time, the cycle stability exceeds 10,000 cycles, and there is no performance degradation after long-term use, making it suitable for high-frequency thermal cycling scenarios.

[0029] The overall platform has a heat dissipation capacity exceeding 1500 watts and can handle heat densities exceeding 1000 W / cm². 2 It can meet the heat dissipation requirements of high-power chips (such as AI chips and server chips) under extreme operating conditions.

[0030] 3. Excellent electrical performance and signal integrity

[0031] Through-Silicon Vias (TSVs) employ a 5-micrometer diameter and 10-micrometer pitch design to achieve an ultra-high bandwidth of 8 terabits per second (Tbps), while having a resistance of less than 20 milliohms (mΩ) and a capacitance of less than 20 femtofarads (fF), significantly reducing signal transmission loss and latency, making them suitable for high-speed interconnect scenarios.

[0032] It supports hybrid Cu-Cu bonding with an alignment accuracy of 0.5 micrometers, far exceeding the industry's <1 micrometer chip alignment requirements, thereby improving chip integration density and interconnect reliability.

[0033] 4. Wide temperature adaptability and long-term reliability

[0034] The operating temperature range covers -40℃ to +175℃, which can adapt to temperature fluctuations in extreme environments (such as industrial control and automotive electronics);

[0035] The reliability indicators far exceed the JEDEC industry standard, with a mean time to failure (MTBF) of more than 30 years. At the same time, the prestressed filler system (containing 75wt% silica + 10wt% aluminum nitride, initial compressive stress -50 MPa) suppresses the risk of failure such as stress relaxation, creep, and delamination, thus extending the package life.

[0036] 5. Real-time and accurate status monitoring

[0037] The monitoring system uses a 64-point strain gauge array, which operates in real time at a frequency of 100Hz. It can simultaneously verify nine thermal drift factors: CTE mismatch, warpage, stress relaxation, creep rate, fatigue accumulation, delamination risk, void growth, interface degradation, and phase separation. The factor accuracy reaches η_B = 1×10^-10, providing early warning of potential failure risks and ensuring long-term stable operation of the package. Attached Figure Description

[0038] Figure 1 It is a complete packaging platform architecture diagram;

[0039] Figure 2 This is a shape memory alloy network layout diagram;

[0040] Figure 3 This is a distribution diagram of microcapsules for phase change materials;

[0041] Figure 4 This is a diagram illustrating the application process of prestressed sublayers;

[0042] Figure 5 It is a real-time monitoring sensor location map;

[0043] Figure 6 This is a diagram of the real-time monitoring sensor mechanism;

[0044] Figure 7 This is a graph showing the reliability test results;

[0045] Figure 8 This is a diagram of the deformation compensation mechanism. Detailed Implementation

[0046] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0047] Example

[0048] 1. Implementation Objectives

[0049] An advanced 3D packaging platform with adaptive thermal management conforming to claims 1-10 was prepared, and its warp compensation, thermal management, electrical performance and reliability indicators were verified.

[0050] 2. Preparation of raw materials and equipment

[0051]

[0052]

[0053] 3. Preparation steps

[0054] Step 1: Through Silicon Via (TSV) Fabrication

[0055] The 4-inch silicon wafer was cleaned (in sequence with acetone, isopropanol, and deionized water, then ultrasonically cleaned and dried with nitrogen).

[0056] TSV vias were fabricated using a deep silicon etching machine: 5μm in diameter, 10μm in spacing, and 300μm in depth.

[0057] Plasma treatment (Ar atmosphere, power 300W, time 5min) was applied to the inner wall of the TSV hole to enhance the adhesion of the coating.

[0058] The holes were filled with copper using electroplating at a current density of 2 A / dm². 2 Time: 60 minutes;

[0059] Chemical mechanical polishing (CMP) was performed on the wafer surface to remove excess copper layer. The electrical performance of the TSV was tested: resistance 18mΩ, capacitance 15fF, which meets the requirements of "<20mΩ, <20fF".

[0060] Step 2: Shape memory alloy network integration

[0061] The Ni-Ti alloy wires are braided into a grid (100μm grid spacing) using a braiding machine and cut to a 4-inch size to match the silicon wafer;

[0062] A high-temperature resistant adhesive (polyimide-based) is coated on the surface of a silicon wafer, and an alloy network is attached to the upper surface of the wafer. The curing temperature is 120℃ and the time is 30min.

[0063] The high-temperature activation test bench was used to simulate temperature changes (25℃→50℃→25℃) to test the warpage compensation effect: the maximum warpage was 1.8μm (<2μm), the reversible strain was 7.8% (close to 8%), and the activation temperature was 44.5℃ (meeting the requirement of 45±2℃).

[0064] Step 3: Microcapsule embedding of phase change materials

[0065] Preparation of phase change material microcapsules: encapsulating paraffin (core material) and acrylic resin (wall material) are mixed at a mass ratio of 7:3 and reacted at 60°C for 2 hours using an in-situ polymerization pelletizing machine to form microcapsules with a diameter of 5-10 μm.

[0066] The microcapsule performance was tested using DSC: the thermal buffer capacity was 182 J / g (>180 J / g), and the thermal buffer capacity decay rate after 10,000 cycles was <5% (meeting the requirements for cycle stability).

[0067] A groove (50 μm deep, 30% of the area) was made on the lower surface of a silicon wafer. Microcapsules were mixed with epoxy resin (1:1 by mass) and filled into the groove. The mixture was cured at 80°C for 20 min to complete the construction of the thermal buffer layer.

[0068] Step 4: Prestressed filler injection

[0069] Preparation of prestressed filler: Add epoxy resin matrix, 75wt% silica filler and 10wt% aluminum nitride filler to planetary mixer, stir at 2000rpm for 30min, and degas for 10min;

[0070] Filler material (100 μm thick) is poured into the gap between the silicon wafer and the carrier substrate (ceramic substrate), and an initial compressive stress of -50 MPa is applied using a compressive stress tester. The mixture is then cured at 100°C for 60 min.

[0071] Stress stability of filler tested: After 100 cycles from -40℃ to 175℃, the compressive stress retention rate was >90%.

[0072] Step 5: Monitoring system and Cu-Cu bonding installation

[0073] The 64-point strain gauge array was attached to key locations on the packaging platform (TSV area, alloy network nodes, microcapsule grooves), connected to the data acquisition module, and the sampling rate was set to 100Hz.

[0074] Plasma cleaning (O2 atmosphere, 200W power, 3min) was performed on the upper surface copper layer of the packaging platform to remove the oxide layer;

[0075] Mixed Cu-Cu bonding was performed using a bonding machine: alignment accuracy 0.4 μm (<0.5 μm), bonding temperature 300℃, pressure 5 MPa, and time 10 s.

[0076] 4. Performance Testing and Verification

[0077]

[0078]

[0079] 5. Conclusion

[0080] The 3D packaging platform prepared in this embodiment meets all the requirements of the invention in terms of performance indicators. It can achieve adaptive thermal management, active warp compensation and long-term high reliability, and is suitable for high-power, high-density semiconductor packaging scenarios (such as AI chips and high-end server chips).

[0081] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. An advanced 3D packaging platform with adaptive thermal management, characterized by, Includes: Shape Memory Alloy Network, Phase Change Material Microcapsule, Pre-stressed Filler System, Through Silicon Via, Monitoring System; Shape Memory Alloy Network: < 2 microns warpage compensation through 100 micron diameter shape memory alloy wire, 8% reversible strain; Phase Change Material Microcapsule: 180 Joules per gram thermal buffer, > 10,000 cycle stability; Pre-stressed Filler System: -50 MegaPascal initial compressive stress; Through Silicon Via: 5 micron diameter, 10 micron pitch, 8 Terabit per second bandwidth; Monitoring System: 100 Hz operation, nine thermal drift factors verified equal to η_B = 1 x 10^-10; Where reliability exceeds JEDEC standards, mean time between failures > 30 years.

2. The advanced 3D packaging platform with adaptive thermal management as claimed in claim 1, wherein: The shape memory alloy wire consists of Ni-Ti alloy, activation temperature 45 ± 2 degrees Celsius.

3. The advanced 3D packaging platform with adaptive thermal management as claimed in claim 1, wherein: The phase change material consists of encapsulated paraffin, transition temperature 55 degrees Celsius.

4. The advanced 3D package platform with adaptive thermal management of claim 1, wherein: The pre-stressed filler contains 75 weight percent silicon dioxide and 10 weight percent aluminum nitride fillers.

5. The advanced 3D package platform with adaptive thermal management of claim 1, wherein: The 3D packaging platform operating temperature range -40 to +175 degrees Celsius.

6. The advanced 3D package platform with adaptive thermal management of claim 1, wherein: The through silicon via achieves less than 20 milliOhm resistance and 20 femtoFarad capacitance.

7. The advanced 3D package platform with adaptive thermal management of claim 1, wherein: The 3D packaging platform thermal dissipation capability exceeds 1500 Watts.

8. The advanced 3D package platform with adaptive thermal management of claim 1, wherein: The nine drift factors include CTE mismatch, warpage rate, stress relaxation, creep rate, fatigue accumulation, delamination risk, void growth, interface degradation, and phase separation.

9. The advanced 3D package platform with adaptive thermal management of claim 1, wherein: The 3D packaging platform can achieve hybrid Cu-Cu bonding, alignment accuracy 0.5 microns.

10. The advanced 3D package platform with adaptive thermal management of claim 1, wherein: The monitoring system uses a 64-point strain gauge array.

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