Single-ended tunnel junction P-channel gallium nitride transistor and preparation method thereof

Abstract

The invention belongs to the technical field of semiconductor devices, and discloses a single-ended tunnel junction P-channel gallium nitride transistor and a preparation method thereof.The single-ended tunnel junction P-channel gallium nitride transistor comprises a substrate layer, a buffer layer, a barrier layer, a p cap layer and a p + + cap layer which are sequentially stacked, and the center of the stacked structure is provided with a groove with the bottom located in the p cap layer; the n + + cap layer is located on the p + + cap layer on one side of the groove, and a drain electrode is arranged on the p + + cap layer on the other side of the groove; a source electrode is arranged on the n + + cap layer; a dielectric layer is arranged between the source electrode and the drain electrode, and the source electrode and the drain electrode are in contact with the dielectric layer; and a gate electrode is arranged on the dielectric layer. According to the single-ended tunnel junction P-channel gallium nitride transistor, the single-ended tunnel junction structure is introduced between the p cap layer and the source electrode, so that the on-resistance of a channel is remarkably reduced, the injection efficiency of carriers is improved, the tunneling current is remarkably improved, and monolithic integration with an N-channel device piece can be realized on the same process line.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a single-ended tunnel junction P-channel gallium nitride transistor and its fabrication method. Background Technology

[0002] Gallium nitride (GaN), a wide-bandgap semiconductor material, has become a core material for fabricating next-generation high-frequency, high-efficiency power electronic devices due to its high breakdown electric field, high electron saturation velocity, and excellent heterojunction interface properties. Currently, enhancement-mode (E-mode) GaN-on-Si power transistors based on p-GaN / AlGaN / GaN heterojunctions have achieved widespread commercial success in areas such as consumer fast charging and are gradually expanding into broader markets such as electric vehicles and industrial power supplies.

[0003] However, most existing gallium nitride power devices still exist in discrete form. Their drive and control circuits have to rely on external silicon-based integrated circuits, connected by wire bonding. This discrete solution not only increases the size and area of ​​the module, but also introduces parasitic inductance from the bonding wires, making the voltage unstable during switching, thus limiting the efficiency advantages that gallium nitride high electron mobility transistors (HEMTs) should have in high-frequency switching applications.

[0004] To achieve monolithic integration of gallium nitride (GaN) power devices, driver circuits, and logic control circuits, constructing all-GaN complementary metal-oxide-semiconductor (CMOS) devices is widely recognized as the ideal solution. This approach minimizes system size and packaging complexity, fully leveraging the potential of GaN devices in high-frequency, high-efficiency applications.

[0005] However, the core bottleneck in the development of all-gallium nitride CMOS technology lies in the lack of high-performance, high-reliability gallium nitride p-channel field-effect transistors (p-FETs). Limited by the low mobility, low carrier concentration, and low activation rate of Mg dopants in the p-GaN channel, the current drive capability of existing gallium nitride p-FETs is far inferior to their n-FET counterparts, making it difficult to achieve performance matching in complementary logic circuits. Although the industry has attempted to use two-dimensional hole gas (2DHG) in p-GaN / AlGaN heterojunctions to improve the current of gallium nitride p-FETs, their output performance remains at a low level (typically below 10 mA / mm), failing to meet practical application requirements.

[0006] Therefore, researching and developing gallium nitride P-channel field-effect transistors with higher current output capability has become the key to promoting the development and monolithic integration of gallium nitride CMOS technology, and ultimately to overcoming the challenges of next-generation high-efficiency electronic systems. Summary of the Invention

[0007] To address the aforementioned problems in the prior art, this invention provides a single-ended tunneling junction P-channel gallium nitride transistor and its fabrication method.

[0008] The technical problem to be solved by this invention is achieved through the following technical solution: A single-ended tunneling junction p-channel gallium nitride transistor includes: a substrate layer, a buffer layer, a barrier layer, a p-cap layer, and a p-channel layer. ++ Hat layer, n ++ Cap layer, dielectric layer, source electrode, drain electrode, and gate electrode; among which, The substrate layer, the buffer layer, the barrier layer, the p-cap layer, and the p-cap layer ++ The cap layers are stacked sequentially, and the center of the stacked structure has a groove whose bottom is located inside the p-cap layer; The n ++ The cap layer is located on one side of the groove at p ++ Above the cap layer, on the other side of the groove, p ++ The drain electrode is provided on the cap layer; the n ++ The source electrode is provided on the cap layer; The dielectric layer is provided between the source electrode and the drain electrode, and both electrodes are in contact with the dielectric layer. The gate electrode is disposed on the dielectric layer.

[0009] Optionally, the buffer layer is made of GaN and has a thickness of 1~10µm.

[0010] Optionally, the barrier layer is an AlGaN barrier layer, wherein the Al composition in the AlGaN barrier layer is 10%~30%, and the thickness of the AlGaN barrier layer is 10~30 nm.

[0011] Optionally, the p-cap layer is made of p-type GaN, with Mg as the p-type dopant and a doping concentration of 5 × 10⁻⁶. 18 cm -3 ~5×10 19 cm -3 The thickness is 50~100nm.

[0012] Optionally, the p ++ The cap layer is a p-type heavily doped GaN layer, with Mg as the p-type dopant and a doping concentration of 1×10⁻⁶. 20 cm -3 ~5×10 20 cm -3 The thickness is 5~30nm.

[0013] Optionally, the n ++ The cap layer is an n-type heavily doped GaN layer, with Si as the n-type dopant and a doping concentration of 1 × 10⁻⁶.20 cm -3 ~5×10 20 cm -3 Its thickness is 5~30nm.

[0014] Optionally, the dielectric layer is made of SiO2, Al2O3, or SiN. x It is composed of one or more layers, wherein the thickness of the dielectric layer is 5~50nm.

[0015] Optionally, the source electrode is a Ti / Al / Ni / Au metal, the drain electrode is a Ni / Au composite metal structure, and the gate electrode is a metal electrode.

[0016] Optionally, the transistor further includes a tunneling layer; The tunneling layer is located on one side of the groove. ++ Hat layer and n ++ Between the cap layers; The tunneling layer is an InGaN tunneling barrier layer, wherein the In composition of the InGaN tunneling barrier layer is 0%~100%, and the thickness of the InGaN tunneling barrier layer is less than 10nm.

[0017] This invention also provides a method for fabricating a single-ended tunnel junction P-channel gallium nitride transistor, comprising: S1: Obtain an epitaxial wafer, the epitaxial wafer comprising a substrate layer, a buffer layer, a barrier layer, a p-cap layer, and a p-cap layer stacked sequentially. ++ Hat layer and n ++ Cap layer; S2: Etching the n ++ One side of the cap layer to expose the p underneath. ++ Cap layer; S3: p exposed by etching ++ The cap layer and the underlying p-cap layer form a groove; the bottom of the groove is located within the p-cap layer; S4: Deposit a dielectric layer on the surface of the current sample; S5: Etch both sides of the dielectric layer, exposing n ++ Source electrodes are fabricated on the surface of the cap layer, exposing p ++ Drain electrodes are fabricated on the surface of the cap layer; S6: Prepare a gate electrode on the surface of the remaining dielectric layer.

[0018] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The single-ended tunneling junction P-channel gallium nitride transistor of the present invention, through p ++ Hat layer and n ++The cap layer constructs a heterojunction tunneling structure at the source end, serving as an efficient hole injection source. This structure utilizes the strong polarization effect of the gallium nitride heterojunction to form strong polarization charges at the interface. These polarization charges significantly alter the energy band distribution at the interface, thereby significantly narrowing the electron tunneling barrier width. This allows holes to achieve efficient tunneling even at low bias voltages, significantly increasing the tunneling probability and providing a high carrier tunneling current.

[0019] 2. The single-ended tunneling junction P-channel gallium nitride transistor of the present invention adopts a single-ended tunneling junction structure, that is, the tunneling junction structure is introduced only on the source side, which can eliminate the potential barrier formed on the drain side tunneling junction when the existing source / drain dual tunneling junction structure is working, realize the optimization of carrier transport path, thereby significantly reducing the on-resistance of the device and ensuring that the device turns on at low voltage.

[0020] 3. The single-ended tunneling junction P-channel gallium nitride transistor of the present invention can maintain low gate leakage current while improving driving capability, thus ensuring device reliability. Furthermore, the structural design of the present invention has good compatibility with traditional p-GaN / AlGaN / GaN enhancement-mode HEMTs, and can be monolithically integrated with N-channel chips on the same process line, laying the foundation for the development of all-GaN-CMOS integrated circuits.

[0021] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a single-ended tunnel junction P-channel gallium nitride transistor provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of another single-ended tunnel junction P-channel gallium nitride transistor provided in an embodiment of the present invention; Figure 3 This is a flowchart of a method for fabricating a single-ended tunnel junction P-channel gallium nitride transistor according to an embodiment of the present invention; Figures 4-9 This is a process flow diagram of the fabrication of a single-ended tunnel junction P-channel gallium nitride transistor provided in an embodiment of the present invention; Figure label: 1. Substrate layer; 2. Buffer layer; 3. Barrier layer; 4. p-cap layer; 5. p-cap layer ++ 6. Cap layer; 7. Tunneling layer; 8. n ++ 8. Cap layer; 9. Dielectric layer; 10. Source electrode; 11. Drain electrode; 12. Gate electrode. Detailed Implementation

[0023] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following describes in detail, with reference to the accompanying drawings and specific embodiments, a single-ended tunnel junction P-channel gallium nitride transistor and its fabrication method proposed in the present invention.

[0024] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0025] Example 1 Please see Figure 1 , Figure 1 This is a schematic diagram of a single-ended tunneling junction P-channel gallium nitride transistor provided in an embodiment of the present invention. As shown in the figure, the single-ended tunneling junction P-channel gallium nitride transistor of this embodiment includes: a substrate layer 1, a buffer layer 2, a barrier layer 3, a p-cap layer 4, and a p-type cap layer 5. ++ Hat layer 5, n ++ 7. Cap layer, 8. Dielectric layer, 9. Source electrode, 10. Drain electrode, and 11. Gate electrode; wherein, 1. Substrate layer, 2. Buffer layer, 3. Barrier layer, 4. p-cap layer, and 5. p-gate layer. ++ The cap layers 5 are stacked sequentially, and the center of the stacked structure has a groove whose bottom is located within the p-cap layer 4; n ++ Cap layer 7 is located on one side of the groove. ++ Above the cap layer 5, on the other side of the groove, p ++ A drain electrode 10 is provided on the cap layer 5; n ++ A source electrode 9 is provided on the cap layer 7; a dielectric layer 8 is provided between the source electrode 9 and the drain electrode 10, and both are in contact with the dielectric layer 8; a gate electrode 11 is provided on the dielectric layer 8.

[0026] Specifically, this single-ended tunneling junction P-channel gallium nitride transistor has a lateral structure, and this transistor passes through p ++ Hat layer 5 and n ++ The cap layer 7 forms a heterojunction tunneling structure, thereby introducing a single-ended tunneling junction structure between the p-cap layer and the source. This significantly reduces the channel's on-resistance and improves carrier injection efficiency, resulting in a higher output current than conventional P-channel gallium nitride transistors. Simultaneously, by placing a dielectric layer at the gate, this invention maintains low gate leakage current. With its high current characteristics, low conduction loss, and ease of integration with gallium nitride n-FETs, this invention has broad application prospects in gallium nitride CMOS integrated circuits and next-generation high-efficiency electronic power systems.

[0027] In one alternative implementation, the buffer layer 2 is made of GaN and has a thickness of 1~10µm.

[0028] In one alternative implementation, the barrier layer 3 is an AlGaN barrier layer, wherein the Al composition in the AlGaN barrier layer is 10% to 30%, and the thickness of the AlGaN barrier layer is 10 to 30 nm.

[0029] In one alternative implementation, the p-cap layer 4 is made of p-type GaN, with Mg as the p-type dopant ion and a doping concentration of 5 × 10⁻⁶. 18 cm -3 ~5×10 19 cm -3 The thickness is 50~100nm.

[0030] In one alternative implementation, p ++ Cap layer 5 is a p-type heavily doped GaN layer, with Mg as the p-type dopant and a doping concentration of 1×10⁻⁶. 20 cm -3 ~5×10 20 cm -3 The thickness is 5~30nm.

[0031] In one alternative implementation, n ++ Cap layer 7 is an n-type heavily doped GaN layer, with Si as the n-type dopant and a doping concentration of 1×10⁻⁶. 20 cm -3 ~5×10 20 cm -3 Its thickness is 5~30nm.

[0032] In one alternative implementation, the material of the dielectric layer 8 is SiO2, Al2O3, and SiN. x It is composed of one or more layers, with the thickness of the dielectric layer being 5~50nm. This dielectric layer 8 can effectively suppress gate leakage.

[0033] In one alternative implementation, the source electrode 9 is a Ti / Al / Ni / Au metal, the drain electrode 10 is a Ni / Au composite metal structure, and the gate electrode 11 is a metal electrode. The thickness of the source electrode 9, the drain electrode 10, and the gate electrode 11 is 100~300nm.

[0034] Specifically, the source electrode 9 is made of Ti / Al / Ni / Au metal, where Ti and n... ++In the GaN material of the cap layer 7, N reacts to form TiN. This process introduces nitrogen vacancies in the interface region, forming donor defects, thereby effectively reducing contact resistance. Al acts as a dopant, attracting N elements to form AlN, while simultaneously generating a large number of N vacancies, further reducing contact resistance. Ni acts as a diffusion barrier layer between Au and Ti / Al; Au prevents metal oxidation and facilitates interconnect bonding. The drain electrode 10 is made of Ni / Au metal. Ni's higher work function facilitates the formation of good ohmic contacts with p-GaN. Similarly, Au prevents metal oxidation and facilitates interconnect bonding. The gate electrode 11 is made of metal, which can be any metal, and its thickness is 100~300 nm.

[0035] See Figure 2 In one alternative implementation, the transistor further includes a tunneling layer 6 located on one side of the recess. ++ Hat layer 5 and n ++ Between the cap layer 7. Furthermore, this tunneling layer 6 is an InGaN tunneling barrier layer, with an In composition of 0%~100% and a thickness of less than 10 nm. Understandably, at this time p ++ Cap layer 5, tunnel layer 6 and n ++ The cap layer 7 forms a heterostructure tunneling structure.

[0036] The single-ended tunneling junction P-channel gallium nitride transistor of the present invention introduces a single-ended tunneling junction structure between the p-cap layer and the source. In this tunneling junction structure, due to the spontaneous polarization and piezoelectric polarization effects of the gallium nitride material system, strong polarization charges are formed at the interface, which alter the energy band distribution at the interface. Specifically, due to the effect of the polarization electric field, the valence band of the p++ cap layer is located above the conduction band of the n++ cap layer, and the barrier width between the valence band of the p++ cap layer and the conduction band of the n++ cap layer is significantly reduced. At the same time, the built-in electric field at the interface is enhanced, which helps carriers to obtain a higher tunneling probability. Therefore, under a relatively small applied bias voltage, holes can more easily tunnel from the valence band of the p++ cap layer to the conduction band of the n++ cap layer (electron reverse tunneling), forming a high-density tunneling current.

[0037] Furthermore, this invention employs a single-ended tunneling junction structure, introducing a tunneling junction only on the source side. This eliminates the potential barrier formed on the drain-side tunneling junction in a source / drain dual tunneling junction structure during operation, thereby optimizing the carrier transport path, reducing the device's on-resistance, and ensuring the device turns on at low voltage. Specifically, traditional P-channel gallium nitride tunneling transistors often use a source / drain symmetrical dual tunneling junction structure, with tunneling junctions at both the source and drain ends. In this dual tunneling junction design, when the device is turned on, only the source-side tunneling junction plays a major role in carrier injection. The drain-side tunneling junction, due to its opposite potential direction, cannot effectively participate in tunneling transport and instead forms an additional barrier region in the energy band, hindering hole flow. This results in a restricted carrier transport path, increased device on-resistance, and deteriorated switching characteristics. This invention, through its single-ended tunneling junction structure, eliminates the potential barrier formed on the drain-side tunneling junction in a source / drain dual tunneling junction structure during operation, thereby reducing the device's on-resistance.

[0038] Furthermore, the single-ended tunneling junction P-channel gallium nitride transistor of this invention exhibits good structural compatibility with traditional p-GaN / AlGaN / GaN enhancement-mode HEMTs. Both are based on GaN heterojunctions and can achieve device structures with different functional regions on the same epitaxial wafer through region doping or control of epitaxial growth parameters, thereby simultaneously constructing P-channel and N-channel devices on the same substrate. Moreover, the fabrication process can be shared, enabling the single-ended tunneling junction P-channel transistor to be integrated with enhancement-mode HEMT devices in the same process flow, improving the overall integration density of GaN CMOS circuits.

[0039] Example 2 This embodiment provides a method for fabricating a single-ended tunnel junction P-channel gallium nitride transistor, such as... Figure 3 As shown, the preparation method includes: S1: Obtain the epitaxial wafer, which includes a substrate layer, a buffer layer, a barrier layer, a p-cap layer, and a p-cap layer stacked sequentially. ++ Hat layer and n ++ Cap layer; Specifically, an epitaxial wafer meeting the requirements is obtained, and then subjected to organic and inorganic cleaning sequentially to effectively remove contaminants and oxide layers from the surface of the epitaxial wafer, reducing the impact of surface contaminants on subsequent experiments. The preparation method of the epitaxial wafer can refer to relevant existing technologies and is not limited here. For example, an epitaxial wafer can be obtained through metal-organic chemical vapor deposition (MOCVD).

[0040] Preferably, the substrate layer is made of Si, sapphire, or SiC.

[0041] Preferably, the buffer layer is made of GaN and has a thickness of 1~10µm.

[0042] Preferably, the barrier layer is an AlGaN barrier layer, wherein the Al composition in the AlGaN barrier layer is 10% to 30%, and the thickness of the AlGaN barrier layer is 10 to 30 nm.

[0043] Preferably, the p-cap layer is made of p-type GaN, with Mg as the p-type dopant ion and a doping concentration of 5 × 10⁻⁶. 18 cm -3 ~5×10 19 cm -3 The thickness is 50~100nm.

[0044] Preferably, p ++ The cap layer is a p-type heavily doped GaN layer, with Mg as the p-type dopant and a doping concentration of 1×10⁻⁶. 20 cm -3 ~5×10 20 cm -3 The thickness is 5~30nm.

[0045] Preferably, n ++ The cap layer is an n-type heavily doped GaN layer, with Si as the n-type dopant and a doping concentration of 1 × 10⁻⁶. 20 cm -3 ~5×10 20 cm -3 Its thickness is 5~30nm.

[0046] S2: Etching n ++ One side of the cap layer to expose the p underneath. ++ Cap layer; Specifically, inductively coupled plasma (ICP) etching technology is used to etch n. ++ The middle and one side areas of the cap layer are used to expose the underlying p. ++ The epitaxial wafer is then subjected to an organic cleaning process to repair etching damage and remove surface contaminants.

[0047] S3: p exposed by etching ++ The cap layer and the underlying p-cap layer form a groove; the bottom of the groove is located inside the p-cap layer. Specifically, inductively coupled plasma (ICP) etching technology is used to etch the exposed p-type material. ++ The cap layer and the underlying p-cap layer form a groove in the middle, with the bottom of the groove located inside the p-cap layer. Then, the current epitaxial wafer is annealed and organically cleaned with TMAH solution.

[0048] S4: Deposit a dielectric layer on the surface of the current sample; Specifically, SiO2, Al2O3, or SiN are deposited using plasma-enhanced atomic layer deposition (PEALD) technology. x Medium with a thickness of 5 nm to 50 nm.

[0049] S5: Etching both sides of the dielectric layer, exposing n ++ Source electrodes are fabricated on the surface of the cap layer, exposing p ++ Drain electrodes are fabricated on the surface of the cap layer; Specifically, reactive ion etching (RIE) is used to etch both sides of the dielectric layer, exposing the n... ++ A Ti / Al / Ni / Au metal layer with a thickness of 100nm~300nm is deposited on the cap layer surface, and then rapidly annealed in a nitrogen atmosphere to form the source electrode; the exposed p ++ A Ni / Au metal layer with a thickness of 100nm~300nm is deposited on the surface of the cap layer, and then the drain electrode is formed by rapid annealing in an oxygen atmosphere.

[0050] S6: Fabricate the gate electrode on the surface of the remaining dielectric layer; Specifically, the shape of the gate electrode is defined by photolithography, and then a Ti / Au metal with a thickness of 100nm~300nm is deposited on the surface of the current sample. Then, the residual adhesive and the Ti / Au metal on the surface of the residual adhesive are removed with a stripping solution to prepare the gate electrode.

[0051] The method for fabricating a single-ended tunneling junction P-channel gallium nitride transistor of the present invention employs ICP dry etching technology to realize the single-ended tunneling structure of the device, and activates the Mg acceptor impurity through high-temperature annealing, further improving the output current. Furthermore, the present invention improves the etching process of the P-channel... ++ After the cap layer and the underlying p-cap layer form the gate groove, the groove interface is organically cleaned with TMAH solution, which effectively repairs interface defects, improves interface quality, and thus reduces gate leakage current.

[0052] Example 3 Please see Figures 4-9 This is a process flow diagram of a single-ended tunneling junction P-channel gallium nitride transistor provided by an embodiment of the present invention. This embodiment specifically describes the fabrication method of the single-ended tunneling junction P-channel gallium nitride transistor in Embodiment 2. The fabrication method includes: S1: Obtain the epitaxial wafer, which includes a substrate layer 1, a buffer layer 2, a barrier layer 3, a p-cap layer 4, and a p-cap layer 5 stacked sequentially. ++ Cap layer 5, tunnel layer 6 and n ++ Hat layer 7; For example, obtaining such Figure 4 The epitaxial wafer shown is as follows: Substrate layer 1 is made of Si; buffer layer 2 is made of undoped GaN with a thickness of 4.5 µm; barrier layer 3 is made of AlGaN with an Al composition of 20% and a thickness of 18 nm; p-cap layer 4 is made of p-type GaN with Mg as the p-type dopant at a doping concentration of 1 × 10⁻⁶. 19 cm -3 Thickness is 50nm; p ++ The cap layer 5 is made of p-type heavily doped GaN, with Mg as the p-type dopant and a doping concentration of 3 × 10⁻⁶. 20 cm -3 p ++ The cap layer 5 has a thickness of 20 nm; the tunneling layer 6 is made of InGaN, with an In composition of 50%, and has a thickness of 3 nm; n ++ The material of cap layer 7 is n-type heavily doped GaN, with Si as the n-type dopant ion and a doping concentration of 3 × 10⁻⁶. 20 cm -3 Its thickness is 30nm.

[0053] Specifically, after obtaining the required epitaxial wafer, the epitaxial wafer is subjected to organic cleaning and inorganic cleaning in sequence to effectively remove dirt and oxide layer from the surface of the epitaxial wafer and reduce the impact of surface contaminants on subsequent experiments.

[0054] When cleaning epitaxial wafers, organic cleaning is used first. The specific steps are as follows: First, place the epitaxial wafer in an acetone solution and sonicate for 10 minutes to remove surface organic contaminants. Then, place the epitaxial wafer in an isopropanol or ethanol solution and sonicate for 10 minutes to remove residual acetone solution from the surface. After that, place the epitaxial wafer in deionized water and sonicate for 5 minutes to remove residual isopropanol or ethanol solution from the surface. This deionized water cleaning process needs to be repeated 2-3 times. Finally, the sample is dried with a nitrogen gun. For inorganic cleaning: First, use a piranha solution prepared with concentrated sulfuric acid and hydrogen peroxide at a ratio of 3:1 for inorganic cleaning to fully oxidize the surface organic matter. Then, use a BOE (7:1) solution or dilute hydrochloric acid solution to remove surface oxides from the epitaxial wafer. After acid washing, rinse the surface of the epitaxial wafer with a large amount of deionized water to wash away residual inorganic solvents. Finally, dry the epitaxial wafer with a nitrogen gun for the next step.

[0055] S2: Etching n ++ One side of the cap layer 7 and tunnel layer 6 to expose the underlying p ++ Hat layer 5; For example, see Figure 5 After cleaning, the epitaxial wafer surface undergoes homogenization, pre-baking, exposure, and development. Inductively coupled plasma (ICP) etching technology is then used for selective etching of n.++ The middle and one side regions of the cap layer 7 and tunnel layer 6 are used to expose the underlying p. ++ Cap layer 5. To ensure the integrity of the morphology of the etched area, a slow etching rate can be used during etching.

[0056] Next, the etched epitaxial wafer is subjected to organic cleaning. Specifically, the photoresist on the surface of the epitaxial wafer is removed using the same organic cleaning method as in step S1. Then, the epitaxial wafer is subjected to organic cleaning again, and heated in a TMAH solution water bath at 80°C for 1 minute to repair etching damage and remove surface contaminants.

[0057] S3: p exposed by etching ++ The cap layer 5 and the lower p-cap layer 4 form a groove; the bottom of the groove is located inside the p-cap layer 4. For example, see Figure 6 After the epitaxial wafer was cleaned again, it underwent homogenization, pre-baking, exposure, and development. Inductively coupled plasma (ICP) etching was then used to etch the exposed p-type epitaxial wafer. ++ The cap layer 5 and the underlying p-cap layer 4 form a groove in the middle, with the bottom of the groove located within the p-cap layer 4. To ensure the integrity of the morphology of the etched area, a slow etching rate is used during etching.

[0058] Then, the current epitaxial wafer is annealed and organically cleaned. Specifically, the photoresist on the surface of the current epitaxial wafer is removed using the organic cleaning method in step S1. Afterwards, it is furnace annealed in dry air at 700°C for 15 minutes to activate the p-type through the gate recess. ++ Cap layer 5 and p-cap layer 4. Next, the epitaxial wafer was organically cleaned again by heating in a TMAH solution at 80°C for 1 min to repair etching damage and remove surface contaminants. Afterward, the surface oxides on the epitaxial wafer surface were removed by treating with BOE (7:1) solution for 2 min.

[0059] S4: Deposit a dielectric layer 8 on the surface of the current sample; For details, see Figure 7 A 20 nm thick layer of Al2O3 was deposited using plasma-enhanced atomic layer deposition (PEALD) to form a dielectric layer 8.

[0060] S5: Etching both sides of the dielectric layer, exposing n ++ Source electrodes are fabricated on the surface of the cap layer, exposing p ++ Drain electrodes are fabricated on the surface of the cap layer; For example, see Figure 8The dielectric layer 8 is subjected to homogenization, pre-baking, exposure, and development. Then, the shape of the source electrode 9 is defined by photolithography. Subsequently, the dielectric layer 8 of the source electrode is removed by reactive ion etching (RIE). Finally, electron beam evaporation is used to expose the n-phase surface. ++ Ti / Al / Ni / Au metal is grown on the surface of cap layer 7, and residual adhesive and metal in the remaining areas are removed with a stripping solution. Finally, the current epitaxial wafer is rapidly annealed for 30 seconds at 850°C in a nitrogen atmosphere to form an ohmic contact at the source and reduce the contact resistance between the metal and the semiconductor.

[0061] Similarly, homogenization, pre-baking, exposure, and development are performed on the surface of dielectric layer 8. The shape of drain electrode 10 is defined by photolithography. Then, the dielectric layer of the drain electrode is removed using RIE, and electron beam evaporation is used on the exposed p-type electrode. ++ Ni / Au metal is grown on the surface of cap layer 5. Then, residual adhesive and the remaining metal are removed using a stripping solution. Finally, the current epitaxial wafer is annealed for 5 minutes at 550°C in an oxygen atmosphere to form an ohmic contact at the drain, reducing the contact resistance between the metal and the semiconductor.

[0062] S6: Fabricate gate electrode 11 on the surface of the remaining dielectric layer; For example, see Figure 9 The process involves homogenizing, pre-baking, exposure, and development on the surface of dielectric layer 8. Then, the shape of the gate electrode is defined by photolithography. After that, Ti / Au metal is deposited on the surface of dielectric layer 8 using electron beam evaporation. Finally, the residual resist and the metal on the surface of the residual resist are removed using a stripping solution.

[0063] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The single-ended tunneling junction P-channel gallium nitride transistor of the present invention, through p ++ Hat layer and n ++ The cap layer constructs a heterojunction tunneling structure at the source end, serving as an efficient hole injection source. This structure utilizes the strong polarization effect of the gallium nitride heterojunction to form strong polarization charges at the interface. These polarization charges significantly alter the energy band distribution at the interface, thereby significantly narrowing the electron tunneling barrier width. This allows holes to achieve efficient tunneling even at low bias voltages, significantly increasing the tunneling probability and providing a high carrier tunneling current.

[0064] 2. The single-ended tunneling junction P-channel gallium nitride transistor of the present invention adopts a single-ended tunneling junction structure, that is, the tunneling junction structure is introduced only on the source side, which can eliminate the potential barrier formed on the drain side tunneling junction when the existing source / drain dual tunneling junction structure is working, realize the optimization of carrier transport path, thereby significantly reducing the on-resistance of the device and ensuring that the device turns on at low voltage.

[0065] 3. The single-ended tunneling junction P-channel gallium nitride transistor of the present invention can maintain low gate leakage current while improving driving capability, thus ensuring device reliability. Furthermore, the structural design of the present invention has good compatibility with traditional p-GaN / AlGaN / GaN enhancement-mode HEMTs, and can be monolithically integrated with N-channel chips on the same process line, laying the foundation for the development of all-GaN-CMOS integrated circuits.

[0066] In the description of this invention, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0067] In the description of this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0068] In the description of this invention, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0069] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention.

[0070] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0071] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings and the disclosure in carrying out the claimed invention. In the description of the invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0072] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A single-ended tunnel junction P-channel gallium nitride transistor, characterized in that, include: Substrate layer (1), buffer layer (2), barrier layer (3), p-cap layer (4), p ++ Hat layer (5), n ++ The structure consists of a cap layer (7), a dielectric layer (8), a source electrode (9), a drain electrode (10), and a gate electrode (11); among which, The substrate layer (1), the buffer layer (2), the barrier layer (3), the p-cap layer (4), and the p ++ The cap layers (5) are stacked one after another, and the center of the stacked structure is provided with a groove whose bottom is located in the p cap layer (4); The n ++ The cap layer (7) is located on one side of the groove at p ++ Above the cap layer (5), p on the other side of the groove ++ The drain electrode (10) is provided on the cap layer (5); the n ++ The source electrode (9) is provided on the cap layer (7); The dielectric layer (8) is provided between the source electrode (9) and the drain electrode (10), and both are in contact with the dielectric layer (8); The gate electrode (11) is provided on the dielectric layer (8).

2. The single-ended tunneling junction P-channel gallium nitride transistor according to claim 1, characterized in that, The buffer layer (2) is made of GaN and has a thickness of 1~10µm.

3. The single-ended tunneling junction P-channel gallium nitride transistor according to claim 1, characterized in that, The barrier layer (3) is an AlGaN barrier layer, wherein the Al composition in the AlGaN barrier layer is 10%~30%, and the thickness of the AlGaN barrier layer is 10~30nm.

4. The single-ended tunneling junction P-channel gallium nitride transistor according to claim 1, characterized in that, The p-cap layer (4) is made of p-type GaN, with Mg as the p-type dopant and a doping concentration of 5 × 10⁻⁶. 18 cm -3 ~5×10 19 cm -3 The thickness is 50~100nm.

5. The single-ended tunneling junction P-channel gallium nitride transistor according to claim 1, characterized in that, The p ++ The cap layer (5) is a p-type heavily doped GaN layer, with Mg as the p-type dopant and a doping concentration of 1×10⁻⁶. 20 cm -3 ~5×10 20 cm -3 The thickness is 5~30nm.

6. The single-ended tunneling junction P-channel gallium nitride transistor according to claim 1, characterized in that, The n ++ The cap layer (7) is an n-type heavily doped GaN layer, with Si as the n-type dopant and a doping concentration of 1×10⁻⁶. 20 cm -3 ~5×10 20 cm -3 Its thickness is 5~30nm.

7. The single-ended tunneling junction P-channel gallium nitride transistor according to claim 1, characterized in that, The dielectric layer (8) is made of SiO2, Al2O3 and SiN. x It is composed of one or more layers, wherein the thickness of the dielectric layer is 5~50nm.

8. The single-ended tunneling junction P-channel gallium nitride transistor according to claim 1, characterized in that, The source electrode (9) is a Ti / Al / Ni / Au metal, the drain electrode (10) is a Ni / Au composite metal structure, and the gate electrode (11) is a metal electrode.

9. The single-ended tunneling junction P-channel gallium nitride transistor according to claim 1, characterized in that, The transistor also includes a tunneling layer (6); The tunneling layer (6) is located on one side of the groove at p ++ Hat layer (5) and n ++ Between the cap layers (7); The tunneling layer (6) is an InGaN tunneling barrier layer, wherein the In composition of the InGaN tunneling barrier layer is 0%~100%, and the thickness of the InGaN tunneling barrier layer is less than 10nm.

10. A method for fabricating a single-ended tunnel junction P-channel gallium nitride transistor, characterized in that, include: S1: Obtain an epitaxial wafer, the epitaxial wafer comprising a substrate layer, a buffer layer, a barrier layer, a p-cap layer, and a p-cap layer stacked sequentially. ++ Hat layer and n ++ Cap layer; S2: Etching the n ++ One side of the cap layer to expose the p underneath. ++ Cap layer; S3: p exposed by etching ++ The cap layer and the underlying p-cap layer form a groove; the bottom of the groove is located within the p-cap layer; S4: Deposit a dielectric layer on the surface of the current sample; S5: Etch both sides of the dielectric layer, exposing n ++ Source electrodes are fabricated on the surface of the cap layer, exposing p ++ Drain electrodes are fabricated on the surface of the cap layer; S6: Prepare a gate electrode on the surface of the remaining dielectric layer.

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