A high-density NAND storage media adaptive repair method

Abstract

The application discloses a high-density NAND storage medium adaptive repair method, which comprises the following steps: a master control chip separates a target feature vector representing a real aging trend of a storage unit from original read data containing random physical noise; the master control chip deduces the target feature vector by using a full integer recursive prediction model to obtain a health state prediction result of the storage unit in a future preset time period; wherein the health state prediction result comprises a best read reference voltage offset and an estimated bit error rate growth curve; and the master control chip adjusts the charge distribution form and the programming voltage parameter of data on the storage unit in the data writing stage according to the health state prediction result. In the above manner, the firmware pipeline blockage and performance jitter problems caused by floating point operation and large model parameter loading can be eliminated in a restricted hardware environment where the master control chip only supports integer operation and the on-chip cache is extremely small.

Description

Technical Field

[0001] This application relates to the field of storage media technology, and in particular to an adaptive repair method for high-density NAND storage media. Background Technology

[0002] As the manufacturing process of 3D NAND Flash evolves towards four bits per cell (QLC) and even five bits per cell (PLC), storage density has significantly increased, but the stability of the physical characteristics of the storage cells has decreased accordingly. In practical applications, with the increase of programming and erasing cycles and the extension of data retention time, the threshold voltage distribution of the storage cells will undergo nonlinear drift, leading to a sharp increase in the original bit error rate.

[0003] Existing memory controller chips typically employ static read retry tables or periodic background checks to address voltage drift. However, this "remedial" approach suffers from significant lag, often triggering deep calibration only after error correction fails, leading to substantial fluctuations in system response latency.

[0004] While the industry has attempted to introduce complex mathematical models to predict voltage drift trends, traditional prediction algorithms typically rely on a large number of floating-point operations and huge parameter matrices. However, the embedded processors within solid-state drive (SSD) controller chips usually possess only limited integer arithmetic capabilities and minimal on-chip SRAM (Static Random-Access Memory). Therefore, achieving high-precision media condition prediction and proactive repair under extremely limited hardware resources has become a technological bottleneck in the industry. Summary of the Invention

[0005] This application provides an adaptive repair method for high-density NAND storage media, which can achieve microsecond-level real-time high-precision prediction of the nonlinear voltage drift trend of each physical storage block in a limited hardware environment where the main control chip only supports integer operations and the on-chip cache is extremely small. This eliminates firmware pipeline blockage and performance jitter caused by floating-point operations and loading of large model parameters.

[0006] In a first aspect, this application provides an adaptive repair method for high-density NAND storage media. The high-density NAND storage media includes a controller chip and storage cells. The controller chip only supports integer operations and has a cache. The method includes: the controller chip extracting a target feature vector representing the true aging trend of the storage cells from raw read data containing random physical noise; the controller chip using a fully integer recursive prediction model to deduce the target feature vector to obtain a health status prediction result for the storage cells in a future preset time period; wherein the health status prediction result includes the optimal read reference voltage offset and the estimated bit error rate growth curve; and the controller chip adjusting the charge distribution pattern and programming voltage parameters of the data on the storage cells during the data writing stage based on the health status prediction result.

[0007] The main control chip extracts a target feature vector representing the true aging trend of the memory cell from the raw read data containing random physical noise. This includes: the main control chip acquiring the threshold voltage distribution numerical vector of the target memory block in the memory cell; each element in the threshold voltage distribution numerical vector represents the memory cell count value within a specific voltage range; the main control chip uses the threshold voltage distribution numerical vector and several sets of historical distribution numerical vectors of the target memory block to obtain a timing state observation matrix; the timing state observation matrix is ​​composed of a first component matrix and a second component matrix; the first component matrix is ​​used to characterize the physical aging trend of the memory cell over time and with increased wear, and the second component matrix is ​​used to characterize the instantaneous, sudden, and irregular voltage fluctuations caused by random telegraph noise, read interference, or coupling between adjacent cells; the main control chip iteratively solves the timing state observation matrix to obtain the optimal solution of the first component matrix; the main control chip uses the column vectors in the optimal solution of the first component matrix as the target feature vector.

[0008] The process of the main control chip acquiring the threshold voltage distribution value vector of the target storage block in the storage unit includes: when the main control chip executes the medium state monitoring instruction, it sends a set of read commands to the target storage block; wherein, the set of read commands has different read reference voltage values; the main control chip counts the number of storage units that are turned on between every two adjacent read reference voltages, and constructs the threshold voltage distribution value vector of the target physical block at the current moment.

[0009] The main control chip iteratively solves the time-series state observation matrix to obtain the optimal solution of the first component matrix. This includes: the main control chip using the first component matrix calculated in the previous time step as a priori reference for the decomposition operation in the current time step, and introducing a weighted difference penalty term during the iterative solution process; and updating the values ​​of the first component matrix and the second component matrix within a finite number of iterations using the alternating direction multiplier method until convergence, thereby obtaining the optimal solution of the first component matrix.

[0010] The fully integer recursive prediction model includes an iterative inference unit and an integer shift operation unit. The main control chip uses the fully integer recursive prediction model to deduce the target feature vector and obtain the health status prediction result of the storage unit in the future preset time period. This includes: the main control chip inputs the target feature vector into the iterative inference unit for iterative inference, and uses the integer shift operation unit to process the output of the iterative inference unit through integer multiplication and binary shift operations; when the iteration terminates, the health status prediction result of the storage unit in the future preset time period is obtained.

[0011] The main control chip adjusts the charge distribution pattern and programming voltage parameters of the data on the storage unit during the data writing stage based on the health status prediction results. This includes: the main control chip determining the status based on the estimated bit error rate growth curve to obtain a status determination result; the status determination result includes a healthy state and a sub-healthy state; in response to the status determination result being a sub-healthy state, a shaping mechanism is triggered to obtain the target programming state; the shaping mechanism includes: performing charge probability distribution adjustment based on generalized enumeration mapping and superimposing neighboring cell interference suppression coding based on nonlinear functions; calculating programming voltage parameters based on the target programming state; and sending programming instructions to the storage unit using the programming voltage parameters.

[0012] The process of adjusting the charge probability distribution based on generalized enumeration mapping includes: constructing an energy-constrained Greli map structure; using binary data as an index to find the corresponding voltage state sequence from the Greli map structure to achieve charge probability distribution adjustment; and superimposing neighboring cell interference suppression coding based on nonlinear functions, including: obtaining a spreading sequence codebook; and using the spreading sequence codebook to modulate the current data so that the charge state distribution pattern of the current memory cell is orthogonal or quasi-orthogonal to the distribution patterns of adjacent memory cells in space.

[0013] The health status prediction results also include the current dielectric aging degree. The programming voltage parameters are calculated based on the target programming state, including: outputting the target programming state and the current dielectric aging degree to the feedforward multilayer weighted logic unit to obtain the programming voltage parameters, which include the optimal starting pulse voltage value and the optimal voltage increment step size of the current programming cycle.

[0014] In implementing the above technical solution, a multi-server queuing logic model is used to quantify the impact of background tasks on front-end request latency, thereby enabling the insertion of background tasks.

[0015] The method utilizes a multi-server queuing logic model to quantify the impact of background tasks on frontend request latency, enabling the insertion of background tasks. This includes: extracting deterministic time parameters for background tasks; these parameters are used to define a fixed time window during which frontend requests are unavailable when a background task is started; pre-calculating the frontend latency caused by a background task before issuing it; determining whether to issue a background task based on the frontend latency; and atomically splitting background tasks into several subtasks, pre-calculating the frontend latency caused by each subtask before issuing it; and determining whether to issue the subtask based on the frontend latency.

[0016] The beneficial effects of this application are as follows: Unlike existing technologies, this application provides an adaptive repair method for high-density NAND storage media. The high-density NAND storage media includes a controller chip and storage cells. The controller chip only supports integer operations and has a cache. The method includes: the controller chip extracts a target feature vector representing the true aging trend of the storage cells from raw read data containing random physical noise; the controller chip uses a fully integer recursive prediction model to deduce the target feature vector, obtaining a health status prediction result for the storage cells over a preset future time period; wherein the health status prediction result includes the optimal read reference voltage offset and the estimated bit error rate growth curve; based on the health status prediction result, the controller chip adjusts the charge distribution pattern and programming voltage parameters on the storage cells during the data writing stage. This enables real-time, high-precision prediction of the nonlinear voltage drift trend of each physical storage block at the microsecond level, even in a limited hardware environment where the controller chip only supports integer operations and has a very small on-chip cache. This eliminates firmware pipeline blockage and performance jitter caused by floating-point operations and loading large model parameters. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0018] Figure 1 This is a flowchart illustrating an embodiment of the adaptive repair method for high-density NAND storage media provided in this application;

[0019] Figure 2 yes Figure 1 A flowchart of an embodiment of step 11;

[0020] Figure 3 yes Figure 1 A flowchart of an embodiment of step 13. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are only for explaining this application and not for limiting it. Furthermore, it should be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, not all structures. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0022] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0023] The technical problem to be solved by this application is: how to achieve microsecond-level real-time high-precision prediction of the nonlinear voltage drift trend of each physical memory block in a limited hardware environment where the main control chip only supports integer operations and the on-chip cache is extremely small, thereby eliminating firmware pipeline blockage and performance jitter caused by floating-point operations and loading of huge model parameters.

[0024] See Figure 1 , Figure 1 This is a flowchart illustrating an embodiment of the adaptive repair method for high-density NAND storage media provided in this application. The high-density NAND storage media includes a controller chip and storage cells. The controller chip only supports integer operations and has a cache. The storage cells in the high-density NAND storage media can be any type such as SLC, MLC, TLC, QLC, or PLC. The method includes:

[0025] Step 11: The main control chip separates the target feature vector representing the true aging trend of the storage cell from the raw read data containing random physical noise.

[0026] In some embodiments, see Figure 2 Step 11 can be the following process:

[0027] Step 111: The main control chip obtains the threshold voltage distribution value vector of the target memory block in the memory unit.

[0028] Each element in the threshold voltage distribution numerical vector represents the memory cell count value within a specific voltage range.

[0029] NAND storage media are composed of storage blocks. A storage block consists of several pages.

[0030] When executing the media status monitoring command, the main control chip sends a set of read commands to the target storage block; among them, the set of read commands have different read reference voltage values; the main control chip counts the number of storage cells that are turned on between every two adjacent read reference voltages, and constructs the threshold voltage distribution numerical vector of the target physical block at the current moment.

[0031] In other words, when executing media state monitoring instructions, the main control chip sends a set of read commands (i.e., soft-decision read or move read operations) with different read reference voltage values ​​to the target physical memory block. The main control chip counts the number of memory cells that are conducting between every two adjacent read reference voltages, thereby constructing a threshold voltage distribution vector for the physical block at the current moment. Each element in this threshold voltage distribution vector represents the memory cell count value within a specific voltage range, reflecting the current charge retention state of the storage medium.

[0032] Step 112: The main control chip uses the threshold voltage distribution numerical vector and several sets of historical distribution numerical vectors of the target memory block to obtain the timing state observation matrix.

[0033] In some embodiments, the main control chip concatenates the threshold voltage distribution value vector acquired at the current moment with several sets of historical distribution value vectors (historical threshold voltage distribution value vectors) acquired by the target memory block in the buffer at historical moments (e.g., after the last program erase cycle or during the last inspection) along the time dimension to construct a two-dimensional time-series state observation matrix. Each column of this time-series state observation matrix represents a voltage distribution sample at a time point or wear node, and each row represents a statistical interval of the voltage distribution.

[0034] The timing state observation matrix is ​​composed of the first component matrix and the second component matrix. The first component matrix is ​​used to characterize the physical aging trend of the memory cell as time goes by and wear increases. The second component matrix is ​​used to characterize the instantaneous, sudden and irregular voltage fluctuations caused by random telegraph noise, read interference or coupling of adjacent cells.

[0035] In the firmware algorithm of the main control chip, the above timing state observation matrix is ​​regarded as being composed of two component matrices superimposed (the first component matrix and the second component matrix).

[0036] First component matrix (principal eigencomponent): This matrix has low-rank properties and characterizes the slow, continuous, and strongly correlated physical aging trend of memory cells over time and with increased wear (such as the overall voltage drift caused by oxide layer trap charge accumulation).

[0037] The second component matrix (interference component): This matrix has sparse properties and represents instantaneous, sudden and irregular voltage fluctuations caused by random telegraph noise (RTN), read interference or coupling between adjacent units.

[0038] The main control chip is configured with a mathematical optimization objective based on iterative convergence. The objective aims to find the optimal solution of the two component matrices (the first component matrix and the second component matrix) such that their sum is equal to the time-series state observation matrix in step 112, while minimizing the rank of the first component matrix (through the nuclear norm constraint) and minimizing the non-zero elements of the second component matrix (through the L1 norm constraint).

[0039] Step 113: The main control chip iteratively solves the timing state observation matrix to obtain the optimal solution of the first component matrix.

[0040] The main control chip uses the first component matrix calculated in the previous time step as a priori reference for the decomposition operation in the current time step, and introduces a weighted difference penalty term in the iterative solution process; through the alternating direction multiplier method, the values ​​of the first component matrix and the second component matrix are updated within a finite number of iterations until convergence is obtained, and the optimal solution of the first component matrix is ​​obtained.

[0041] To address the issue of high computational complexity in traditional decomposition methods and to improve the ability to track the gradual changes in storage media, this step introduces a time-domain consistency constraint mechanism during the solution process.

[0042] Specifically, the first component matrix (historical aging characteristics) calculated in the previous time step is used as a priori reference for the decomposition operation in the current time step. During the iterative solution process, a weighted difference penalty term is introduced, which calculates the difference between the first component matrix generated in the current iteration and the historical first component matrix.

[0043] The values ​​of the first and second component matrices are updated within a finite number of iterations using the Alternating Direction Method of Multipliers (ADMM) or similar numerical iterative methods until convergence.

[0044] Step 114: The main control chip uses the column vectors in the optimal solution of the first component matrix as the target feature vectors.

[0045] After the iterative calculation is completed, the main control chip discards the calculated second component matrix (i.e., filters out instantaneous noise interference) and retains the column vector of the first component matrix corresponding to the current moment. This column vector is the clean medium state feature vector (target feature vector) after "denoising". This feature vector accurately reflects the true physical offset position of the current physical block, is not affected by random noise at the time of reading, and is passed as an input parameter to the subsequent prediction module (all-integer recursive prediction model). At the same time, the clean feature vector (target feature vector) is updated to the historical state cache for temporal consistency reference in the next sampling, forming a closed-loop update.

[0046] Step 12: The main control chip uses a fully integer recursive prediction model to deduce the target feature vector and obtain the health status prediction result of the storage unit in the future preset time period.

[0047] The health status prediction results include the optimal read reference voltage offset and the estimated bit error rate growth curve.

[0048] This step aims to establish a predictive model (full integer recursive predictive model) that occupies very little storage space and relies entirely on integer operation logic in a constrained main control chip hardware environment. This model is used to deduce the future threshold voltage drift of the memory cell (optimal read reference voltage offset) based on the feature vector (target feature vector) extracted in step 11.

[0049] In some embodiments, the all-integer recursive prediction model includes an iterative inference unit and an integer shift operation unit. The main control chip inputs the target feature vector into the iterative inference unit for iterative inference, and uses the integer shift operation unit to process the output of the iterative inference unit through integer multiplication and binary shift operations; when the iteration terminates, the health status prediction result of the storage unit in the future preset time period is obtained.

[0050] In some embodiments, a set of recursive state update equations are defined in the firmware logic of the main control chip. These equations do not use static weight parameters, but instead introduce a dynamic gain adjustment mechanism. The dynamic gain adjustment mechanism includes the following steps: calculating the prediction error, generating dynamic gain coefficients, and updating the internal memory state.

[0051] The main method for calculating the prediction error (Innovation) is to compare the current medium state feature vector (observation value) input in step 11 with the previous predicted state vector maintained internally by the system, and calculate the difference vector between the two.

[0052] The main method for generating dynamic gain coefficients is to transform the aforementioned difference vector into dynamic gain coefficients through a nonlinear mapping function. These dynamic gain coefficients characterize the importance weight of the current observation data (observations) relative to historical memory.

[0053] The main method for updating the internal memory state is to use a dynamic gain coefficient to weight and update the historical memory state vector stored internally by the system. This process simulates the transformation from short-term input to long-term trend memory, enabling the model to distinguish between instantaneous state fluctuations and long-term physical aging trends.

[0054] To address the issue of the extremely small on-chip cache (SRAM) capacity of the main control chip, which prevents the loading of large parameter matrices, this application does not employ a multi-layered cascaded deep structure, but instead uses a time-reused cyclic iterative structure. This mainly includes the following methods:

[0055] Define a micro-inference unit (iterative inference unit): This unit allocates a fixed-size set of parameter memory within the firmware to store the weight parameters of a single inference layer. The number of parameters is only a fraction of that in a typical multi-layer model.

[0056] Iterative approximation: During prediction, the main control chip sends the input data to the micro inference unit for calculation to obtain an intermediate result; then, the intermediate result is used as feedback input and sent to the same micro inference unit for the next round of calculation.

[0057] Iteration termination condition: Repeat the above process several times (e.g., 3-5 times), gradually correcting the prediction results by reusing the same set of calculation parameters multiple times, until the output voltage drift prediction value (the optimal read reference voltage offset in the health state prediction result) converges to the preset accuracy range. This method trades a small increase in microsecond-level calculation time for a significant saving in storage space.

[0058] Furthermore, the full integer recursive prediction model employs a full integer operation conversion (integer shift operation unit) that removes the floating-point normalization module. That is, to adapt to the hardware characteristics of the main control chip that only supports fixed-point integer operations, the data normalization processing module (i.e., the BatchNormalization layer) that relies on floating-point division and square root operations is completely removed during the full integer recursive prediction model design stage.

[0059] If an integer scaling factor is used instead, a fixed integer scaling factor is preset after each computation node of the aforementioned micro-inference unit. This factor is used to simulate the adjustment effect of normalization operations on data distribution, but its implementation is accomplished only through integer multiplication and binary shift operations.

[0060] Furthermore, end-to-end fixed-point mapping is performed, mapping all weight parameters, activation values, and intermediate variables in the all-integer recursive prediction model to 8-bit or 16-bit integers. This ensures that the arithmetic logic unit (ALU) operations throughout the prediction process do not contain any floating-point instructions, thereby avoiding floating-point exceptions and performance losses during firmware execution.

[0061] Furthermore, offline progressive cascaded parameter fixation is required for the fully integer recursive prediction model. To obtain the control parameters of the aforementioned fully integer recursive prediction model, an progressive cascaded learning method is used for offline parameter calculation during the firmware compilation stage before the storage device (storage medium) leaves the factory. For example, a high-precision reference model needs to be constructed, followed by layer-by-layer parameter migration and fixation, and then local error correction.

[0062] The main approach to building a high-precision reference model is as follows: First, a high-precision reference model containing a complete normalization layer and floating-point parameters is built on a high-performance computer, which acts as the "teacher".

[0063] The main method for layer-by-layer parameter transfer and solidification is as follows: a miniature full-integer model (full-integer recursive prediction model) to be deployed is constructed as the "student". During training, the parameters of the reference model are frozen, allowing the miniature full-integer model to approximate the output of the reference model layer by layer.

[0064] The main method for local error correction is as follows: For each layer of calculation, the local error between the integer operation result of the micro full-integer model and the floating-point operation result of the reference model is calculated, and compensation is made by adjusting the aforementioned integer scaling factor until the output accuracy of the micro full-integer model meets the requirements. The finally generated integer weight table is stored in the read-only memory of the main control chip.

[0065] Based on this, the real-time lifespan trend of the firmware is predicted as follows:

[0066] During the operation of the storage device, the background task scheduler of the main control chip calls the aforementioned fixed integer weight table and recursive calculation logic.

[0067] Input: The pure medium state feature vector output from step 11.

[0068] Execution: Utilize the loop iteration logic and integer shift operation described above.

[0069] Output: Calculates the optimal read reference voltage offset and the estimated bit error rate growth curve for the target physical block over a preset time period. This output directly guides subsequent write strategy adjustments without the need for a host computer or external processor.

[0070] Step 13: Based on the health status prediction results, the main control chip adjusts the charge distribution pattern and programming voltage parameters of the data on the storage unit during the data writing stage.

[0071] This step aims to proactively intervene during the data writing stage based on the physical block health status prediction results output in step 12. By adjusting the charge distribution pattern and programming voltage parameters of the data on the physical medium, it can delay medium aging and reduce interference from a physical perspective.

[0072] In some embodiments, see Figure 3 Step 13 can be the following process:

[0073] Step 131: The main control chip performs a status determination based on the estimated bit error rate growth curve and obtains the status determination result.

[0074] The status assessment results include healthy state and sub-healthy state.

[0075] The main approach involves establishing a tiered write strategy triggering mechanism based on health status (healthy and sub-healthy states). The storage controller chip monitors in real time the estimated bit error rate growth trend value of each physical block output in step 12.

[0076] The main method for determining the status is as follows: the main control chip compares the trend value in the estimated bit error rate growth curve with a preset safety threshold. If it is lower than the threshold, it is determined to be in a "healthy state" and the standard write mode is adopted; if it is higher than the threshold, it is determined to be in a "sub-healthy state" and the subsequent charge distribution shaping and interference suppression coding mechanism is activated.

[0077] Strategy Selection: Based on the severity of the "sub-healthy state," the main control chip selects the corresponding shaping strength level from the encoding configuration table pre-stored in the firmware. The higher the level, the stronger the suppression of high-voltage programming states, but it may sacrifice a small amount of user-available capacity (i.e., using a more redundant coding rate).

[0078] Step 132: In response to the state determination result being sub-healthy, trigger the shaping mechanism to obtain the target programming state.

[0079] The shaping mechanism includes: performing charge probability distribution adjustment based on generalized enumeration mapping (charge distribution shaping) and superimposing neighboring unit interference suppression coding based on nonlinear functions (interference suppression coding).

[0080] The main methods for adjusting the charge probability distribution based on generalized enumeration mapping are as follows: constructing an energy-constrained Greli map structure; using binary data as an index to find the corresponding voltage state sequence from the Greli map structure to achieve charge probability distribution adjustment.

[0081] When the shaping mechanism (charge distribution shaping) is triggered, the main control chip re-encodes the original binary data stream sent by the host to change the threshold voltage state distribution corresponding to the data in the physical storage unit.

[0082] Constructing an energy-constrained Trellis mapping structure: In the main control chip logic, a set of rules is predefined to map binary data sequences to storage cell voltage state sequences. These rules, based on a generalized enumeration algorithm, sort all possible voltage state sequences according to their corresponding "physical energy value" (i.e., the number of electrons injected for programming or the corresponding threshold voltage level).

[0083] Probabilistic amplitude shaping encoding: The main control chip uses the input binary data as an index to look up the corresponding voltage state sequence in the above mapping structure. The characteristic of this mapping structure is that it maps the vast majority of input data to the physical codes corresponding to low threshold voltage states (such as erase state or intermediate state), while forcibly reducing the frequency of physical codes corresponding to high threshold voltage states (such as the highest programming level).

[0084] The effect is that, through this encoding conversion, the number of storage cells in the physical block under high voltage stress is significantly reduced, thereby reducing lattice damage caused by electrons traveling through the tunnel oxide layer and physically delaying the aging of the device.

[0085] The superposition of neighboring cell interference suppression coding based on nonlinear functions mainly includes the following methods: obtaining the spreading sequence codebook; using the spreading sequence codebook to perform modulation operations on the current data, so that the charge state distribution pattern of the current memory cell and the distribution pattern of the adjacent memory cells exhibit orthogonal or quasi-orthogonal characteristics in space.

[0086] To reduce parasitic capacitive coupling interference between adjacent word lines in high-density stacked memory, a layer of spread spectrum coding is superimposed on the above-mentioned shaping coding. The main approach is to first generate a low cross-correlation codebook, and then perform orthogonal data modulation.

[0087] The main process for generating a low cross-correlation codebook is as follows: a set of spread spectrum sequence codebooks generated based on the maximum nonlinearity Boolean function (i.e., the Bent function) is pre-stored in the read-only memory of the main control chip. This codebook has the mathematical characteristic of low coherence, that is, the cross-correlation value between any two sequences is extremely low.

[0088] The main process of orthogonal data modulation is as follows: Before writing data to the current physical page, the main control chip reads the data patterns that have been written or are yet to be written to adjacent physical pages (such as adjacent word lines). The current data is modulated using the spread spectrum sequence codebook mentioned above, so that the charge state distribution pattern of the current physical cell and the distribution pattern of adjacent memory cells exhibit orthogonal or quasi-orthogonal characteristics in space.

[0089] The effect is that this step effectively disrupts the "resonance" effect of charge states between adjacent memory cells, significantly reduces cell-to-cell interference caused by adjacent memory cells being in a specific voltage state at the same time, and improves the signal-to-noise ratio.

[0090] Step 133: Calculate the programming voltage parameters based on the target programming state.

[0091] The health status prediction result also includes the current dielectric aging degree. The target programming state and the current dielectric aging degree are output to the feedforward multilayer weighted logic unit to obtain the programming voltage parameters. The programming voltage parameters include the optimal starting pulse voltage value and the optimal voltage increment step size of the current programming cycle.

[0092] For example, when applying the final programming pulse, the traditional fixed step voltage (ISPP) strategy is abandoned in favor of dynamically optimized voltage control logic. Specifically, the control objective is first obtained, and then the optimal programming parameters are calculated based on the control objective.

[0093] The main process for obtaining the control target is as follows: the main control chip uses the target programming state generated above and the predicted current dielectric aging degree (such as the estimated value of charge trapping layer density) as the input parameter vector.

[0094] The main process for calculating the optimal programming parameters is as follows: The parameter vector is input into a feedforward multilayer weighted logic unit (i.e., a model predictive control approximation network with complex operators removed). This unit calculates using fixed-point integers and outputs the optimal starting pulse voltage value and the optimal voltage increment step size for the current programming cycle.

[0095] Step 134: Send programming instructions to the memory cell using the programming voltage parameters.

[0096] The flash memory interface controller (master chip) uses the calculated voltage parameters (programming voltage parameters) to send programming instructions to the memory chip (memory cell). This control logic aims to achieve the target threshold voltage with the fewest programming pulses, while avoiding overprogramming caused by excessively large voltage steps, thereby obtaining a narrower and more accurate threshold voltage distribution curve while ensuring write speed.

[0097] In some embodiments, during the implementation of the above technical solution, a multi-server queuing logic model is used to quantify the impact of background tasks on front-end request latency, thereby enabling the insertion of background tasks. This step aims to address the resource contention problem that may arise when the storage device performs the media sampling, calculation, and repair operations described in steps 11 to 13 on read and write requests initiated by the front-end host. By constructing a mathematical model with deterministic time constraints, the impact of background tasks on front-end request latency is accurately quantified, thereby achieving seamless insertion of background tasks.

[0098] Specifically, a queuing service model for multi-channel concurrent resources can be constructed. For example, a multi-server queuing logic model can be established in the firmware scheduling layer of the main control chip. This involves resource mapping, request flow mapping, and state definition.

[0099] The main process of resource mapping is to map each flash transmission channel (Channel) or logical unit (LUN) in the solid-state drive (storage medium) to an independent service node (Server) in the queuing model.

[0100] The main process of request flow mapping is as follows: the random read and write command stream issued by the front-end host is mapped to the client request stream arriving at the service node, and the arrival interval follows a statistical distribution (such as a Poisson distribution).

[0101] The main process of defining the status is as follows: the status of the service node is defined as one of three states: "in service" (processing front-end requests), "idle" (no requests), and "established / occupied" (executing background repair tasks (background tasks)).

[0102] Specifically, by using a multi-server queuing logic model to quantify the impact of background tasks on frontend request latency, the insertion of background tasks can be implemented as follows:

[0103] Extract the deterministic time parameters of the background task; the deterministic time parameters are used to define a fixed time window during which the frontend request is unavailable when the background task is started.

[0104] Unlike traditional queuing theory, which assumes that service times follow an exponential distribution (having randomness), this application utilizes the characteristics of NAND Flash physical operations, namely, programming, erasing, and sensing operations have physically fixed and known durations. This mainly involves parameter solidification and time-slice quantization.

[0105] The main method for parameter solidification is as follows: Read the device characteristic parameter table of the flash memory chip (main control chip), obtain the physical execution time required for various repair operations (such as recoding and writing, voltage sampling) involved in step 13, and define it as the deterministic setup time parameter. β ).

[0106] The main method of time slice quantization is to use this deterministic time parameter as input and substitute it into the scheduler's calculation logic, treating it as if the service node will be active once the background task is started. β A fixed time window during which the frontend is unavailable for requests.

[0107] In addition, before issuing a background task, calculate the front-end latency caused by the background task in advance; decide whether to issue the background task based on the front-end latency.

[0108] For example, calculating the theoretical upper bound of frontend request wait times. Before the scheduler prepares to issue a background repair task, the worst-case frontend latency that the operation might cause is pre-calculated. This specifically involves obtaining real-time load and executing an upper bound algorithm.

[0109] The main way to obtain real-time load is by having the main control chip statistically analyze the current front-end I / O request arrival rate (i.e., system load density).

[0110] The main method for implementing the upper bound algorithm is to utilize the pre-defined formula for calculating the upper bound of the waiting time in the firmware. This formula, based on deterministic setup time parameters and current load density, derives the maximum backlog length and maximum waiting time that the frontend request queue may generate after inserting a background task at the current moment.

[0111] The algorithm simulates the "accumulation phase" (request backlog) after the system inserts a background task and the "dissipation phase due to service capacity recovery" after the task ends, thus outputting an accurate prediction of the latency increment.

[0112] And after obtaining the predicted latency increment, dynamic admission decisions are made based on service quality thresholds. For example, a gating mechanism based on predicted latency is established to determine whether to issue a repair command. This mainly involves processes such as preset QoS thresholds, comparison and decision-making, admission conditions, and postponement strategies.

[0113] The main way to preset QoS thresholds is to set the maximum allowable latency threshold in the firmware configuration (for example, requiring 99.9% of read request latency to be below a certain number of milliseconds).

[0114] The main method of comparison and decision-making is to compare the calculated delay increment prediction value with the QoS threshold.

[0115] The admission criteria include: the scheduler determines the current moment as a "safe window" only when the predicted delay increment is lower than or equal to the QoS threshold, allowing the immediate issuance of the sampling and repair instructions generated in step 11 or step 13 to the corresponding channel.

[0116] The postponement strategy includes: if the predicted latency increment is higher than the QoS threshold, it means that inserting a background task at this time will cause front-end lag. The scheduler will suspend the repair task and put it in a low-priority queue, and continue to monitor load changes until the calculated latency impact falls back to a safe range.

[0117] Additionally, the background task is atomically split into several subtasks. Before each subtask is sent out, the front-end latency caused by the subtask is pre-calculated; the decision to send out the subtask is based on the front-end latency.

[0118] For repair operations with long physical processing times (such as full-block data reshaping), a time-slicing execution strategy (task slices and opportunistic execution) is adopted to further reduce the time consumed by deterministic operations. This involves atomic splitting and gap insertion.

[0119] The main method of atomic decomposition is to break down a complete, long-running repair task into several small, atomic sub-operations (for example, breaking down the rewriting of a block into multiple writes per page).

[0120] The main method for intermittent insertion is to utilize the theoretical upper bound of the frontend request waiting time as described above. Before the scheduler prepares to issue a background repair task, the worst-case frontend latency that the operation may cause is pre-calculated. After obtaining the predicted latency increment, dynamic admission decisions are made based on service quality thresholds. In the tiny gaps between frontend I / O requests, these atomic sub-operations are executed in a distributed manner through multiple decisions, ensuring that the deterministic time occupied by any single operation will not cause the frontend request waiting time to exceed the upper bound.

[0121] That is, this application constructs a closed-loop system that includes media state feature extraction, full integer recursive prediction, dynamic write control and deterministic task scheduling, to achieve adaptive repair of media at the underlying physical level.

[0122] Compared with existing technologies, this technical solution produces the following unexpected technical effects:

[0123] 1. High-precision prediction capability with extremely low resources: By combining a "fully integer network with floating-point normalization layer removed" and a "micro recursive iterative structure," high-precision fitting of nonlinear physical aging curves was successfully achieved on low-end embedded cores that only support integer operations and have extremely small memory footprints. Compared to traditional floating-point models, memory usage is reduced by more than two orders of magnitude, making it possible to perform independent real-time lifetime prediction for each physical block.

[0124] 2. Active life extension effect at the physical level: Unlike traditional methods that rely solely on error correction codes for passive data recovery, this solution actively alters the charge distribution characteristics of the written data on the physical medium through "charge distribution shaping" and "low coherence coding," thereby reducing charge stress and cell interference at the source and significantly extending the programming and erasing cycle life of high-density flash memory.

[0125] 3. Deterministic latency guarantee: Task scheduling is performed using a queuing theory model based on deterministic setup time. The impact boundary of background repair operations on front-end performance is strictly defined mathematically. This effectively eliminates the long-tail latency phenomenon commonly seen in traditional solid-state drives when performing background maintenance tasks, ensuring the stringent service quality and stability requirements of enterprise-level applications.

[0126] The following describes the application scenarios of this application:

[0127] Example 1: Automatic maintenance scenario for long-term retention of static cold data.

[0128] Application scenario description: In enterprise-level storage, some data (such as archived files) may not be accessed for a long time after being written. Over time, electrons in the floating gate or charge trapping layer may naturally leak, causing the threshold voltage to shift to the left, which can easily lead to read errors.

[0129] Collaborative implementation process:

[0130] 1. Scheduling Trigger:

[0131] The main control chip's background scanning timer triggers a patrol request. At this time, the deterministic time scheduler, based on the aforementioned seamless insertion logic of background tasks, collects the arrival rate of current front-end host I / O requests in real time, and combines this with the physical execution time parameter (deterministic setup time) of the "voltage distribution sampling operation" pre-stored in the register. β The maximum latency increment caused by inserting the sampling task to the front-end read / write is calculated. A sampling command is only sent to the flash channel if this increment is lower than a preset Quality of Service (QoS) threshold.

[0132] 2. Feature separation (can be achieved using the collaborative approach from step 11):

[0133] The main control chip performs soft-decision readings on the target physical block to obtain a voltage distribution histogram containing noise. The sparse noise separation logic unit runs an adaptive robust principal component analysis algorithm to decompose the collected data. At this point, the algorithm automatically identifies and removes sparse noise components caused by accidental read disturbances, extracting only the low-rank aging feature vector representing the charge leakage trend.

[0134] 3. Trend projection (can be achieved through collaboration with step 12):

[0135] The extracted clean feature vector is fed into a miniature all-integer recursive prediction unit. This unit calls the fixed integer weight parameters, combines them with the historical state memory (Context) of the physical block, and outputs the predicted voltage drift amplitude of the physical block within a preset time window (e.g., the next 30 days) through multiple fixed-point iterative calculations.

[0136] 4. Decision-making and execution (can be coordinated using step 13):

[0137] If the predicted value indicates that the future bit error rate will exceed the error correction limit, the main control chip determines that the block has entered a "holding force critical state". At this time, the scheduler, again based on the aforementioned logic of seamless insertion of background tasks, searches for an idle time window and triggers a data rewrite operation. During the rewrite process, the dynamic encoder automatically selects a stronger generalized enumeration spherical shaping parameter based on the degree of predicted drift to re-encode the data, reducing the proportion of programming in high-voltage states, thereby reducing the rate of charge leakage at the physical level.

[0138] Example 2: Delaying write endurance for high-frequency hot data.

[0139] Application scenario description: Frequent updates to database logs or index areas lead to a rapid increase in the number of program / erase (P / E) cycles for specific physical blocks, resulting in severe oxide layer damage. Conventional write strategies may cause bad blocks to be generated prematurely.

[0140] Collaborative implementation process:

[0141] 1. Pre-write evaluation (can be done in collaboration with step 12):

[0142] When the host issues a write command, the main control chip first queries the health status register of the target physical block cached in the recursive prediction model. This status is the cumulative damage index calculated in step 2 based on the feature vector (extracted in step 1) after the last erase operation.

[0143] 2. Dynamic coding modulation (can be coordinated with step 13):

[0144] If the damage index exceeds the warning threshold, the write pipeline immediately activates the charge distribution shaping logic.

[0145] First, the host data is remapped using a generalized enumeration algorithm, which forces the high-probability programming states to be concentrated in the low-voltage range, thereby reducing the electron tunneling stress on the oxide layer.

[0146] Secondly, the Bent function codebook in the read-only memory is called to spread spectrum modulation of the written data, so that the data mode of the physical page remains orthogonal to that of the adjacent physical pages, reducing inter-cell crosstalk caused by oxide layer defects.

[0147] 3. Closed-loop voltage control (steps 13 and 11 can be used in combination):

[0148] During the execution of the programming pulse, learning-based model predictive control (MPC) logic intervenes. It utilizes the "programming speed characteristics" extracted in step 11 to calculate the current optimal step voltage (ISPP Step) in real time. While ensuring that the write does not exceed the timeout limit, it uses the minimum voltage increment for programming, avoiding over-programming which further exacerbates the deterioration of the threshold voltage distribution.

[0149] 4. Seamless Intervention (Seamless Integration and Collaboration of Background Tasks):

[0150] The aforementioned encoding and voltage calculation processes are both completed within the high-speed stream of the main control chip, but the physical programming operation is time-consuming. The scheduler uses a deterministic timing model of background task seamless insertion to calculate the blocking time of the current write operation on subsequent read requests. If necessary, it splits large write blocks into multiple subpage write sequences (slicing execution) to smooth I / O latency.

[0151] Example 3: Suppression of Read Disturbance under Intensive Reading.

[0152] Application scenario description: In AI training sets or video streaming applications, the same physical block is read millions of times repeatedly, and unaccessed adjacent cells generate unexpected soft errors due to high voltage on the word lines.

[0153] Collaborative implementation process:

[0154] 1. Feature recognition (which can utilize the core function of step 11):

[0155] When the physical block's read counter reaches the threshold and triggers sampling, the sparse noise separation logic plays a crucial role. It compares the current sampled data with historical benchmarks to identify sudden increases in sparse components in the voltage distribution matrix (which is a typical characteristic of read interference, completely different from the low-rank shift characteristic of charge leakage).

[0156] 2. Status update (can be achieved through collaboration in step 12):

[0157] After receiving this isolated interference feature, the recursive prediction model does not update the long-term aging trend memory (to avoid misjudging it as media aging), but instead outputs a short-term interference risk warning signal.

[0158] 3. Precise recovery (can be achieved through collaboration with step 13):

[0159] After receiving an interference risk signal, the main control chip does not perform a full rewrite (to avoid unnecessary P / E wear), but instead utilizes the error correction assistance strategy from step 13. When reading the affected area again, it refers to the offset output by the prediction model and directly applies dynamic Vref offset compensation to the specific voltage state affected by the interference (usually a cell in an intermediate state). These high-risk bits affected by interference are then marked as "erasure bits" in the LDPC decoder for processing, thus achieving error-free reading without data relocation.

[0160] Example 4: QoS guarantee scenario for background garbage collection.

[0161] Application scenario description: SSDs require a large amount of data movement (reading valid pages and writing new blocks) during garbage collection. Traditional solutions are prone to causing stuttering (long-tail latency) for front-end user requests.

[0162] Collaborative implementation process:

[0163] 1. Global resource mapping (seamless insertion and collaboration of background tasks):

[0164] The deterministic time scheduler treats all pending garbage collection tasks (source block reads, target block writes) as "service requests" that occupy a fixed time slice.

[0165] 2. Upper bound calculation and admission (seamless insertion and collaboration of background tasks):

[0166] The scheduler continuously polls the arrival rate of the front-end I / O queue. Using the upper bound formula for waiting time, it calculates in real time whether initiating a data migration for garbage collection at the current moment would cause the waiting time of front-end requests in the queue to exceed the 99.99% latency requirement set by enterprise users (e.g., 2ms).

[0167] 3. Opportunistic restructuring (which can be achieved by combining steps 11 and 13):

[0168] Once the scheduler identifies a "safe time window" and grants permission to execute, the data flows through the digital signal processing unit of the main control chip during the process of moving from the source block to the target block.

[0169] At this point, the main control chip also performs feature extraction from the source block in step 11 and updates the wear record of the block.

[0170] Simultaneously, the dynamic shaping encoding of step 13 is performed on the data written to the target block, and optimal matching is performed for writing based on the physical characteristics of the target block.

[0171] The entire process was completed during the data migration intervals, achieving both space reclamation and media lifespan extension maintenance, without impacting front-end QoS.

[0172] Example 5: Fault prediction and emergency response scenario at the end of life cycle (EOL).

[0173] Application scenario description: When NAND Flash is close to its nominal lifespan (e.g., P / E Cycle > 3000), the physical cells are in a highly unstable state and are prone to unrecoverable errors.

[0174] Collaborative implementation process:

[0175] 1. High-sensitivity prediction (can be achieved through the synergy of step 12):

[0176] At this point, the number of recursive iterations of the miniature all-integer recursive prediction model automatically increases. Utilizing its context memory capability, the model keenly captures the nonlinear acceleration trend of the broadening threshold voltage distribution (even before the conventional ECC reports an error).

[0177] 2. Radical plastic surgery strategy (can be combined with step 13):

[0178] Once the predictive model outputs a "dying" signal, the main control chip immediately switches to the most aggressive write control strategy.

[0179] The strength of spherical shaping is greatly improved, even at the cost of sacrificing some user capacity (e.g., encoding 4KB user data into 5KB physical data, using only the most stable intermediate voltage state) to ensure that data can be safely written and retained for a long time.

[0180] At the same time, the Bent function interference suppression is forcibly enabled for all word lines to minimize inter-cell crosstalk.

[0181] 3. Priority scheduling (seamless insertion and collaboration of background tasks):

[0182] The deterministic scheduler marks data migration tasks for such dying blocks as the highest priority. Even if the calculated latency impact is slightly higher than the normal QoS threshold, for data security, the scheduler will use the weight factor adjustment mechanism in the algorithm to prioritize the execution of this rescue task and immediately mark the physical block as "retired" after the task is completed.

[0183] As can be seen from the above five embodiments, the four core steps of this application do not operate in isolation, but achieve deep systematic collaboration in the four dimensions of perception, decision-making, execution and scheduling through real-time interaction of feature vectors, prediction results, control parameters and scheduling signals.

[0184] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0185] If the integrated units in the other embodiments described above are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0186] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. An adaptive repair method for high-density NAND storage media, characterized in that, The high-density NAND storage medium includes a controller chip and storage units. The controller chip only supports integer operations and has a cache. The method includes: The main control chip extracts a target feature vector that characterizes the true aging trend of the storage unit from the raw read data containing random physical noise. The main control chip uses a fully integer recursive prediction model to deduce the target feature vector and obtain the health status prediction result of the storage unit in the future preset time period; wherein, the health status prediction result includes the optimal read reference voltage offset and the estimated bit error rate growth curve. Based on the health status prediction results, the main control chip adjusts the charge distribution pattern and programming voltage parameters of the data on the storage unit during the data writing phase. The main control chip extracts a target feature vector characterizing the true aging trend of the storage unit from the raw read data containing random physical noise, including: The main control chip acquires the threshold voltage distribution value vector of the target memory block in the memory cell; each element in the threshold voltage distribution value vector represents the memory cell count value within a specific voltage range; The main control chip uses the threshold voltage distribution numerical vector and several sets of historical distribution numerical vectors of the target memory block to obtain a timing state observation matrix; wherein, the timing state observation matrix is ​​composed of a first component matrix and a second component matrix superimposed; the first component matrix is ​​used to characterize the physical aging trend of the memory cell as time goes by and wear increases, and the second component matrix is ​​used to characterize the instantaneous, sudden and irregular voltage fluctuations caused by random telegraph noise, read interference or coupling of adjacent cells; The main control chip iteratively solves the timing state observation matrix to obtain the optimal solution of the first component matrix; The main control chip uses the column vectors in the optimal solution of the first component matrix as the target feature vector.

2. The method according to claim 1, characterized in that, The main control chip acquires the threshold voltage distribution value vector of the target memory block in the memory unit, including: When executing a media status monitoring instruction, the main control chip sends a set of read commands to the target storage block; wherein the set of read commands has different read reference voltage values. The main control chip counts the number of memory cells that are turned on between every two adjacent read reference voltages, and constructs the threshold voltage distribution numerical vector of the target physical block at the current moment.

3. The method according to claim 1, characterized in that, The main control chip iteratively solves the timing state observation matrix to obtain the optimal solution for the first component matrix, including: The main control chip uses the first component matrix calculated in the previous time step as a priori reference for the decomposition operation in the current time step, and introduces a weighted difference penalty term in the iterative solution process; By using the alternating direction multiplier method, the values ​​of the first component matrix and the second component matrix are updated within a finite number of iterations until convergence, thus obtaining the optimal solution for the first component matrix.

4. The method according to claim 1, characterized in that, The fully integer recursive prediction model includes an iterative inference unit and an integer shift operation unit; the main control chip uses the fully integer recursive prediction model to deduce the target feature vector, and obtains the health status prediction result of the storage unit in a future preset time period, including: The main control chip inputs the target feature vector to the iterative inference unit for iterative inference, and uses the integer shift operation unit to process the output of the iterative inference unit through integer multiplication and binary shift operations; When the iteration terminates, the health status prediction result of the storage unit is obtained in the future preset time period.

5. The method according to claim 1, characterized in that, Based on the health status prediction results, the main control chip adjusts the charge distribution pattern and programming voltage parameters of the data on the storage unit during the data writing phase, including: The main control chip performs a status determination based on the estimated bit error rate growth curve to obtain a status determination result; wherein, the status determination result includes a healthy state and a sub-healthy state; In response to the state determination result being the sub-healthy state, a shaping mechanism is triggered to obtain the target programming state; wherein, the shaping mechanism includes: performing charge probability distribution adjustment based on generalized enumeration mapping and superimposing neighboring unit interference suppression coding based on nonlinear functions; Calculate the programming voltage parameters based on the target programming state; The programming voltage parameters are used to send programming instructions to the memory cell.

6. The method according to claim 5, characterized in that, The process of adjusting the charge probability distribution based on a generalized enumeration mapping includes: Construct an energy-constrained Greiley map structure; Using binary data as an index, the corresponding voltage state sequence is found from the Greli map structure to achieve charge probability distribution adjustment; The superposition-based neighbor-unit interference suppression coding based on nonlinear functions includes: Obtain the spread spectrum sequence codebook; The current data is modulated using the spread spectrum sequence codebook, so that the charge state distribution pattern of the current memory cell is orthogonal or quasi-orthogonal to the distribution pattern of the adjacent memory cells in space.

7. The method according to claim 5, characterized in that, The health status prediction result also includes the current dielectric aging degree, and the calculation of the programming voltage parameters based on the target programming state includes: The target programming state and the current dielectric aging degree are output to the feedforward multilayer weighted logic unit to obtain the programming voltage parameters, which include the optimal starting pulse voltage value and the optimal voltage increment step size of the current programming cycle.

8. The method according to any one of claims 1-7, characterized in that, In implementing any one of claims 1-7, a multi-server queuing logic model is used to quantify the impact of background tasks on front-end request latency, thereby enabling the insertion of the background tasks.

9. The method according to claim 8, characterized in that, The method of quantifying the impact of background tasks on frontend request latency using a multi-server queuing logic model to implement the insertion of background tasks includes: Extract the deterministic time parameter of the background task; the deterministic time parameter is used to determine a fixed time window when the frontend request is unavailable when the background task is started; Furthermore, before issuing a background task, the front-end latency caused by the background task is calculated in advance; Whether to issue the background task is determined based on the front-end delay. Furthermore, the background task is atomically split into several subtasks, and the front-end latency caused by each subtask is pre-calculated before it is sent out. The decision on whether to issue the subtask is based on the front-end latency.

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