Chip atomic clock performance optimization method and test system
By remotely adjusting the parameters of the chip atomic clock via a host computer and optimizing them using Bayesian algorithms, the time-consuming and labor-intensive problems in existing technologies have been solved, achieving efficient performance optimization and automated monitoring, and improving the production efficiency of the chip atomic clock.
Patent Information
- Application Number
- CN202511989566.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-26
- Publication Date
- 2026-03-17
Smart Images
Figure CN121680022A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip atomic clocks, and in particular to a method and testing system for optimizing the performance of chip atomic clocks. Background Technology
[0002] A chip-based atomic clock, as a portable, low-power, and small-size time and frequency reference device, consists of a quantum physics system, a laser, a closed-loop feedback control system, and supporting circuitry. To achieve a highly stable reference frequency output, the closed-loop feedback control system needs to precisely control multiple physical parameters; the selection of these parameters plays a decisive role in the atomic clock's performance. Existing methods for optimizing atomic clock performance typically involve selecting the operating temperature of the quantum physics system within a temperature-insensitive region. This is achieved by manually adjusting the operating temperature of the physics system and measuring the output frequency of the chip-level atomic clock as the operating temperature changes, then selecting the extreme point of the frequency change trend. However, since the performance of each quantum physics system is not uniform, optimizing the atomic clock's performance requires manually adjusting the operating temperature of the physics system to ensure it operates at its optimal temperature, suppressing the impact of external temperature changes on the system's operating temperature, and further reducing frequency variations caused by temperature control. Furthermore, chip-level atomic clocks involve setting parameters for multiple closed-loop control circuits. Control systems typically employ proportional-integral-derivative (PID) methods to ensure the stable operation of relevant controlled parameters, such as the operating temperature and current of the laser, the operating temperature of the physical system, and the stable operation of the voltage-controlled crystal oscillator. In traditional solutions, PID parameter tuning usually involves trial and error. For measuring the performance indicators of atomic clocks, determining the parameters is time-consuming and laborious, with low optimization efficiency, making it difficult to meet the needs of mass production and differentiated manufacturing.
[0003] Therefore, how to achieve an integrated process of parameter debugging and performance monitoring, reduce manual input, reduce the number of experiments, save human resources, and improve the efficiency of optimizing atomic clock performance indicators has become one of the existing technical problems that urgently need to be solved. Summary of the Invention
[0004] This invention provides a method and testing system for optimizing the performance of a chip atomic clock, which integrates parameter debugging and performance monitoring, reduces manual input, reduces the number of experiments, saves human resources, and improves the efficiency of optimizing atomic clock performance indicators.
[0005] Firstly, a method for optimizing the performance of a chip atomic clock is provided, including:
[0006] After the atomic clock under test is started, the host computer reads the preset parameter set inside the atomic clock, monitors the working status of the atomic clock under test, and records and stores the changes of the atomic clock monitoring performance indicators over time.
[0007] After the atomic clock is locked, the frequency measurement module is activated to record the change of the atomic clock output frequency value over time and calculate the frequency stability as the objective function based on the change.
[0008] The host computer remotely adjusts the operating parameters of the atomic clock under test;
[0009] By controlling variables, a parameter optimization scheme based on orthogonal experiments was constructed to complete the setting of basic variable parameters and the acquisition of detection data.
[0010] An optimization model is established based on the operating parameters and output frequency to determine the operating parameters of the atomic clock at the insensitive point of operation.
[0011] The host computer outputs remote operating parameters to the atomic clock under test and further remotely adjusts the control parameters. Based on the control parameters, it records the change of the measured frequency value over time, constructs a frequency stability model of the control parameters, and determines the optimized control parameters.
[0012] By using a host computer algorithm optimization platform, a Bayesian algorithm is established to optimize the stability of atomic clocks. The stability of the measured atomic clock is used as the optimization target, and the performance parameters of the atomic clock are stabilized through iterative optimization by controlling sensitive parameters.
[0013] In one embodiment, the atomic clock monitoring performance indicators include: laser lockout current, laser operating temperature, physical system operating temperature, physical system magnetic field operating voltage, crystal oscillator control voltage, and laser fluorescence signal voltage.
[0014] In one embodiment, the operating parameters of the atomic clock under test include: parameters of the physical system, the laser operating temperature point, the physical system temperature control loop, the laser temperature control loop, the laser current control loop, and the crystal oscillator voltage control loop.
[0015] In one implementation, after constructing a frequency stability model of control parameters and determining the optimized control parameters, the process includes: determining the influence of key parameters on the stability of the atomic clock under test and eliminating the influence of insensitive parameters on the atomic clock.
[0016] In one implementation, the stability of the atomic clock under test is used as the optimization target, and the atomic clock performance parameters are stabilized through iterative optimization of the control sensitive parameters. Then, the host computer outputs the optimized control parameters to the atomic clock under test to complete the optimization of the atomic clock performance parameters.
[0017] Secondly, a chip atomic clock performance testing system is provided, comprising: a reference frequency source, a frequency measurement module, a host computer, and the atomic clock module of the chip under test; wherein,
[0018] A reference frequency source is used to generate a standard frequency reference signal to provide to the frequency measurement module.
[0019] The frequency measurement module is used to measure the frequency deviation of the atomic clock of the chip under test relative to the reference frequency source in real time, and transmit the measurement results to the host computer.
[0020] The host computer is used to transmit setting parameters to the atomic clock under test; to receive test data transmitted to the host computer from the atomic clock under test and the frequency measurement module; and to establish a multi-parameter-multi-monitoring-frequency model based on existing parameters and monitoring data and optimization algorithms, generate parameter adjustment datasets through optimization algorithms, and send the generated datasets and other parameters to the atomic clock under test.
[0021] The atomic clock module of the chip under test is used to output the frequency signal under test. The built-in optical sensing module detects the performance indicators of the atomic clock in real time and transmits the relevant setting parameters and detection results to the host computer through the communication serial port.
[0022] In one embodiment, the atomic clock monitoring performance indicators include: laser lockout current, laser operating temperature, physical system operating temperature, physical system magnetic field operating voltage, crystal oscillator control voltage, and laser fluorescence signal voltage.
[0023] In one embodiment, the host computer is specifically used to collect and record the measured parameters and operating status of the atomic clock under test in real time through a communication interface, including the laser operating temperature, laser operating current, quantum physics system operating temperature, and fluorescence signal voltage of the quantum physics system.
[0024] In one embodiment, the host computer is also used to store and record the changes of relevant parameters over time, and at the same time transmit the laser operating temperature point, the physical system operating temperature point, the laser temperature, the current, and the crystal oscillator loop locking parameters to the atomic clock module of the chip under test through the communication interface.
[0025] In one implementation, the atomic clock under test is connected to a reference atomic clock. The frequency measurement module records the frequency difference between the atomic clock under test and the reference atomic clock. The host computer remotely adjusts the key parameter settings of the atomic clock and monitors the frequency value and stability index of the atomic clock after it has been running stably. Based on the input optimization parameters, an optimization model is established and the optimization parameters are transmitted to the atomic clock to achieve atomic clock performance optimization.
[0026] This invention provides a method and testing system for optimizing the performance of a chip atomic clock. The method includes: after starting the atomic clock under test, a host computer reads the preset parameter set inside the atomic clock and monitors the working status of the atomic clock, recording and storing the changes in the atomic clock's monitoring performance indicators over time; after the atomic clock is locked, a frequency measurement module is started, recording the changes in the output frequency value of the atomic clock over time and calculating the frequency stability as the objective function based on the changes; the host computer remotely adjusts the working parameters of the atomic clock under test; by controlling variables, a parameter optimization setting scheme based on orthogonal experiments is constructed to complete the setting of basic variable parameters and the acquisition of detection data; and so on. An optimization model is established based on the operating parameters and output frequency to determine the operating parameters of the atomic clock at its insensitive operating point. The host computer outputs remote operating parameters to the atomic clock under test and further remotely adjusts the control parameters. Based on the control parameters, the frequency value of the measured value changes over time, and a frequency stability model of the control parameters is constructed to determine the optimized control parameters. Through the host computer algorithm optimization platform, a Bayesian algorithm is established to optimize the stability of the atomic clock. The stability of the atomic clock under test is used as the optimization target, and the performance parameters of the atomic clock are stabilized through iterative optimization of the sensitive control parameters. Through the above methods, the efficiency of optimizing the performance indicators of the atomic clock is improved.
[0027] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and accompanying drawings. Attached Figure Description
[0028] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:
[0029] Figure 1 This is a flowchart of a chip atomic clock performance optimization method according to an embodiment of the present invention;
[0030] Figure 2 This is a schematic diagram of a chip atomic clock performance testing system according to an embodiment of the present invention. Detailed Implementation
[0031] To achieve an integrated process of parameter debugging and performance monitoring, reduce manual input, reduce the number of experiments, save human resources, and improve the efficiency of optimizing atomic clock performance indicators, a chip atomic clock performance optimization method and testing system are provided.
[0032] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention. Furthermore, the embodiments and features in the embodiments of the present invention can be combined with each other without conflict.
[0033] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of the embodiments of the present invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein.
[0034] like Figure 1 As shown in the embodiment, a method for optimizing the performance of a chip atomic clock is provided, including:
[0035] After the atomic clock under test is started, the host computer reads the preset parameter set inside the atomic clock, monitors the working status of the atomic clock under test, and records and stores the changes of the atomic clock monitoring performance indicators over time.
[0036] After the atomic clock is locked, the frequency measurement module is activated to record the change of the atomic clock output frequency value over time and calculate the frequency stability as the objective function based on the change.
[0037] The host computer remotely adjusts the operating parameters of the atomic clock under test;
[0038] By controlling variables, a parameter optimization scheme based on orthogonal experiments was constructed to complete the setting of basic variable parameters and the acquisition of detection data.
[0039] An optimization model is established based on the operating parameters and output frequency to determine the operating parameters of the atomic clock at the insensitive point of operation.
[0040] The host computer outputs remote operating parameters to the atomic clock under test and further remotely adjusts the control parameters. Based on the control parameters, it records the change of the measured frequency value over time, constructs a frequency stability model of the control parameters, and determines the optimized control parameters.
[0041] By using a host computer algorithm optimization platform, a Bayesian algorithm is established to optimize the stability of atomic clocks. The stability of the measured atomic clock is used as the optimization target, and the performance parameters of the atomic clock are stabilized through iterative optimization by controlling sensitive parameters.
[0042] In one embodiment, the atomic clock monitoring performance indicators include: laser lockout current, laser operating temperature, physical system operating temperature, physical system magnetic field operating voltage, crystal oscillator control voltage, and laser fluorescence signal voltage.
[0043] In one embodiment, the operating parameters of the atomic clock under test include: parameters of the physical system, the laser operating temperature point, the physical system temperature control loop, the laser temperature control loop, the laser current control loop, and the crystal oscillator voltage control loop.
[0044] In one implementation, after constructing a frequency stability model of control parameters and determining the optimized control parameters, the process includes: determining the influence of key parameters on the stability of the atomic clock under test and eliminating the influence of insensitive parameters on the atomic clock.
[0045] In one implementation, the stability of the atomic clock under test is used as the optimization target, and the atomic clock performance parameters are stabilized through iterative optimization of the control sensitive parameters. Then, the host computer outputs the optimized control parameters to the atomic clock under test to complete the optimization of the atomic clock performance parameters.
[0046] In one implementation, the host computer collects preset parameters. In this example, the preset parameters include the laser temperature T. laser Physical system operating temperature T phy Laser current closed-loop feedback loop P Ilaser I Ilaser Physical system temperature closed-loop feedback loop P Tphy I Tphy Laser operating temperature closed-loop feedback loop P Tlaser I Tlaser Crystal oscillator voltage closed-loop feedback circuit P O I O .
[0047] In one implementation, orthogonal experiments are used to generate orthogonal arrays and establish Ln(m K In the orthogonal array, n represents the number of trials, m represents the number of levels for each factor, and k represents the number of factors, indicating the number of columns in the orthogonal array. An orthogonal screening model is established. Orthogonal experiments with the above preset parameters are conducted based on the orthogonal array to obtain stability results under different parameters. An analysis of variance is then established to determine the influence of the above 10 factors on the experimental results, identifying x factors as having significant influence.
[0048] In one implementation, a system optimization process is established based on the Bayesian algorithm, which mainly includes the following steps:
[0049] 1. Establish a set of x parameter values xt based on the maximization acquisition function.
[0050] 2. Based on the set of values, set the relevant parameters of the atomic clock and perform closed-loop feedback on the atomic clock to obtain the frequency stability of the atomic clock as the objective function yt=f(xt)+e(t);
[0051] 3. Improve the historical dataset D1:t-1 based on xt and yt; update the probabilistic surrogate model, and re-execute step 1 until the optimized parameters for frequency stability are achieved.
[0052] This embodiment provides a method for optimizing the performance of a chip-based atomic clock. Through digital and automated means, it achieves intelligent optimization of key internal parameters of the chip-based atomic clock. The system integrates parameter optimization and performance monitoring, enabling automated optimization of multiple and key parameters of the atomic clock. The system has a simple structure, is easy to operate, and effectively improves the optimization efficiency and performance of chip-level atomic clocks.
[0053] like Figure 2 As shown, this embodiment provides a chip atomic clock performance testing system, including: a reference frequency source, a frequency measurement module, a host computer, and a chip atomic clock module under test; wherein,
[0054] A reference frequency source is used to generate a standard frequency reference signal to provide to the frequency measurement module.
[0055] The frequency measurement module is used to measure the frequency deviation of the atomic clock of the chip under test relative to the reference frequency source in real time, and transmit the measurement results to the host computer.
[0056] The host computer is used to transmit setting parameters to the atomic clock under test; to receive test data transmitted to the host computer from the atomic clock under test and the frequency measurement module; and to establish a multi-parameter-multi-monitoring-frequency model based on existing parameters and monitoring data and optimization algorithms, generate parameter adjustment datasets through optimization algorithms, and send the generated datasets and other parameters to the atomic clock under test.
[0057] The atomic clock module of the chip under test is used to output the frequency signal under test. The built-in optical sensing module detects the performance indicators of the atomic clock in real time and transmits the relevant setting parameters and detection results to the host computer through the communication serial port.
[0058] In one embodiment, the atomic clock monitoring performance indicators include: laser lockout current, laser operating temperature, physical system operating temperature, physical system magnetic field operating voltage, crystal oscillator control voltage, and laser fluorescence signal voltage.
[0059] In one embodiment, the host computer is specifically used to collect and record the measured parameters and operating status of the atomic clock under test in real time through a communication interface, including the laser operating temperature, laser operating current, quantum physics system operating temperature, and fluorescence signal voltage of the quantum physics system.
[0060] In one embodiment, the host computer is also used to store and record the changes of relevant parameters over time, and at the same time transmit the laser operating temperature point, the physical system operating temperature point, the laser temperature, the current, and the crystal oscillator loop locking parameters to the atomic clock module of the chip under test through the communication interface.
[0061] In one implementation, the atomic clock under test is connected to a reference atomic clock. The frequency measurement module records the frequency difference between the atomic clock under test and the reference atomic clock. The host computer remotely adjusts the key parameter settings of the atomic clock and monitors the frequency value and stability index of the atomic clock after it has been running stably. Based on the input optimization parameters, an optimization model is established and the optimization parameters are transmitted to the atomic clock to achieve atomic clock performance optimization.
[0062] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the invention.
[0063] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.
Claims
1. A method for optimizing the performance of a chip atomic clock, characterized in that, The application relates to a method for optimizing the stability of an atomic clock. After the atomic clock is started, an upper computer reads preset parameter sets in the atomic clock, monitors the working state of the atomic clock, records and stores the changes of atomic clock monitoring performance indexes with time; After the atomic clock is locked, a frequency measurement module is started, the changes of the measured atomic clock output frequency value with time are recorded, and the frequency stability is calculated as a target function according to the changes; The upper computer remotely adjusts the working parameters of the measured atomic clock; Through control variables, an optimization setting scheme based on orthogonal experiment parameters is constructed, basic variable parameter setting is completed, and detection data is acquired; An optimization model is established according to the working parameters and the output frequency, and the working parameters of the atomic clock at a working insensitive point are determined; The upper computer outputs remote working parameters to the measured atomic clock, and further remotely adjusts control parameters; the changes of the measured frequency value with time are recorded according to the control parameters, a control parameter frequency stability model is constructed, and the optimized control parameters are determined; Through an algorithm optimization platform of the upper computer, a Bayesian algorithm is established to realize the optimization of the stability of the atomic clock; the stability of the measured atomic clock is taken as an optimization target, and the performance parameter stability of the atomic clock is realized through iterative optimization of control sensitive parameters.
2. The method for optimizing the performance of a chip atomic clock according to claim 1, characterized in that, The atomic clock monitoring performance indexes include a laser locking working current, a laser working temperature, a physical system working temperature, a physical system magnetic field working voltage, a crystal oscillator control voltage and a laser fluorescence signal voltage.
3. The method for optimizing the performance of a chip atomic clock according to claim 2, characterized in that, The working parameters of the measured atomic clock include the parameters of a physical system, a laser working temperature point, a physical system temperature control loop, a laser temperature control loop, a laser current control loop and a crystal oscillator voltage control loop.
4. The method for optimizing the performance of a chip atomic clock according to claim 3, characterized in that, After the control parameter frequency stability model is constructed and the optimized control parameters are determined, the following steps are included: the influence of key parameters on the frequency of the stability of the measured atomic clock is determined, and the influence of insensitive parameters of the atomic clock is eliminated.
5. The method for optimizing the performance of a chip atomic clock according to claim 4, characterized in that, After the stability of the measured atomic clock is taken as an optimization target and the performance parameter stability of the atomic clock is realized through iterative optimization of control sensitive parameters, the following steps are included: the upper computer outputs the optimized control parameters to the measured atomic clock, and the optimization of the performance parameters of the atomic clock is completed.
6. A chip atomic clock performance test system, characterized by, The application relates to a method for optimizing the stability of an atomic clock. The method comprises the following steps: A reference frequency source, a frequency measurement module, an upper computer and a measured chip atomic clock module are provided; The reference frequency source is used for generating a standard frequency reference signal and providing the frequency reference signal to the frequency measurement module; The frequency measurement module is used for measuring the frequency deviation of the measured chip atomic clock relative to the reference frequency source in real time, and transmitting the measurement result to the upper computer; The upper computer is used for transmitting setting parameters to the measured atomic clock, receiving test data transmitted by the measured atomic clock and the frequency measurement module to the upper computer, and establishing a multi-parameter-multi-monitoring-frequency model based on an optimization algorithm according to the existing parameters and monitoring data; the upper computer generates parameter adjustment data sets through the optimization algorithm, and transmits the generated data sets and parameters to the measured atomic clock; The measured chip atomic clock module is used for outputting a measured frequency signal, and an internal optical sensing module is used for detecting the atomic clock monitoring performance indexes in real time, and transmitting the related setting parameters and detection results to the upper computer through a communication serial port.
7. The chip atomic clock performance test system of claim 6, wherein, The atomic clock monitoring performance index comprises: laser locking working current, laser working temperature, physical system working temperature, physical system magnetic field working voltage, crystal oscillator control voltage, and laser fluorescence signal voltage.
8. The chip atomic clock performance test system of claim 7, wherein, The host computer is specifically configured to collect and record the measured parameters and working states of the measured atomic clock in real time through a communication interface, including the laser working temperature, laser working current, quantum physical system working temperature, and fluorescence signal voltage of the measured atomic clock.
9. The chip atomic clock performance test system of claim 8, wherein, The host computer is also configured to store and record the changes of the related parameters over time, and transmit the laser working temperature point, physical system working temperature point, laser temperature, current, and crystal oscillator loop locking parameters to the measured chip atomic clock module through the communication interface.
10. The chip atomic clock performance test system of claim 9, wherein, The measured atomic clock is connected with a reference atomic clock, a frequency measurement module records the frequency difference between the measured atomic clock and the reference atomic clock, the host computer remotely adjusts the key parameter setting value of the atomic clock, simultaneously monitors the frequency value and stability index of the measured atomic clock after stable operation, establishes an optimization model according to the input optimization parameters, and transmits the optimization parameters to the atomic clock, so as to realize the performance optimization of the atomic clock.